tcg/sparc/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef NDEBUG
  26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  27     "%g0",
  28     "%g1",
  29     "%g2",
  30     "%g3",
  31     "%g4",
  32     "%g5",
  33     "%g6",
  34     "%g7",
  35     "%o0",
  36     "%o1",
  37     "%o2",
  38     "%o3",
  39     "%o4",
  40     "%o5",
  41     "%o6",
  42     "%o7",
  43     "%l0",
  44     "%l1",
  45     "%l2",
  46     "%l3",
  47     "%l4",
  48     "%l5",
  49     "%l6",
  50     "%l7",
  51     "%i0",
  52     "%i1",
  53     "%i2",
  54     "%i3",
  55     "%i4",
  56     "%i5",
  57     "%i6",
  58     "%i7",
  59 };
  60 #endif
  61
  62 static const int tcg_target_reg_alloc_order[] = {
  63     TCG_REG_L0,
  64     TCG_REG_L1,
  65     TCG_REG_L2,
  66     TCG_REG_L3,
  67     TCG_REG_L4,
  68     TCG_REG_L5,
  69     TCG_REG_L6,
  70     TCG_REG_L7,
  71     TCG_REG_I0,
  72     TCG_REG_I1,
  73     TCG_REG_I2,
  74     TCG_REG_I3,
  75     TCG_REG_I4,
  76 };
  77
  78 static const int tcg_target_call_iarg_regs[6] = {
  79     TCG_REG_O0,
  80     TCG_REG_O1,
  81     TCG_REG_O2,
  82     TCG_REG_O3,
  83     TCG_REG_O4,
  84     TCG_REG_O5,
  85 };
  86
  87 static const int tcg_target_call_oarg_regs[2] = {
  88     TCG_REG_O0,
  89     TCG_REG_O1,
  90 };
  91
  92 static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
  93 {
  94     return (val << ((sizeof(tcg_target_long) * 8 - bits))
  95             >> (sizeof(tcg_target_long) * 8 - bits)) == val;
  96 }
  97
  98 static inline int check_fit_i32(uint32_t val, unsigned int bits)
  99 {
 100     return ((val << (32 - bits)) >> (32 - bits)) == val;
 101 }
 102
 103 static void patch_reloc(uint8_t *code_ptr, int type,
 104                         tcg_target_long value, tcg_target_long addend)
 105 {
 106     value += addend;
 107     switch (type) {
 108     case R_SPARC_32:
 109         if (value != (uint32_t)value)
 110             tcg_abort();
 111         *(uint32_t *)code_ptr = value;
 112         break;
 113     case R_SPARC_WDISP22:
 114         value -= (long)code_ptr;
 115         value >>= 2;
 116         if (!check_fit_tl(value, 22))
 117             tcg_abort();
 118         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
 119         break;
 120     case R_SPARC_WDISP19:
 121         value -= (long)code_ptr;
 122         value >>= 2;
 123         if (!check_fit_tl(value, 19))
 124             tcg_abort();
 125         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
 126         break;
 127     default:
 128         tcg_abort();
 129     }
 130 }
 131
 132 /* maximum number of register used for input function arguments */
 133 static inline int tcg_target_get_call_iarg_regs_count(int flags)
 134 {
 135     return 6;
 136 }
 137
 138 /* parse target specific constraints */
 139 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 140 {
 141     const char *ct_str;
 142
 143     ct_str = *pct_str;
 144     switch (ct_str[0]) {
 145     case 'r':
 146         ct->ct |= TCG_CT_REG;
 147         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 148         break;
 149     case 'L': /* qemu_ld/st constraint */
 150         ct->ct |= TCG_CT_REG;
 151         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 152         // Helper args
 153         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
 154         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
 155         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
 156         break;
 157     case 'I':
 158         ct->ct |= TCG_CT_CONST_S11;
 159         break;
 160     case 'J':
 161         ct->ct |= TCG_CT_CONST_S13;
 162         break;
 163     default:
 164         return -1;
 165     }
 166     ct_str++;
 167     *pct_str = ct_str;
 168     return 0;
 169 }
 170
 171 /* test if a constant matches the constraint */
 172 static inline int tcg_target_const_match(tcg_target_long val,
 173                                          const TCGArgConstraint *arg_ct)
 174 {
 175     int ct;
 176
 177     ct = arg_ct->ct;
 178     if (ct & TCG_CT_CONST)
 179         return 1;
 180     else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
 181         return 1;
 182     else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
 183         return 1;
 184     else
 185         return 0;
 186 }
 187
 188 #define INSN_OP(x)  ((x) << 30)
 189 #define INSN_OP2(x) ((x) << 22)
 190 #define INSN_OP3(x) ((x) << 19)
 191 #define INSN_OPF(x) ((x) << 5)
 192 #define INSN_RD(x)  ((x) << 25)
 193 #define INSN_RS1(x) ((x) << 14)
 194 #define INSN_RS2(x) (x)
 195 #define INSN_ASI(x) ((x) << 5)
 196
 197 #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
 198 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
 199 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
 200 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
 201
 202 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
 203 #define COND_N     0x0
 204 #define COND_E     0x1
 205 #define COND_LE    0x2
 206 #define COND_L     0x3
 207 #define COND_LEU   0x4
 208 #define COND_CS    0x5
 209 #define COND_NEG   0x6
 210 #define COND_VS    0x7
 211 #define COND_A     0x8
 212 #define COND_NE    0x9
 213 #define COND_G     0xa
 214 #define COND_GE    0xb
 215 #define COND_GU    0xc
 216 #define COND_CC    0xd
 217 #define COND_POS   0xe
 218 #define COND_VC    0xf
 219 #define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
 220
 221 #define MOVCC_ICC  (1 << 18)
 222 #define MOVCC_XCC  (1 << 18 | 1 << 12)
 223
 224 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 225 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
 226 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 227 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 228 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
 229 #define ARITH_ORN  (INSN_OP(2) | INSN_OP3(0x06))
 230 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 231 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
 232 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
 233 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
 234 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
 235 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
 236 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
 237 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
 238 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
 239 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
 240 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
 241 #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
 242
 243 #define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
 244 #define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
 245 #define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
 246
 247 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
 248 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
 249 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
 250
 251 #define RDY        (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
 252 #define WRY        (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
 253 #define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
 254 #define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
 255 #define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
 256 #define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
 257 #define CALL       INSN_OP(1)
 258 #define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
 259 #define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
 260 #define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
 261 #define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
 262 #define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
 263 #define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
 264 #define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
 265 #define STB        (INSN_OP(3) | INSN_OP3(0x05))
 266 #define STH        (INSN_OP(3) | INSN_OP3(0x06))
 267 #define STW        (INSN_OP(3) | INSN_OP3(0x04))
 268 #define STX        (INSN_OP(3) | INSN_OP3(0x0e))
 269 #define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
 270 #define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
 271 #define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
 272 #define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
 273 #define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
 274 #define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
 275 #define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
 276 #define STBA       (INSN_OP(3) | INSN_OP3(0x15))
 277 #define STHA       (INSN_OP(3) | INSN_OP3(0x16))
 278 #define STWA       (INSN_OP(3) | INSN_OP3(0x14))
 279 #define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
 280
 281 #ifndef ASI_PRIMARY_LITTLE
 282 #define ASI_PRIMARY_LITTLE 0x88
 283 #endif
 284
 285 static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
 286                                  int op)
 287 {
 288     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 289               INSN_RS2(rs2));
 290 }
 291
 292 static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
 293                                   uint32_t offset, int op)
 294 {
 295     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 296               INSN_IMM13(offset));
 297 }
 298
 299 static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
 300                            int val2, int val2const, int op)
 301 {
 302     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
 303               | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
 304 }
 305
 306 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
 307 {
 308     tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
 309 }
 310
 311 static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
 312 {
 313     tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
 314 }
 315
 316 static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
 317 {
 318     tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
 319 }
 320
 321 static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
 322 {
 323     if (check_fit_tl(arg, 13))
 324         tcg_out_movi_imm13(s, ret, arg);
 325     else {
 326         tcg_out_sethi(s, ret, arg);
 327         if (arg & 0x3ff)
 328             tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
 329     }
 330 }
 331
 332 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 333                                 int ret, tcg_target_long arg)
 334 {
 335     /* All 32-bit constants, as well as 64-bit constants with
 336        no high bits set go through movi_imm32.  */
 337     if (TCG_TARGET_REG_BITS == 32
 338         || type == TCG_TYPE_I32
 339         || (arg & ~(tcg_target_long)0xffffffff) == 0) {
 340         tcg_out_movi_imm32(s, ret, arg);
 341     } else if (check_fit_tl(arg, 13)) {
 342         /* A 13-bit constant sign-extended to 64-bits.  */
 343         tcg_out_movi_imm13(s, ret, arg);
 344     } else if (check_fit_tl(arg, 32)) {
 345         /* A 32-bit constant sign-extended to 64-bits.  */
 346         tcg_out_sethi(s, ret, ~arg);
 347         tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
 348     } else {
 349         tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
 350         tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
 351         tcg_out_movi_imm32(s, ret, arg);
 352         tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
 353     }
 354 }
 355
 356 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
 357                                   tcg_target_long arg)
 358 {
 359     tcg_out_sethi(s, ret, arg);
 360     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 361               INSN_IMM13(arg & 0x3ff));
 362 }
 363
 364 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
 365                                   tcg_target_long arg)
 366 {
 367     if (!check_fit_tl(arg, 10))
 368         tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
 369     if (TCG_TARGET_REG_BITS == 64) {
 370         tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
 371                   INSN_IMM13(arg & 0x3ff));
 372     } else {
 373         tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 374                   INSN_IMM13(arg & 0x3ff));
 375     }
 376 }
 377
 378 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
 379 {
 380     if (check_fit_tl(offset, 13))
 381         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
 382                   INSN_IMM13(offset));
 383     else {
 384         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 385         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 386                   INSN_RS2(addr));
 387     }
 388 }
 389
 390 static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
 391                                     int offset, int op, int asi)
 392 {
 393     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 394     tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 395               INSN_ASI(asi) | INSN_RS2(addr));
 396 }
 397
 398 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
 399                               int arg1, tcg_target_long arg2)
 400 {
 401     if (type == TCG_TYPE_I32)
 402         tcg_out_ldst(s, ret, arg1, arg2, LDUW);
 403     else
 404         tcg_out_ldst(s, ret, arg1, arg2, LDX);
 405 }
 406
 407 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
 408                               int arg1, tcg_target_long arg2)
 409 {
 410     if (type == TCG_TYPE_I32)
 411         tcg_out_ldst(s, arg, arg1, arg2, STW);
 412     else
 413         tcg_out_ldst(s, arg, arg1, arg2, STX);
 414 }
 415
 416 static inline void tcg_out_sety(TCGContext *s, int rs)
 417 {
 418     tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
 419 }
 420
 421 static inline void tcg_out_rdy(TCGContext *s, int rd)
 422 {
 423     tcg_out32(s, RDY | INSN_RD(rd));
 424 }
 425
 426 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
 427 {
 428     if (val != 0) {
 429         if (check_fit_tl(val, 13))
 430             tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
 431         else {
 432             tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
 433             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
 434         }
 435     }
 436 }
 437
 438 static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
 439 {
 440     if (val != 0) {
 441         if (check_fit_tl(val, 13))
 442             tcg_out_arithi(s, reg, reg, val, ARITH_AND);
 443         else {
 444             tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
 445             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
 446         }
 447     }
 448 }
 449
 450 static void tcg_out_div32(TCGContext *s, int rd, int rs1,
 451                           int val2, int val2const, int uns)
 452 {
 453     /* Load Y with the sign/zero extension of RS1 to 64-bits.  */
 454     if (uns) {
 455         tcg_out_sety(s, TCG_REG_G0);
 456     } else {
 457         tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
 458         tcg_out_sety(s, TCG_REG_I5);
 459     }
 460
 461     tcg_out_arithc(s, rd, rs1, val2, val2const,
 462                    uns ? ARITH_UDIV : ARITH_SDIV);
 463 }
 464
 465 static inline void tcg_out_nop(TCGContext *s)
 466 {
 467     tcg_out_sethi(s, TCG_REG_G0, 0);
 468 }
 469
 470 static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
 471 {
 472     int32_t val;
 473     TCGLabel *l = &s->labels[label_index];
 474
 475     if (l->has_value) {
 476         val = l->u.value - (tcg_target_long)s->code_ptr;
 477         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
 478                       | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
 479     } else {
 480         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
 481         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
 482     }
 483 }
 484
 485 #if TCG_TARGET_REG_BITS == 64
 486 static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
 487 {
 488     int32_t val;
 489     TCGLabel *l = &s->labels[label_index];
 490
 491     if (l->has_value) {
 492         val = l->u.value - (tcg_target_long)s->code_ptr;
 493         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
 494                       (0x5 << 19) |
 495                       INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
 496     } else {
 497         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
 498         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
 499                       (0x5 << 19) | 0));
 500     }
 501 }
 502 #endif
 503
 504 static const uint8_t tcg_cond_to_bcond[10] = {
 505     [TCG_COND_EQ] = COND_E,
 506     [TCG_COND_NE] = COND_NE,
 507     [TCG_COND_LT] = COND_L,
 508     [TCG_COND_GE] = COND_GE,
 509     [TCG_COND_LE] = COND_LE,
 510     [TCG_COND_GT] = COND_G,
 511     [TCG_COND_LTU] = COND_CS,
 512     [TCG_COND_GEU] = COND_CC,
 513     [TCG_COND_LEU] = COND_LEU,
 514     [TCG_COND_GTU] = COND_GU,
 515 };
 516
 517 static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
 518 {
 519     tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
 520 }
 521
 522 static void tcg_out_brcond_i32(TCGContext *s, int cond,
 523                                TCGArg arg1, TCGArg arg2, int const_arg2,
 524                                int label_index)
 525 {
 526     tcg_out_cmp(s, arg1, arg2, const_arg2);
 527     tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
 528     tcg_out_nop(s);
 529 }
 530
 531 #if TCG_TARGET_REG_BITS == 64
 532 static void tcg_out_brcond_i64(TCGContext *s, int cond,
 533                                TCGArg arg1, TCGArg arg2, int const_arg2,
 534                                int label_index)
 535 {
 536     tcg_out_cmp(s, arg1, arg2, const_arg2);
 537     tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
 538     tcg_out_nop(s);
 539 }
 540 #else
 541 static void tcg_out_brcond2_i32(TCGContext *s, int cond,
 542                                 TCGArg al, TCGArg ah,
 543                                 TCGArg bl, int blconst,
 544                                 TCGArg bh, int bhconst, int label_dest)
 545 {
 546     int cc, label_next = gen_new_label();
 547
 548     tcg_out_cmp(s, ah, bh, bhconst);
 549
 550     /* Note that we fill one of the delay slots with the second compare.  */
 551     switch (cond) {
 552     case TCG_COND_EQ:
 553         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 554         tcg_out_branch_i32(s, cc, label_next);
 555         tcg_out_cmp(s, al, bl, blconst);
 556         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
 557         tcg_out_branch_i32(s, cc, label_dest);
 558         break;
 559
 560     case TCG_COND_NE:
 561         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 562         tcg_out_branch_i32(s, cc, label_dest);
 563         tcg_out_cmp(s, al, bl, blconst);
 564         tcg_out_branch_i32(s, cc, label_dest);
 565         break;
 566
 567     default:
 568         /* ??? One could fairly easily special-case 64-bit unsigned
 569            compares against 32-bit zero-extended constants.  For instance,
 570            we know that (unsigned)AH < 0 is false and need not emit it.
 571            Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
 572            second branch will never be taken.  */
 573         cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
 574         tcg_out_branch_i32(s, cc, label_dest);
 575         tcg_out_nop(s);
 576         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 577         tcg_out_branch_i32(s, cc, label_next);
 578         tcg_out_cmp(s, al, bl, blconst);
 579         cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
 580         tcg_out_branch_i32(s, cc, label_dest);
 581         break;
 582     }
 583     tcg_out_nop(s);
 584
 585     tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
 586 }
 587 #endif
 588
 589 static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
 590                                 TCGArg c1, TCGArg c2, int c2const)
 591 {
 592     TCGArg t;
 593
 594     /* For 32-bit comparisons, we can play games with ADDX/SUBX.  */
 595     switch (cond) {
 596     case TCG_COND_EQ:
 597     case TCG_COND_NE:
 598         if (c2 != 0) {
 599             tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
 600         }
 601         c1 = TCG_REG_G0, c2 = ret, c2const = 0;
 602         cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
 603         break;
 604
 605     case TCG_COND_GTU:
 606     case TCG_COND_GEU:
 607         if (c2const && c2 != 0) {
 608             tcg_out_movi_imm13(s, TCG_REG_I5, c2);
 609             c2 = TCG_REG_I5;
 610         }
 611         t = c1, c1 = c2, c2 = t, c2const = 0;
 612         cond = tcg_swap_cond(cond);
 613         break;
 614
 615     case TCG_COND_LTU:
 616     case TCG_COND_LEU:
 617         break;
 618
 619     default:
 620         tcg_out_cmp(s, c1, c2, c2const);
 621 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
 622         tcg_out_movi_imm13(s, ret, 0);
 623         tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
 624                    | INSN_RS1(tcg_cond_to_bcond[cond])
 625                    | MOVCC_ICC | INSN_IMM11(1));
 626 #else
 627         t = gen_new_label();
 628         tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
 629         tcg_out_movi_imm13(s, ret, 1);
 630         tcg_out_movi_imm13(s, ret, 0);
 631         tcg_out_label(s, t, (tcg_target_long)s->code_ptr);
 632 #endif
 633         return;
 634     }
 635
 636     tcg_out_cmp(s, c1, c2, c2const);
 637     if (cond == TCG_COND_LTU) {
 638         tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
 639     } else {
 640         tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
 641     }
 642 }
 643
 644 #if TCG_TARGET_REG_BITS == 64
 645 static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
 646                                 TCGArg c1, TCGArg c2, int c2const)
 647 {
 648     tcg_out_cmp(s, c1, c2, c2const);
 649     tcg_out_movi_imm13(s, ret, 0);
 650     tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
 651                | INSN_RS1(tcg_cond_to_bcond[cond])
 652                | MOVCC_XCC | INSN_IMM11(1));
 653 }
 654 #else
 655 static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret,
 656                                  TCGArg al, TCGArg ah,
 657                                  TCGArg bl, int blconst,
 658                                  TCGArg bh, int bhconst)
 659 {
 660     int lab;
 661
 662     switch (cond) {
 663     case TCG_COND_EQ:
 664         tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
 665         tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
 666         tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
 667         break;
 668
 669     case TCG_COND_NE:
 670         tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
 671         tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
 672         tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
 673         break;
 674
 675     default:
 676         lab = gen_new_label();
 677
 678         tcg_out_cmp(s, ah, bh, bhconst);
 679         tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
 680         tcg_out_movi_imm13(s, ret, 1);
 681         tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
 682         tcg_out_movi_imm13(s, ret, 0);
 683
 684         tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
 685
 686         tcg_out_label(s, lab, (tcg_target_long)s->code_ptr);
 687         break;
 688     }
 689 }
 690 #endif
 691
 692 /* Generate global QEMU prologue and epilogue code */
 693 void tcg_target_qemu_prologue(TCGContext *s)
 694 {
 695     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
 696               INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
 697     tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
 698               INSN_RS2(TCG_REG_G0));
 699     tcg_out_nop(s);
 700 }
 701
 702 #if defined(CONFIG_SOFTMMU)
 703
 704 #include "../../softmmu_defs.h"
 705
 706 static const void * const qemu_ld_helpers[4] = {
 707     __ldb_mmu,
 708     __ldw_mmu,
 709     __ldl_mmu,
 710     __ldq_mmu,
 711 };
 712
 713 static const void * const qemu_st_helpers[4] = {
 714     __stb_mmu,
 715     __stw_mmu,
 716     __stl_mmu,
 717     __stq_mmu,
 718 };
 719 #endif
 720
 721 #if TARGET_LONG_BITS == 32
 722 #define TARGET_LD_OP LDUW
 723 #else
 724 #define TARGET_LD_OP LDX
 725 #endif
 726
 727 #if TARGET_PHYS_ADDR_BITS == 32
 728 #define TARGET_ADDEND_LD_OP LDUW
 729 #else
 730 #define TARGET_ADDEND_LD_OP LDX
 731 #endif
 732
 733 #ifdef __arch64__
 734 #define HOST_LD_OP LDX
 735 #define HOST_ST_OP STX
 736 #define HOST_SLL_OP SHIFT_SLLX
 737 #define HOST_SRA_OP SHIFT_SRAX
 738 #else
 739 #define HOST_LD_OP LDUW
 740 #define HOST_ST_OP STW
 741 #define HOST_SLL_OP SHIFT_SLL
 742 #define HOST_SRA_OP SHIFT_SRA
 743 #endif
 744
 745 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
 746                             int opc)
 747 {
 748     int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
 749 #if defined(CONFIG_SOFTMMU)
 750     uint32_t *label1_ptr, *label2_ptr;
 751 #endif
 752
 753     data_reg = *args++;
 754     addr_reg = *args++;
 755     mem_index = *args;
 756     s_bits = opc & 3;
 757
 758     arg0 = TCG_REG_O0;
 759     arg1 = TCG_REG_O1;
 760     arg2 = TCG_REG_O2;
 761
 762 #if defined(CONFIG_SOFTMMU)
 763     /* srl addr_reg, x, arg1 */
 764     tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 765                    SHIFT_SRL);
 766     /* and addr_reg, x, arg0 */
 767     tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 768                    ARITH_AND);
 769
 770     /* and arg1, x, arg1 */
 771     tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
 772
 773     /* add arg1, x, arg1 */
 774     tcg_out_addi(s, arg1, offsetof(CPUState,
 775                                    tlb_table[mem_index][0].addr_read));
 776
 777     /* add env, arg1, arg1 */
 778     tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
 779
 780     /* ld [arg1], arg2 */
 781     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
 782               INSN_RS2(TCG_REG_G0));
 783
 784     /* subcc arg0, arg2, %g0 */
 785     tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
 786
 787     /* will become:
 788        be label1
 789         or
 790        be,pt %xcc label1 */
 791     label1_ptr = (uint32_t *)s->code_ptr;
 792     tcg_out32(s, 0);
 793
 794     /* mov (delay slot) */
 795     tcg_out_mov(s, arg0, addr_reg);
 796
 797     /* mov */
 798     tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
 799
 800     /* XXX: move that code at the end of the TB */
 801     /* qemu_ld_helper[s_bits](arg0, arg1) */
 802     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
 803                            - (tcg_target_ulong)s->code_ptr) >> 2)
 804                          & 0x3fffffff));
 805     /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
 806        global registers */
 807     // delay slot
 808     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 809                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 810                  sizeof(long), HOST_ST_OP);
 811     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 812                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 813                  sizeof(long), HOST_LD_OP);
 814
 815     /* data_reg = sign_extend(arg0) */
 816     switch(opc) {
 817     case 0 | 4:
 818         /* sll arg0, 24/56, data_reg */
 819         tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
 820                        HOST_SLL_OP);
 821         /* sra data_reg, 24/56, data_reg */
 822         tcg_out_arithi(s, data_reg, data_reg,
 823                        (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
 824         break;
 825     case 1 | 4:
 826         /* sll arg0, 16/48, data_reg */
 827         tcg_out_arithi(s, data_reg, arg0,
 828                        (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
 829         /* sra data_reg, 16/48, data_reg */
 830         tcg_out_arithi(s, data_reg, data_reg,
 831                        (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
 832         break;
 833     case 2 | 4:
 834         /* sll arg0, 32, data_reg */
 835         tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
 836         /* sra data_reg, 32, data_reg */
 837         tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
 838         break;
 839     case 0:
 840     case 1:
 841     case 2:
 842     case 3:
 843     default:
 844         /* mov */
 845         tcg_out_mov(s, data_reg, arg0);
 846         break;
 847     }
 848
 849     /* will become:
 850        ba label2 */
 851     label2_ptr = (uint32_t *)s->code_ptr;
 852     tcg_out32(s, 0);
 853
 854     /* nop (delay slot */
 855     tcg_out_nop(s);
 856
 857     /* label1: */
 858 #if TARGET_LONG_BITS == 32
 859     /* be label1 */
 860     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
 861                    INSN_OFF22((unsigned long)s->code_ptr -
 862                               (unsigned long)label1_ptr));
 863 #else
 864     /* be,pt %xcc label1 */
 865     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
 866                    (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
 867                               (unsigned long)label1_ptr));
 868 #endif
 869
 870     /* ld [arg1 + x], arg1 */
 871     tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
 872                  offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
 873
 874 #if TARGET_LONG_BITS == 32
 875     /* and addr_reg, x, arg0 */
 876     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
 877     tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
 878     /* add arg0, arg1, arg0 */
 879     tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
 880 #else
 881     /* add addr_reg, arg1, arg0 */
 882     tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
 883 #endif
 884
 885 #else
 886     arg0 = addr_reg;
 887 #endif
 888
 889     switch(opc) {
 890     case 0:
 891         /* ldub [arg0], data_reg */
 892         tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
 893         break;
 894     case 0 | 4:
 895         /* ldsb [arg0], data_reg */
 896         tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
 897         break;
 898     case 1:
 899 #ifdef TARGET_WORDS_BIGENDIAN
 900         /* lduh [arg0], data_reg */
 901         tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
 902 #else
 903         /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
 904         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
 905 #endif
 906         break;
 907     case 1 | 4:
 908 #ifdef TARGET_WORDS_BIGENDIAN
 909         /* ldsh [arg0], data_reg */
 910         tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
 911 #else
 912         /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
 913         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
 914 #endif
 915         break;
 916     case 2:
 917 #ifdef TARGET_WORDS_BIGENDIAN
 918         /* lduw [arg0], data_reg */
 919         tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
 920 #else
 921         /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 922         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
 923 #endif
 924         break;
 925     case 2 | 4:
 926 #ifdef TARGET_WORDS_BIGENDIAN
 927         /* ldsw [arg0], data_reg */
 928         tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
 929 #else
 930         /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 931         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
 932 #endif
 933         break;
 934     case 3:
 935 #ifdef TARGET_WORDS_BIGENDIAN
 936         /* ldx [arg0], data_reg */
 937         tcg_out_ldst(s, data_reg, arg0, 0, LDX);
 938 #else
 939         /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 940         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
 941 #endif
 942         break;
 943     default:
 944         tcg_abort();
 945     }
 946
 947 #if defined(CONFIG_SOFTMMU)
 948     /* label2: */
 949     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 950                    INSN_OFF22((unsigned long)s->code_ptr -
 951                               (unsigned long)label2_ptr));
 952 #endif
 953 }
 954
 955 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
 956                             int opc)
 957 {
 958     int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
 959 #if defined(CONFIG_SOFTMMU)
 960     uint32_t *label1_ptr, *label2_ptr;
 961 #endif
 962
 963     data_reg = *args++;
 964     addr_reg = *args++;
 965     mem_index = *args;
 966
 967     s_bits = opc;
 968
 969     arg0 = TCG_REG_O0;
 970     arg1 = TCG_REG_O1;
 971     arg2 = TCG_REG_O2;
 972
 973 #if defined(CONFIG_SOFTMMU)
 974     /* srl addr_reg, x, arg1 */
 975     tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 976                    SHIFT_SRL);
 977
 978     /* and addr_reg, x, arg0 */
 979     tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 980                    ARITH_AND);
 981
 982     /* and arg1, x, arg1 */
 983     tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
 984
 985     /* add arg1, x, arg1 */
 986     tcg_out_addi(s, arg1, offsetof(CPUState,
 987                                    tlb_table[mem_index][0].addr_write));
 988
 989     /* add env, arg1, arg1 */
 990     tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
 991
 992     /* ld [arg1], arg2 */
 993     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
 994               INSN_RS2(TCG_REG_G0));
 995
 996     /* subcc arg0, arg2, %g0 */
 997     tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
 998
 999     /* will become:
1000        be label1
1001         or
1002        be,pt %xcc label1 */
1003     label1_ptr = (uint32_t *)s->code_ptr;
1004     tcg_out32(s, 0);
1005
1006     /* mov (delay slot) */
1007     tcg_out_mov(s, arg0, addr_reg);
1008
1009     /* mov */
1010     tcg_out_mov(s, arg1, data_reg);
1011
1012     /* mov */
1013     tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
1014
1015     /* XXX: move that code at the end of the TB */
1016     /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
1017     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1018                            - (tcg_target_ulong)s->code_ptr) >> 2)
1019                          & 0x3fffffff));
1020     /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1021        global registers */
1022     // delay slot
1023     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1024                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1025                  sizeof(long), HOST_ST_OP);
1026     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1027                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1028                  sizeof(long), HOST_LD_OP);
1029
1030     /* will become:
1031        ba label2 */
1032     label2_ptr = (uint32_t *)s->code_ptr;
1033     tcg_out32(s, 0);
1034
1035     /* nop (delay slot) */
1036     tcg_out_nop(s);
1037
1038 #if TARGET_LONG_BITS == 32
1039     /* be label1 */
1040     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
1041                    INSN_OFF22((unsigned long)s->code_ptr -
1042                               (unsigned long)label1_ptr));
1043 #else
1044     /* be,pt %xcc label1 */
1045     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
1046                    (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
1047                               (unsigned long)label1_ptr));
1048 #endif
1049
1050     /* ld [arg1 + x], arg1 */
1051     tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
1052                  offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
1053
1054 #if TARGET_LONG_BITS == 32
1055     /* and addr_reg, x, arg0 */
1056     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
1057     tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
1058     /* add arg0, arg1, arg0 */
1059     tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
1060 #else
1061     /* add addr_reg, arg1, arg0 */
1062     tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
1063 #endif
1064
1065 #else
1066     arg0 = addr_reg;
1067 #endif
1068
1069     switch(opc) {
1070     case 0:
1071         /* stb data_reg, [arg0] */
1072         tcg_out_ldst(s, data_reg, arg0, 0, STB);
1073         break;
1074     case 1:
1075 #ifdef TARGET_WORDS_BIGENDIAN
1076         /* sth data_reg, [arg0] */
1077         tcg_out_ldst(s, data_reg, arg0, 0, STH);
1078 #else
1079         /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
1080         tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
1081 #endif
1082         break;
1083     case 2:
1084 #ifdef TARGET_WORDS_BIGENDIAN
1085         /* stw data_reg, [arg0] */
1086         tcg_out_ldst(s, data_reg, arg0, 0, STW);
1087 #else
1088         /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1089         tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
1090 #endif
1091         break;
1092     case 3:
1093 #ifdef TARGET_WORDS_BIGENDIAN
1094         /* stx data_reg, [arg0] */
1095         tcg_out_ldst(s, data_reg, arg0, 0, STX);
1096 #else
1097         /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1098         tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
1099 #endif
1100         break;
1101     default:
1102         tcg_abort();
1103     }
1104
1105 #if defined(CONFIG_SOFTMMU)
1106     /* label2: */
1107     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
1108                    INSN_OFF22((unsigned long)s->code_ptr -
1109                               (unsigned long)label2_ptr));
1110 #endif
1111 }
1112
1113 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1114                               const int *const_args)
1115 {
1116     int c;
1117
1118     switch (opc) {
1119     case INDEX_op_exit_tb:
1120         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1121         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1122                   INSN_IMM13(8));
1123         tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1124                       INSN_RS2(TCG_REG_G0));
1125         break;
1126     case INDEX_op_goto_tb:
1127         if (s->tb_jmp_offset) {
1128             /* direct jump method */
1129             tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
1130             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1131                       INSN_IMM13((args[0] & 0x1fff)));
1132             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1133         } else {
1134             /* indirect jump method */
1135             tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1136             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1137                       INSN_RS2(TCG_REG_G0));
1138         }
1139         tcg_out_nop(s);
1140         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1141         break;
1142     case INDEX_op_call:
1143         if (const_args[0])
1144             tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1145                                    - (tcg_target_ulong)s->code_ptr) >> 2)
1146                                  & 0x3fffffff));
1147         else {
1148             tcg_out_ld_ptr(s, TCG_REG_I5,
1149                            (tcg_target_long)(s->tb_next + args[0]));
1150             tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1151                       INSN_RS2(TCG_REG_G0));
1152         }
1153         /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1154            global registers */
1155         // delay slot
1156         tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1157                      TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1158                      sizeof(long), HOST_ST_OP);
1159         tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1160                      TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1161                      sizeof(long), HOST_LD_OP);
1162         break;
1163     case INDEX_op_jmp:
1164     case INDEX_op_br:
1165         tcg_out_branch_i32(s, COND_A, args[0]);
1166         tcg_out_nop(s);
1167         break;
1168     case INDEX_op_movi_i32:
1169         tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1170         break;
1171
1172 #if TCG_TARGET_REG_BITS == 64
1173 #define OP_32_64(x)                             \
1174         glue(glue(case INDEX_op_, x), _i32):    \
1175         glue(glue(case INDEX_op_, x), _i64)
1176 #else
1177 #define OP_32_64(x)                             \
1178         glue(glue(case INDEX_op_, x), _i32)
1179 #endif
1180     OP_32_64(ld8u):
1181         tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1182         break;
1183     OP_32_64(ld8s):
1184         tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1185         break;
1186     OP_32_64(ld16u):
1187         tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1188         break;
1189     OP_32_64(ld16s):
1190         tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1191         break;
1192     case INDEX_op_ld_i32:
1193 #if TCG_TARGET_REG_BITS == 64
1194     case INDEX_op_ld32u_i64:
1195 #endif
1196         tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1197         break;
1198     OP_32_64(st8):
1199         tcg_out_ldst(s, args[0], args[1], args[2], STB);
1200         break;
1201     OP_32_64(st16):
1202         tcg_out_ldst(s, args[0], args[1], args[2], STH);
1203         break;
1204     case INDEX_op_st_i32:
1205 #if TCG_TARGET_REG_BITS == 64
1206     case INDEX_op_st32_i64:
1207 #endif
1208         tcg_out_ldst(s, args[0], args[1], args[2], STW);
1209         break;
1210     OP_32_64(add):
1211         c = ARITH_ADD;
1212         goto gen_arith;
1213     OP_32_64(sub):
1214         c = ARITH_SUB;
1215         goto gen_arith;
1216     OP_32_64(and):
1217         c = ARITH_AND;
1218         goto gen_arith;
1219     OP_32_64(or):
1220         c = ARITH_OR;
1221         goto gen_arith;
1222     OP_32_64(xor):
1223         c = ARITH_XOR;
1224         goto gen_arith;
1225     case INDEX_op_shl_i32:
1226         c = SHIFT_SLL;
1227         goto gen_arith;
1228     case INDEX_op_shr_i32:
1229         c = SHIFT_SRL;
1230         goto gen_arith;
1231     case INDEX_op_sar_i32:
1232         c = SHIFT_SRA;
1233         goto gen_arith;
1234     case INDEX_op_mul_i32:
1235         c = ARITH_UMUL;
1236         goto gen_arith;
1237
1238     OP_32_64(neg):
1239         c = ARITH_SUB;
1240         goto gen_arith1;
1241     OP_32_64(not):
1242         c = ARITH_ORN;
1243         goto gen_arith1;
1244
1245     case INDEX_op_div_i32:
1246         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1247         break;
1248     case INDEX_op_divu_i32:
1249         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1250         break;
1251
1252     case INDEX_op_rem_i32:
1253     case INDEX_op_remu_i32:
1254         tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1255                       opc == INDEX_op_remu_i32);
1256         tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1257                        ARITH_UMUL);
1258         tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1259         break;
1260
1261     case INDEX_op_brcond_i32:
1262         tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1263                            args[3]);
1264         break;
1265     case INDEX_op_setcond_i32:
1266         tcg_out_setcond_i32(s, args[3], args[0], args[1],
1267                             args[2], const_args[2]);
1268         break;
1269
1270 #if TCG_TARGET_REG_BITS == 32
1271     case INDEX_op_brcond2_i32:
1272         tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1273                             args[2], const_args[2],
1274                             args[3], const_args[3], args[5]);
1275         break;
1276     case INDEX_op_setcond2_i32:
1277         tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
1278                              args[3], const_args[3],
1279                              args[4], const_args[4]);
1280         break;
1281     case INDEX_op_add2_i32:
1282         tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1283                        ARITH_ADDCC);
1284         tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1285                        ARITH_ADDX);
1286         break;
1287     case INDEX_op_sub2_i32:
1288         tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1289                        ARITH_SUBCC);
1290         tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1291                        ARITH_SUBX);
1292         break;
1293     case INDEX_op_mulu2_i32:
1294         tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1295                        ARITH_UMUL);
1296         tcg_out_rdy(s, args[1]);
1297         break;
1298 #endif
1299
1300     case INDEX_op_qemu_ld8u:
1301         tcg_out_qemu_ld(s, args, 0);
1302         break;
1303     case INDEX_op_qemu_ld8s:
1304         tcg_out_qemu_ld(s, args, 0 | 4);
1305         break;
1306     case INDEX_op_qemu_ld16u:
1307         tcg_out_qemu_ld(s, args, 1);
1308         break;
1309     case INDEX_op_qemu_ld16s:
1310         tcg_out_qemu_ld(s, args, 1 | 4);
1311         break;
1312     case INDEX_op_qemu_ld32u:
1313         tcg_out_qemu_ld(s, args, 2);
1314         break;
1315     case INDEX_op_qemu_ld32s:
1316         tcg_out_qemu_ld(s, args, 2 | 4);
1317         break;
1318     case INDEX_op_qemu_st8:
1319         tcg_out_qemu_st(s, args, 0);
1320         break;
1321     case INDEX_op_qemu_st16:
1322         tcg_out_qemu_st(s, args, 1);
1323         break;
1324     case INDEX_op_qemu_st32:
1325         tcg_out_qemu_st(s, args, 2);
1326         break;
1327
1328 #if TCG_TARGET_REG_BITS == 64
1329     case INDEX_op_movi_i64:
1330         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1331         break;
1332     case INDEX_op_ld32s_i64:
1333         tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1334         break;
1335     case INDEX_op_ld_i64:
1336         tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1337         break;
1338     case INDEX_op_st_i64:
1339         tcg_out_ldst(s, args[0], args[1], args[2], STX);
1340         break;
1341     case INDEX_op_shl_i64:
1342         c = SHIFT_SLLX;
1343         goto gen_arith;
1344     case INDEX_op_shr_i64:
1345         c = SHIFT_SRLX;
1346         goto gen_arith;
1347     case INDEX_op_sar_i64:
1348         c = SHIFT_SRAX;
1349         goto gen_arith;
1350     case INDEX_op_mul_i64:
1351         c = ARITH_MULX;
1352         goto gen_arith;
1353     case INDEX_op_div_i64:
1354         c = ARITH_SDIVX;
1355         goto gen_arith;
1356     case INDEX_op_divu_i64:
1357         c = ARITH_UDIVX;
1358         goto gen_arith;
1359     case INDEX_op_rem_i64:
1360     case INDEX_op_remu_i64:
1361         tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1362                        opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1363         tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1364                        ARITH_MULX);
1365         tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1366         break;
1367     case INDEX_op_ext32s_i64:
1368         if (const_args[1]) {
1369             tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1370         } else {
1371             tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1372         }
1373         break;
1374     case INDEX_op_ext32u_i64:
1375         if (const_args[1]) {
1376             tcg_out_movi_imm32(s, args[0], args[1]);
1377         } else {
1378             tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1379         }
1380         break;
1381
1382     case INDEX_op_brcond_i64:
1383         tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1384                            args[3]);
1385         break;
1386     case INDEX_op_setcond_i64:
1387         tcg_out_setcond_i64(s, args[3], args[0], args[1],
1388                             args[2], const_args[2]);
1389         break;
1390
1391     case INDEX_op_qemu_ld64:
1392         tcg_out_qemu_ld(s, args, 3);
1393         break;
1394     case INDEX_op_qemu_st64:
1395         tcg_out_qemu_st(s, args, 3);
1396         break;
1397
1398 #endif
1399     gen_arith:
1400         tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
1401         break;
1402
1403     gen_arith1:
1404         tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
1405         break;
1406
1407     default:
1408         fprintf(stderr, "unknown opcode 0x%x\n", opc);
1409         tcg_abort();
1410     }
1411 }
1412
1413 static const TCGTargetOpDef sparc_op_defs[] = {
1414     { INDEX_op_exit_tb, { } },
1415     { INDEX_op_goto_tb, { } },
1416     { INDEX_op_call, { "ri" } },
1417     { INDEX_op_jmp, { "ri" } },
1418     { INDEX_op_br, { } },
1419
1420     { INDEX_op_mov_i32, { "r", "r" } },
1421     { INDEX_op_movi_i32, { "r" } },
1422     { INDEX_op_ld8u_i32, { "r", "r" } },
1423     { INDEX_op_ld8s_i32, { "r", "r" } },
1424     { INDEX_op_ld16u_i32, { "r", "r" } },
1425     { INDEX_op_ld16s_i32, { "r", "r" } },
1426     { INDEX_op_ld_i32, { "r", "r" } },
1427     { INDEX_op_st8_i32, { "r", "r" } },
1428     { INDEX_op_st16_i32, { "r", "r" } },
1429     { INDEX_op_st_i32, { "r", "r" } },
1430
1431     { INDEX_op_add_i32, { "r", "r", "rJ" } },
1432     { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1433     { INDEX_op_div_i32, { "r", "r", "rJ" } },
1434     { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1435     { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1436     { INDEX_op_remu_i32, { "r", "r", "rJ" } },
1437     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1438     { INDEX_op_and_i32, { "r", "r", "rJ" } },
1439     { INDEX_op_or_i32, { "r", "r", "rJ" } },
1440     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1441
1442     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1443     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1444     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1445
1446     { INDEX_op_neg_i32, { "r", "rJ" } },
1447     { INDEX_op_not_i32, { "r", "rJ" } },
1448
1449     { INDEX_op_brcond_i32, { "r", "rJ" } },
1450     { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
1451
1452 #if TCG_TARGET_REG_BITS == 32
1453     { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
1454     { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
1455     { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1456     { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1457     { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
1458 #endif
1459
1460     { INDEX_op_qemu_ld8u, { "r", "L" } },
1461     { INDEX_op_qemu_ld8s, { "r", "L" } },
1462     { INDEX_op_qemu_ld16u, { "r", "L" } },
1463     { INDEX_op_qemu_ld16s, { "r", "L" } },
1464     { INDEX_op_qemu_ld32u, { "r", "L" } },
1465     { INDEX_op_qemu_ld32s, { "r", "L" } },
1466
1467     { INDEX_op_qemu_st8, { "L", "L" } },
1468     { INDEX_op_qemu_st16, { "L", "L" } },
1469     { INDEX_op_qemu_st32, { "L", "L" } },
1470
1471 #if TCG_TARGET_REG_BITS == 64
1472     { INDEX_op_mov_i64, { "r", "r" } },
1473     { INDEX_op_movi_i64, { "r" } },
1474     { INDEX_op_ld8u_i64, { "r", "r" } },
1475     { INDEX_op_ld8s_i64, { "r", "r" } },
1476     { INDEX_op_ld16u_i64, { "r", "r" } },
1477     { INDEX_op_ld16s_i64, { "r", "r" } },
1478     { INDEX_op_ld32u_i64, { "r", "r" } },
1479     { INDEX_op_ld32s_i64, { "r", "r" } },
1480     { INDEX_op_ld_i64, { "r", "r" } },
1481     { INDEX_op_st8_i64, { "r", "r" } },
1482     { INDEX_op_st16_i64, { "r", "r" } },
1483     { INDEX_op_st32_i64, { "r", "r" } },
1484     { INDEX_op_st_i64, { "r", "r" } },
1485     { INDEX_op_qemu_ld64, { "L", "L" } },
1486     { INDEX_op_qemu_st64, { "L", "L" } },
1487
1488     { INDEX_op_add_i64, { "r", "r", "rJ" } },
1489     { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1490     { INDEX_op_div_i64, { "r", "r", "rJ" } },
1491     { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1492     { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1493     { INDEX_op_remu_i64, { "r", "r", "rJ" } },
1494     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1495     { INDEX_op_and_i64, { "r", "r", "rJ" } },
1496     { INDEX_op_or_i64, { "r", "r", "rJ" } },
1497     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1498
1499     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1500     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1501     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1502
1503     { INDEX_op_neg_i64, { "r", "rJ" } },
1504     { INDEX_op_not_i64, { "r", "rJ" } },
1505
1506     { INDEX_op_ext32s_i64, { "r", "ri" } },
1507     { INDEX_op_ext32u_i64, { "r", "ri" } },
1508
1509     { INDEX_op_brcond_i64, { "r", "rJ" } },
1510     { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
1511 #endif
1512     { -1 },
1513 };
1514
1515 void tcg_target_init(TCGContext *s)
1516 {
1517     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1518 #if TCG_TARGET_REG_BITS == 64
1519     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1520 #endif
1521     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1522                      (1 << TCG_REG_G1) |
1523                      (1 << TCG_REG_G2) |
1524                      (1 << TCG_REG_G3) |
1525                      (1 << TCG_REG_G4) |
1526                      (1 << TCG_REG_G5) |
1527                      (1 << TCG_REG_G6) |
1528                      (1 << TCG_REG_G7) |
1529                      (1 << TCG_REG_O0) |
1530                      (1 << TCG_REG_O1) |
1531                      (1 << TCG_REG_O2) |
1532                      (1 << TCG_REG_O3) |
1533                      (1 << TCG_REG_O4) |
1534                      (1 << TCG_REG_O5) |
1535                      (1 << TCG_REG_O7));
1536
1537     tcg_regset_clear(s->reserved_regs);
1538     tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1539 #if TCG_TARGET_REG_BITS == 64
1540     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1541 #endif
1542     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1543     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1544     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1545     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1546     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1547     tcg_add_target_add_op_defs(sparc_op_defs);
1548 }