hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  34
  35 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  36 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  37 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  38 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  39
  40 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  41 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  42
  43 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  44 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  45 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  46 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  47 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  48
  49 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  50 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  51
  52 /*
  53  * These are the definitions for the Modem Control Register
  54  */
  55 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  56 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  57 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  58 #define UART_MCR_RTS    0x02    /* RTS complement */
  59 #define UART_MCR_DTR    0x01    /* DTR complement */
  60
  61 /*
  62  * These are the definitions for the Modem Status Register
  63  */
  64 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  65 #define UART_MSR_RI     0x40    /* Ring Indicator */
  66 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  67 #define UART_MSR_CTS    0x10    /* Clear to Send */
  68 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  69 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  70 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  71 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  73
  74 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  75 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  76 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  77 #define UART_LSR_FE     0x08    /* Frame error indicator */
  78 #define UART_LSR_PE     0x04    /* Parity error indicator */
  79 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  80 #define UART_LSR_DR     0x01    /* Receiver data ready */
  81 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  82
  83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  84
  85 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  86 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  87 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  88 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  89
  90 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  91 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  92 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  93 #define UART_FCR_FE         0x01    /* FIFO Enable */
  94
  95 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  96
  97 #define XMIT_FIFO           0
  98 #define RECV_FIFO           1
  99 #define MAX_XMIT_RETRY      4
 100
 101 typedef struct SerialFIFO {
 102     uint8_t data[UART_FIFO_LENGTH];
 103     uint8_t count;
 104     uint8_t itl;                        /* Interrupt Trigger Level */
 105     uint8_t tail;
 106     uint8_t head;
 107 } SerialFIFO;
 108
 109 struct SerialState {
 110     uint16_t divider;
 111     uint8_t rbr; /* receive register */
 112     uint8_t thr; /* transmit holding register */
 113     uint8_t tsr; /* transmit shift register */
 114     uint8_t ier;
 115     uint8_t iir; /* read only */
 116     uint8_t lcr;
 117     uint8_t mcr;
 118     uint8_t lsr; /* read only */
 119     uint8_t msr; /* read only */
 120     uint8_t scr;
 121     uint8_t fcr;
 122     uint8_t fcr_vmstate; /* we can't write directly this value
 123                             it has side effects */
 124     /* NOTE: this hidden state is necessary for tx irq generation as
 125        it can be reset while reading iir */
 126     int thr_ipending;
 127     qemu_irq irq;
 128     CharDriverState *chr;
 129     int last_break_enable;
 130     int it_shift;
 131     int baudbase;
 132     int tsr_retry;
 133
 134     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 135     SerialFIFO recv_fifo;
 136     SerialFIFO xmit_fifo;
 137
 138     struct QEMUTimer *fifo_timeout_timer;
 139     int timeout_ipending;                   /* timeout interrupt pending state */
 140     struct QEMUTimer *transmit_timer;
 141
 142
 143     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 144     int poll_msl;
 145
 146     struct QEMUTimer *modem_status_poll;
 147 };
 148
 149 typedef struct ISASerialState {
 150     ISADevice dev;
 151     uint32_t iobase;
 152     uint32_t isairq;
 153     SerialState state;
 154 } ISASerialState;
 155
 156 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 157
 158 static void fifo_clear(SerialState *s, int fifo)
 159 {
 160     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 161     memset(f->data, 0, UART_FIFO_LENGTH);
 162     f->count = 0;
 163     f->head = 0;
 164     f->tail = 0;
 165 }
 166
 167 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 168 {
 169     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 170
 171     f->data[f->head++] = chr;
 172
 173     if (f->head == UART_FIFO_LENGTH)
 174         f->head = 0;
 175     f->count++;
 176
 177     return 1;
 178 }
 179
 180 static uint8_t fifo_get(SerialState *s, int fifo)
 181 {
 182     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 183     uint8_t c;
 184
 185     if(f->count == 0)
 186         return 0;
 187
 188     c = f->data[f->tail++];
 189     if (f->tail == UART_FIFO_LENGTH)
 190         f->tail = 0;
 191     f->count--;
 192
 193     return c;
 194 }
 195
 196 static void serial_update_irq(SerialState *s)
 197 {
 198     uint8_t tmp_iir = UART_IIR_NO_INT;
 199
 200     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 201         tmp_iir = UART_IIR_RLSI;
 202     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 203         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 204          * this is not in the specification but is observed on existing
 205          * hardware.  */
 206         tmp_iir = UART_IIR_CTI;
 207     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 208                (!(s->fcr & UART_FCR_FE) ||
 209                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 210         tmp_iir = UART_IIR_RDI;
 211     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 212         tmp_iir = UART_IIR_THRI;
 213     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 214         tmp_iir = UART_IIR_MSI;
 215     }
 216
 217     s->iir = tmp_iir | (s->iir & 0xF0);
 218
 219     if (tmp_iir != UART_IIR_NO_INT) {
 220         qemu_irq_raise(s->irq);
 221     } else {
 222         qemu_irq_lower(s->irq);
 223     }
 224 }
 225
 226 static void serial_update_parameters(SerialState *s)
 227 {
 228     int speed, parity, data_bits, stop_bits, frame_size;
 229     QEMUSerialSetParams ssp;
 230
 231     if (s->divider == 0)
 232         return;
 233
 234     frame_size = 1;
 235     if (s->lcr & 0x08) {
 236         if (s->lcr & 0x10)
 237             parity = 'E';
 238         else
 239             parity = 'O';
 240     } else {
 241             parity = 'N';
 242             frame_size = 0;
 243     }
 244     if (s->lcr & 0x04)
 245         stop_bits = 2;
 246     else
 247         stop_bits = 1;
 248
 249     data_bits = (s->lcr & 0x03) + 5;
 250     frame_size += data_bits + stop_bits;
 251     speed = s->baudbase / s->divider;
 252     ssp.speed = speed;
 253     ssp.parity = parity;
 254     ssp.data_bits = data_bits;
 255     ssp.stop_bits = stop_bits;
 256     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 257     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 258 #if 0
 259     printf("speed=%d parity=%c data=%d stop=%d\n",
 260            speed, parity, data_bits, stop_bits);
 261 #endif
 262 }
 263
 264 static void serial_update_msl(SerialState *s)
 265 {
 266     uint8_t omsr;
 267     int flags;
 268
 269     qemu_del_timer(s->modem_status_poll);
 270
 271     if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 272         s->poll_msl = -1;
 273         return;
 274     }
 275
 276     omsr = s->msr;
 277
 278     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 279     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 280     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 281     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 282
 283     if (s->msr != omsr) {
 284          /* Set delta bits */
 285          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 286          /* UART_MSR_TERI only if change was from 1 -> 0 */
 287          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 288              s->msr &= ~UART_MSR_TERI;
 289          serial_update_irq(s);
 290     }
 291
 292     /* The real 16550A apparently has a 250ns response latency to line status changes.
 293        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 294
 295     if (s->poll_msl)
 296         qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
 297 }
 298
 299 static void serial_xmit(void *opaque)
 300 {
 301     SerialState *s = opaque;
 302     uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
 303
 304     if (s->tsr_retry <= 0) {
 305         if (s->fcr & UART_FCR_FE) {
 306             s->tsr = fifo_get(s,XMIT_FIFO);
 307             if (!s->xmit_fifo.count)
 308                 s->lsr |= UART_LSR_THRE;
 309         } else {
 310             s->tsr = s->thr;
 311             s->lsr |= UART_LSR_THRE;
 312         }
 313     }
 314
 315     if (s->mcr & UART_MCR_LOOP) {
 316         /* in loopback mode, say that we just received a char */
 317         serial_receive1(s, &s->tsr, 1);
 318     } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
 319         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 320             s->tsr_retry++;
 321             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 322             return;
 323         } else if (s->poll_msl < 0) {
 324             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 325             drop any further failed writes instantly, until we get one that goes through.
 326             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 327             s->tsr_retry = -1;
 328         }
 329     }
 330     else {
 331         s->tsr_retry = 0;
 332     }
 333
 334     s->last_xmit_ts = qemu_get_clock(vm_clock);
 335     if (!(s->lsr & UART_LSR_THRE))
 336         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 337
 338     if (s->lsr & UART_LSR_THRE) {
 339         s->lsr |= UART_LSR_TEMT;
 340         s->thr_ipending = 1;
 341         serial_update_irq(s);
 342     }
 343 }
 344
 345
 346 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 347 {
 348     SerialState *s = opaque;
 349
 350     addr &= 7;
 351 #ifdef DEBUG_SERIAL
 352     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 353 #endif
 354     switch(addr) {
 355     default:
 356     case 0:
 357         if (s->lcr & UART_LCR_DLAB) {
 358             s->divider = (s->divider & 0xff00) | val;
 359             serial_update_parameters(s);
 360         } else {
 361             s->thr = (uint8_t) val;
 362             if(s->fcr & UART_FCR_FE) {
 363                   fifo_put(s, XMIT_FIFO, s->thr);
 364             s->thr_ipending = 0;
 365                   s->lsr &= ~UART_LSR_TEMT;
 366             s->lsr &= ~UART_LSR_THRE;
 367             serial_update_irq(s);
 368             } else {
 369                   s->thr_ipending = 0;
 370                   s->lsr &= ~UART_LSR_THRE;
 371                   serial_update_irq(s);
 372             }
 373             serial_xmit(s);
 374         }
 375         break;
 376     case 1:
 377         if (s->lcr & UART_LCR_DLAB) {
 378             s->divider = (s->divider & 0x00ff) | (val << 8);
 379             serial_update_parameters(s);
 380         } else {
 381             s->ier = val & 0x0f;
 382             /* If the backend device is a real serial port, turn polling of the modem
 383                status lines on physical port on or off depending on UART_IER_MSI state */
 384             if (s->poll_msl >= 0) {
 385                 if (s->ier & UART_IER_MSI) {
 386                      s->poll_msl = 1;
 387                      serial_update_msl(s);
 388                 } else {
 389                      qemu_del_timer(s->modem_status_poll);
 390                      s->poll_msl = 0;
 391                 }
 392             }
 393             if (s->lsr & UART_LSR_THRE) {
 394                 s->thr_ipending = 1;
 395                 serial_update_irq(s);
 396             }
 397         }
 398         break;
 399     case 2:
 400         val = val & 0xFF;
 401
 402         if (s->fcr == val)
 403             break;
 404
 405         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 406         if ((val ^ s->fcr) & UART_FCR_FE)
 407             val |= UART_FCR_XFR | UART_FCR_RFR;
 408
 409         /* FIFO clear */
 410
 411         if (val & UART_FCR_RFR) {
 412             qemu_del_timer(s->fifo_timeout_timer);
 413             s->timeout_ipending=0;
 414             fifo_clear(s,RECV_FIFO);
 415         }
 416
 417         if (val & UART_FCR_XFR) {
 418             fifo_clear(s,XMIT_FIFO);
 419         }
 420
 421         if (val & UART_FCR_FE) {
 422             s->iir |= UART_IIR_FE;
 423             /* Set RECV_FIFO trigger Level */
 424             switch (val & 0xC0) {
 425             case UART_FCR_ITL_1:
 426                 s->recv_fifo.itl = 1;
 427                 break;
 428             case UART_FCR_ITL_2:
 429                 s->recv_fifo.itl = 4;
 430                 break;
 431             case UART_FCR_ITL_3:
 432                 s->recv_fifo.itl = 8;
 433                 break;
 434             case UART_FCR_ITL_4:
 435                 s->recv_fifo.itl = 14;
 436                 break;
 437             }
 438         } else
 439             s->iir &= ~UART_IIR_FE;
 440
 441         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 442         s->fcr = val & 0xC9;
 443         serial_update_irq(s);
 444         break;
 445     case 3:
 446         {
 447             int break_enable;
 448             s->lcr = val;
 449             serial_update_parameters(s);
 450             break_enable = (val >> 6) & 1;
 451             if (break_enable != s->last_break_enable) {
 452                 s->last_break_enable = break_enable;
 453                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 454                                &break_enable);
 455             }
 456         }
 457         break;
 458     case 4:
 459         {
 460             int flags;
 461             int old_mcr = s->mcr;
 462             s->mcr = val & 0x1f;
 463             if (val & UART_MCR_LOOP)
 464                 break;
 465
 466             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 467
 468                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 469
 470                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 471
 472                 if (val & UART_MCR_RTS)
 473                     flags |= CHR_TIOCM_RTS;
 474                 if (val & UART_MCR_DTR)
 475                     flags |= CHR_TIOCM_DTR;
 476
 477                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 478                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 479                    from the device/computer at the other end of the serial line */
 480                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
 481             }
 482         }
 483         break;
 484     case 5:
 485         break;
 486     case 6:
 487         break;
 488     case 7:
 489         s->scr = val;
 490         break;
 491     }
 492 }
 493
 494 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 495 {
 496     SerialState *s = opaque;
 497     uint32_t ret;
 498
 499     addr &= 7;
 500     switch(addr) {
 501     default:
 502     case 0:
 503         if (s->lcr & UART_LCR_DLAB) {
 504             ret = s->divider & 0xff;
 505         } else {
 506             if(s->fcr & UART_FCR_FE) {
 507                 ret = fifo_get(s,RECV_FIFO);
 508                 if (s->recv_fifo.count == 0)
 509                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 510                 else
 511                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 512                 s->timeout_ipending = 0;
 513             } else {
 514                 ret = s->rbr;
 515                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 516             }
 517             serial_update_irq(s);
 518             if (!(s->mcr & UART_MCR_LOOP)) {
 519                 /* in loopback mode, don't receive any data */
 520                 qemu_chr_accept_input(s->chr);
 521             }
 522         }
 523         break;
 524     case 1:
 525         if (s->lcr & UART_LCR_DLAB) {
 526             ret = (s->divider >> 8) & 0xff;
 527         } else {
 528             ret = s->ier;
 529         }
 530         break;
 531     case 2:
 532         ret = s->iir;
 533             s->thr_ipending = 0;
 534         serial_update_irq(s);
 535         break;
 536     case 3:
 537         ret = s->lcr;
 538         break;
 539     case 4:
 540         ret = s->mcr;
 541         break;
 542     case 5:
 543         ret = s->lsr;
 544         /* Clear break interrupt */
 545         if (s->lsr & UART_LSR_BI) {
 546             s->lsr &= ~UART_LSR_BI;
 547             serial_update_irq(s);
 548         }
 549         break;
 550     case 6:
 551         if (s->mcr & UART_MCR_LOOP) {
 552             /* in loopback, the modem output pins are connected to the
 553                inputs */
 554             ret = (s->mcr & 0x0c) << 4;
 555             ret |= (s->mcr & 0x02) << 3;
 556             ret |= (s->mcr & 0x01) << 5;
 557         } else {
 558             if (s->poll_msl >= 0)
 559                 serial_update_msl(s);
 560             ret = s->msr;
 561             /* Clear delta bits & msr int after read, if they were set */
 562             if (s->msr & UART_MSR_ANY_DELTA) {
 563                 s->msr &= 0xF0;
 564                 serial_update_irq(s);
 565             }
 566         }
 567         break;
 568     case 7:
 569         ret = s->scr;
 570         break;
 571     }
 572 #ifdef DEBUG_SERIAL
 573     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 574 #endif
 575     return ret;
 576 }
 577
 578 static int serial_can_receive(SerialState *s)
 579 {
 580     if(s->fcr & UART_FCR_FE) {
 581         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 582         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 583         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 584         effectively overriding the ITL that the guest has set. */
 585              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 586         else
 587              return 0;
 588     } else {
 589     return !(s->lsr & UART_LSR_DR);
 590     }
 591 }
 592
 593 static void serial_receive_break(SerialState *s)
 594 {
 595     s->rbr = 0;
 596     /* When the LSR_DR is set a null byte is pushed into the fifo */
 597     fifo_put(s, RECV_FIFO, '\0');
 598     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 599     serial_update_irq(s);
 600 }
 601
 602 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 603 static void fifo_timeout_int (void *opaque) {
 604     SerialState *s = opaque;
 605     if (s->recv_fifo.count) {
 606         s->timeout_ipending = 1;
 607         serial_update_irq(s);
 608     }
 609 }
 610
 611 static int serial_can_receive1(void *opaque)
 612 {
 613     SerialState *s = opaque;
 614     return serial_can_receive(s);
 615 }
 616
 617 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 618 {
 619     SerialState *s = opaque;
 620     if(s->fcr & UART_FCR_FE) {
 621         int i;
 622         for (i = 0; i < size; i++) {
 623             fifo_put(s, RECV_FIFO, buf[i]);
 624         }
 625         s->lsr |= UART_LSR_DR;
 626         /* call the timeout receive callback in 4 char transmit time */
 627         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 628     } else {
 629         s->rbr = buf[0];
 630         s->lsr |= UART_LSR_DR;
 631     }
 632     serial_update_irq(s);
 633 }
 634
 635 static void serial_event(void *opaque, int event)
 636 {
 637     SerialState *s = opaque;
 638 #ifdef DEBUG_SERIAL
 639     printf("serial: event %x\n", event);
 640 #endif
 641     if (event == CHR_EVENT_BREAK)
 642         serial_receive_break(s);
 643 }
 644
 645 static void serial_pre_save(void *opaque)
 646 {
 647     SerialState *s = opaque;
 648     s->fcr_vmstate = s->fcr;
 649 }
 650
 651 static int serial_pre_load(void *opaque)
 652 {
 653     SerialState *s = opaque;
 654     s->fcr_vmstate = 0;
 655     return 0;
 656 }
 657
 658 static int serial_post_load(void *opaque, int version_id)
 659 {
 660     SerialState *s = opaque;
 661
 662     /* Initialize fcr via setter to perform essential side-effects */
 663     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 664     return 0;
 665 }
 666
 667 static const VMStateDescription vmstate_serial = {
 668     .name = "serial",
 669     .version_id = 3,
 670     .minimum_version_id = 2,
 671     .pre_save = serial_pre_save,
 672     .pre_load = serial_pre_load,
 673     .post_load = serial_post_load,
 674     .fields      = (VMStateField []) {
 675         VMSTATE_UINT16_V(divider, SerialState, 2),
 676         VMSTATE_UINT8(rbr, SerialState),
 677         VMSTATE_UINT8(ier, SerialState),
 678         VMSTATE_UINT8(iir, SerialState),
 679         VMSTATE_UINT8(lcr, SerialState),
 680         VMSTATE_UINT8(mcr, SerialState),
 681         VMSTATE_UINT8(lsr, SerialState),
 682         VMSTATE_UINT8(msr, SerialState),
 683         VMSTATE_UINT8(scr, SerialState),
 684         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 685         VMSTATE_END_OF_LIST()
 686     }
 687 };
 688
 689 static void serial_reset(void *opaque)
 690 {
 691     SerialState *s = opaque;
 692
 693     s->rbr = 0;
 694     s->ier = 0;
 695     s->iir = UART_IIR_NO_INT;
 696     s->lcr = 0;
 697     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 698     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 699     /* Default to 9600 baud, no parity, one stop bit */
 700     s->divider = 0x0C;
 701     s->mcr = UART_MCR_OUT2;
 702     s->scr = 0;
 703     s->tsr_retry = 0;
 704     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9;
 705     s->poll_msl = 0;
 706
 707     fifo_clear(s,RECV_FIFO);
 708     fifo_clear(s,XMIT_FIFO);
 709
 710     s->last_xmit_ts = qemu_get_clock(vm_clock);
 711
 712     s->thr_ipending = 0;
 713     s->last_break_enable = 0;
 714     qemu_irq_lower(s->irq);
 715 }
 716
 717 static void serial_init_core(SerialState *s)
 718 {
 719     if (!s->chr) {
 720         fprintf(stderr, "Can't create serial device, empty char device\n");
 721         exit(1);
 722     }
 723
 724     s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 725
 726     s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 727     s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 728
 729     qemu_register_reset(serial_reset, s);
 730     serial_reset(s);
 731
 732     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 733                           serial_event, s);
 734 }
 735
 736 static int serial_isa_initfn(ISADevice *dev)
 737 {
 738     ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
 739     SerialState *s = &isa->state;
 740
 741     s->baudbase = 115200;
 742     isa_init_irq(dev, &s->irq, isa->isairq);
 743     serial_init_core(s);
 744     vmstate_register(isa->iobase, &vmstate_serial, s);
 745
 746     register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
 747     register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
 748     return 0;
 749 }
 750
 751 static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 752 static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 753
 754 SerialState *serial_isa_init(int index, CharDriverState *chr)
 755 {
 756     ISADevice *dev;
 757
 758     dev = isa_create("isa-serial");
 759     qdev_prop_set_uint32(&dev->qdev, "iobase", isa_serial_io[index]);
 760     qdev_prop_set_uint32(&dev->qdev, "irq", isa_serial_irq[index]);
 761     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
 762     if (qdev_init(&dev->qdev) < 0)
 763         return NULL;
 764     return &DO_UPCAST(ISASerialState, dev, dev)->state;
 765 }
 766
 767 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 768                          CharDriverState *chr)
 769 {
 770     SerialState *s;
 771
 772     s = qemu_mallocz(sizeof(SerialState));
 773
 774     s->irq = irq;
 775     s->baudbase = baudbase;
 776     s->chr = chr;
 777     serial_init_core(s);
 778
 779     vmstate_register(base, &vmstate_serial, s);
 780
 781     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 782     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 783     return s;
 784 }
 785
 786 /* Memory mapped interface */
 787 static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
 788 {
 789     SerialState *s = opaque;
 790
 791     return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
 792 }
 793
 794 static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
 795                              uint32_t value)
 796 {
 797     SerialState *s = opaque;
 798
 799     serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 800 }
 801
 802 static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
 803 {
 804     SerialState *s = opaque;
 805     uint32_t val;
 806
 807     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 808 #ifdef TARGET_WORDS_BIGENDIAN
 809     val = bswap16(val);
 810 #endif
 811     return val;
 812 }
 813
 814 static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
 815                              uint32_t value)
 816 {
 817     SerialState *s = opaque;
 818 #ifdef TARGET_WORDS_BIGENDIAN
 819     value = bswap16(value);
 820 #endif
 821     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 822 }
 823
 824 static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
 825 {
 826     SerialState *s = opaque;
 827     uint32_t val;
 828
 829     val = serial_ioport_read(s, addr >> s->it_shift);
 830 #ifdef TARGET_WORDS_BIGENDIAN
 831     val = bswap32(val);
 832 #endif
 833     return val;
 834 }
 835
 836 static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
 837                              uint32_t value)
 838 {
 839     SerialState *s = opaque;
 840 #ifdef TARGET_WORDS_BIGENDIAN
 841     value = bswap32(value);
 842 #endif
 843     serial_ioport_write(s, addr >> s->it_shift, value);
 844 }
 845
 846 static CPUReadMemoryFunc * const serial_mm_read[] = {
 847     &serial_mm_readb,
 848     &serial_mm_readw,
 849     &serial_mm_readl,
 850 };
 851
 852 static CPUWriteMemoryFunc * const serial_mm_write[] = {
 853     &serial_mm_writeb,
 854     &serial_mm_writew,
 855     &serial_mm_writel,
 856 };
 857
 858 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 859                              qemu_irq irq, int baudbase,
 860                              CharDriverState *chr, int ioregister)
 861 {
 862     SerialState *s;
 863     int s_io_memory;
 864
 865     s = qemu_mallocz(sizeof(SerialState));
 866
 867     s->it_shift = it_shift;
 868     s->irq = irq;
 869     s->baudbase = baudbase;
 870     s->chr = chr;
 871
 872     serial_init_core(s);
 873     vmstate_register(base, &vmstate_serial, s);
 874
 875     if (ioregister) {
 876         s_io_memory = cpu_register_io_memory(serial_mm_read,
 877                                              serial_mm_write, s);
 878         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 879     }
 880     serial_update_msl(s);
 881     return s;
 882 }
 883
 884 static ISADeviceInfo serial_isa_info = {
 885     .qdev.name  = "isa-serial",
 886     .qdev.size  = sizeof(ISASerialState),
 887     .init       = serial_isa_initfn,
 888     .qdev.props = (Property[]) {
 889         DEFINE_PROP_HEX32("iobase", ISASerialState, iobase,  0x3f8),
 890         DEFINE_PROP_UINT32("irq",   ISASerialState, isairq,  4),
 891         DEFINE_PROP_CHR("chardev",  ISASerialState, state.chr),
 892         DEFINE_PROP_END_OF_LIST(),
 893     },
 894 };
 895
 896 static void serial_register_devices(void)
 897 {
 898     isa_qdev_register(&serial_isa_info);
 899 }
 900
 901 device_init(serial_register_devices)