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configure: fix compilation on hosts without -fstack-protector-all
[qemu/aliguori-queue.git] / target-i386 / translate.c
bloba597e80b9f25212fc43c69e6947031130f923203
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30
31 #include "helper.h"
32 #define GEN_HELPER 1
33 #include "helper.h"
34
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40
41 #ifdef TARGET_X86_64
42 #define X86_64_ONLY(x) x
43 #define X86_64_DEF(...) __VA_ARGS__
44 #define CODE64(s) ((s)->code64)
45 #define REX_X(s) ((s)->rex_x)
46 #define REX_B(s) ((s)->rex_b)
47 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48 #if 1
49 #define BUGGY_64(x) NULL
50 #endif
51 #else
52 #define X86_64_ONLY(x) NULL
53 #define X86_64_DEF(...)
54 #define CODE64(s) 0
55 #define REX_X(s) 0
56 #define REX_B(s) 0
57 #endif
58
59 //#define MACRO_TEST 1
60
61 /* global register indexes */
62 static TCGv_ptr cpu_env;
63 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
64 static TCGv_i32 cpu_cc_op;
65 static TCGv cpu_regs[CPU_NB_REGS];
66 /* local temps */
67 static TCGv cpu_T[2], cpu_T3;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0, cpu_tmp4;
70 static TCGv_ptr cpu_ptr0, cpu_ptr1;
71 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72 static TCGv_i64 cpu_tmp1_i64;
73 static TCGv cpu_tmp5;
74
75 #include "gen-icount.h"
76
77 #ifdef TARGET_X86_64
78 static int x86_64_hregs;
79 #endif
80
81 typedef struct DisasContext {
82 /* current insn context */
83 int override; /* -1 if no override */
84 int prefix;
85 int aflag, dflag;
86 target_ulong pc; /* pc = eip + cs_base */
87 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
88 static state change (stop translation) */
89 /* current block context */
90 target_ulong cs_base; /* base of CS segment */
91 int pe; /* protected mode */
92 int code32; /* 32 bit code segment */
93 #ifdef TARGET_X86_64
94 int lma; /* long mode active */
95 int code64; /* 64 bit code segment */
96 int rex_x, rex_b;
97 #endif
98 int ss32; /* 32 bit stack segment */
99 int cc_op; /* current CC operation */
100 int addseg; /* non zero if either DS/ES/SS have a non zero base */
101 int f_st; /* currently unused */
102 int vm86; /* vm86 mode */
103 int cpl;
104 int iopl;
105 int tf; /* TF cpu flag */
106 int singlestep_enabled; /* "hardware" single step enabled */
107 int jmp_opt; /* use direct block chaining for direct jumps */
108 int mem_index; /* select memory access functions */
109 uint64_t flags; /* all execution flags */
110 struct TranslationBlock *tb;
111 int popl_esp_hack; /* for correct popl with esp base handling */
112 int rip_offset; /* only used in x86_64, but left for simplicity */
113 int cpuid_features;
114 int cpuid_ext_features;
115 int cpuid_ext2_features;
116 int cpuid_ext3_features;
117 } DisasContext;
118
119 static void gen_eob(DisasContext *s);
120 static void gen_jmp(DisasContext *s, target_ulong eip);
121 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
122
123 /* i386 arith/logic operations */
124 enum {
125 OP_ADDL,
126 OP_ORL,
127 OP_ADCL,
128 OP_SBBL,
129 OP_ANDL,
130 OP_SUBL,
131 OP_XORL,
132 OP_CMPL,
133 };
134
135 /* i386 shift ops */
136 enum {
137 OP_ROL,
138 OP_ROR,
139 OP_RCL,
140 OP_RCR,
141 OP_SHL,
142 OP_SHR,
143 OP_SHL1, /* undocumented */
144 OP_SAR = 7,
145 };
146
147 enum {
148 JCC_O,
149 JCC_B,
150 JCC_Z,
151 JCC_BE,
152 JCC_S,
153 JCC_P,
154 JCC_L,
155 JCC_LE,
156 };
157
158 /* operand size */
159 enum {
160 OT_BYTE = 0,
161 OT_WORD,
162 OT_LONG,
163 OT_QUAD,
164 };
165
166 enum {
167 /* I386 int registers */
168 OR_EAX, /* MUST be even numbered */
169 OR_ECX,
170 OR_EDX,
171 OR_EBX,
172 OR_ESP,
173 OR_EBP,
174 OR_ESI,
175 OR_EDI,
176
177 OR_TMP0 = 16, /* temporary operand register */
178 OR_TMP1,
179 OR_A0, /* temporary register used when doing address evaluation */
180 };
181
182 static inline void gen_op_movl_T0_0(void)
183 {
184 tcg_gen_movi_tl(cpu_T[0], 0);
185 }
186
187 static inline void gen_op_movl_T0_im(int32_t val)
188 {
189 tcg_gen_movi_tl(cpu_T[0], val);
190 }
191
192 static inline void gen_op_movl_T0_imu(uint32_t val)
193 {
194 tcg_gen_movi_tl(cpu_T[0], val);
195 }
196
197 static inline void gen_op_movl_T1_im(int32_t val)
198 {
199 tcg_gen_movi_tl(cpu_T[1], val);
200 }
201
202 static inline void gen_op_movl_T1_imu(uint32_t val)
203 {
204 tcg_gen_movi_tl(cpu_T[1], val);
205 }
206
207 static inline void gen_op_movl_A0_im(uint32_t val)
208 {
209 tcg_gen_movi_tl(cpu_A0, val);
210 }
211
212 #ifdef TARGET_X86_64
213 static inline void gen_op_movq_A0_im(int64_t val)
214 {
215 tcg_gen_movi_tl(cpu_A0, val);
216 }
217 #endif
218
219 static inline void gen_movtl_T0_im(target_ulong val)
220 {
221 tcg_gen_movi_tl(cpu_T[0], val);
222 }
223
224 static inline void gen_movtl_T1_im(target_ulong val)
225 {
226 tcg_gen_movi_tl(cpu_T[1], val);
227 }
228
229 static inline void gen_op_andl_T0_ffff(void)
230 {
231 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
232 }
233
234 static inline void gen_op_andl_T0_im(uint32_t val)
235 {
236 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
237 }
238
239 static inline void gen_op_movl_T0_T1(void)
240 {
241 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
242 }
243
244 static inline void gen_op_andl_A0_ffff(void)
245 {
246 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
247 }
248
249 #ifdef TARGET_X86_64
250
251 #define NB_OP_SIZES 4
252
253 #else /* !TARGET_X86_64 */
254
255 #define NB_OP_SIZES 3
256
257 #endif /* !TARGET_X86_64 */
258
259 #if defined(HOST_WORDS_BIGENDIAN)
260 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
261 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
262 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
263 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
264 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
265 #else
266 #define REG_B_OFFSET 0
267 #define REG_H_OFFSET 1
268 #define REG_W_OFFSET 0
269 #define REG_L_OFFSET 0
270 #define REG_LH_OFFSET 4
271 #endif
272
273 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
274 {
275 TCGv tmp;
276
277 switch(ot) {
278 case OT_BYTE:
279 tmp = tcg_temp_new();
280 tcg_gen_ext8u_tl(tmp, t0);
281 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
282 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
283 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
284 } else {
285 tcg_gen_shli_tl(tmp, tmp, 8);
286 tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
287 tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp);
288 }
289 tcg_temp_free(tmp);
290 break;
291 case OT_WORD:
292 tmp = tcg_temp_new();
293 tcg_gen_ext16u_tl(tmp, t0);
294 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
295 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
296 tcg_temp_free(tmp);
297 break;
298 default: /* XXX this shouldn't be reached; abort? */
299 case OT_LONG:
300 /* For x86_64, this sets the higher half of register to zero.
301 For i386, this is equivalent to a mov. */
302 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
303 break;
304 #ifdef TARGET_X86_64
305 case OT_QUAD:
306 tcg_gen_mov_tl(cpu_regs[reg], t0);
307 break;
308 #endif
309 }
310 }
311
312 static inline void gen_op_mov_reg_T0(int ot, int reg)
313 {
314 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
315 }
316
317 static inline void gen_op_mov_reg_T1(int ot, int reg)
318 {
319 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
320 }
321
322 static inline void gen_op_mov_reg_A0(int size, int reg)
323 {
324 TCGv tmp;
325
326 switch(size) {
327 case 0:
328 tmp = tcg_temp_new();
329 tcg_gen_ext16u_tl(tmp, cpu_A0);
330 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
331 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
332 tcg_temp_free(tmp);
333 break;
334 default: /* XXX this shouldn't be reached; abort? */
335 case 1:
336 /* For x86_64, this sets the higher half of register to zero.
337 For i386, this is equivalent to a mov. */
338 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
339 break;
340 #ifdef TARGET_X86_64
341 case 2:
342 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
343 break;
344 #endif
345 }
346 }
347
348 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
349 {
350 switch(ot) {
351 case OT_BYTE:
352 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
353 goto std_case;
354 } else {
355 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
356 tcg_gen_ext8u_tl(t0, t0);
357 }
358 break;
359 default:
360 std_case:
361 tcg_gen_mov_tl(t0, cpu_regs[reg]);
362 break;
363 }
364 }
365
366 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
367 {
368 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
369 }
370
371 static inline void gen_op_movl_A0_reg(int reg)
372 {
373 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
374 }
375
376 static inline void gen_op_addl_A0_im(int32_t val)
377 {
378 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
379 #ifdef TARGET_X86_64
380 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
381 #endif
382 }
383
384 #ifdef TARGET_X86_64
385 static inline void gen_op_addq_A0_im(int64_t val)
386 {
387 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
388 }
389 #endif
390
391 static void gen_add_A0_im(DisasContext *s, int val)
392 {
393 #ifdef TARGET_X86_64
394 if (CODE64(s))
395 gen_op_addq_A0_im(val);
396 else
397 #endif
398 gen_op_addl_A0_im(val);
399 }
400
401 static inline void gen_op_addl_T0_T1(void)
402 {
403 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
404 }
405
406 static inline void gen_op_jmp_T0(void)
407 {
408 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
409 }
410
411 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
412 {
413 switch(size) {
414 case 0:
415 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
416 tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
417 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
418 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
419 break;
420 case 1:
421 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
422 /* For x86_64, this sets the higher half of register to zero.
423 For i386, this is equivalent to a nop. */
424 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
425 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
426 break;
427 #ifdef TARGET_X86_64
428 case 2:
429 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
430 break;
431 #endif
432 }
433 }
434
435 static inline void gen_op_add_reg_T0(int size, int reg)
436 {
437 switch(size) {
438 case 0:
439 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
440 tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
441 tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
442 tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
443 break;
444 case 1:
445 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
446 /* For x86_64, this sets the higher half of register to zero.
447 For i386, this is equivalent to a nop. */
448 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
449 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
450 break;
451 #ifdef TARGET_X86_64
452 case 2:
453 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
454 break;
455 #endif
456 }
457 }
458
459 static inline void gen_op_set_cc_op(int32_t val)
460 {
461 tcg_gen_movi_i32(cpu_cc_op, val);
462 }
463
464 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
465 {
466 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
467 if (shift != 0)
468 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
469 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
470 /* For x86_64, this sets the higher half of register to zero.
471 For i386, this is equivalent to a nop. */
472 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
473 }
474
475 static inline void gen_op_movl_A0_seg(int reg)
476 {
477 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
478 }
479
480 static inline void gen_op_addl_A0_seg(int reg)
481 {
482 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
483 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
484 #ifdef TARGET_X86_64
485 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
486 #endif
487 }
488
489 #ifdef TARGET_X86_64
490 static inline void gen_op_movq_A0_seg(int reg)
491 {
492 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
493 }
494
495 static inline void gen_op_addq_A0_seg(int reg)
496 {
497 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
498 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
499 }
500
501 static inline void gen_op_movq_A0_reg(int reg)
502 {
503 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
504 }
505
506 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
507 {
508 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
509 if (shift != 0)
510 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
511 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
512 }
513 #endif
514
515 static inline void gen_op_lds_T0_A0(int idx)
516 {
517 int mem_index = (idx >> 2) - 1;
518 switch(idx & 3) {
519 case 0:
520 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
521 break;
522 case 1:
523 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
524 break;
525 default:
526 case 2:
527 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
528 break;
529 }
530 }
531
532 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
533 {
534 int mem_index = (idx >> 2) - 1;
535 switch(idx & 3) {
536 case 0:
537 tcg_gen_qemu_ld8u(t0, a0, mem_index);
538 break;
539 case 1:
540 tcg_gen_qemu_ld16u(t0, a0, mem_index);
541 break;
542 case 2:
543 tcg_gen_qemu_ld32u(t0, a0, mem_index);
544 break;
545 default:
546 case 3:
547 /* Should never happen on 32-bit targets. */
548 #ifdef TARGET_X86_64
549 tcg_gen_qemu_ld64(t0, a0, mem_index);
550 #endif
551 break;
552 }
553 }
554
555 /* XXX: always use ldu or lds */
556 static inline void gen_op_ld_T0_A0(int idx)
557 {
558 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
559 }
560
561 static inline void gen_op_ldu_T0_A0(int idx)
562 {
563 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
564 }
565
566 static inline void gen_op_ld_T1_A0(int idx)
567 {
568 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
569 }
570
571 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
572 {
573 int mem_index = (idx >> 2) - 1;
574 switch(idx & 3) {
575 case 0:
576 tcg_gen_qemu_st8(t0, a0, mem_index);
577 break;
578 case 1:
579 tcg_gen_qemu_st16(t0, a0, mem_index);
580 break;
581 case 2:
582 tcg_gen_qemu_st32(t0, a0, mem_index);
583 break;
584 default:
585 case 3:
586 /* Should never happen on 32-bit targets. */
587 #ifdef TARGET_X86_64
588 tcg_gen_qemu_st64(t0, a0, mem_index);
589 #endif
590 break;
591 }
592 }
593
594 static inline void gen_op_st_T0_A0(int idx)
595 {
596 gen_op_st_v(idx, cpu_T[0], cpu_A0);
597 }
598
599 static inline void gen_op_st_T1_A0(int idx)
600 {
601 gen_op_st_v(idx, cpu_T[1], cpu_A0);
602 }
603
604 static inline void gen_jmp_im(target_ulong pc)
605 {
606 tcg_gen_movi_tl(cpu_tmp0, pc);
607 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
608 }
609
610 static inline void gen_string_movl_A0_ESI(DisasContext *s)
611 {
612 int override;
613
614 override = s->override;
615 #ifdef TARGET_X86_64
616 if (s->aflag == 2) {
617 if (override >= 0) {
618 gen_op_movq_A0_seg(override);
619 gen_op_addq_A0_reg_sN(0, R_ESI);
620 } else {
621 gen_op_movq_A0_reg(R_ESI);
622 }
623 } else
624 #endif
625 if (s->aflag) {
626 /* 32 bit address */
627 if (s->addseg && override < 0)
628 override = R_DS;
629 if (override >= 0) {
630 gen_op_movl_A0_seg(override);
631 gen_op_addl_A0_reg_sN(0, R_ESI);
632 } else {
633 gen_op_movl_A0_reg(R_ESI);
634 }
635 } else {
636 /* 16 address, always override */
637 if (override < 0)
638 override = R_DS;
639 gen_op_movl_A0_reg(R_ESI);
640 gen_op_andl_A0_ffff();
641 gen_op_addl_A0_seg(override);
642 }
643 }
644
645 static inline void gen_string_movl_A0_EDI(DisasContext *s)
646 {
647 #ifdef TARGET_X86_64
648 if (s->aflag == 2) {
649 gen_op_movq_A0_reg(R_EDI);
650 } else
651 #endif
652 if (s->aflag) {
653 if (s->addseg) {
654 gen_op_movl_A0_seg(R_ES);
655 gen_op_addl_A0_reg_sN(0, R_EDI);
656 } else {
657 gen_op_movl_A0_reg(R_EDI);
658 }
659 } else {
660 gen_op_movl_A0_reg(R_EDI);
661 gen_op_andl_A0_ffff();
662 gen_op_addl_A0_seg(R_ES);
663 }
664 }
665
666 static inline void gen_op_movl_T0_Dshift(int ot)
667 {
668 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
669 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
670 };
671
672 static void gen_extu(int ot, TCGv reg)
673 {
674 switch(ot) {
675 case OT_BYTE:
676 tcg_gen_ext8u_tl(reg, reg);
677 break;
678 case OT_WORD:
679 tcg_gen_ext16u_tl(reg, reg);
680 break;
681 case OT_LONG:
682 tcg_gen_ext32u_tl(reg, reg);
683 break;
684 default:
685 break;
686 }
687 }
688
689 static void gen_exts(int ot, TCGv reg)
690 {
691 switch(ot) {
692 case OT_BYTE:
693 tcg_gen_ext8s_tl(reg, reg);
694 break;
695 case OT_WORD:
696 tcg_gen_ext16s_tl(reg, reg);
697 break;
698 case OT_LONG:
699 tcg_gen_ext32s_tl(reg, reg);
700 break;
701 default:
702 break;
703 }
704 }
705
706 static inline void gen_op_jnz_ecx(int size, int label1)
707 {
708 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
709 gen_extu(size + 1, cpu_tmp0);
710 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
711 }
712
713 static inline void gen_op_jz_ecx(int size, int label1)
714 {
715 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
716 gen_extu(size + 1, cpu_tmp0);
717 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
718 }
719
720 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
721 {
722 switch (ot) {
723 case 0: gen_helper_inb(v, n); break;
724 case 1: gen_helper_inw(v, n); break;
725 case 2: gen_helper_inl(v, n); break;
726 }
727
728 }
729
730 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
731 {
732 switch (ot) {
733 case 0: gen_helper_outb(v, n); break;
734 case 1: gen_helper_outw(v, n); break;
735 case 2: gen_helper_outl(v, n); break;
736 }
737
738 }
739
740 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
741 uint32_t svm_flags)
742 {
743 int state_saved;
744 target_ulong next_eip;
745
746 state_saved = 0;
747 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
748 if (s->cc_op != CC_OP_DYNAMIC)
749 gen_op_set_cc_op(s->cc_op);
750 gen_jmp_im(cur_eip);
751 state_saved = 1;
752 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
753 switch (ot) {
754 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
755 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
756 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
757 }
758 }
759 if(s->flags & HF_SVMI_MASK) {
760 if (!state_saved) {
761 if (s->cc_op != CC_OP_DYNAMIC)
762 gen_op_set_cc_op(s->cc_op);
763 gen_jmp_im(cur_eip);
764 state_saved = 1;
765 }
766 svm_flags |= (1 << (4 + ot));
767 next_eip = s->pc - s->cs_base;
768 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
769 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
770 tcg_const_i32(next_eip - cur_eip));
771 }
772 }
773
774 static inline void gen_movs(DisasContext *s, int ot)
775 {
776 gen_string_movl_A0_ESI(s);
777 gen_op_ld_T0_A0(ot + s->mem_index);
778 gen_string_movl_A0_EDI(s);
779 gen_op_st_T0_A0(ot + s->mem_index);
780 gen_op_movl_T0_Dshift(ot);
781 gen_op_add_reg_T0(s->aflag, R_ESI);
782 gen_op_add_reg_T0(s->aflag, R_EDI);
783 }
784
785 static inline void gen_update_cc_op(DisasContext *s)
786 {
787 if (s->cc_op != CC_OP_DYNAMIC) {
788 gen_op_set_cc_op(s->cc_op);
789 s->cc_op = CC_OP_DYNAMIC;
790 }
791 }
792
793 static void gen_op_update1_cc(void)
794 {
795 tcg_gen_discard_tl(cpu_cc_src);
796 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
797 }
798
799 static void gen_op_update2_cc(void)
800 {
801 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
802 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
803 }
804
805 static inline void gen_op_cmpl_T0_T1_cc(void)
806 {
807 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
808 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
809 }
810
811 static inline void gen_op_testl_T0_T1_cc(void)
812 {
813 tcg_gen_discard_tl(cpu_cc_src);
814 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
815 }
816
817 static void gen_op_update_neg_cc(void)
818 {
819 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
820 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
821 }
822
823 /* compute eflags.C to reg */
824 static void gen_compute_eflags_c(TCGv reg)
825 {
826 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
827 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
828 }
829
830 /* compute all eflags to cc_src */
831 static void gen_compute_eflags(TCGv reg)
832 {
833 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
834 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
835 }
836
837 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
838 {
839 if (s->cc_op != CC_OP_DYNAMIC)
840 gen_op_set_cc_op(s->cc_op);
841 switch(jcc_op) {
842 case JCC_O:
843 gen_compute_eflags(cpu_T[0]);
844 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
845 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
846 break;
847 case JCC_B:
848 gen_compute_eflags_c(cpu_T[0]);
849 break;
850 case JCC_Z:
851 gen_compute_eflags(cpu_T[0]);
852 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
853 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
854 break;
855 case JCC_BE:
856 gen_compute_eflags(cpu_tmp0);
857 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
858 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
859 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
860 break;
861 case JCC_S:
862 gen_compute_eflags(cpu_T[0]);
863 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
864 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865 break;
866 case JCC_P:
867 gen_compute_eflags(cpu_T[0]);
868 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
869 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
870 break;
871 case JCC_L:
872 gen_compute_eflags(cpu_tmp0);
873 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
874 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
875 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
876 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
877 break;
878 default:
879 case JCC_LE:
880 gen_compute_eflags(cpu_tmp0);
881 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
882 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
883 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
884 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
885 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
886 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
887 break;
888 }
889 }
890
891 /* return true if setcc_slow is not needed (WARNING: must be kept in
892 sync with gen_jcc1) */
893 static int is_fast_jcc_case(DisasContext *s, int b)
894 {
895 int jcc_op;
896 jcc_op = (b >> 1) & 7;
897 switch(s->cc_op) {
898 /* we optimize the cmp/jcc case */
899 case CC_OP_SUBB:
900 case CC_OP_SUBW:
901 case CC_OP_SUBL:
902 case CC_OP_SUBQ:
903 if (jcc_op == JCC_O || jcc_op == JCC_P)
904 goto slow_jcc;
905 break;
906
907 /* some jumps are easy to compute */
908 case CC_OP_ADDB:
909 case CC_OP_ADDW:
910 case CC_OP_ADDL:
911 case CC_OP_ADDQ:
912
913 case CC_OP_LOGICB:
914 case CC_OP_LOGICW:
915 case CC_OP_LOGICL:
916 case CC_OP_LOGICQ:
917
918 case CC_OP_INCB:
919 case CC_OP_INCW:
920 case CC_OP_INCL:
921 case CC_OP_INCQ:
922
923 case CC_OP_DECB:
924 case CC_OP_DECW:
925 case CC_OP_DECL:
926 case CC_OP_DECQ:
927
928 case CC_OP_SHLB:
929 case CC_OP_SHLW:
930 case CC_OP_SHLL:
931 case CC_OP_SHLQ:
932 if (jcc_op != JCC_Z && jcc_op != JCC_S)
933 goto slow_jcc;
934 break;
935 default:
936 slow_jcc:
937 return 0;
938 }
939 return 1;
940 }
941
942 /* generate a conditional jump to label 'l1' according to jump opcode
943 value 'b'. In the fast case, T0 is guaranted not to be used. */
944 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
945 {
946 int inv, jcc_op, size, cond;
947 TCGv t0;
948
949 inv = b & 1;
950 jcc_op = (b >> 1) & 7;
951
952 switch(cc_op) {
953 /* we optimize the cmp/jcc case */
954 case CC_OP_SUBB:
955 case CC_OP_SUBW:
956 case CC_OP_SUBL:
957 case CC_OP_SUBQ:
958
959 size = cc_op - CC_OP_SUBB;
960 switch(jcc_op) {
961 case JCC_Z:
962 fast_jcc_z:
963 switch(size) {
964 case 0:
965 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
966 t0 = cpu_tmp0;
967 break;
968 case 1:
969 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
970 t0 = cpu_tmp0;
971 break;
972 #ifdef TARGET_X86_64
973 case 2:
974 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
975 t0 = cpu_tmp0;
976 break;
977 #endif
978 default:
979 t0 = cpu_cc_dst;
980 break;
981 }
982 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
983 break;
984 case JCC_S:
985 fast_jcc_s:
986 switch(size) {
987 case 0:
988 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
989 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
990 0, l1);
991 break;
992 case 1:
993 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
994 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
995 0, l1);
996 break;
997 #ifdef TARGET_X86_64
998 case 2:
999 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1000 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1001 0, l1);
1002 break;
1003 #endif
1004 default:
1005 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1006 0, l1);
1007 break;
1008 }
1009 break;
1010
1011 case JCC_B:
1012 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1013 goto fast_jcc_b;
1014 case JCC_BE:
1015 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1016 fast_jcc_b:
1017 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1018 switch(size) {
1019 case 0:
1020 t0 = cpu_tmp0;
1021 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1022 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1023 break;
1024 case 1:
1025 t0 = cpu_tmp0;
1026 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1027 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1028 break;
1029 #ifdef TARGET_X86_64
1030 case 2:
1031 t0 = cpu_tmp0;
1032 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1033 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1034 break;
1035 #endif
1036 default:
1037 t0 = cpu_cc_src;
1038 break;
1039 }
1040 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1041 break;
1042
1043 case JCC_L:
1044 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1045 goto fast_jcc_l;
1046 case JCC_LE:
1047 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1048 fast_jcc_l:
1049 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1050 switch(size) {
1051 case 0:
1052 t0 = cpu_tmp0;
1053 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1054 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1055 break;
1056 case 1:
1057 t0 = cpu_tmp0;
1058 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1059 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1060 break;
1061 #ifdef TARGET_X86_64
1062 case 2:
1063 t0 = cpu_tmp0;
1064 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1065 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1066 break;
1067 #endif
1068 default:
1069 t0 = cpu_cc_src;
1070 break;
1071 }
1072 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1073 break;
1074
1075 default:
1076 goto slow_jcc;
1077 }
1078 break;
1079
1080 /* some jumps are easy to compute */
1081 case CC_OP_ADDB:
1082 case CC_OP_ADDW:
1083 case CC_OP_ADDL:
1084 case CC_OP_ADDQ:
1085
1086 case CC_OP_ADCB:
1087 case CC_OP_ADCW:
1088 case CC_OP_ADCL:
1089 case CC_OP_ADCQ:
1090
1091 case CC_OP_SBBB:
1092 case CC_OP_SBBW:
1093 case CC_OP_SBBL:
1094 case CC_OP_SBBQ:
1095
1096 case CC_OP_LOGICB:
1097 case CC_OP_LOGICW:
1098 case CC_OP_LOGICL:
1099 case CC_OP_LOGICQ:
1100
1101 case CC_OP_INCB:
1102 case CC_OP_INCW:
1103 case CC_OP_INCL:
1104 case CC_OP_INCQ:
1105
1106 case CC_OP_DECB:
1107 case CC_OP_DECW:
1108 case CC_OP_DECL:
1109 case CC_OP_DECQ:
1110
1111 case CC_OP_SHLB:
1112 case CC_OP_SHLW:
1113 case CC_OP_SHLL:
1114 case CC_OP_SHLQ:
1115
1116 case CC_OP_SARB:
1117 case CC_OP_SARW:
1118 case CC_OP_SARL:
1119 case CC_OP_SARQ:
1120 switch(jcc_op) {
1121 case JCC_Z:
1122 size = (cc_op - CC_OP_ADDB) & 3;
1123 goto fast_jcc_z;
1124 case JCC_S:
1125 size = (cc_op - CC_OP_ADDB) & 3;
1126 goto fast_jcc_s;
1127 default:
1128 goto slow_jcc;
1129 }
1130 break;
1131 default:
1132 slow_jcc:
1133 gen_setcc_slow_T0(s, jcc_op);
1134 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1135 cpu_T[0], 0, l1);
1136 break;
1137 }
1138 }
1139
1140 /* XXX: does not work with gdbstub "ice" single step - not a
1141 serious problem */
1142 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1143 {
1144 int l1, l2;
1145
1146 l1 = gen_new_label();
1147 l2 = gen_new_label();
1148 gen_op_jnz_ecx(s->aflag, l1);
1149 gen_set_label(l2);
1150 gen_jmp_tb(s, next_eip, 1);
1151 gen_set_label(l1);
1152 return l2;
1153 }
1154
1155 static inline void gen_stos(DisasContext *s, int ot)
1156 {
1157 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1158 gen_string_movl_A0_EDI(s);
1159 gen_op_st_T0_A0(ot + s->mem_index);
1160 gen_op_movl_T0_Dshift(ot);
1161 gen_op_add_reg_T0(s->aflag, R_EDI);
1162 }
1163
1164 static inline void gen_lods(DisasContext *s, int ot)
1165 {
1166 gen_string_movl_A0_ESI(s);
1167 gen_op_ld_T0_A0(ot + s->mem_index);
1168 gen_op_mov_reg_T0(ot, R_EAX);
1169 gen_op_movl_T0_Dshift(ot);
1170 gen_op_add_reg_T0(s->aflag, R_ESI);
1171 }
1172
1173 static inline void gen_scas(DisasContext *s, int ot)
1174 {
1175 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1176 gen_string_movl_A0_EDI(s);
1177 gen_op_ld_T1_A0(ot + s->mem_index);
1178 gen_op_cmpl_T0_T1_cc();
1179 gen_op_movl_T0_Dshift(ot);
1180 gen_op_add_reg_T0(s->aflag, R_EDI);
1181 }
1182
1183 static inline void gen_cmps(DisasContext *s, int ot)
1184 {
1185 gen_string_movl_A0_ESI(s);
1186 gen_op_ld_T0_A0(ot + s->mem_index);
1187 gen_string_movl_A0_EDI(s);
1188 gen_op_ld_T1_A0(ot + s->mem_index);
1189 gen_op_cmpl_T0_T1_cc();
1190 gen_op_movl_T0_Dshift(ot);
1191 gen_op_add_reg_T0(s->aflag, R_ESI);
1192 gen_op_add_reg_T0(s->aflag, R_EDI);
1193 }
1194
1195 static inline void gen_ins(DisasContext *s, int ot)
1196 {
1197 if (use_icount)
1198 gen_io_start();
1199 gen_string_movl_A0_EDI(s);
1200 /* Note: we must do this dummy write first to be restartable in
1201 case of page fault. */
1202 gen_op_movl_T0_0();
1203 gen_op_st_T0_A0(ot + s->mem_index);
1204 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1205 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1206 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1207 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1208 gen_op_st_T0_A0(ot + s->mem_index);
1209 gen_op_movl_T0_Dshift(ot);
1210 gen_op_add_reg_T0(s->aflag, R_EDI);
1211 if (use_icount)
1212 gen_io_end();
1213 }
1214
1215 static inline void gen_outs(DisasContext *s, int ot)
1216 {
1217 if (use_icount)
1218 gen_io_start();
1219 gen_string_movl_A0_ESI(s);
1220 gen_op_ld_T0_A0(ot + s->mem_index);
1221
1222 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1223 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1224 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1225 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1226 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1227
1228 gen_op_movl_T0_Dshift(ot);
1229 gen_op_add_reg_T0(s->aflag, R_ESI);
1230 if (use_icount)
1231 gen_io_end();
1232 }
1233
1234 /* same method as Valgrind : we generate jumps to current or next
1235 instruction */
1236 #define GEN_REPZ(op) \
1237 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1238 target_ulong cur_eip, target_ulong next_eip) \
1239 { \
1240 int l2;\
1241 gen_update_cc_op(s); \
1242 l2 = gen_jz_ecx_string(s, next_eip); \
1243 gen_ ## op(s, ot); \
1244 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1245 /* a loop would cause two single step exceptions if ECX = 1 \
1246 before rep string_insn */ \
1247 if (!s->jmp_opt) \
1248 gen_op_jz_ecx(s->aflag, l2); \
1249 gen_jmp(s, cur_eip); \
1250 }
1251
1252 #define GEN_REPZ2(op) \
1253 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1254 target_ulong cur_eip, \
1255 target_ulong next_eip, \
1256 int nz) \
1257 { \
1258 int l2;\
1259 gen_update_cc_op(s); \
1260 l2 = gen_jz_ecx_string(s, next_eip); \
1261 gen_ ## op(s, ot); \
1262 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1263 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1264 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1265 if (!s->jmp_opt) \
1266 gen_op_jz_ecx(s->aflag, l2); \
1267 gen_jmp(s, cur_eip); \
1268 }
1269
1270 GEN_REPZ(movs)
1271 GEN_REPZ(stos)
1272 GEN_REPZ(lods)
1273 GEN_REPZ(ins)
1274 GEN_REPZ(outs)
1275 GEN_REPZ2(scas)
1276 GEN_REPZ2(cmps)
1277
1278 static void gen_helper_fp_arith_ST0_FT0(int op)
1279 {
1280 switch (op) {
1281 case 0: gen_helper_fadd_ST0_FT0(); break;
1282 case 1: gen_helper_fmul_ST0_FT0(); break;
1283 case 2: gen_helper_fcom_ST0_FT0(); break;
1284 case 3: gen_helper_fcom_ST0_FT0(); break;
1285 case 4: gen_helper_fsub_ST0_FT0(); break;
1286 case 5: gen_helper_fsubr_ST0_FT0(); break;
1287 case 6: gen_helper_fdiv_ST0_FT0(); break;
1288 case 7: gen_helper_fdivr_ST0_FT0(); break;
1289 }
1290 }
1291
1292 /* NOTE the exception in "r" op ordering */
1293 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1294 {
1295 TCGv_i32 tmp = tcg_const_i32(opreg);
1296 switch (op) {
1297 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1298 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1299 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1300 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1301 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1302 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1303 }
1304 }
1305
1306 /* if d == OR_TMP0, it means memory operand (address in A0) */
1307 static void gen_op(DisasContext *s1, int op, int ot, int d)
1308 {
1309 if (d != OR_TMP0) {
1310 gen_op_mov_TN_reg(ot, 0, d);
1311 } else {
1312 gen_op_ld_T0_A0(ot + s1->mem_index);
1313 }
1314 switch(op) {
1315 case OP_ADCL:
1316 if (s1->cc_op != CC_OP_DYNAMIC)
1317 gen_op_set_cc_op(s1->cc_op);
1318 gen_compute_eflags_c(cpu_tmp4);
1319 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1320 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1321 if (d != OR_TMP0)
1322 gen_op_mov_reg_T0(ot, d);
1323 else
1324 gen_op_st_T0_A0(ot + s1->mem_index);
1325 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1326 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1327 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1328 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1329 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1330 s1->cc_op = CC_OP_DYNAMIC;
1331 break;
1332 case OP_SBBL:
1333 if (s1->cc_op != CC_OP_DYNAMIC)
1334 gen_op_set_cc_op(s1->cc_op);
1335 gen_compute_eflags_c(cpu_tmp4);
1336 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1337 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1338 if (d != OR_TMP0)
1339 gen_op_mov_reg_T0(ot, d);
1340 else
1341 gen_op_st_T0_A0(ot + s1->mem_index);
1342 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1343 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1344 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1345 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1346 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1347 s1->cc_op = CC_OP_DYNAMIC;
1348 break;
1349 case OP_ADDL:
1350 gen_op_addl_T0_T1();
1351 if (d != OR_TMP0)
1352 gen_op_mov_reg_T0(ot, d);
1353 else
1354 gen_op_st_T0_A0(ot + s1->mem_index);
1355 gen_op_update2_cc();
1356 s1->cc_op = CC_OP_ADDB + ot;
1357 break;
1358 case OP_SUBL:
1359 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1360 if (d != OR_TMP0)
1361 gen_op_mov_reg_T0(ot, d);
1362 else
1363 gen_op_st_T0_A0(ot + s1->mem_index);
1364 gen_op_update2_cc();
1365 s1->cc_op = CC_OP_SUBB + ot;
1366 break;
1367 default:
1368 case OP_ANDL:
1369 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1370 if (d != OR_TMP0)
1371 gen_op_mov_reg_T0(ot, d);
1372 else
1373 gen_op_st_T0_A0(ot + s1->mem_index);
1374 gen_op_update1_cc();
1375 s1->cc_op = CC_OP_LOGICB + ot;
1376 break;
1377 case OP_ORL:
1378 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1379 if (d != OR_TMP0)
1380 gen_op_mov_reg_T0(ot, d);
1381 else
1382 gen_op_st_T0_A0(ot + s1->mem_index);
1383 gen_op_update1_cc();
1384 s1->cc_op = CC_OP_LOGICB + ot;
1385 break;
1386 case OP_XORL:
1387 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1388 if (d != OR_TMP0)
1389 gen_op_mov_reg_T0(ot, d);
1390 else
1391 gen_op_st_T0_A0(ot + s1->mem_index);
1392 gen_op_update1_cc();
1393 s1->cc_op = CC_OP_LOGICB + ot;
1394 break;
1395 case OP_CMPL:
1396 gen_op_cmpl_T0_T1_cc();
1397 s1->cc_op = CC_OP_SUBB + ot;
1398 break;
1399 }
1400 }
1401
1402 /* if d == OR_TMP0, it means memory operand (address in A0) */
1403 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1404 {
1405 if (d != OR_TMP0)
1406 gen_op_mov_TN_reg(ot, 0, d);
1407 else
1408 gen_op_ld_T0_A0(ot + s1->mem_index);
1409 if (s1->cc_op != CC_OP_DYNAMIC)
1410 gen_op_set_cc_op(s1->cc_op);
1411 if (c > 0) {
1412 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1413 s1->cc_op = CC_OP_INCB + ot;
1414 } else {
1415 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1416 s1->cc_op = CC_OP_DECB + ot;
1417 }
1418 if (d != OR_TMP0)
1419 gen_op_mov_reg_T0(ot, d);
1420 else
1421 gen_op_st_T0_A0(ot + s1->mem_index);
1422 gen_compute_eflags_c(cpu_cc_src);
1423 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1424 }
1425
1426 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1427 int is_right, int is_arith)
1428 {
1429 target_ulong mask;
1430 int shift_label;
1431 TCGv t0, t1;
1432
1433 if (ot == OT_QUAD)
1434 mask = 0x3f;
1435 else
1436 mask = 0x1f;
1437
1438 /* load */
1439 if (op1 == OR_TMP0)
1440 gen_op_ld_T0_A0(ot + s->mem_index);
1441 else
1442 gen_op_mov_TN_reg(ot, 0, op1);
1443
1444 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1445
1446 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1447
1448 if (is_right) {
1449 if (is_arith) {
1450 gen_exts(ot, cpu_T[0]);
1451 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1452 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1453 } else {
1454 gen_extu(ot, cpu_T[0]);
1455 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1456 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1457 }
1458 } else {
1459 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1460 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1461 }
1462
1463 /* store */
1464 if (op1 == OR_TMP0)
1465 gen_op_st_T0_A0(ot + s->mem_index);
1466 else
1467 gen_op_mov_reg_T0(ot, op1);
1468
1469 /* update eflags if non zero shift */
1470 if (s->cc_op != CC_OP_DYNAMIC)
1471 gen_op_set_cc_op(s->cc_op);
1472
1473 /* XXX: inefficient */
1474 t0 = tcg_temp_local_new();
1475 t1 = tcg_temp_local_new();
1476
1477 tcg_gen_mov_tl(t0, cpu_T[0]);
1478 tcg_gen_mov_tl(t1, cpu_T3);
1479
1480 shift_label = gen_new_label();
1481 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1482
1483 tcg_gen_mov_tl(cpu_cc_src, t1);
1484 tcg_gen_mov_tl(cpu_cc_dst, t0);
1485 if (is_right)
1486 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1487 else
1488 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1489
1490 gen_set_label(shift_label);
1491 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1492
1493 tcg_temp_free(t0);
1494 tcg_temp_free(t1);
1495 }
1496
1497 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1498 int is_right, int is_arith)
1499 {
1500 int mask;
1501
1502 if (ot == OT_QUAD)
1503 mask = 0x3f;
1504 else
1505 mask = 0x1f;
1506
1507 /* load */
1508 if (op1 == OR_TMP0)
1509 gen_op_ld_T0_A0(ot + s->mem_index);
1510 else
1511 gen_op_mov_TN_reg(ot, 0, op1);
1512
1513 op2 &= mask;
1514 if (op2 != 0) {
1515 if (is_right) {
1516 if (is_arith) {
1517 gen_exts(ot, cpu_T[0]);
1518 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1519 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1520 } else {
1521 gen_extu(ot, cpu_T[0]);
1522 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1523 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1524 }
1525 } else {
1526 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1527 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1528 }
1529 }
1530
1531 /* store */
1532 if (op1 == OR_TMP0)
1533 gen_op_st_T0_A0(ot + s->mem_index);
1534 else
1535 gen_op_mov_reg_T0(ot, op1);
1536
1537 /* update eflags if non zero shift */
1538 if (op2 != 0) {
1539 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1540 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1541 if (is_right)
1542 s->cc_op = CC_OP_SARB + ot;
1543 else
1544 s->cc_op = CC_OP_SHLB + ot;
1545 }
1546 }
1547
1548 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1549 {
1550 if (arg2 >= 0)
1551 tcg_gen_shli_tl(ret, arg1, arg2);
1552 else
1553 tcg_gen_shri_tl(ret, arg1, -arg2);
1554 }
1555
1556 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1557 int is_right)
1558 {
1559 target_ulong mask;
1560 int label1, label2, data_bits;
1561 TCGv t0, t1, t2, a0;
1562
1563 /* XXX: inefficient, but we must use local temps */
1564 t0 = tcg_temp_local_new();
1565 t1 = tcg_temp_local_new();
1566 t2 = tcg_temp_local_new();
1567 a0 = tcg_temp_local_new();
1568
1569 if (ot == OT_QUAD)
1570 mask = 0x3f;
1571 else
1572 mask = 0x1f;
1573
1574 /* load */
1575 if (op1 == OR_TMP0) {
1576 tcg_gen_mov_tl(a0, cpu_A0);
1577 gen_op_ld_v(ot + s->mem_index, t0, a0);
1578 } else {
1579 gen_op_mov_v_reg(ot, t0, op1);
1580 }
1581
1582 tcg_gen_mov_tl(t1, cpu_T[1]);
1583
1584 tcg_gen_andi_tl(t1, t1, mask);
1585
1586 /* Must test zero case to avoid using undefined behaviour in TCG
1587 shifts. */
1588 label1 = gen_new_label();
1589 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1590
1591 if (ot <= OT_WORD)
1592 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1593 else
1594 tcg_gen_mov_tl(cpu_tmp0, t1);
1595
1596 gen_extu(ot, t0);
1597 tcg_gen_mov_tl(t2, t0);
1598
1599 data_bits = 8 << ot;
1600 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1601 fix TCG definition) */
1602 if (is_right) {
1603 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1604 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1605 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1606 } else {
1607 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1608 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1609 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1610 }
1611 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1612
1613 gen_set_label(label1);
1614 /* store */
1615 if (op1 == OR_TMP0) {
1616 gen_op_st_v(ot + s->mem_index, t0, a0);
1617 } else {
1618 gen_op_mov_reg_v(ot, op1, t0);
1619 }
1620
1621 /* update eflags */
1622 if (s->cc_op != CC_OP_DYNAMIC)
1623 gen_op_set_cc_op(s->cc_op);
1624
1625 label2 = gen_new_label();
1626 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1627
1628 gen_compute_eflags(cpu_cc_src);
1629 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1630 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1631 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1632 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1633 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1634 if (is_right) {
1635 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1636 }
1637 tcg_gen_andi_tl(t0, t0, CC_C);
1638 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1639
1640 tcg_gen_discard_tl(cpu_cc_dst);
1641 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1642
1643 gen_set_label(label2);
1644 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1645
1646 tcg_temp_free(t0);
1647 tcg_temp_free(t1);
1648 tcg_temp_free(t2);
1649 tcg_temp_free(a0);
1650 }
1651
1652 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1653 int is_right)
1654 {
1655 int mask;
1656 int data_bits;
1657 TCGv t0, t1, a0;
1658
1659 /* XXX: inefficient, but we must use local temps */
1660 t0 = tcg_temp_local_new();
1661 t1 = tcg_temp_local_new();
1662 a0 = tcg_temp_local_new();
1663
1664 if (ot == OT_QUAD)
1665 mask = 0x3f;
1666 else
1667 mask = 0x1f;
1668
1669 /* load */
1670 if (op1 == OR_TMP0) {
1671 tcg_gen_mov_tl(a0, cpu_A0);
1672 gen_op_ld_v(ot + s->mem_index, t0, a0);
1673 } else {
1674 gen_op_mov_v_reg(ot, t0, op1);
1675 }
1676
1677 gen_extu(ot, t0);
1678 tcg_gen_mov_tl(t1, t0);
1679
1680 op2 &= mask;
1681 data_bits = 8 << ot;
1682 if (op2 != 0) {
1683 int shift = op2 & ((1 << (3 + ot)) - 1);
1684 if (is_right) {
1685 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1686 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1687 }
1688 else {
1689 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1690 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1691 }
1692 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1693 }
1694
1695 /* store */
1696 if (op1 == OR_TMP0) {
1697 gen_op_st_v(ot + s->mem_index, t0, a0);
1698 } else {
1699 gen_op_mov_reg_v(ot, op1, t0);
1700 }
1701
1702 if (op2 != 0) {
1703 /* update eflags */
1704 if (s->cc_op != CC_OP_DYNAMIC)
1705 gen_op_set_cc_op(s->cc_op);
1706
1707 gen_compute_eflags(cpu_cc_src);
1708 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1709 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1710 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1711 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1712 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1713 if (is_right) {
1714 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1715 }
1716 tcg_gen_andi_tl(t0, t0, CC_C);
1717 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1718
1719 tcg_gen_discard_tl(cpu_cc_dst);
1720 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1721 s->cc_op = CC_OP_EFLAGS;
1722 }
1723
1724 tcg_temp_free(t0);
1725 tcg_temp_free(t1);
1726 tcg_temp_free(a0);
1727 }
1728
1729 /* XXX: add faster immediate = 1 case */
1730 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1731 int is_right)
1732 {
1733 int label1;
1734
1735 if (s->cc_op != CC_OP_DYNAMIC)
1736 gen_op_set_cc_op(s->cc_op);
1737
1738 /* load */
1739 if (op1 == OR_TMP0)
1740 gen_op_ld_T0_A0(ot + s->mem_index);
1741 else
1742 gen_op_mov_TN_reg(ot, 0, op1);
1743
1744 if (is_right) {
1745 switch (ot) {
1746 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1747 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749 #ifdef TARGET_X86_64
1750 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1751 #endif
1752 }
1753 } else {
1754 switch (ot) {
1755 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1756 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1757 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1758 #ifdef TARGET_X86_64
1759 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1760 #endif
1761 }
1762 }
1763 /* store */
1764 if (op1 == OR_TMP0)
1765 gen_op_st_T0_A0(ot + s->mem_index);
1766 else
1767 gen_op_mov_reg_T0(ot, op1);
1768
1769 /* update eflags */
1770 label1 = gen_new_label();
1771 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1772
1773 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1774 tcg_gen_discard_tl(cpu_cc_dst);
1775 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1776
1777 gen_set_label(label1);
1778 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1779 }
1780
1781 /* XXX: add faster immediate case */
1782 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1783 int is_right)
1784 {
1785 int label1, label2, data_bits;
1786 target_ulong mask;
1787 TCGv t0, t1, t2, a0;
1788
1789 t0 = tcg_temp_local_new();
1790 t1 = tcg_temp_local_new();
1791 t2 = tcg_temp_local_new();
1792 a0 = tcg_temp_local_new();
1793
1794 if (ot == OT_QUAD)
1795 mask = 0x3f;
1796 else
1797 mask = 0x1f;
1798
1799 /* load */
1800 if (op1 == OR_TMP0) {
1801 tcg_gen_mov_tl(a0, cpu_A0);
1802 gen_op_ld_v(ot + s->mem_index, t0, a0);
1803 } else {
1804 gen_op_mov_v_reg(ot, t0, op1);
1805 }
1806
1807 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1808
1809 tcg_gen_mov_tl(t1, cpu_T[1]);
1810 tcg_gen_mov_tl(t2, cpu_T3);
1811
1812 /* Must test zero case to avoid using undefined behaviour in TCG
1813 shifts. */
1814 label1 = gen_new_label();
1815 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1816
1817 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1818 if (ot == OT_WORD) {
1819 /* Note: we implement the Intel behaviour for shift count > 16 */
1820 if (is_right) {
1821 tcg_gen_andi_tl(t0, t0, 0xffff);
1822 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1823 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1824 tcg_gen_ext32u_tl(t0, t0);
1825
1826 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1827
1828 /* only needed if count > 16, but a test would complicate */
1829 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1830 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1831
1832 tcg_gen_shr_tl(t0, t0, t2);
1833
1834 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1835 } else {
1836 /* XXX: not optimal */
1837 tcg_gen_andi_tl(t0, t0, 0xffff);
1838 tcg_gen_shli_tl(t1, t1, 16);
1839 tcg_gen_or_tl(t1, t1, t0);
1840 tcg_gen_ext32u_tl(t1, t1);
1841
1842 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1843 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1844 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1845 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1846
1847 tcg_gen_shl_tl(t0, t0, t2);
1848 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1849 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1850 tcg_gen_or_tl(t0, t0, t1);
1851 }
1852 } else {
1853 data_bits = 8 << ot;
1854 if (is_right) {
1855 if (ot == OT_LONG)
1856 tcg_gen_ext32u_tl(t0, t0);
1857
1858 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1859
1860 tcg_gen_shr_tl(t0, t0, t2);
1861 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1862 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1863 tcg_gen_or_tl(t0, t0, t1);
1864
1865 } else {
1866 if (ot == OT_LONG)
1867 tcg_gen_ext32u_tl(t1, t1);
1868
1869 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1870
1871 tcg_gen_shl_tl(t0, t0, t2);
1872 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1873 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1874 tcg_gen_or_tl(t0, t0, t1);
1875 }
1876 }
1877 tcg_gen_mov_tl(t1, cpu_tmp4);
1878
1879 gen_set_label(label1);
1880 /* store */
1881 if (op1 == OR_TMP0) {
1882 gen_op_st_v(ot + s->mem_index, t0, a0);
1883 } else {
1884 gen_op_mov_reg_v(ot, op1, t0);
1885 }
1886
1887 /* update eflags */
1888 if (s->cc_op != CC_OP_DYNAMIC)
1889 gen_op_set_cc_op(s->cc_op);
1890
1891 label2 = gen_new_label();
1892 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1893
1894 tcg_gen_mov_tl(cpu_cc_src, t1);
1895 tcg_gen_mov_tl(cpu_cc_dst, t0);
1896 if (is_right) {
1897 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1898 } else {
1899 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1900 }
1901 gen_set_label(label2);
1902 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1903
1904 tcg_temp_free(t0);
1905 tcg_temp_free(t1);
1906 tcg_temp_free(t2);
1907 tcg_temp_free(a0);
1908 }
1909
1910 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1911 {
1912 if (s != OR_TMP1)
1913 gen_op_mov_TN_reg(ot, 1, s);
1914 switch(op) {
1915 case OP_ROL:
1916 gen_rot_rm_T1(s1, ot, d, 0);
1917 break;
1918 case OP_ROR:
1919 gen_rot_rm_T1(s1, ot, d, 1);
1920 break;
1921 case OP_SHL:
1922 case OP_SHL1:
1923 gen_shift_rm_T1(s1, ot, d, 0, 0);
1924 break;
1925 case OP_SHR:
1926 gen_shift_rm_T1(s1, ot, d, 1, 0);
1927 break;
1928 case OP_SAR:
1929 gen_shift_rm_T1(s1, ot, d, 1, 1);
1930 break;
1931 case OP_RCL:
1932 gen_rotc_rm_T1(s1, ot, d, 0);
1933 break;
1934 case OP_RCR:
1935 gen_rotc_rm_T1(s1, ot, d, 1);
1936 break;
1937 }
1938 }
1939
1940 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1941 {
1942 switch(op) {
1943 case OP_ROL:
1944 gen_rot_rm_im(s1, ot, d, c, 0);
1945 break;
1946 case OP_ROR:
1947 gen_rot_rm_im(s1, ot, d, c, 1);
1948 break;
1949 case OP_SHL:
1950 case OP_SHL1:
1951 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1952 break;
1953 case OP_SHR:
1954 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1955 break;
1956 case OP_SAR:
1957 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1958 break;
1959 default:
1960 /* currently not optimized */
1961 gen_op_movl_T1_im(c);
1962 gen_shift(s1, op, ot, d, OR_TMP1);
1963 break;
1964 }
1965 }
1966
1967 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1968 {
1969 target_long disp;
1970 int havesib;
1971 int base;
1972 int index;
1973 int scale;
1974 int opreg;
1975 int mod, rm, code, override, must_add_seg;
1976
1977 override = s->override;
1978 must_add_seg = s->addseg;
1979 if (override >= 0)
1980 must_add_seg = 1;
1981 mod = (modrm >> 6) & 3;
1982 rm = modrm & 7;
1983
1984 if (s->aflag) {
1985
1986 havesib = 0;
1987 base = rm;
1988 index = 0;
1989 scale = 0;
1990
1991 if (base == 4) {
1992 havesib = 1;
1993 code = ldub_code(s->pc++);
1994 scale = (code >> 6) & 3;
1995 index = ((code >> 3) & 7) | REX_X(s);
1996 base = (code & 7);
1997 }
1998 base |= REX_B(s);
1999
2000 switch (mod) {
2001 case 0:
2002 if ((base & 7) == 5) {
2003 base = -1;
2004 disp = (int32_t)ldl_code(s->pc);
2005 s->pc += 4;
2006 if (CODE64(s) && !havesib) {
2007 disp += s->pc + s->rip_offset;
2008 }
2009 } else {
2010 disp = 0;
2011 }
2012 break;
2013 case 1:
2014 disp = (int8_t)ldub_code(s->pc++);
2015 break;
2016 default:
2017 case 2:
2018 disp = ldl_code(s->pc);
2019 s->pc += 4;
2020 break;
2021 }
2022
2023 if (base >= 0) {
2024 /* for correct popl handling with esp */
2025 if (base == 4 && s->popl_esp_hack)
2026 disp += s->popl_esp_hack;
2027 #ifdef TARGET_X86_64
2028 if (s->aflag == 2) {
2029 gen_op_movq_A0_reg(base);
2030 if (disp != 0) {
2031 gen_op_addq_A0_im(disp);
2032 }
2033 } else
2034 #endif
2035 {
2036 gen_op_movl_A0_reg(base);
2037 if (disp != 0)
2038 gen_op_addl_A0_im(disp);
2039 }
2040 } else {
2041 #ifdef TARGET_X86_64
2042 if (s->aflag == 2) {
2043 gen_op_movq_A0_im(disp);
2044 } else
2045 #endif
2046 {
2047 gen_op_movl_A0_im(disp);
2048 }
2049 }
2050 /* XXX: index == 4 is always invalid */
2051 if (havesib && (index != 4 || scale != 0)) {
2052 #ifdef TARGET_X86_64
2053 if (s->aflag == 2) {
2054 gen_op_addq_A0_reg_sN(scale, index);
2055 } else
2056 #endif
2057 {
2058 gen_op_addl_A0_reg_sN(scale, index);
2059 }
2060 }
2061 if (must_add_seg) {
2062 if (override < 0) {
2063 if (base == R_EBP || base == R_ESP)
2064 override = R_SS;
2065 else
2066 override = R_DS;
2067 }
2068 #ifdef TARGET_X86_64
2069 if (s->aflag == 2) {
2070 gen_op_addq_A0_seg(override);
2071 } else
2072 #endif
2073 {
2074 gen_op_addl_A0_seg(override);
2075 }
2076 }
2077 } else {
2078 switch (mod) {
2079 case 0:
2080 if (rm == 6) {
2081 disp = lduw_code(s->pc);
2082 s->pc += 2;
2083 gen_op_movl_A0_im(disp);
2084 rm = 0; /* avoid SS override */
2085 goto no_rm;
2086 } else {
2087 disp = 0;
2088 }
2089 break;
2090 case 1:
2091 disp = (int8_t)ldub_code(s->pc++);
2092 break;
2093 default:
2094 case 2:
2095 disp = lduw_code(s->pc);
2096 s->pc += 2;
2097 break;
2098 }
2099 switch(rm) {
2100 case 0:
2101 gen_op_movl_A0_reg(R_EBX);
2102 gen_op_addl_A0_reg_sN(0, R_ESI);
2103 break;
2104 case 1:
2105 gen_op_movl_A0_reg(R_EBX);
2106 gen_op_addl_A0_reg_sN(0, R_EDI);
2107 break;
2108 case 2:
2109 gen_op_movl_A0_reg(R_EBP);
2110 gen_op_addl_A0_reg_sN(0, R_ESI);
2111 break;
2112 case 3:
2113 gen_op_movl_A0_reg(R_EBP);
2114 gen_op_addl_A0_reg_sN(0, R_EDI);
2115 break;
2116 case 4:
2117 gen_op_movl_A0_reg(R_ESI);
2118 break;
2119 case 5:
2120 gen_op_movl_A0_reg(R_EDI);
2121 break;
2122 case 6:
2123 gen_op_movl_A0_reg(R_EBP);
2124 break;
2125 default:
2126 case 7:
2127 gen_op_movl_A0_reg(R_EBX);
2128 break;
2129 }
2130 if (disp != 0)
2131 gen_op_addl_A0_im(disp);
2132 gen_op_andl_A0_ffff();
2133 no_rm:
2134 if (must_add_seg) {
2135 if (override < 0) {
2136 if (rm == 2 || rm == 3 || rm == 6)
2137 override = R_SS;
2138 else
2139 override = R_DS;
2140 }
2141 gen_op_addl_A0_seg(override);
2142 }
2143 }
2144
2145 opreg = OR_A0;
2146 disp = 0;
2147 *reg_ptr = opreg;
2148 *offset_ptr = disp;
2149 }
2150
2151 static void gen_nop_modrm(DisasContext *s, int modrm)
2152 {
2153 int mod, rm, base, code;
2154
2155 mod = (modrm >> 6) & 3;
2156 if (mod == 3)
2157 return;
2158 rm = modrm & 7;
2159
2160 if (s->aflag) {
2161
2162 base = rm;
2163
2164 if (base == 4) {
2165 code = ldub_code(s->pc++);
2166 base = (code & 7);
2167 }
2168
2169 switch (mod) {
2170 case 0:
2171 if (base == 5) {
2172 s->pc += 4;
2173 }
2174 break;
2175 case 1:
2176 s->pc++;
2177 break;
2178 default:
2179 case 2:
2180 s->pc += 4;
2181 break;
2182 }
2183 } else {
2184 switch (mod) {
2185 case 0:
2186 if (rm == 6) {
2187 s->pc += 2;
2188 }
2189 break;
2190 case 1:
2191 s->pc++;
2192 break;
2193 default:
2194 case 2:
2195 s->pc += 2;
2196 break;
2197 }
2198 }
2199 }
2200
2201 /* used for LEA and MOV AX, mem */
2202 static void gen_add_A0_ds_seg(DisasContext *s)
2203 {
2204 int override, must_add_seg;
2205 must_add_seg = s->addseg;
2206 override = R_DS;
2207 if (s->override >= 0) {
2208 override = s->override;
2209 must_add_seg = 1;
2210 }
2211 if (must_add_seg) {
2212 #ifdef TARGET_X86_64
2213 if (CODE64(s)) {
2214 gen_op_addq_A0_seg(override);
2215 } else
2216 #endif
2217 {
2218 gen_op_addl_A0_seg(override);
2219 }
2220 }
2221 }
2222
2223 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2224 OR_TMP0 */
2225 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2226 {
2227 int mod, rm, opreg, disp;
2228
2229 mod = (modrm >> 6) & 3;
2230 rm = (modrm & 7) | REX_B(s);
2231 if (mod == 3) {
2232 if (is_store) {
2233 if (reg != OR_TMP0)
2234 gen_op_mov_TN_reg(ot, 0, reg);
2235 gen_op_mov_reg_T0(ot, rm);
2236 } else {
2237 gen_op_mov_TN_reg(ot, 0, rm);
2238 if (reg != OR_TMP0)
2239 gen_op_mov_reg_T0(ot, reg);
2240 }
2241 } else {
2242 gen_lea_modrm(s, modrm, &opreg, &disp);
2243 if (is_store) {
2244 if (reg != OR_TMP0)
2245 gen_op_mov_TN_reg(ot, 0, reg);
2246 gen_op_st_T0_A0(ot + s->mem_index);
2247 } else {
2248 gen_op_ld_T0_A0(ot + s->mem_index);
2249 if (reg != OR_TMP0)
2250 gen_op_mov_reg_T0(ot, reg);
2251 }
2252 }
2253 }
2254
2255 static inline uint32_t insn_get(DisasContext *s, int ot)
2256 {
2257 uint32_t ret;
2258
2259 switch(ot) {
2260 case OT_BYTE:
2261 ret = ldub_code(s->pc);
2262 s->pc++;
2263 break;
2264 case OT_WORD:
2265 ret = lduw_code(s->pc);
2266 s->pc += 2;
2267 break;
2268 default:
2269 case OT_LONG:
2270 ret = ldl_code(s->pc);
2271 s->pc += 4;
2272 break;
2273 }
2274 return ret;
2275 }
2276
2277 static inline int insn_const_size(unsigned int ot)
2278 {
2279 if (ot <= OT_LONG)
2280 return 1 << ot;
2281 else
2282 return 4;
2283 }
2284
2285 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2286 {
2287 TranslationBlock *tb;
2288 target_ulong pc;
2289
2290 pc = s->cs_base + eip;
2291 tb = s->tb;
2292 /* NOTE: we handle the case where the TB spans two pages here */
2293 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2294 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2295 /* jump to same page: we can use a direct jump */
2296 tcg_gen_goto_tb(tb_num);
2297 gen_jmp_im(eip);
2298 tcg_gen_exit_tb((long)tb + tb_num);
2299 } else {
2300 /* jump to another page: currently not optimized */
2301 gen_jmp_im(eip);
2302 gen_eob(s);
2303 }
2304 }
2305
2306 static inline void gen_jcc(DisasContext *s, int b,
2307 target_ulong val, target_ulong next_eip)
2308 {
2309 int l1, l2, cc_op;
2310
2311 cc_op = s->cc_op;
2312 if (s->cc_op != CC_OP_DYNAMIC) {
2313 gen_op_set_cc_op(s->cc_op);
2314 s->cc_op = CC_OP_DYNAMIC;
2315 }
2316 if (s->jmp_opt) {
2317 l1 = gen_new_label();
2318 gen_jcc1(s, cc_op, b, l1);
2319
2320 gen_goto_tb(s, 0, next_eip);
2321
2322 gen_set_label(l1);
2323 gen_goto_tb(s, 1, val);
2324 s->is_jmp = 3;
2325 } else {
2326
2327 l1 = gen_new_label();
2328 l2 = gen_new_label();
2329 gen_jcc1(s, cc_op, b, l1);
2330
2331 gen_jmp_im(next_eip);
2332 tcg_gen_br(l2);
2333
2334 gen_set_label(l1);
2335 gen_jmp_im(val);
2336 gen_set_label(l2);
2337 gen_eob(s);
2338 }
2339 }
2340
2341 static void gen_setcc(DisasContext *s, int b)
2342 {
2343 int inv, jcc_op, l1;
2344 TCGv t0;
2345
2346 if (is_fast_jcc_case(s, b)) {
2347 /* nominal case: we use a jump */
2348 /* XXX: make it faster by adding new instructions in TCG */
2349 t0 = tcg_temp_local_new();
2350 tcg_gen_movi_tl(t0, 0);
2351 l1 = gen_new_label();
2352 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2353 tcg_gen_movi_tl(t0, 1);
2354 gen_set_label(l1);
2355 tcg_gen_mov_tl(cpu_T[0], t0);
2356 tcg_temp_free(t0);
2357 } else {
2358 /* slow case: it is more efficient not to generate a jump,
2359 although it is questionnable whether this optimization is
2360 worth to */
2361 inv = b & 1;
2362 jcc_op = (b >> 1) & 7;
2363 gen_setcc_slow_T0(s, jcc_op);
2364 if (inv) {
2365 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2366 }
2367 }
2368 }
2369
2370 static inline void gen_op_movl_T0_seg(int seg_reg)
2371 {
2372 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2373 offsetof(CPUX86State,segs[seg_reg].selector));
2374 }
2375
2376 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2377 {
2378 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2379 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2380 offsetof(CPUX86State,segs[seg_reg].selector));
2381 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2382 tcg_gen_st_tl(cpu_T[0], cpu_env,
2383 offsetof(CPUX86State,segs[seg_reg].base));
2384 }
2385
2386 /* move T0 to seg_reg and compute if the CPU state may change. Never
2387 call this function with seg_reg == R_CS */
2388 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2389 {
2390 if (s->pe && !s->vm86) {
2391 /* XXX: optimize by finding processor state dynamically */
2392 if (s->cc_op != CC_OP_DYNAMIC)
2393 gen_op_set_cc_op(s->cc_op);
2394 gen_jmp_im(cur_eip);
2395 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2396 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2397 /* abort translation because the addseg value may change or
2398 because ss32 may change. For R_SS, translation must always
2399 stop as a special handling must be done to disable hardware
2400 interrupts for the next instruction */
2401 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2402 s->is_jmp = 3;
2403 } else {
2404 gen_op_movl_seg_T0_vm(seg_reg);
2405 if (seg_reg == R_SS)
2406 s->is_jmp = 3;
2407 }
2408 }
2409
2410 static inline int svm_is_rep(int prefixes)
2411 {
2412 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2413 }
2414
2415 static inline void
2416 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2417 uint32_t type, uint64_t param)
2418 {
2419 /* no SVM activated; fast case */
2420 if (likely(!(s->flags & HF_SVMI_MASK)))
2421 return;
2422 if (s->cc_op != CC_OP_DYNAMIC)
2423 gen_op_set_cc_op(s->cc_op);
2424 gen_jmp_im(pc_start - s->cs_base);
2425 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2426 tcg_const_i64(param));
2427 }
2428
2429 static inline void
2430 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2431 {
2432 gen_svm_check_intercept_param(s, pc_start, type, 0);
2433 }
2434
2435 static inline void gen_stack_update(DisasContext *s, int addend)
2436 {
2437 #ifdef TARGET_X86_64
2438 if (CODE64(s)) {
2439 gen_op_add_reg_im(2, R_ESP, addend);
2440 } else
2441 #endif
2442 if (s->ss32) {
2443 gen_op_add_reg_im(1, R_ESP, addend);
2444 } else {
2445 gen_op_add_reg_im(0, R_ESP, addend);
2446 }
2447 }
2448
2449 /* generate a push. It depends on ss32, addseg and dflag */
2450 static void gen_push_T0(DisasContext *s)
2451 {
2452 #ifdef TARGET_X86_64
2453 if (CODE64(s)) {
2454 gen_op_movq_A0_reg(R_ESP);
2455 if (s->dflag) {
2456 gen_op_addq_A0_im(-8);
2457 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2458 } else {
2459 gen_op_addq_A0_im(-2);
2460 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2461 }
2462 gen_op_mov_reg_A0(2, R_ESP);
2463 } else
2464 #endif
2465 {
2466 gen_op_movl_A0_reg(R_ESP);
2467 if (!s->dflag)
2468 gen_op_addl_A0_im(-2);
2469 else
2470 gen_op_addl_A0_im(-4);
2471 if (s->ss32) {
2472 if (s->addseg) {
2473 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2474 gen_op_addl_A0_seg(R_SS);
2475 }
2476 } else {
2477 gen_op_andl_A0_ffff();
2478 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2479 gen_op_addl_A0_seg(R_SS);
2480 }
2481 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2482 if (s->ss32 && !s->addseg)
2483 gen_op_mov_reg_A0(1, R_ESP);
2484 else
2485 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2486 }
2487 }
2488
2489 /* generate a push. It depends on ss32, addseg and dflag */
2490 /* slower version for T1, only used for call Ev */
2491 static void gen_push_T1(DisasContext *s)
2492 {
2493 #ifdef TARGET_X86_64
2494 if (CODE64(s)) {
2495 gen_op_movq_A0_reg(R_ESP);
2496 if (s->dflag) {
2497 gen_op_addq_A0_im(-8);
2498 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2499 } else {
2500 gen_op_addq_A0_im(-2);
2501 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2502 }
2503 gen_op_mov_reg_A0(2, R_ESP);
2504 } else
2505 #endif
2506 {
2507 gen_op_movl_A0_reg(R_ESP);
2508 if (!s->dflag)
2509 gen_op_addl_A0_im(-2);
2510 else
2511 gen_op_addl_A0_im(-4);
2512 if (s->ss32) {
2513 if (s->addseg) {
2514 gen_op_addl_A0_seg(R_SS);
2515 }
2516 } else {
2517 gen_op_andl_A0_ffff();
2518 gen_op_addl_A0_seg(R_SS);
2519 }
2520 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2521
2522 if (s->ss32 && !s->addseg)
2523 gen_op_mov_reg_A0(1, R_ESP);
2524 else
2525 gen_stack_update(s, (-2) << s->dflag);
2526 }
2527 }
2528
2529 /* two step pop is necessary for precise exceptions */
2530 static void gen_pop_T0(DisasContext *s)
2531 {
2532 #ifdef TARGET_X86_64
2533 if (CODE64(s)) {
2534 gen_op_movq_A0_reg(R_ESP);
2535 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2536 } else
2537 #endif
2538 {
2539 gen_op_movl_A0_reg(R_ESP);
2540 if (s->ss32) {
2541 if (s->addseg)
2542 gen_op_addl_A0_seg(R_SS);
2543 } else {
2544 gen_op_andl_A0_ffff();
2545 gen_op_addl_A0_seg(R_SS);
2546 }
2547 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2548 }
2549 }
2550
2551 static void gen_pop_update(DisasContext *s)
2552 {
2553 #ifdef TARGET_X86_64
2554 if (CODE64(s) && s->dflag) {
2555 gen_stack_update(s, 8);
2556 } else
2557 #endif
2558 {
2559 gen_stack_update(s, 2 << s->dflag);
2560 }
2561 }
2562
2563 static void gen_stack_A0(DisasContext *s)
2564 {
2565 gen_op_movl_A0_reg(R_ESP);
2566 if (!s->ss32)
2567 gen_op_andl_A0_ffff();
2568 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2569 if (s->addseg)
2570 gen_op_addl_A0_seg(R_SS);
2571 }
2572
2573 /* NOTE: wrap around in 16 bit not fully handled */
2574 static void gen_pusha(DisasContext *s)
2575 {
2576 int i;
2577 gen_op_movl_A0_reg(R_ESP);
2578 gen_op_addl_A0_im(-16 << s->dflag);
2579 if (!s->ss32)
2580 gen_op_andl_A0_ffff();
2581 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2582 if (s->addseg)
2583 gen_op_addl_A0_seg(R_SS);
2584 for(i = 0;i < 8; i++) {
2585 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2586 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2587 gen_op_addl_A0_im(2 << s->dflag);
2588 }
2589 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2590 }
2591
2592 /* NOTE: wrap around in 16 bit not fully handled */
2593 static void gen_popa(DisasContext *s)
2594 {
2595 int i;
2596 gen_op_movl_A0_reg(R_ESP);
2597 if (!s->ss32)
2598 gen_op_andl_A0_ffff();
2599 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2600 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2601 if (s->addseg)
2602 gen_op_addl_A0_seg(R_SS);
2603 for(i = 0;i < 8; i++) {
2604 /* ESP is not reloaded */
2605 if (i != 3) {
2606 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2607 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2608 }
2609 gen_op_addl_A0_im(2 << s->dflag);
2610 }
2611 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2612 }
2613
2614 static void gen_enter(DisasContext *s, int esp_addend, int level)
2615 {
2616 int ot, opsize;
2617
2618 level &= 0x1f;
2619 #ifdef TARGET_X86_64
2620 if (CODE64(s)) {
2621 ot = s->dflag ? OT_QUAD : OT_WORD;
2622 opsize = 1 << ot;
2623
2624 gen_op_movl_A0_reg(R_ESP);
2625 gen_op_addq_A0_im(-opsize);
2626 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2627
2628 /* push bp */
2629 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2630 gen_op_st_T0_A0(ot + s->mem_index);
2631 if (level) {
2632 /* XXX: must save state */
2633 gen_helper_enter64_level(tcg_const_i32(level),
2634 tcg_const_i32((ot == OT_QUAD)),
2635 cpu_T[1]);
2636 }
2637 gen_op_mov_reg_T1(ot, R_EBP);
2638 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2639 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2640 } else
2641 #endif
2642 {
2643 ot = s->dflag + OT_WORD;
2644 opsize = 2 << s->dflag;
2645
2646 gen_op_movl_A0_reg(R_ESP);
2647 gen_op_addl_A0_im(-opsize);
2648 if (!s->ss32)
2649 gen_op_andl_A0_ffff();
2650 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2651 if (s->addseg)
2652 gen_op_addl_A0_seg(R_SS);
2653 /* push bp */
2654 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2655 gen_op_st_T0_A0(ot + s->mem_index);
2656 if (level) {
2657 /* XXX: must save state */
2658 gen_helper_enter_level(tcg_const_i32(level),
2659 tcg_const_i32(s->dflag),
2660 cpu_T[1]);
2661 }
2662 gen_op_mov_reg_T1(ot, R_EBP);
2663 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2664 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2665 }
2666 }
2667
2668 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2669 {
2670 if (s->cc_op != CC_OP_DYNAMIC)
2671 gen_op_set_cc_op(s->cc_op);
2672 gen_jmp_im(cur_eip);
2673 gen_helper_raise_exception(tcg_const_i32(trapno));
2674 s->is_jmp = 3;
2675 }
2676
2677 /* an interrupt is different from an exception because of the
2678 privilege checks */
2679 static void gen_interrupt(DisasContext *s, int intno,
2680 target_ulong cur_eip, target_ulong next_eip)
2681 {
2682 if (s->cc_op != CC_OP_DYNAMIC)
2683 gen_op_set_cc_op(s->cc_op);
2684 gen_jmp_im(cur_eip);
2685 gen_helper_raise_interrupt(tcg_const_i32(intno),
2686 tcg_const_i32(next_eip - cur_eip));
2687 s->is_jmp = 3;
2688 }
2689
2690 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2691 {
2692 if (s->cc_op != CC_OP_DYNAMIC)
2693 gen_op_set_cc_op(s->cc_op);
2694 gen_jmp_im(cur_eip);
2695 gen_helper_debug();
2696 s->is_jmp = 3;
2697 }
2698
2699 /* generate a generic end of block. Trace exception is also generated
2700 if needed */
2701 static void gen_eob(DisasContext *s)
2702 {
2703 if (s->cc_op != CC_OP_DYNAMIC)
2704 gen_op_set_cc_op(s->cc_op);
2705 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2706 gen_helper_reset_inhibit_irq();
2707 }
2708 if (s->tb->flags & HF_RF_MASK) {
2709 gen_helper_reset_rf();
2710 }
2711 if (s->singlestep_enabled) {
2712 gen_helper_debug();
2713 } else if (s->tf) {
2714 gen_helper_single_step();
2715 } else {
2716 tcg_gen_exit_tb(0);
2717 }
2718 s->is_jmp = 3;
2719 }
2720
2721 /* generate a jump to eip. No segment change must happen before as a
2722 direct call to the next block may occur */
2723 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2724 {
2725 if (s->jmp_opt) {
2726 if (s->cc_op != CC_OP_DYNAMIC) {
2727 gen_op_set_cc_op(s->cc_op);
2728 s->cc_op = CC_OP_DYNAMIC;
2729 }
2730 gen_goto_tb(s, tb_num, eip);
2731 s->is_jmp = 3;
2732 } else {
2733 gen_jmp_im(eip);
2734 gen_eob(s);
2735 }
2736 }
2737
2738 static void gen_jmp(DisasContext *s, target_ulong eip)
2739 {
2740 gen_jmp_tb(s, eip, 0);
2741 }
2742
2743 static inline void gen_ldq_env_A0(int idx, int offset)
2744 {
2745 int mem_index = (idx >> 2) - 1;
2746 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2747 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2748 }
2749
2750 static inline void gen_stq_env_A0(int idx, int offset)
2751 {
2752 int mem_index = (idx >> 2) - 1;
2753 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2754 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2755 }
2756
2757 static inline void gen_ldo_env_A0(int idx, int offset)
2758 {
2759 int mem_index = (idx >> 2) - 1;
2760 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2761 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2762 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2763 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2764 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2765 }
2766
2767 static inline void gen_sto_env_A0(int idx, int offset)
2768 {
2769 int mem_index = (idx >> 2) - 1;
2770 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2771 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2772 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2773 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2774 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2775 }
2776
2777 static inline void gen_op_movo(int d_offset, int s_offset)
2778 {
2779 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2780 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2781 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2782 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2783 }
2784
2785 static inline void gen_op_movq(int d_offset, int s_offset)
2786 {
2787 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2788 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2789 }
2790
2791 static inline void gen_op_movl(int d_offset, int s_offset)
2792 {
2793 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2794 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2795 }
2796
2797 static inline void gen_op_movq_env_0(int d_offset)
2798 {
2799 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2800 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2801 }
2802
2803 #define SSE_SPECIAL ((void *)1)
2804 #define SSE_DUMMY ((void *)2)
2805
2806 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2807 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2808 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2809
2810 static void *sse_op_table1[256][4] = {
2811 /* 3DNow! extensions */
2812 [0x0e] = { SSE_DUMMY }, /* femms */
2813 [0x0f] = { SSE_DUMMY }, /* pf... */
2814 /* pure SSE operations */
2815 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2816 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2817 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2818 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2819 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2820 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2821 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2822 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2823
2824 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2825 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2826 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2827 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2828 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2829 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2830 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2831 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2832 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2833 [0x51] = SSE_FOP(sqrt),
2834 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2835 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2836 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2837 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2838 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2839 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2840 [0x58] = SSE_FOP(add),
2841 [0x59] = SSE_FOP(mul),
2842 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2843 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2844 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2845 [0x5c] = SSE_FOP(sub),
2846 [0x5d] = SSE_FOP(min),
2847 [0x5e] = SSE_FOP(div),
2848 [0x5f] = SSE_FOP(max),
2849
2850 [0xc2] = SSE_FOP(cmpeq),
2851 [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2852
2853 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2854 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2855
2856 /* MMX ops and their SSE extensions */
2857 [0x60] = MMX_OP2(punpcklbw),
2858 [0x61] = MMX_OP2(punpcklwd),
2859 [0x62] = MMX_OP2(punpckldq),
2860 [0x63] = MMX_OP2(packsswb),
2861 [0x64] = MMX_OP2(pcmpgtb),
2862 [0x65] = MMX_OP2(pcmpgtw),
2863 [0x66] = MMX_OP2(pcmpgtl),
2864 [0x67] = MMX_OP2(packuswb),
2865 [0x68] = MMX_OP2(punpckhbw),
2866 [0x69] = MMX_OP2(punpckhwd),
2867 [0x6a] = MMX_OP2(punpckhdq),
2868 [0x6b] = MMX_OP2(packssdw),
2869 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2870 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2871 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2872 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2873 [0x70] = { gen_helper_pshufw_mmx,
2874 gen_helper_pshufd_xmm,
2875 gen_helper_pshufhw_xmm,
2876 gen_helper_pshuflw_xmm },
2877 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2878 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2879 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2880 [0x74] = MMX_OP2(pcmpeqb),
2881 [0x75] = MMX_OP2(pcmpeqw),
2882 [0x76] = MMX_OP2(pcmpeql),
2883 [0x77] = { SSE_DUMMY }, /* emms */
2884 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2885 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2886 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2887 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2888 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2889 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2890 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2891 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2892 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2893 [0xd1] = MMX_OP2(psrlw),
2894 [0xd2] = MMX_OP2(psrld),
2895 [0xd3] = MMX_OP2(psrlq),
2896 [0xd4] = MMX_OP2(paddq),
2897 [0xd5] = MMX_OP2(pmullw),
2898 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2899 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2900 [0xd8] = MMX_OP2(psubusb),
2901 [0xd9] = MMX_OP2(psubusw),
2902 [0xda] = MMX_OP2(pminub),
2903 [0xdb] = MMX_OP2(pand),
2904 [0xdc] = MMX_OP2(paddusb),
2905 [0xdd] = MMX_OP2(paddusw),
2906 [0xde] = MMX_OP2(pmaxub),
2907 [0xdf] = MMX_OP2(pandn),
2908 [0xe0] = MMX_OP2(pavgb),
2909 [0xe1] = MMX_OP2(psraw),
2910 [0xe2] = MMX_OP2(psrad),
2911 [0xe3] = MMX_OP2(pavgw),
2912 [0xe4] = MMX_OP2(pmulhuw),
2913 [0xe5] = MMX_OP2(pmulhw),
2914 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2915 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2916 [0xe8] = MMX_OP2(psubsb),
2917 [0xe9] = MMX_OP2(psubsw),
2918 [0xea] = MMX_OP2(pminsw),
2919 [0xeb] = MMX_OP2(por),
2920 [0xec] = MMX_OP2(paddsb),
2921 [0xed] = MMX_OP2(paddsw),
2922 [0xee] = MMX_OP2(pmaxsw),
2923 [0xef] = MMX_OP2(pxor),
2924 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2925 [0xf1] = MMX_OP2(psllw),
2926 [0xf2] = MMX_OP2(pslld),
2927 [0xf3] = MMX_OP2(psllq),
2928 [0xf4] = MMX_OP2(pmuludq),
2929 [0xf5] = MMX_OP2(pmaddwd),
2930 [0xf6] = MMX_OP2(psadbw),
2931 [0xf7] = MMX_OP2(maskmov),
2932 [0xf8] = MMX_OP2(psubb),
2933 [0xf9] = MMX_OP2(psubw),
2934 [0xfa] = MMX_OP2(psubl),
2935 [0xfb] = MMX_OP2(psubq),
2936 [0xfc] = MMX_OP2(paddb),
2937 [0xfd] = MMX_OP2(paddw),
2938 [0xfe] = MMX_OP2(paddl),
2939 };
2940
2941 static void *sse_op_table2[3 * 8][2] = {
2942 [0 + 2] = MMX_OP2(psrlw),
2943 [0 + 4] = MMX_OP2(psraw),
2944 [0 + 6] = MMX_OP2(psllw),
2945 [8 + 2] = MMX_OP2(psrld),
2946 [8 + 4] = MMX_OP2(psrad),
2947 [8 + 6] = MMX_OP2(pslld),
2948 [16 + 2] = MMX_OP2(psrlq),
2949 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2950 [16 + 6] = MMX_OP2(psllq),
2951 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2952 };
2953
2954 static void *sse_op_table3[4 * 3] = {
2955 gen_helper_cvtsi2ss,
2956 gen_helper_cvtsi2sd,
2957 X86_64_ONLY(gen_helper_cvtsq2ss),
2958 X86_64_ONLY(gen_helper_cvtsq2sd),
2959
2960 gen_helper_cvttss2si,
2961 gen_helper_cvttsd2si,
2962 X86_64_ONLY(gen_helper_cvttss2sq),
2963 X86_64_ONLY(gen_helper_cvttsd2sq),
2964
2965 gen_helper_cvtss2si,
2966 gen_helper_cvtsd2si,
2967 X86_64_ONLY(gen_helper_cvtss2sq),
2968 X86_64_ONLY(gen_helper_cvtsd2sq),
2969 };
2970
2971 static void *sse_op_table4[8][4] = {
2972 SSE_FOP(cmpeq),
2973 SSE_FOP(cmplt),
2974 SSE_FOP(cmple),
2975 SSE_FOP(cmpunord),
2976 SSE_FOP(cmpneq),
2977 SSE_FOP(cmpnlt),
2978 SSE_FOP(cmpnle),
2979 SSE_FOP(cmpord),
2980 };
2981
2982 static void *sse_op_table5[256] = {
2983 [0x0c] = gen_helper_pi2fw,
2984 [0x0d] = gen_helper_pi2fd,
2985 [0x1c] = gen_helper_pf2iw,
2986 [0x1d] = gen_helper_pf2id,
2987 [0x8a] = gen_helper_pfnacc,
2988 [0x8e] = gen_helper_pfpnacc,
2989 [0x90] = gen_helper_pfcmpge,
2990 [0x94] = gen_helper_pfmin,
2991 [0x96] = gen_helper_pfrcp,
2992 [0x97] = gen_helper_pfrsqrt,
2993 [0x9a] = gen_helper_pfsub,
2994 [0x9e] = gen_helper_pfadd,
2995 [0xa0] = gen_helper_pfcmpgt,
2996 [0xa4] = gen_helper_pfmax,
2997 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2998 [0xa7] = gen_helper_movq, /* pfrsqit1 */
2999 [0xaa] = gen_helper_pfsubr,
3000 [0xae] = gen_helper_pfacc,
3001 [0xb0] = gen_helper_pfcmpeq,
3002 [0xb4] = gen_helper_pfmul,
3003 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3004 [0xb7] = gen_helper_pmulhrw_mmx,
3005 [0xbb] = gen_helper_pswapd,
3006 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3007 };
3008
3009 struct sse_op_helper_s {
3010 void *op[2]; uint32_t ext_mask;
3011 };
3012 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3013 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3014 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3015 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3016 static struct sse_op_helper_s sse_op_table6[256] = {
3017 [0x00] = SSSE3_OP(pshufb),
3018 [0x01] = SSSE3_OP(phaddw),
3019 [0x02] = SSSE3_OP(phaddd),
3020 [0x03] = SSSE3_OP(phaddsw),
3021 [0x04] = SSSE3_OP(pmaddubsw),
3022 [0x05] = SSSE3_OP(phsubw),
3023 [0x06] = SSSE3_OP(phsubd),
3024 [0x07] = SSSE3_OP(phsubsw),
3025 [0x08] = SSSE3_OP(psignb),
3026 [0x09] = SSSE3_OP(psignw),
3027 [0x0a] = SSSE3_OP(psignd),
3028 [0x0b] = SSSE3_OP(pmulhrsw),
3029 [0x10] = SSE41_OP(pblendvb),
3030 [0x14] = SSE41_OP(blendvps),
3031 [0x15] = SSE41_OP(blendvpd),
3032 [0x17] = SSE41_OP(ptest),
3033 [0x1c] = SSSE3_OP(pabsb),
3034 [0x1d] = SSSE3_OP(pabsw),
3035 [0x1e] = SSSE3_OP(pabsd),
3036 [0x20] = SSE41_OP(pmovsxbw),
3037 [0x21] = SSE41_OP(pmovsxbd),
3038 [0x22] = SSE41_OP(pmovsxbq),
3039 [0x23] = SSE41_OP(pmovsxwd),
3040 [0x24] = SSE41_OP(pmovsxwq),
3041 [0x25] = SSE41_OP(pmovsxdq),
3042 [0x28] = SSE41_OP(pmuldq),
3043 [0x29] = SSE41_OP(pcmpeqq),
3044 [0x2a] = SSE41_SPECIAL, /* movntqda */
3045 [0x2b] = SSE41_OP(packusdw),
3046 [0x30] = SSE41_OP(pmovzxbw),
3047 [0x31] = SSE41_OP(pmovzxbd),
3048 [0x32] = SSE41_OP(pmovzxbq),
3049 [0x33] = SSE41_OP(pmovzxwd),
3050 [0x34] = SSE41_OP(pmovzxwq),
3051 [0x35] = SSE41_OP(pmovzxdq),
3052 [0x37] = SSE42_OP(pcmpgtq),
3053 [0x38] = SSE41_OP(pminsb),
3054 [0x39] = SSE41_OP(pminsd),
3055 [0x3a] = SSE41_OP(pminuw),
3056 [0x3b] = SSE41_OP(pminud),
3057 [0x3c] = SSE41_OP(pmaxsb),
3058 [0x3d] = SSE41_OP(pmaxsd),
3059 [0x3e] = SSE41_OP(pmaxuw),
3060 [0x3f] = SSE41_OP(pmaxud),
3061 [0x40] = SSE41_OP(pmulld),
3062 [0x41] = SSE41_OP(phminposuw),
3063 };
3064
3065 static struct sse_op_helper_s sse_op_table7[256] = {
3066 [0x08] = SSE41_OP(roundps),
3067 [0x09] = SSE41_OP(roundpd),
3068 [0x0a] = SSE41_OP(roundss),
3069 [0x0b] = SSE41_OP(roundsd),
3070 [0x0c] = SSE41_OP(blendps),
3071 [0x0d] = SSE41_OP(blendpd),
3072 [0x0e] = SSE41_OP(pblendw),
3073 [0x0f] = SSSE3_OP(palignr),
3074 [0x14] = SSE41_SPECIAL, /* pextrb */
3075 [0x15] = SSE41_SPECIAL, /* pextrw */
3076 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3077 [0x17] = SSE41_SPECIAL, /* extractps */
3078 [0x20] = SSE41_SPECIAL, /* pinsrb */
3079 [0x21] = SSE41_SPECIAL, /* insertps */
3080 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3081 [0x40] = SSE41_OP(dpps),
3082 [0x41] = SSE41_OP(dppd),
3083 [0x42] = SSE41_OP(mpsadbw),
3084 [0x60] = SSE42_OP(pcmpestrm),
3085 [0x61] = SSE42_OP(pcmpestri),
3086 [0x62] = SSE42_OP(pcmpistrm),
3087 [0x63] = SSE42_OP(pcmpistri),
3088 };
3089
3090 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3091 {
3092 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3093 int modrm, mod, rm, reg, reg_addr, offset_addr;
3094 void *sse_op2;
3095
3096 b &= 0xff;
3097 if (s->prefix & PREFIX_DATA)
3098 b1 = 1;
3099 else if (s->prefix & PREFIX_REPZ)
3100 b1 = 2;
3101 else if (s->prefix & PREFIX_REPNZ)
3102 b1 = 3;
3103 else
3104 b1 = 0;
3105 sse_op2 = sse_op_table1[b][b1];
3106 if (!sse_op2)
3107 goto illegal_op;
3108 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3109 is_xmm = 1;
3110 } else {
3111 if (b1 == 0) {
3112 /* MMX case */
3113 is_xmm = 0;
3114 } else {
3115 is_xmm = 1;
3116 }
3117 }
3118 /* simple MMX/SSE operation */
3119 if (s->flags & HF_TS_MASK) {
3120 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3121 return;
3122 }
3123 if (s->flags & HF_EM_MASK) {
3124 illegal_op:
3125 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3126 return;
3127 }
3128 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3129 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3130 goto illegal_op;
3131 if (b == 0x0e) {
3132 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3133 goto illegal_op;
3134 /* femms */
3135 gen_helper_emms();
3136 return;
3137 }
3138 if (b == 0x77) {
3139 /* emms */
3140 gen_helper_emms();
3141 return;
3142 }
3143 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3144 the static cpu state) */
3145 if (!is_xmm) {
3146 gen_helper_enter_mmx();
3147 }
3148
3149 modrm = ldub_code(s->pc++);
3150 reg = ((modrm >> 3) & 7);
3151 if (is_xmm)
3152 reg |= rex_r;
3153 mod = (modrm >> 6) & 3;
3154 if (sse_op2 == SSE_SPECIAL) {
3155 b |= (b1 << 8);
3156 switch(b) {
3157 case 0x0e7: /* movntq */
3158 if (mod == 3)
3159 goto illegal_op;
3160 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3161 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3162 break;
3163 case 0x1e7: /* movntdq */
3164 case 0x02b: /* movntps */
3165 case 0x12b: /* movntps */
3166 case 0x3f0: /* lddqu */
3167 if (mod == 3)
3168 goto illegal_op;
3169 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3170 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3171 break;
3172 case 0x22b: /* movntss */
3173 case 0x32b: /* movntsd */
3174 if (mod == 3)
3175 goto illegal_op;
3176 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3177 if (b1 & 1) {
3178 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3179 xmm_regs[reg]));
3180 } else {
3181 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3182 xmm_regs[reg].XMM_L(0)));
3183 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3184 }
3185 break;
3186 case 0x6e: /* movd mm, ea */
3187 #ifdef TARGET_X86_64
3188 if (s->dflag == 2) {
3189 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3190 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3191 } else
3192 #endif
3193 {
3194 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3195 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3196 offsetof(CPUX86State,fpregs[reg].mmx));
3197 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3198 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3199 }
3200 break;
3201 case 0x16e: /* movd xmm, ea */
3202 #ifdef TARGET_X86_64
3203 if (s->dflag == 2) {
3204 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3205 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3206 offsetof(CPUX86State,xmm_regs[reg]));
3207 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3208 } else
3209 #endif
3210 {
3211 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3212 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3213 offsetof(CPUX86State,xmm_regs[reg]));
3214 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3215 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3216 }
3217 break;
3218 case 0x6f: /* movq mm, ea */
3219 if (mod != 3) {
3220 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3221 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3222 } else {
3223 rm = (modrm & 7);
3224 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3225 offsetof(CPUX86State,fpregs[rm].mmx));
3226 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3227 offsetof(CPUX86State,fpregs[reg].mmx));
3228 }
3229 break;
3230 case 0x010: /* movups */
3231 case 0x110: /* movupd */
3232 case 0x028: /* movaps */
3233 case 0x128: /* movapd */
3234 case 0x16f: /* movdqa xmm, ea */
3235 case 0x26f: /* movdqu xmm, ea */
3236 if (mod != 3) {
3237 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3238 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3239 } else {
3240 rm = (modrm & 7) | REX_B(s);
3241 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3242 offsetof(CPUX86State,xmm_regs[rm]));
3243 }
3244 break;
3245 case 0x210: /* movss xmm, ea */
3246 if (mod != 3) {
3247 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3248 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3249 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3250 gen_op_movl_T0_0();
3251 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3252 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3253 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3254 } else {
3255 rm = (modrm & 7) | REX_B(s);
3256 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3257 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3258 }
3259 break;
3260 case 0x310: /* movsd xmm, ea */
3261 if (mod != 3) {
3262 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3263 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3264 gen_op_movl_T0_0();
3265 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3266 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3267 } else {
3268 rm = (modrm & 7) | REX_B(s);
3269 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3270 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3271 }
3272 break;
3273 case 0x012: /* movlps */
3274 case 0x112: /* movlpd */
3275 if (mod != 3) {
3276 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3277 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3278 } else {
3279 /* movhlps */
3280 rm = (modrm & 7) | REX_B(s);
3281 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3282 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3283 }
3284 break;
3285 case 0x212: /* movsldup */
3286 if (mod != 3) {
3287 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3288 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3289 } else {
3290 rm = (modrm & 7) | REX_B(s);
3291 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3292 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3293 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3294 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3295 }
3296 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3297 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3298 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3299 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3300 break;
3301 case 0x312: /* movddup */
3302 if (mod != 3) {
3303 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3304 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3305 } else {
3306 rm = (modrm & 7) | REX_B(s);
3307 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3308 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3309 }
3310 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3311 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3312 break;
3313 case 0x016: /* movhps */
3314 case 0x116: /* movhpd */
3315 if (mod != 3) {
3316 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3317 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3318 } else {
3319 /* movlhps */
3320 rm = (modrm & 7) | REX_B(s);
3321 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3322 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3323 }
3324 break;
3325 case 0x216: /* movshdup */
3326 if (mod != 3) {
3327 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3328 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3329 } else {
3330 rm = (modrm & 7) | REX_B(s);
3331 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3332 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3333 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3334 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3335 }
3336 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3337 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3338 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3339 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3340 break;
3341 case 0x178:
3342 case 0x378:
3343 {
3344 int bit_index, field_length;
3345
3346 if (b1 == 1 && reg != 0)
3347 goto illegal_op;
3348 field_length = ldub_code(s->pc++) & 0x3F;
3349 bit_index = ldub_code(s->pc++) & 0x3F;
3350 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3351 offsetof(CPUX86State,xmm_regs[reg]));
3352 if (b1 == 1)
3353 gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3354 tcg_const_i32(field_length));
3355 else
3356 gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3357 tcg_const_i32(field_length));
3358 }
3359 break;
3360 case 0x7e: /* movd ea, mm */
3361 #ifdef TARGET_X86_64
3362 if (s->dflag == 2) {
3363 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3364 offsetof(CPUX86State,fpregs[reg].mmx));
3365 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3366 } else
3367 #endif
3368 {
3369 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3370 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3371 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3372 }
3373 break;
3374 case 0x17e: /* movd ea, xmm */
3375 #ifdef TARGET_X86_64
3376 if (s->dflag == 2) {
3377 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3378 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3379 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3380 } else
3381 #endif
3382 {
3383 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3384 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3385 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3386 }
3387 break;
3388 case 0x27e: /* movq xmm, ea */
3389 if (mod != 3) {
3390 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3391 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3392 } else {
3393 rm = (modrm & 7) | REX_B(s);
3394 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3395 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3396 }
3397 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3398 break;
3399 case 0x7f: /* movq ea, mm */
3400 if (mod != 3) {
3401 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3402 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3403 } else {
3404 rm = (modrm & 7);
3405 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3406 offsetof(CPUX86State,fpregs[reg].mmx));
3407 }
3408 break;
3409 case 0x011: /* movups */
3410 case 0x111: /* movupd */
3411 case 0x029: /* movaps */
3412 case 0x129: /* movapd */
3413 case 0x17f: /* movdqa ea, xmm */
3414 case 0x27f: /* movdqu ea, xmm */
3415 if (mod != 3) {
3416 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3417 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3418 } else {
3419 rm = (modrm & 7) | REX_B(s);
3420 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3421 offsetof(CPUX86State,xmm_regs[reg]));
3422 }
3423 break;
3424 case 0x211: /* movss ea, xmm */
3425 if (mod != 3) {
3426 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3427 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3428 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3429 } else {
3430 rm = (modrm & 7) | REX_B(s);
3431 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3432 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3433 }
3434 break;
3435 case 0x311: /* movsd ea, xmm */
3436 if (mod != 3) {
3437 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3438 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3439 } else {
3440 rm = (modrm & 7) | REX_B(s);
3441 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3442 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3443 }
3444 break;
3445 case 0x013: /* movlps */
3446 case 0x113: /* movlpd */
3447 if (mod != 3) {
3448 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3449 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3450 } else {
3451 goto illegal_op;
3452 }
3453 break;
3454 case 0x017: /* movhps */
3455 case 0x117: /* movhpd */
3456 if (mod != 3) {
3457 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3458 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3459 } else {
3460 goto illegal_op;
3461 }
3462 break;
3463 case 0x71: /* shift mm, im */
3464 case 0x72:
3465 case 0x73:
3466 case 0x171: /* shift xmm, im */
3467 case 0x172:
3468 case 0x173:
3469 val = ldub_code(s->pc++);
3470 if (is_xmm) {
3471 gen_op_movl_T0_im(val);
3472 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3473 gen_op_movl_T0_0();
3474 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3475 op1_offset = offsetof(CPUX86State,xmm_t0);
3476 } else {
3477 gen_op_movl_T0_im(val);
3478 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3479 gen_op_movl_T0_0();
3480 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3481 op1_offset = offsetof(CPUX86State,mmx_t0);
3482 }
3483 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3484 if (!sse_op2)
3485 goto illegal_op;
3486 if (is_xmm) {
3487 rm = (modrm & 7) | REX_B(s);
3488 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3489 } else {
3490 rm = (modrm & 7);
3491 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3492 }
3493 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3494 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3495 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3496 break;
3497 case 0x050: /* movmskps */
3498 rm = (modrm & 7) | REX_B(s);
3499 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3500 offsetof(CPUX86State,xmm_regs[rm]));
3501 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3502 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3503 gen_op_mov_reg_T0(OT_LONG, reg);
3504 break;
3505 case 0x150: /* movmskpd */
3506 rm = (modrm & 7) | REX_B(s);
3507 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3508 offsetof(CPUX86State,xmm_regs[rm]));
3509 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3510 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3511 gen_op_mov_reg_T0(OT_LONG, reg);
3512 break;
3513 case 0x02a: /* cvtpi2ps */
3514 case 0x12a: /* cvtpi2pd */
3515 gen_helper_enter_mmx();
3516 if (mod != 3) {
3517 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3518 op2_offset = offsetof(CPUX86State,mmx_t0);
3519 gen_ldq_env_A0(s->mem_index, op2_offset);
3520 } else {
3521 rm = (modrm & 7);
3522 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3523 }
3524 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3525 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3526 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3527 switch(b >> 8) {
3528 case 0x0:
3529 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3530 break;
3531 default:
3532 case 0x1:
3533 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3534 break;
3535 }
3536 break;
3537 case 0x22a: /* cvtsi2ss */
3538 case 0x32a: /* cvtsi2sd */
3539 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3540 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3541 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3542 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3543 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3544 if (ot == OT_LONG) {
3545 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3546 ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
3547 } else {
3548 ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
3549 }
3550 break;
3551 case 0x02c: /* cvttps2pi */
3552 case 0x12c: /* cvttpd2pi */
3553 case 0x02d: /* cvtps2pi */
3554 case 0x12d: /* cvtpd2pi */
3555 gen_helper_enter_mmx();
3556 if (mod != 3) {
3557 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3558 op2_offset = offsetof(CPUX86State,xmm_t0);
3559 gen_ldo_env_A0(s->mem_index, op2_offset);
3560 } else {
3561 rm = (modrm & 7) | REX_B(s);
3562 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3563 }
3564 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3565 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3566 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3567 switch(b) {
3568 case 0x02c:
3569 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3570 break;
3571 case 0x12c:
3572 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3573 break;
3574 case 0x02d:
3575 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3576 break;
3577 case 0x12d:
3578 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3579 break;
3580 }
3581 break;
3582 case 0x22c: /* cvttss2si */
3583 case 0x32c: /* cvttsd2si */
3584 case 0x22d: /* cvtss2si */
3585 case 0x32d: /* cvtsd2si */
3586 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3587 if (mod != 3) {
3588 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3589 if ((b >> 8) & 1) {
3590 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3591 } else {
3592 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3593 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3594 }
3595 op2_offset = offsetof(CPUX86State,xmm_t0);
3596 } else {
3597 rm = (modrm & 7) | REX_B(s);
3598 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3599 }
3600 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3601 (b & 1) * 4];
3602 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3603 if (ot == OT_LONG) {
3604 ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
3605 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3606 } else {
3607 ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
3608 }
3609 gen_op_mov_reg_T0(ot, reg);
3610 break;
3611 case 0xc4: /* pinsrw */
3612 case 0x1c4:
3613 s->rip_offset = 1;
3614 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3615 val = ldub_code(s->pc++);
3616 if (b1) {
3617 val &= 7;
3618 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3619 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3620 } else {
3621 val &= 3;
3622 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3623 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3624 }
3625 break;
3626 case 0xc5: /* pextrw */
3627 case 0x1c5:
3628 if (mod != 3)
3629 goto illegal_op;
3630 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3631 val = ldub_code(s->pc++);
3632 if (b1) {
3633 val &= 7;
3634 rm = (modrm & 7) | REX_B(s);
3635 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3636 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3637 } else {
3638 val &= 3;
3639 rm = (modrm & 7);
3640 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3641 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3642 }
3643 reg = ((modrm >> 3) & 7) | rex_r;
3644 gen_op_mov_reg_T0(ot, reg);
3645 break;
3646 case 0x1d6: /* movq ea, xmm */
3647 if (mod != 3) {
3648 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3649 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3650 } else {
3651 rm = (modrm & 7) | REX_B(s);
3652 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3653 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3654 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3655 }
3656 break;
3657 case 0x2d6: /* movq2dq */
3658 gen_helper_enter_mmx();
3659 rm = (modrm & 7);
3660 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3661 offsetof(CPUX86State,fpregs[rm].mmx));
3662 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3663 break;
3664 case 0x3d6: /* movdq2q */
3665 gen_helper_enter_mmx();
3666 rm = (modrm & 7) | REX_B(s);
3667 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3668 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3669 break;
3670 case 0xd7: /* pmovmskb */
3671 case 0x1d7:
3672 if (mod != 3)
3673 goto illegal_op;
3674 if (b1) {
3675 rm = (modrm & 7) | REX_B(s);
3676 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3677 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3678 } else {
3679 rm = (modrm & 7);
3680 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3681 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3682 }
3683 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3684 reg = ((modrm >> 3) & 7) | rex_r;
3685 gen_op_mov_reg_T0(OT_LONG, reg);
3686 break;
3687 case 0x138:
3688 if (s->prefix & PREFIX_REPNZ)
3689 goto crc32;
3690 case 0x038:
3691 b = modrm;
3692 modrm = ldub_code(s->pc++);
3693 rm = modrm & 7;
3694 reg = ((modrm >> 3) & 7) | rex_r;
3695 mod = (modrm >> 6) & 3;
3696
3697 sse_op2 = sse_op_table6[b].op[b1];
3698 if (!sse_op2)
3699 goto illegal_op;
3700 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3701 goto illegal_op;
3702
3703 if (b1) {
3704 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3705 if (mod == 3) {
3706 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3707 } else {
3708 op2_offset = offsetof(CPUX86State,xmm_t0);
3709 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3710 switch (b) {
3711 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3712 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3713 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3714 gen_ldq_env_A0(s->mem_index, op2_offset +
3715 offsetof(XMMReg, XMM_Q(0)));
3716 break;
3717 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3718 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3719 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3720 (s->mem_index >> 2) - 1);
3721 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3722 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3723 offsetof(XMMReg, XMM_L(0)));
3724 break;
3725 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3726 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3727 (s->mem_index >> 2) - 1);
3728 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3729 offsetof(XMMReg, XMM_W(0)));
3730 break;
3731 case 0x2a: /* movntqda */
3732 gen_ldo_env_A0(s->mem_index, op1_offset);
3733 return;
3734 default:
3735 gen_ldo_env_A0(s->mem_index, op2_offset);
3736 }
3737 }
3738 } else {
3739 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3740 if (mod == 3) {
3741 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3742 } else {
3743 op2_offset = offsetof(CPUX86State,mmx_t0);
3744 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3745 gen_ldq_env_A0(s->mem_index, op2_offset);
3746 }
3747 }
3748 if (sse_op2 == SSE_SPECIAL)
3749 goto illegal_op;
3750
3751 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3752 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3753 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3754
3755 if (b == 0x17)
3756 s->cc_op = CC_OP_EFLAGS;
3757 break;
3758 case 0x338: /* crc32 */
3759 crc32:
3760 b = modrm;
3761 modrm = ldub_code(s->pc++);
3762 reg = ((modrm >> 3) & 7) | rex_r;
3763
3764 if (b != 0xf0 && b != 0xf1)
3765 goto illegal_op;
3766 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3767 goto illegal_op;
3768
3769 if (b == 0xf0)
3770 ot = OT_BYTE;
3771 else if (b == 0xf1 && s->dflag != 2)
3772 if (s->prefix & PREFIX_DATA)
3773 ot = OT_WORD;
3774 else
3775 ot = OT_LONG;
3776 else
3777 ot = OT_QUAD;
3778
3779 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3780 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3781 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3782 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3783 cpu_T[0], tcg_const_i32(8 << ot));
3784
3785 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3786 gen_op_mov_reg_T0(ot, reg);
3787 break;
3788 case 0x03a:
3789 case 0x13a:
3790 b = modrm;
3791 modrm = ldub_code(s->pc++);
3792 rm = modrm & 7;
3793 reg = ((modrm >> 3) & 7) | rex_r;
3794 mod = (modrm >> 6) & 3;
3795
3796 sse_op2 = sse_op_table7[b].op[b1];
3797 if (!sse_op2)
3798 goto illegal_op;
3799 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3800 goto illegal_op;
3801
3802 if (sse_op2 == SSE_SPECIAL) {
3803 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3804 rm = (modrm & 7) | REX_B(s);
3805 if (mod != 3)
3806 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3807 reg = ((modrm >> 3) & 7) | rex_r;
3808 val = ldub_code(s->pc++);
3809 switch (b) {
3810 case 0x14: /* pextrb */
3811 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3812 xmm_regs[reg].XMM_B(val & 15)));
3813 if (mod == 3)
3814 gen_op_mov_reg_T0(ot, rm);
3815 else
3816 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3817 (s->mem_index >> 2) - 1);
3818 break;
3819 case 0x15: /* pextrw */
3820 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3821 xmm_regs[reg].XMM_W(val & 7)));
3822 if (mod == 3)
3823 gen_op_mov_reg_T0(ot, rm);
3824 else
3825 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3826 (s->mem_index >> 2) - 1);
3827 break;
3828 case 0x16:
3829 if (ot == OT_LONG) { /* pextrd */
3830 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3831 offsetof(CPUX86State,
3832 xmm_regs[reg].XMM_L(val & 3)));
3833 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3834 if (mod == 3)
3835 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3836 else
3837 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3838 (s->mem_index >> 2) - 1);
3839 } else { /* pextrq */
3840 #ifdef TARGET_X86_64
3841 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3842 offsetof(CPUX86State,
3843 xmm_regs[reg].XMM_Q(val & 1)));
3844 if (mod == 3)
3845 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3846 else
3847 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3848 (s->mem_index >> 2) - 1);
3849 #else
3850 goto illegal_op;
3851 #endif
3852 }
3853 break;
3854 case 0x17: /* extractps */
3855 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3856 xmm_regs[reg].XMM_L(val & 3)));
3857 if (mod == 3)
3858 gen_op_mov_reg_T0(ot, rm);
3859 else
3860 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3861 (s->mem_index >> 2) - 1);
3862 break;
3863 case 0x20: /* pinsrb */
3864 if (mod == 3)
3865 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3866 else
3867 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3868 (s->mem_index >> 2) - 1);
3869 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3870 xmm_regs[reg].XMM_B(val & 15)));
3871 break;
3872 case 0x21: /* insertps */
3873 if (mod == 3) {
3874 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3875 offsetof(CPUX86State,xmm_regs[rm]
3876 .XMM_L((val >> 6) & 3)));
3877 } else {
3878 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3879 (s->mem_index >> 2) - 1);
3880 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3881 }
3882 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3883 offsetof(CPUX86State,xmm_regs[reg]
3884 .XMM_L((val >> 4) & 3)));
3885 if ((val >> 0) & 1)
3886 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3887 cpu_env, offsetof(CPUX86State,
3888 xmm_regs[reg].XMM_L(0)));
3889 if ((val >> 1) & 1)
3890 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3891 cpu_env, offsetof(CPUX86State,
3892 xmm_regs[reg].XMM_L(1)));
3893 if ((val >> 2) & 1)
3894 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3895 cpu_env, offsetof(CPUX86State,
3896 xmm_regs[reg].XMM_L(2)));
3897 if ((val >> 3) & 1)
3898 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3899 cpu_env, offsetof(CPUX86State,
3900 xmm_regs[reg].XMM_L(3)));
3901 break;
3902 case 0x22:
3903 if (ot == OT_LONG) { /* pinsrd */
3904 if (mod == 3)
3905 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3906 else
3907 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3908 (s->mem_index >> 2) - 1);
3909 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3910 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3911 offsetof(CPUX86State,
3912 xmm_regs[reg].XMM_L(val & 3)));
3913 } else { /* pinsrq */
3914 #ifdef TARGET_X86_64
3915 if (mod == 3)
3916 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3917 else
3918 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3919 (s->mem_index >> 2) - 1);
3920 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3921 offsetof(CPUX86State,
3922 xmm_regs[reg].XMM_Q(val & 1)));
3923 #else
3924 goto illegal_op;
3925 #endif
3926 }
3927 break;
3928 }
3929 return;
3930 }
3931
3932 if (b1) {
3933 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3934 if (mod == 3) {
3935 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3936 } else {
3937 op2_offset = offsetof(CPUX86State,xmm_t0);
3938 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3939 gen_ldo_env_A0(s->mem_index, op2_offset);
3940 }
3941 } else {
3942 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3943 if (mod == 3) {
3944 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3945 } else {
3946 op2_offset = offsetof(CPUX86State,mmx_t0);
3947 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3948 gen_ldq_env_A0(s->mem_index, op2_offset);
3949 }
3950 }
3951 val = ldub_code(s->pc++);
3952
3953 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3954 s->cc_op = CC_OP_EFLAGS;
3955
3956 if (s->dflag == 2)
3957 /* The helper must use entire 64-bit gp registers */
3958 val |= 1 << 8;
3959 }
3960
3961 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3962 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3963 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3964 break;
3965 default:
3966 goto illegal_op;
3967 }
3968 } else {
3969 /* generic MMX or SSE operation */
3970 switch(b) {
3971 case 0x70: /* pshufx insn */
3972 case 0xc6: /* pshufx insn */
3973 case 0xc2: /* compare insns */
3974 s->rip_offset = 1;
3975 break;
3976 default:
3977 break;
3978 }
3979 if (is_xmm) {
3980 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3981 if (mod != 3) {
3982 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3983 op2_offset = offsetof(CPUX86State,xmm_t0);
3984 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3985 b == 0xc2)) {
3986 /* specific case for SSE single instructions */
3987 if (b1 == 2) {
3988 /* 32 bit access */
3989 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3990 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3991 } else {
3992 /* 64 bit access */
3993 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3994 }
3995 } else {
3996 gen_ldo_env_A0(s->mem_index, op2_offset);
3997 }
3998 } else {
3999 rm = (modrm & 7) | REX_B(s);
4000 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4001 }
4002 } else {
4003 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4004 if (mod != 3) {
4005 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4006 op2_offset = offsetof(CPUX86State,mmx_t0);
4007 gen_ldq_env_A0(s->mem_index, op2_offset);
4008 } else {
4009 rm = (modrm & 7);
4010 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4011 }
4012 }
4013 switch(b) {
4014 case 0x0f: /* 3DNow! data insns */
4015 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4016 goto illegal_op;
4017 val = ldub_code(s->pc++);
4018 sse_op2 = sse_op_table5[val];
4019 if (!sse_op2)
4020 goto illegal_op;
4021 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4022 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4023 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4024 break;
4025 case 0x70: /* pshufx insn */
4026 case 0xc6: /* pshufx insn */
4027 val = ldub_code(s->pc++);
4028 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4029 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4030 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4031 break;
4032 case 0xc2:
4033 /* compare insns */
4034 val = ldub_code(s->pc++);
4035 if (val >= 8)
4036 goto illegal_op;
4037 sse_op2 = sse_op_table4[val][b1];
4038 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4039 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4040 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4041 break;
4042 case 0xf7:
4043 /* maskmov : we must prepare A0 */
4044 if (mod != 3)
4045 goto illegal_op;
4046 #ifdef TARGET_X86_64
4047 if (s->aflag == 2) {
4048 gen_op_movq_A0_reg(R_EDI);
4049 } else
4050 #endif
4051 {
4052 gen_op_movl_A0_reg(R_EDI);
4053 if (s->aflag == 0)
4054 gen_op_andl_A0_ffff();
4055 }
4056 gen_add_A0_ds_seg(s);
4057
4058 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4059 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4060 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
4061 break;
4062 default:
4063 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4064 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4065 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4066 break;
4067 }
4068 if (b == 0x2e || b == 0x2f) {
4069 s->cc_op = CC_OP_EFLAGS;
4070 }
4071 }
4072 }
4073
4074 /* convert one instruction. s->is_jmp is set if the translation must
4075 be stopped. Return the next pc value */
4076 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4077 {
4078 int b, prefixes, aflag, dflag;
4079 int shift, ot;
4080 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4081 target_ulong next_eip, tval;
4082 int rex_w, rex_r;
4083
4084 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4085 tcg_gen_debug_insn_start(pc_start);
4086 s->pc = pc_start;
4087 prefixes = 0;
4088 aflag = s->code32;
4089 dflag = s->code32;
4090 s->override = -1;
4091 rex_w = -1;
4092 rex_r = 0;
4093 #ifdef TARGET_X86_64
4094 s->rex_x = 0;
4095 s->rex_b = 0;
4096 x86_64_hregs = 0;
4097 #endif
4098 s->rip_offset = 0; /* for relative ip address */
4099 next_byte:
4100 b = ldub_code(s->pc);
4101 s->pc++;
4102 /* check prefixes */
4103 #ifdef TARGET_X86_64
4104 if (CODE64(s)) {
4105 switch (b) {
4106 case 0xf3:
4107 prefixes |= PREFIX_REPZ;
4108 goto next_byte;
4109 case 0xf2:
4110 prefixes |= PREFIX_REPNZ;
4111 goto next_byte;
4112 case 0xf0:
4113 prefixes |= PREFIX_LOCK;
4114 goto next_byte;
4115 case 0x2e:
4116 s->override = R_CS;
4117 goto next_byte;
4118 case 0x36:
4119 s->override = R_SS;
4120 goto next_byte;
4121 case 0x3e:
4122 s->override = R_DS;
4123 goto next_byte;
4124 case 0x26:
4125 s->override = R_ES;
4126 goto next_byte;
4127 case 0x64:
4128 s->override = R_FS;
4129 goto next_byte;
4130 case 0x65:
4131 s->override = R_GS;
4132 goto next_byte;
4133 case 0x66:
4134 prefixes |= PREFIX_DATA;
4135 goto next_byte;
4136 case 0x67:
4137 prefixes |= PREFIX_ADR;
4138 goto next_byte;
4139 case 0x40 ... 0x4f:
4140 /* REX prefix */
4141 rex_w = (b >> 3) & 1;
4142 rex_r = (b & 0x4) << 1;
4143 s->rex_x = (b & 0x2) << 2;
4144 REX_B(s) = (b & 0x1) << 3;
4145 x86_64_hregs = 1; /* select uniform byte register addressing */
4146 goto next_byte;
4147 }
4148 if (rex_w == 1) {
4149 /* 0x66 is ignored if rex.w is set */
4150 dflag = 2;
4151 } else {
4152 if (prefixes & PREFIX_DATA)
4153 dflag ^= 1;
4154 }
4155 if (!(prefixes & PREFIX_ADR))
4156 aflag = 2;
4157 } else
4158 #endif
4159 {
4160 switch (b) {
4161 case 0xf3:
4162 prefixes |= PREFIX_REPZ;
4163 goto next_byte;
4164 case 0xf2:
4165 prefixes |= PREFIX_REPNZ;
4166 goto next_byte;
4167 case 0xf0:
4168 prefixes |= PREFIX_LOCK;
4169 goto next_byte;
4170 case 0x2e:
4171 s->override = R_CS;
4172 goto next_byte;
4173 case 0x36:
4174 s->override = R_SS;
4175 goto next_byte;
4176 case 0x3e:
4177 s->override = R_DS;
4178 goto next_byte;
4179 case 0x26:
4180 s->override = R_ES;
4181 goto next_byte;
4182 case 0x64:
4183 s->override = R_FS;
4184 goto next_byte;
4185 case 0x65:
4186 s->override = R_GS;
4187 goto next_byte;
4188 case 0x66:
4189 prefixes |= PREFIX_DATA;
4190 goto next_byte;
4191 case 0x67:
4192 prefixes |= PREFIX_ADR;
4193 goto next_byte;
4194 }
4195 if (prefixes & PREFIX_DATA)
4196 dflag ^= 1;
4197 if (prefixes & PREFIX_ADR)
4198 aflag ^= 1;
4199 }
4200
4201 s->prefix = prefixes;
4202 s->aflag = aflag;
4203 s->dflag = dflag;
4204
4205 /* lock generation */
4206 if (prefixes & PREFIX_LOCK)
4207 gen_helper_lock();
4208
4209 /* now check op code */
4210 reswitch:
4211 switch(b) {
4212 case 0x0f:
4213 /**************************/
4214 /* extended op code */
4215 b = ldub_code(s->pc++) | 0x100;
4216 goto reswitch;
4217
4218 /**************************/
4219 /* arith & logic */
4220 case 0x00 ... 0x05:
4221 case 0x08 ... 0x0d:
4222 case 0x10 ... 0x15:
4223 case 0x18 ... 0x1d:
4224 case 0x20 ... 0x25:
4225 case 0x28 ... 0x2d:
4226 case 0x30 ... 0x35:
4227 case 0x38 ... 0x3d:
4228 {
4229 int op, f, val;
4230 op = (b >> 3) & 7;
4231 f = (b >> 1) & 3;
4232
4233 if ((b & 1) == 0)
4234 ot = OT_BYTE;
4235 else
4236 ot = dflag + OT_WORD;
4237
4238 switch(f) {
4239 case 0: /* OP Ev, Gv */
4240 modrm = ldub_code(s->pc++);
4241 reg = ((modrm >> 3) & 7) | rex_r;
4242 mod = (modrm >> 6) & 3;
4243 rm = (modrm & 7) | REX_B(s);
4244 if (mod != 3) {
4245 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4246 opreg = OR_TMP0;
4247 } else if (op == OP_XORL && rm == reg) {
4248 xor_zero:
4249 /* xor reg, reg optimisation */
4250 gen_op_movl_T0_0();
4251 s->cc_op = CC_OP_LOGICB + ot;
4252 gen_op_mov_reg_T0(ot, reg);
4253 gen_op_update1_cc();
4254 break;
4255 } else {
4256 opreg = rm;
4257 }
4258 gen_op_mov_TN_reg(ot, 1, reg);
4259 gen_op(s, op, ot, opreg);
4260 break;
4261 case 1: /* OP Gv, Ev */
4262 modrm = ldub_code(s->pc++);
4263 mod = (modrm >> 6) & 3;
4264 reg = ((modrm >> 3) & 7) | rex_r;
4265 rm = (modrm & 7) | REX_B(s);
4266 if (mod != 3) {
4267 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4268 gen_op_ld_T1_A0(ot + s->mem_index);
4269 } else if (op == OP_XORL && rm == reg) {
4270 goto xor_zero;
4271 } else {
4272 gen_op_mov_TN_reg(ot, 1, rm);
4273 }
4274 gen_op(s, op, ot, reg);
4275 break;
4276 case 2: /* OP A, Iv */
4277 val = insn_get(s, ot);
4278 gen_op_movl_T1_im(val);
4279 gen_op(s, op, ot, OR_EAX);
4280 break;
4281 }
4282 }
4283 break;
4284
4285 case 0x82:
4286 if (CODE64(s))
4287 goto illegal_op;
4288 case 0x80: /* GRP1 */
4289 case 0x81:
4290 case 0x83:
4291 {
4292 int val;
4293
4294 if ((b & 1) == 0)
4295 ot = OT_BYTE;
4296 else
4297 ot = dflag + OT_WORD;
4298
4299 modrm = ldub_code(s->pc++);
4300 mod = (modrm >> 6) & 3;
4301 rm = (modrm & 7) | REX_B(s);
4302 op = (modrm >> 3) & 7;
4303
4304 if (mod != 3) {
4305 if (b == 0x83)
4306 s->rip_offset = 1;
4307 else
4308 s->rip_offset = insn_const_size(ot);
4309 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4310 opreg = OR_TMP0;
4311 } else {
4312 opreg = rm;
4313 }
4314
4315 switch(b) {
4316 default:
4317 case 0x80:
4318 case 0x81:
4319 case 0x82:
4320 val = insn_get(s, ot);
4321 break;
4322 case 0x83:
4323 val = (int8_t)insn_get(s, OT_BYTE);
4324 break;
4325 }
4326 gen_op_movl_T1_im(val);
4327 gen_op(s, op, ot, opreg);
4328 }
4329 break;
4330
4331 /**************************/
4332 /* inc, dec, and other misc arith */
4333 case 0x40 ... 0x47: /* inc Gv */
4334 ot = dflag ? OT_LONG : OT_WORD;
4335 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4336 break;
4337 case 0x48 ... 0x4f: /* dec Gv */
4338 ot = dflag ? OT_LONG : OT_WORD;
4339 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4340 break;
4341 case 0xf6: /* GRP3 */
4342 case 0xf7:
4343 if ((b & 1) == 0)
4344 ot = OT_BYTE;
4345 else
4346 ot = dflag + OT_WORD;
4347
4348 modrm = ldub_code(s->pc++);
4349 mod = (modrm >> 6) & 3;
4350 rm = (modrm & 7) | REX_B(s);
4351 op = (modrm >> 3) & 7;
4352 if (mod != 3) {
4353 if (op == 0)
4354 s->rip_offset = insn_const_size(ot);
4355 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4356 gen_op_ld_T0_A0(ot + s->mem_index);
4357 } else {
4358 gen_op_mov_TN_reg(ot, 0, rm);
4359 }
4360
4361 switch(op) {
4362 case 0: /* test */
4363 val = insn_get(s, ot);
4364 gen_op_movl_T1_im(val);
4365 gen_op_testl_T0_T1_cc();
4366 s->cc_op = CC_OP_LOGICB + ot;
4367 break;
4368 case 2: /* not */
4369 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4370 if (mod != 3) {
4371 gen_op_st_T0_A0(ot + s->mem_index);
4372 } else {
4373 gen_op_mov_reg_T0(ot, rm);
4374 }
4375 break;
4376 case 3: /* neg */
4377 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4378 if (mod != 3) {
4379 gen_op_st_T0_A0(ot + s->mem_index);
4380 } else {
4381 gen_op_mov_reg_T0(ot, rm);
4382 }
4383 gen_op_update_neg_cc();
4384 s->cc_op = CC_OP_SUBB + ot;
4385 break;
4386 case 4: /* mul */
4387 switch(ot) {
4388 case OT_BYTE:
4389 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4390 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4391 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4392 /* XXX: use 32 bit mul which could be faster */
4393 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4394 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4395 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4396 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4397 s->cc_op = CC_OP_MULB;
4398 break;
4399 case OT_WORD:
4400 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4401 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4402 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4403 /* XXX: use 32 bit mul which could be faster */
4404 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4405 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4406 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4407 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4408 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4409 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4410 s->cc_op = CC_OP_MULW;
4411 break;
4412 default:
4413 case OT_LONG:
4414 #ifdef TARGET_X86_64
4415 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4416 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4417 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4418 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4419 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4420 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4421 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4422 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4423 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4424 #else
4425 {
4426 TCGv_i64 t0, t1;
4427 t0 = tcg_temp_new_i64();
4428 t1 = tcg_temp_new_i64();
4429 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4430 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4431 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4432 tcg_gen_mul_i64(t0, t0, t1);
4433 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4434 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4435 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4436 tcg_gen_shri_i64(t0, t0, 32);
4437 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4438 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4439 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4440 }
4441 #endif
4442 s->cc_op = CC_OP_MULL;
4443 break;
4444 #ifdef TARGET_X86_64
4445 case OT_QUAD:
4446 gen_helper_mulq_EAX_T0(cpu_T[0]);
4447 s->cc_op = CC_OP_MULQ;
4448 break;
4449 #endif
4450 }
4451 break;
4452 case 5: /* imul */
4453 switch(ot) {
4454 case OT_BYTE:
4455 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4456 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4457 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4458 /* XXX: use 32 bit mul which could be faster */
4459 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4460 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4461 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4462 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4463 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4464 s->cc_op = CC_OP_MULB;
4465 break;
4466 case OT_WORD:
4467 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4468 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4469 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4470 /* XXX: use 32 bit mul which could be faster */
4471 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4472 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4473 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4474 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4475 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4476 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4477 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4478 s->cc_op = CC_OP_MULW;
4479 break;
4480 default:
4481 case OT_LONG:
4482 #ifdef TARGET_X86_64
4483 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4484 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4485 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4486 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4487 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4488 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4489 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4490 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4491 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4492 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4493 #else
4494 {
4495 TCGv_i64 t0, t1;
4496 t0 = tcg_temp_new_i64();
4497 t1 = tcg_temp_new_i64();
4498 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4499 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4500 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4501 tcg_gen_mul_i64(t0, t0, t1);
4502 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4503 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4504 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4505 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4506 tcg_gen_shri_i64(t0, t0, 32);
4507 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4508 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4509 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4510 }
4511 #endif
4512 s->cc_op = CC_OP_MULL;
4513 break;
4514 #ifdef TARGET_X86_64
4515 case OT_QUAD:
4516 gen_helper_imulq_EAX_T0(cpu_T[0]);
4517 s->cc_op = CC_OP_MULQ;
4518 break;
4519 #endif
4520 }
4521 break;
4522 case 6: /* div */
4523 switch(ot) {
4524 case OT_BYTE:
4525 gen_jmp_im(pc_start - s->cs_base);
4526 gen_helper_divb_AL(cpu_T[0]);
4527 break;
4528 case OT_WORD:
4529 gen_jmp_im(pc_start - s->cs_base);
4530 gen_helper_divw_AX(cpu_T[0]);
4531 break;
4532 default:
4533 case OT_LONG:
4534 gen_jmp_im(pc_start - s->cs_base);
4535 gen_helper_divl_EAX(cpu_T[0]);
4536 break;
4537 #ifdef TARGET_X86_64
4538 case OT_QUAD:
4539 gen_jmp_im(pc_start - s->cs_base);
4540 gen_helper_divq_EAX(cpu_T[0]);
4541 break;
4542 #endif
4543 }
4544 break;
4545 case 7: /* idiv */
4546 switch(ot) {
4547 case OT_BYTE:
4548 gen_jmp_im(pc_start - s->cs_base);
4549 gen_helper_idivb_AL(cpu_T[0]);
4550 break;
4551 case OT_WORD:
4552 gen_jmp_im(pc_start - s->cs_base);
4553 gen_helper_idivw_AX(cpu_T[0]);
4554 break;
4555 default:
4556 case OT_LONG:
4557 gen_jmp_im(pc_start - s->cs_base);
4558 gen_helper_idivl_EAX(cpu_T[0]);
4559 break;
4560 #ifdef TARGET_X86_64
4561 case OT_QUAD:
4562 gen_jmp_im(pc_start - s->cs_base);
4563 gen_helper_idivq_EAX(cpu_T[0]);
4564 break;
4565 #endif
4566 }
4567 break;
4568 default:
4569 goto illegal_op;
4570 }
4571 break;
4572
4573 case 0xfe: /* GRP4 */
4574 case 0xff: /* GRP5 */
4575 if ((b & 1) == 0)
4576 ot = OT_BYTE;
4577 else
4578 ot = dflag + OT_WORD;
4579
4580 modrm = ldub_code(s->pc++);
4581 mod = (modrm >> 6) & 3;
4582 rm = (modrm & 7) | REX_B(s);
4583 op = (modrm >> 3) & 7;
4584 if (op >= 2 && b == 0xfe) {
4585 goto illegal_op;
4586 }
4587 if (CODE64(s)) {
4588 if (op == 2 || op == 4) {
4589 /* operand size for jumps is 64 bit */
4590 ot = OT_QUAD;
4591 } else if (op == 3 || op == 5) {
4592 /* for call calls, the operand is 16 or 32 bit, even
4593 in long mode */
4594 ot = dflag ? OT_LONG : OT_WORD;
4595 } else if (op == 6) {
4596 /* default push size is 64 bit */
4597 ot = dflag ? OT_QUAD : OT_WORD;
4598 }
4599 }
4600 if (mod != 3) {
4601 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4602 if (op >= 2 && op != 3 && op != 5)
4603 gen_op_ld_T0_A0(ot + s->mem_index);
4604 } else {
4605 gen_op_mov_TN_reg(ot, 0, rm);
4606 }
4607
4608 switch(op) {
4609 case 0: /* inc Ev */
4610 if (mod != 3)
4611 opreg = OR_TMP0;
4612 else
4613 opreg = rm;
4614 gen_inc(s, ot, opreg, 1);
4615 break;
4616 case 1: /* dec Ev */
4617 if (mod != 3)
4618 opreg = OR_TMP0;
4619 else
4620 opreg = rm;
4621 gen_inc(s, ot, opreg, -1);
4622 break;
4623 case 2: /* call Ev */
4624 /* XXX: optimize if memory (no 'and' is necessary) */
4625 if (s->dflag == 0)
4626 gen_op_andl_T0_ffff();
4627 next_eip = s->pc - s->cs_base;
4628 gen_movtl_T1_im(next_eip);
4629 gen_push_T1(s);
4630 gen_op_jmp_T0();
4631 gen_eob(s);
4632 break;
4633 case 3: /* lcall Ev */
4634 gen_op_ld_T1_A0(ot + s->mem_index);
4635 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4636 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4637 do_lcall:
4638 if (s->pe && !s->vm86) {
4639 if (s->cc_op != CC_OP_DYNAMIC)
4640 gen_op_set_cc_op(s->cc_op);
4641 gen_jmp_im(pc_start - s->cs_base);
4642 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4643 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4644 tcg_const_i32(dflag),
4645 tcg_const_i32(s->pc - pc_start));
4646 } else {
4647 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4648 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4649 tcg_const_i32(dflag),
4650 tcg_const_i32(s->pc - s->cs_base));
4651 }
4652 gen_eob(s);
4653 break;
4654 case 4: /* jmp Ev */
4655 if (s->dflag == 0)
4656 gen_op_andl_T0_ffff();
4657 gen_op_jmp_T0();
4658 gen_eob(s);
4659 break;
4660 case 5: /* ljmp Ev */
4661 gen_op_ld_T1_A0(ot + s->mem_index);
4662 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4663 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4664 do_ljmp:
4665 if (s->pe && !s->vm86) {
4666 if (s->cc_op != CC_OP_DYNAMIC)
4667 gen_op_set_cc_op(s->cc_op);
4668 gen_jmp_im(pc_start - s->cs_base);
4669 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4670 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4671 tcg_const_i32(s->pc - pc_start));
4672 } else {
4673 gen_op_movl_seg_T0_vm(R_CS);
4674 gen_op_movl_T0_T1();
4675 gen_op_jmp_T0();
4676 }
4677 gen_eob(s);
4678 break;
4679 case 6: /* push Ev */
4680 gen_push_T0(s);
4681 break;
4682 default:
4683 goto illegal_op;
4684 }
4685 break;
4686
4687 case 0x84: /* test Ev, Gv */
4688 case 0x85:
4689 if ((b & 1) == 0)
4690 ot = OT_BYTE;
4691 else
4692 ot = dflag + OT_WORD;
4693
4694 modrm = ldub_code(s->pc++);
4695 reg = ((modrm >> 3) & 7) | rex_r;
4696
4697 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4698 gen_op_mov_TN_reg(ot, 1, reg);
4699 gen_op_testl_T0_T1_cc();
4700 s->cc_op = CC_OP_LOGICB + ot;
4701 break;
4702
4703 case 0xa8: /* test eAX, Iv */
4704 case 0xa9:
4705 if ((b & 1) == 0)
4706 ot = OT_BYTE;
4707 else
4708 ot = dflag + OT_WORD;
4709 val = insn_get(s, ot);
4710
4711 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4712 gen_op_movl_T1_im(val);
4713 gen_op_testl_T0_T1_cc();
4714 s->cc_op = CC_OP_LOGICB + ot;
4715 break;
4716
4717 case 0x98: /* CWDE/CBW */
4718 #ifdef TARGET_X86_64
4719 if (dflag == 2) {
4720 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4721 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4722 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4723 } else
4724 #endif
4725 if (dflag == 1) {
4726 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4727 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4728 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4729 } else {
4730 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4731 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4732 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4733 }
4734 break;
4735 case 0x99: /* CDQ/CWD */
4736 #ifdef TARGET_X86_64
4737 if (dflag == 2) {
4738 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4739 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4740 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4741 } else
4742 #endif
4743 if (dflag == 1) {
4744 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4745 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4746 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4747 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4748 } else {
4749 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4750 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4751 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4752 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4753 }
4754 break;
4755 case 0x1af: /* imul Gv, Ev */
4756 case 0x69: /* imul Gv, Ev, I */
4757 case 0x6b:
4758 ot = dflag + OT_WORD;
4759 modrm = ldub_code(s->pc++);
4760 reg = ((modrm >> 3) & 7) | rex_r;
4761 if (b == 0x69)
4762 s->rip_offset = insn_const_size(ot);
4763 else if (b == 0x6b)
4764 s->rip_offset = 1;
4765 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4766 if (b == 0x69) {
4767 val = insn_get(s, ot);
4768 gen_op_movl_T1_im(val);
4769 } else if (b == 0x6b) {
4770 val = (int8_t)insn_get(s, OT_BYTE);
4771 gen_op_movl_T1_im(val);
4772 } else {
4773 gen_op_mov_TN_reg(ot, 1, reg);
4774 }
4775
4776 #ifdef TARGET_X86_64
4777 if (ot == OT_QUAD) {
4778 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4779 } else
4780 #endif
4781 if (ot == OT_LONG) {
4782 #ifdef TARGET_X86_64
4783 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4784 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4785 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4786 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4787 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4788 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4789 #else
4790 {
4791 TCGv_i64 t0, t1;
4792 t0 = tcg_temp_new_i64();
4793 t1 = tcg_temp_new_i64();
4794 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4795 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4796 tcg_gen_mul_i64(t0, t0, t1);
4797 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4798 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4799 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4800 tcg_gen_shri_i64(t0, t0, 32);
4801 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4802 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4803 }
4804 #endif
4805 } else {
4806 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4807 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4808 /* XXX: use 32 bit mul which could be faster */
4809 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4810 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4811 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4812 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4813 }
4814 gen_op_mov_reg_T0(ot, reg);
4815 s->cc_op = CC_OP_MULB + ot;
4816 break;
4817 case 0x1c0:
4818 case 0x1c1: /* xadd Ev, Gv */
4819 if ((b & 1) == 0)
4820 ot = OT_BYTE;
4821 else
4822 ot = dflag + OT_WORD;
4823 modrm = ldub_code(s->pc++);
4824 reg = ((modrm >> 3) & 7) | rex_r;
4825 mod = (modrm >> 6) & 3;
4826 if (mod == 3) {
4827 rm = (modrm & 7) | REX_B(s);
4828 gen_op_mov_TN_reg(ot, 0, reg);
4829 gen_op_mov_TN_reg(ot, 1, rm);
4830 gen_op_addl_T0_T1();
4831 gen_op_mov_reg_T1(ot, reg);
4832 gen_op_mov_reg_T0(ot, rm);
4833 } else {
4834 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4835 gen_op_mov_TN_reg(ot, 0, reg);
4836 gen_op_ld_T1_A0(ot + s->mem_index);
4837 gen_op_addl_T0_T1();
4838 gen_op_st_T0_A0(ot + s->mem_index);
4839 gen_op_mov_reg_T1(ot, reg);
4840 }
4841 gen_op_update2_cc();
4842 s->cc_op = CC_OP_ADDB + ot;
4843 break;
4844 case 0x1b0:
4845 case 0x1b1: /* cmpxchg Ev, Gv */
4846 {
4847 int label1, label2;
4848 TCGv t0, t1, t2, a0;
4849
4850 if ((b & 1) == 0)
4851 ot = OT_BYTE;
4852 else
4853 ot = dflag + OT_WORD;
4854 modrm = ldub_code(s->pc++);
4855 reg = ((modrm >> 3) & 7) | rex_r;
4856 mod = (modrm >> 6) & 3;
4857 t0 = tcg_temp_local_new();
4858 t1 = tcg_temp_local_new();
4859 t2 = tcg_temp_local_new();
4860 a0 = tcg_temp_local_new();
4861 gen_op_mov_v_reg(ot, t1, reg);
4862 if (mod == 3) {
4863 rm = (modrm & 7) | REX_B(s);
4864 gen_op_mov_v_reg(ot, t0, rm);
4865 } else {
4866 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4867 tcg_gen_mov_tl(a0, cpu_A0);
4868 gen_op_ld_v(ot + s->mem_index, t0, a0);
4869 rm = 0; /* avoid warning */
4870 }
4871 label1 = gen_new_label();
4872 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
4873 gen_extu(ot, t2);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4875 if (mod == 3) {
4876 label2 = gen_new_label();
4877 gen_op_mov_reg_v(ot, R_EAX, t0);
4878 tcg_gen_br(label2);
4879 gen_set_label(label1);
4880 gen_op_mov_reg_v(ot, rm, t1);
4881 gen_set_label(label2);
4882 } else {
4883 tcg_gen_mov_tl(t1, t0);
4884 gen_op_mov_reg_v(ot, R_EAX, t0);
4885 gen_set_label(label1);
4886 /* always store */
4887 gen_op_st_v(ot + s->mem_index, t1, a0);
4888 }
4889 tcg_gen_mov_tl(cpu_cc_src, t0);
4890 tcg_gen_mov_tl(cpu_cc_dst, t2);
4891 s->cc_op = CC_OP_SUBB + ot;
4892 tcg_temp_free(t0);
4893 tcg_temp_free(t1);
4894 tcg_temp_free(t2);
4895 tcg_temp_free(a0);
4896 }
4897 break;
4898 case 0x1c7: /* cmpxchg8b */
4899 modrm = ldub_code(s->pc++);
4900 mod = (modrm >> 6) & 3;
4901 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4902 goto illegal_op;
4903 #ifdef TARGET_X86_64
4904 if (dflag == 2) {
4905 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4906 goto illegal_op;
4907 gen_jmp_im(pc_start - s->cs_base);
4908 if (s->cc_op != CC_OP_DYNAMIC)
4909 gen_op_set_cc_op(s->cc_op);
4910 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4911 gen_helper_cmpxchg16b(cpu_A0);
4912 } else
4913 #endif
4914 {
4915 if (!(s->cpuid_features & CPUID_CX8))
4916 goto illegal_op;
4917 gen_jmp_im(pc_start - s->cs_base);
4918 if (s->cc_op != CC_OP_DYNAMIC)
4919 gen_op_set_cc_op(s->cc_op);
4920 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4921 gen_helper_cmpxchg8b(cpu_A0);
4922 }
4923 s->cc_op = CC_OP_EFLAGS;
4924 break;
4925
4926 /**************************/
4927 /* push/pop */
4928 case 0x50 ... 0x57: /* push */
4929 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4930 gen_push_T0(s);
4931 break;
4932 case 0x58 ... 0x5f: /* pop */
4933 if (CODE64(s)) {
4934 ot = dflag ? OT_QUAD : OT_WORD;
4935 } else {
4936 ot = dflag + OT_WORD;
4937 }
4938 gen_pop_T0(s);
4939 /* NOTE: order is important for pop %sp */
4940 gen_pop_update(s);
4941 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4942 break;
4943 case 0x60: /* pusha */
4944 if (CODE64(s))
4945 goto illegal_op;
4946 gen_pusha(s);
4947 break;
4948 case 0x61: /* popa */
4949 if (CODE64(s))
4950 goto illegal_op;
4951 gen_popa(s);
4952 break;
4953 case 0x68: /* push Iv */
4954 case 0x6a:
4955 if (CODE64(s)) {
4956 ot = dflag ? OT_QUAD : OT_WORD;
4957 } else {
4958 ot = dflag + OT_WORD;
4959 }
4960 if (b == 0x68)
4961 val = insn_get(s, ot);
4962 else
4963 val = (int8_t)insn_get(s, OT_BYTE);
4964 gen_op_movl_T0_im(val);
4965 gen_push_T0(s);
4966 break;
4967 case 0x8f: /* pop Ev */
4968 if (CODE64(s)) {
4969 ot = dflag ? OT_QUAD : OT_WORD;
4970 } else {
4971 ot = dflag + OT_WORD;
4972 }
4973 modrm = ldub_code(s->pc++);
4974 mod = (modrm >> 6) & 3;
4975 gen_pop_T0(s);
4976 if (mod == 3) {
4977 /* NOTE: order is important for pop %sp */
4978 gen_pop_update(s);
4979 rm = (modrm & 7) | REX_B(s);
4980 gen_op_mov_reg_T0(ot, rm);
4981 } else {
4982 /* NOTE: order is important too for MMU exceptions */
4983 s->popl_esp_hack = 1 << ot;
4984 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4985 s->popl_esp_hack = 0;
4986 gen_pop_update(s);
4987 }
4988 break;
4989 case 0xc8: /* enter */
4990 {
4991 int level;
4992 val = lduw_code(s->pc);
4993 s->pc += 2;
4994 level = ldub_code(s->pc++);
4995 gen_enter(s, val, level);
4996 }
4997 break;
4998 case 0xc9: /* leave */
4999 /* XXX: exception not precise (ESP is updated before potential exception) */
5000 if (CODE64(s)) {
5001 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5002 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5003 } else if (s->ss32) {
5004 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5005 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5006 } else {
5007 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5008 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5009 }
5010 gen_pop_T0(s);
5011 if (CODE64(s)) {
5012 ot = dflag ? OT_QUAD : OT_WORD;
5013 } else {
5014 ot = dflag + OT_WORD;
5015 }
5016 gen_op_mov_reg_T0(ot, R_EBP);
5017 gen_pop_update(s);
5018 break;
5019 case 0x06: /* push es */
5020 case 0x0e: /* push cs */
5021 case 0x16: /* push ss */
5022 case 0x1e: /* push ds */
5023 if (CODE64(s))
5024 goto illegal_op;
5025 gen_op_movl_T0_seg(b >> 3);
5026 gen_push_T0(s);
5027 break;
5028 case 0x1a0: /* push fs */
5029 case 0x1a8: /* push gs */
5030 gen_op_movl_T0_seg((b >> 3) & 7);
5031 gen_push_T0(s);
5032 break;
5033 case 0x07: /* pop es */
5034 case 0x17: /* pop ss */
5035 case 0x1f: /* pop ds */
5036 if (CODE64(s))
5037 goto illegal_op;
5038 reg = b >> 3;
5039 gen_pop_T0(s);
5040 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5041 gen_pop_update(s);
5042 if (reg == R_SS) {
5043 /* if reg == SS, inhibit interrupts/trace. */
5044 /* If several instructions disable interrupts, only the
5045 _first_ does it */
5046 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5047 gen_helper_set_inhibit_irq();
5048 s->tf = 0;
5049 }
5050 if (s->is_jmp) {
5051 gen_jmp_im(s->pc - s->cs_base);
5052 gen_eob(s);
5053 }
5054 break;
5055 case 0x1a1: /* pop fs */
5056 case 0x1a9: /* pop gs */
5057 gen_pop_T0(s);
5058 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5059 gen_pop_update(s);
5060 if (s->is_jmp) {
5061 gen_jmp_im(s->pc - s->cs_base);
5062 gen_eob(s);
5063 }
5064 break;
5065
5066 /**************************/
5067 /* mov */
5068 case 0x88:
5069 case 0x89: /* mov Gv, Ev */
5070 if ((b & 1) == 0)
5071 ot = OT_BYTE;
5072 else
5073 ot = dflag + OT_WORD;
5074 modrm = ldub_code(s->pc++);
5075 reg = ((modrm >> 3) & 7) | rex_r;
5076
5077 /* generate a generic store */
5078 gen_ldst_modrm(s, modrm, ot, reg, 1);
5079 break;
5080 case 0xc6:
5081 case 0xc7: /* mov Ev, Iv */
5082 if ((b & 1) == 0)
5083 ot = OT_BYTE;
5084 else
5085 ot = dflag + OT_WORD;
5086 modrm = ldub_code(s->pc++);
5087 mod = (modrm >> 6) & 3;
5088 if (mod != 3) {
5089 s->rip_offset = insn_const_size(ot);
5090 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5091 }
5092 val = insn_get(s, ot);
5093 gen_op_movl_T0_im(val);
5094 if (mod != 3)
5095 gen_op_st_T0_A0(ot + s->mem_index);
5096 else
5097 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5098 break;
5099 case 0x8a:
5100 case 0x8b: /* mov Ev, Gv */
5101 if ((b & 1) == 0)
5102 ot = OT_BYTE;
5103 else
5104 ot = OT_WORD + dflag;
5105 modrm = ldub_code(s->pc++);
5106 reg = ((modrm >> 3) & 7) | rex_r;
5107
5108 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5109 gen_op_mov_reg_T0(ot, reg);
5110 break;
5111 case 0x8e: /* mov seg, Gv */
5112 modrm = ldub_code(s->pc++);
5113 reg = (modrm >> 3) & 7;
5114 if (reg >= 6 || reg == R_CS)
5115 goto illegal_op;
5116 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5117 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5118 if (reg == R_SS) {
5119 /* if reg == SS, inhibit interrupts/trace */
5120 /* If several instructions disable interrupts, only the
5121 _first_ does it */
5122 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5123 gen_helper_set_inhibit_irq();
5124 s->tf = 0;
5125 }
5126 if (s->is_jmp) {
5127 gen_jmp_im(s->pc - s->cs_base);
5128 gen_eob(s);
5129 }
5130 break;
5131 case 0x8c: /* mov Gv, seg */
5132 modrm = ldub_code(s->pc++);
5133 reg = (modrm >> 3) & 7;
5134 mod = (modrm >> 6) & 3;
5135 if (reg >= 6)
5136 goto illegal_op;
5137 gen_op_movl_T0_seg(reg);
5138 if (mod == 3)
5139 ot = OT_WORD + dflag;
5140 else
5141 ot = OT_WORD;
5142 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5143 break;
5144
5145 case 0x1b6: /* movzbS Gv, Eb */
5146 case 0x1b7: /* movzwS Gv, Eb */
5147 case 0x1be: /* movsbS Gv, Eb */
5148 case 0x1bf: /* movswS Gv, Eb */
5149 {
5150 int d_ot;
5151 /* d_ot is the size of destination */
5152 d_ot = dflag + OT_WORD;
5153 /* ot is the size of source */
5154 ot = (b & 1) + OT_BYTE;
5155 modrm = ldub_code(s->pc++);
5156 reg = ((modrm >> 3) & 7) | rex_r;
5157 mod = (modrm >> 6) & 3;
5158 rm = (modrm & 7) | REX_B(s);
5159
5160 if (mod == 3) {
5161 gen_op_mov_TN_reg(ot, 0, rm);
5162 switch(ot | (b & 8)) {
5163 case OT_BYTE:
5164 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5165 break;
5166 case OT_BYTE | 8:
5167 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5168 break;
5169 case OT_WORD:
5170 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5171 break;
5172 default:
5173 case OT_WORD | 8:
5174 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5175 break;
5176 }
5177 gen_op_mov_reg_T0(d_ot, reg);
5178 } else {
5179 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5180 if (b & 8) {
5181 gen_op_lds_T0_A0(ot + s->mem_index);
5182 } else {
5183 gen_op_ldu_T0_A0(ot + s->mem_index);
5184 }
5185 gen_op_mov_reg_T0(d_ot, reg);
5186 }
5187 }
5188 break;
5189
5190 case 0x8d: /* lea */
5191 ot = dflag + OT_WORD;
5192 modrm = ldub_code(s->pc++);
5193 mod = (modrm >> 6) & 3;
5194 if (mod == 3)
5195 goto illegal_op;
5196 reg = ((modrm >> 3) & 7) | rex_r;
5197 /* we must ensure that no segment is added */
5198 s->override = -1;
5199 val = s->addseg;
5200 s->addseg = 0;
5201 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5202 s->addseg = val;
5203 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5204 break;
5205
5206 case 0xa0: /* mov EAX, Ov */
5207 case 0xa1:
5208 case 0xa2: /* mov Ov, EAX */
5209 case 0xa3:
5210 {
5211 target_ulong offset_addr;
5212
5213 if ((b & 1) == 0)
5214 ot = OT_BYTE;
5215 else
5216 ot = dflag + OT_WORD;
5217 #ifdef TARGET_X86_64
5218 if (s->aflag == 2) {
5219 offset_addr = ldq_code(s->pc);
5220 s->pc += 8;
5221 gen_op_movq_A0_im(offset_addr);
5222 } else
5223 #endif
5224 {
5225 if (s->aflag) {
5226 offset_addr = insn_get(s, OT_LONG);
5227 } else {
5228 offset_addr = insn_get(s, OT_WORD);
5229 }
5230 gen_op_movl_A0_im(offset_addr);
5231 }
5232 gen_add_A0_ds_seg(s);
5233 if ((b & 2) == 0) {
5234 gen_op_ld_T0_A0(ot + s->mem_index);
5235 gen_op_mov_reg_T0(ot, R_EAX);
5236 } else {
5237 gen_op_mov_TN_reg(ot, 0, R_EAX);
5238 gen_op_st_T0_A0(ot + s->mem_index);
5239 }
5240 }
5241 break;
5242 case 0xd7: /* xlat */
5243 #ifdef TARGET_X86_64
5244 if (s->aflag == 2) {
5245 gen_op_movq_A0_reg(R_EBX);
5246 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5247 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5248 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5249 } else
5250 #endif
5251 {
5252 gen_op_movl_A0_reg(R_EBX);
5253 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5254 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5255 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5256 if (s->aflag == 0)
5257 gen_op_andl_A0_ffff();
5258 else
5259 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5260 }
5261 gen_add_A0_ds_seg(s);
5262 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5263 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5264 break;
5265 case 0xb0 ... 0xb7: /* mov R, Ib */
5266 val = insn_get(s, OT_BYTE);
5267 gen_op_movl_T0_im(val);
5268 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5269 break;
5270 case 0xb8 ... 0xbf: /* mov R, Iv */
5271 #ifdef TARGET_X86_64
5272 if (dflag == 2) {
5273 uint64_t tmp;
5274 /* 64 bit case */
5275 tmp = ldq_code(s->pc);
5276 s->pc += 8;
5277 reg = (b & 7) | REX_B(s);
5278 gen_movtl_T0_im(tmp);
5279 gen_op_mov_reg_T0(OT_QUAD, reg);
5280 } else
5281 #endif
5282 {
5283 ot = dflag ? OT_LONG : OT_WORD;
5284 val = insn_get(s, ot);
5285 reg = (b & 7) | REX_B(s);
5286 gen_op_movl_T0_im(val);
5287 gen_op_mov_reg_T0(ot, reg);
5288 }
5289 break;
5290
5291 case 0x91 ... 0x97: /* xchg R, EAX */
5292 ot = dflag + OT_WORD;
5293 reg = (b & 7) | REX_B(s);
5294 rm = R_EAX;
5295 goto do_xchg_reg;
5296 case 0x86:
5297 case 0x87: /* xchg Ev, Gv */
5298 if ((b & 1) == 0)
5299 ot = OT_BYTE;
5300 else
5301 ot = dflag + OT_WORD;
5302 modrm = ldub_code(s->pc++);
5303 reg = ((modrm >> 3) & 7) | rex_r;
5304 mod = (modrm >> 6) & 3;
5305 if (mod == 3) {
5306 rm = (modrm & 7) | REX_B(s);
5307 do_xchg_reg:
5308 gen_op_mov_TN_reg(ot, 0, reg);
5309 gen_op_mov_TN_reg(ot, 1, rm);
5310 gen_op_mov_reg_T0(ot, rm);
5311 gen_op_mov_reg_T1(ot, reg);
5312 } else {
5313 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5314 gen_op_mov_TN_reg(ot, 0, reg);
5315 /* for xchg, lock is implicit */
5316 if (!(prefixes & PREFIX_LOCK))
5317 gen_helper_lock();
5318 gen_op_ld_T1_A0(ot + s->mem_index);
5319 gen_op_st_T0_A0(ot + s->mem_index);
5320 if (!(prefixes & PREFIX_LOCK))
5321 gen_helper_unlock();
5322 gen_op_mov_reg_T1(ot, reg);
5323 }
5324 break;
5325 case 0xc4: /* les Gv */
5326 if (CODE64(s))
5327 goto illegal_op;
5328 op = R_ES;
5329 goto do_lxx;
5330 case 0xc5: /* lds Gv */
5331 if (CODE64(s))
5332 goto illegal_op;
5333 op = R_DS;
5334 goto do_lxx;
5335 case 0x1b2: /* lss Gv */
5336 op = R_SS;
5337 goto do_lxx;
5338 case 0x1b4: /* lfs Gv */
5339 op = R_FS;
5340 goto do_lxx;
5341 case 0x1b5: /* lgs Gv */
5342 op = R_GS;
5343 do_lxx:
5344 ot = dflag ? OT_LONG : OT_WORD;
5345 modrm = ldub_code(s->pc++);
5346 reg = ((modrm >> 3) & 7) | rex_r;
5347 mod = (modrm >> 6) & 3;
5348 if (mod == 3)
5349 goto illegal_op;
5350 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5351 gen_op_ld_T1_A0(ot + s->mem_index);
5352 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5353 /* load the segment first to handle exceptions properly */
5354 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5355 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5356 /* then put the data */
5357 gen_op_mov_reg_T1(ot, reg);
5358 if (s->is_jmp) {
5359 gen_jmp_im(s->pc - s->cs_base);
5360 gen_eob(s);
5361 }
5362 break;
5363
5364 /************************/
5365 /* shifts */
5366 case 0xc0:
5367 case 0xc1:
5368 /* shift Ev,Ib */
5369 shift = 2;
5370 grp2:
5371 {
5372 if ((b & 1) == 0)
5373 ot = OT_BYTE;
5374 else
5375 ot = dflag + OT_WORD;
5376
5377 modrm = ldub_code(s->pc++);
5378 mod = (modrm >> 6) & 3;
5379 op = (modrm >> 3) & 7;
5380
5381 if (mod != 3) {
5382 if (shift == 2) {
5383 s->rip_offset = 1;
5384 }
5385 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5386 opreg = OR_TMP0;
5387 } else {
5388 opreg = (modrm & 7) | REX_B(s);
5389 }
5390
5391 /* simpler op */
5392 if (shift == 0) {
5393 gen_shift(s, op, ot, opreg, OR_ECX);
5394 } else {
5395 if (shift == 2) {
5396 shift = ldub_code(s->pc++);
5397 }
5398 gen_shifti(s, op, ot, opreg, shift);
5399 }
5400 }
5401 break;
5402 case 0xd0:
5403 case 0xd1:
5404 /* shift Ev,1 */
5405 shift = 1;
5406 goto grp2;
5407 case 0xd2:
5408 case 0xd3:
5409 /* shift Ev,cl */
5410 shift = 0;
5411 goto grp2;
5412
5413 case 0x1a4: /* shld imm */
5414 op = 0;
5415 shift = 1;
5416 goto do_shiftd;
5417 case 0x1a5: /* shld cl */
5418 op = 0;
5419 shift = 0;
5420 goto do_shiftd;
5421 case 0x1ac: /* shrd imm */
5422 op = 1;
5423 shift = 1;
5424 goto do_shiftd;
5425 case 0x1ad: /* shrd cl */
5426 op = 1;
5427 shift = 0;
5428 do_shiftd:
5429 ot = dflag + OT_WORD;
5430 modrm = ldub_code(s->pc++);
5431 mod = (modrm >> 6) & 3;
5432 rm = (modrm & 7) | REX_B(s);
5433 reg = ((modrm >> 3) & 7) | rex_r;
5434 if (mod != 3) {
5435 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5436 opreg = OR_TMP0;
5437 } else {
5438 opreg = rm;
5439 }
5440 gen_op_mov_TN_reg(ot, 1, reg);
5441
5442 if (shift) {
5443 val = ldub_code(s->pc++);
5444 tcg_gen_movi_tl(cpu_T3, val);
5445 } else {
5446 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5447 }
5448 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5449 break;
5450
5451 /************************/
5452 /* floats */
5453 case 0xd8 ... 0xdf:
5454 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5455 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5456 /* XXX: what to do if illegal op ? */
5457 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5458 break;
5459 }
5460 modrm = ldub_code(s->pc++);
5461 mod = (modrm >> 6) & 3;
5462 rm = modrm & 7;
5463 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5464 if (mod != 3) {
5465 /* memory op */
5466 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5467 switch(op) {
5468 case 0x00 ... 0x07: /* fxxxs */
5469 case 0x10 ... 0x17: /* fixxxl */
5470 case 0x20 ... 0x27: /* fxxxl */
5471 case 0x30 ... 0x37: /* fixxx */
5472 {
5473 int op1;
5474 op1 = op & 7;
5475
5476 switch(op >> 4) {
5477 case 0:
5478 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5479 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5480 gen_helper_flds_FT0(cpu_tmp2_i32);
5481 break;
5482 case 1:
5483 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5484 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5485 gen_helper_fildl_FT0(cpu_tmp2_i32);
5486 break;
5487 case 2:
5488 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5489 (s->mem_index >> 2) - 1);
5490 gen_helper_fldl_FT0(cpu_tmp1_i64);
5491 break;
5492 case 3:
5493 default:
5494 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5495 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5496 gen_helper_fildl_FT0(cpu_tmp2_i32);
5497 break;
5498 }
5499
5500 gen_helper_fp_arith_ST0_FT0(op1);
5501 if (op1 == 3) {
5502 /* fcomp needs pop */
5503 gen_helper_fpop();
5504 }
5505 }
5506 break;
5507 case 0x08: /* flds */
5508 case 0x0a: /* fsts */
5509 case 0x0b: /* fstps */
5510 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5511 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5512 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5513 switch(op & 7) {
5514 case 0:
5515 switch(op >> 4) {
5516 case 0:
5517 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5518 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5519 gen_helper_flds_ST0(cpu_tmp2_i32);
5520 break;
5521 case 1:
5522 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5523 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5524 gen_helper_fildl_ST0(cpu_tmp2_i32);
5525 break;
5526 case 2:
5527 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5528 (s->mem_index >> 2) - 1);
5529 gen_helper_fldl_ST0(cpu_tmp1_i64);
5530 break;
5531 case 3:
5532 default:
5533 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5534 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5535 gen_helper_fildl_ST0(cpu_tmp2_i32);
5536 break;
5537 }
5538 break;
5539 case 1:
5540 /* XXX: the corresponding CPUID bit must be tested ! */
5541 switch(op >> 4) {
5542 case 1:
5543 gen_helper_fisttl_ST0(cpu_tmp2_i32);
5544 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5545 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5546 break;
5547 case 2:
5548 gen_helper_fisttll_ST0(cpu_tmp1_i64);
5549 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5550 (s->mem_index >> 2) - 1);
5551 break;
5552 case 3:
5553 default:
5554 gen_helper_fistt_ST0(cpu_tmp2_i32);
5555 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5556 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5557 break;
5558 }
5559 gen_helper_fpop();
5560 break;
5561 default:
5562 switch(op >> 4) {
5563 case 0:
5564 gen_helper_fsts_ST0(cpu_tmp2_i32);
5565 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5566 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5567 break;
5568 case 1:
5569 gen_helper_fistl_ST0(cpu_tmp2_i32);
5570 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5571 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5572 break;
5573 case 2:
5574 gen_helper_fstl_ST0(cpu_tmp1_i64);
5575 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5576 (s->mem_index >> 2) - 1);
5577 break;
5578 case 3:
5579 default:
5580 gen_helper_fist_ST0(cpu_tmp2_i32);
5581 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5582 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5583 break;
5584 }
5585 if ((op & 7) == 3)
5586 gen_helper_fpop();
5587 break;
5588 }
5589 break;
5590 case 0x0c: /* fldenv mem */
5591 if (s->cc_op != CC_OP_DYNAMIC)
5592 gen_op_set_cc_op(s->cc_op);
5593 gen_jmp_im(pc_start - s->cs_base);
5594 gen_helper_fldenv(
5595 cpu_A0, tcg_const_i32(s->dflag));
5596 break;
5597 case 0x0d: /* fldcw mem */
5598 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5599 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5600 gen_helper_fldcw(cpu_tmp2_i32);
5601 break;
5602 case 0x0e: /* fnstenv mem */
5603 if (s->cc_op != CC_OP_DYNAMIC)
5604 gen_op_set_cc_op(s->cc_op);
5605 gen_jmp_im(pc_start - s->cs_base);
5606 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
5607 break;
5608 case 0x0f: /* fnstcw mem */
5609 gen_helper_fnstcw(cpu_tmp2_i32);
5610 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5611 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5612 break;
5613 case 0x1d: /* fldt mem */
5614 if (s->cc_op != CC_OP_DYNAMIC)
5615 gen_op_set_cc_op(s->cc_op);
5616 gen_jmp_im(pc_start - s->cs_base);
5617 gen_helper_fldt_ST0(cpu_A0);
5618 break;
5619 case 0x1f: /* fstpt mem */
5620 if (s->cc_op != CC_OP_DYNAMIC)
5621 gen_op_set_cc_op(s->cc_op);
5622 gen_jmp_im(pc_start - s->cs_base);
5623 gen_helper_fstt_ST0(cpu_A0);
5624 gen_helper_fpop();
5625 break;
5626 case 0x2c: /* frstor mem */
5627 if (s->cc_op != CC_OP_DYNAMIC)
5628 gen_op_set_cc_op(s->cc_op);
5629 gen_jmp_im(pc_start - s->cs_base);
5630 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
5631 break;
5632 case 0x2e: /* fnsave mem */
5633 if (s->cc_op != CC_OP_DYNAMIC)
5634 gen_op_set_cc_op(s->cc_op);
5635 gen_jmp_im(pc_start - s->cs_base);
5636 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
5637 break;
5638 case 0x2f: /* fnstsw mem */
5639 gen_helper_fnstsw(cpu_tmp2_i32);
5640 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5641 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5642 break;
5643 case 0x3c: /* fbld */
5644 if (s->cc_op != CC_OP_DYNAMIC)
5645 gen_op_set_cc_op(s->cc_op);
5646 gen_jmp_im(pc_start - s->cs_base);
5647 gen_helper_fbld_ST0(cpu_A0);
5648 break;
5649 case 0x3e: /* fbstp */
5650 if (s->cc_op != CC_OP_DYNAMIC)
5651 gen_op_set_cc_op(s->cc_op);
5652 gen_jmp_im(pc_start - s->cs_base);
5653 gen_helper_fbst_ST0(cpu_A0);
5654 gen_helper_fpop();
5655 break;
5656 case 0x3d: /* fildll */
5657 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5658 (s->mem_index >> 2) - 1);
5659 gen_helper_fildll_ST0(cpu_tmp1_i64);
5660 break;
5661 case 0x3f: /* fistpll */
5662 gen_helper_fistll_ST0(cpu_tmp1_i64);
5663 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5664 (s->mem_index >> 2) - 1);
5665 gen_helper_fpop();
5666 break;
5667 default:
5668 goto illegal_op;
5669 }
5670 } else {
5671 /* register float ops */
5672 opreg = rm;
5673
5674 switch(op) {
5675 case 0x08: /* fld sti */
5676 gen_helper_fpush();
5677 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
5678 break;
5679 case 0x09: /* fxchg sti */
5680 case 0x29: /* fxchg4 sti, undocumented op */
5681 case 0x39: /* fxchg7 sti, undocumented op */
5682 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
5683 break;
5684 case 0x0a: /* grp d9/2 */
5685 switch(rm) {
5686 case 0: /* fnop */
5687 /* check exceptions (FreeBSD FPU probe) */
5688 if (s->cc_op != CC_OP_DYNAMIC)
5689 gen_op_set_cc_op(s->cc_op);
5690 gen_jmp_im(pc_start - s->cs_base);
5691 gen_helper_fwait();
5692 break;
5693 default:
5694 goto illegal_op;
5695 }
5696 break;
5697 case 0x0c: /* grp d9/4 */
5698 switch(rm) {
5699 case 0: /* fchs */
5700 gen_helper_fchs_ST0();
5701 break;
5702 case 1: /* fabs */
5703 gen_helper_fabs_ST0();
5704 break;
5705 case 4: /* ftst */
5706 gen_helper_fldz_FT0();
5707 gen_helper_fcom_ST0_FT0();
5708 break;
5709 case 5: /* fxam */
5710 gen_helper_fxam_ST0();
5711 break;
5712 default:
5713 goto illegal_op;
5714 }
5715 break;
5716 case 0x0d: /* grp d9/5 */
5717 {
5718 switch(rm) {
5719 case 0:
5720 gen_helper_fpush();
5721 gen_helper_fld1_ST0();
5722 break;
5723 case 1:
5724 gen_helper_fpush();
5725 gen_helper_fldl2t_ST0();
5726 break;
5727 case 2:
5728 gen_helper_fpush();
5729 gen_helper_fldl2e_ST0();
5730 break;
5731 case 3:
5732 gen_helper_fpush();
5733 gen_helper_fldpi_ST0();
5734 break;
5735 case 4:
5736 gen_helper_fpush();
5737 gen_helper_fldlg2_ST0();
5738 break;
5739 case 5:
5740 gen_helper_fpush();
5741 gen_helper_fldln2_ST0();
5742 break;
5743 case 6:
5744 gen_helper_fpush();
5745 gen_helper_fldz_ST0();
5746 break;
5747 default:
5748 goto illegal_op;
5749 }
5750 }
5751 break;
5752 case 0x0e: /* grp d9/6 */
5753 switch(rm) {
5754 case 0: /* f2xm1 */
5755 gen_helper_f2xm1();
5756 break;
5757 case 1: /* fyl2x */
5758 gen_helper_fyl2x();
5759 break;
5760 case 2: /* fptan */
5761 gen_helper_fptan();
5762 break;
5763 case 3: /* fpatan */
5764 gen_helper_fpatan();
5765 break;
5766 case 4: /* fxtract */
5767 gen_helper_fxtract();
5768 break;
5769 case 5: /* fprem1 */
5770 gen_helper_fprem1();
5771 break;
5772 case 6: /* fdecstp */
5773 gen_helper_fdecstp();
5774 break;
5775 default:
5776 case 7: /* fincstp */
5777 gen_helper_fincstp();
5778 break;
5779 }
5780 break;
5781 case 0x0f: /* grp d9/7 */
5782 switch(rm) {
5783 case 0: /* fprem */
5784 gen_helper_fprem();
5785 break;
5786 case 1: /* fyl2xp1 */
5787 gen_helper_fyl2xp1();
5788 break;
5789 case 2: /* fsqrt */
5790 gen_helper_fsqrt();
5791 break;
5792 case 3: /* fsincos */
5793 gen_helper_fsincos();
5794 break;
5795 case 5: /* fscale */
5796 gen_helper_fscale();
5797 break;
5798 case 4: /* frndint */
5799 gen_helper_frndint();
5800 break;
5801 case 6: /* fsin */
5802 gen_helper_fsin();
5803 break;
5804 default:
5805 case 7: /* fcos */
5806 gen_helper_fcos();
5807 break;
5808 }
5809 break;
5810 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5811 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5812 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5813 {
5814 int op1;
5815
5816 op1 = op & 7;
5817 if (op >= 0x20) {
5818 gen_helper_fp_arith_STN_ST0(op1, opreg);
5819 if (op >= 0x30)
5820 gen_helper_fpop();
5821 } else {
5822 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5823 gen_helper_fp_arith_ST0_FT0(op1);
5824 }
5825 }
5826 break;
5827 case 0x02: /* fcom */
5828 case 0x22: /* fcom2, undocumented op */
5829 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5830 gen_helper_fcom_ST0_FT0();
5831 break;
5832 case 0x03: /* fcomp */
5833 case 0x23: /* fcomp3, undocumented op */
5834 case 0x32: /* fcomp5, undocumented op */
5835 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5836 gen_helper_fcom_ST0_FT0();
5837 gen_helper_fpop();
5838 break;
5839 case 0x15: /* da/5 */
5840 switch(rm) {
5841 case 1: /* fucompp */
5842 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5843 gen_helper_fucom_ST0_FT0();
5844 gen_helper_fpop();
5845 gen_helper_fpop();
5846 break;
5847 default:
5848 goto illegal_op;
5849 }
5850 break;
5851 case 0x1c:
5852 switch(rm) {
5853 case 0: /* feni (287 only, just do nop here) */
5854 break;
5855 case 1: /* fdisi (287 only, just do nop here) */
5856 break;
5857 case 2: /* fclex */
5858 gen_helper_fclex();
5859 break;
5860 case 3: /* fninit */
5861 gen_helper_fninit();
5862 break;
5863 case 4: /* fsetpm (287 only, just do nop here) */
5864 break;
5865 default:
5866 goto illegal_op;
5867 }
5868 break;
5869 case 0x1d: /* fucomi */
5870 if (s->cc_op != CC_OP_DYNAMIC)
5871 gen_op_set_cc_op(s->cc_op);
5872 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5873 gen_helper_fucomi_ST0_FT0();
5874 s->cc_op = CC_OP_EFLAGS;
5875 break;
5876 case 0x1e: /* fcomi */
5877 if (s->cc_op != CC_OP_DYNAMIC)
5878 gen_op_set_cc_op(s->cc_op);
5879 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5880 gen_helper_fcomi_ST0_FT0();
5881 s->cc_op = CC_OP_EFLAGS;
5882 break;
5883 case 0x28: /* ffree sti */
5884 gen_helper_ffree_STN(tcg_const_i32(opreg));
5885 break;
5886 case 0x2a: /* fst sti */
5887 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5888 break;
5889 case 0x2b: /* fstp sti */
5890 case 0x0b: /* fstp1 sti, undocumented op */
5891 case 0x3a: /* fstp8 sti, undocumented op */
5892 case 0x3b: /* fstp9 sti, undocumented op */
5893 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5894 gen_helper_fpop();
5895 break;
5896 case 0x2c: /* fucom st(i) */
5897 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5898 gen_helper_fucom_ST0_FT0();
5899 break;
5900 case 0x2d: /* fucomp st(i) */
5901 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5902 gen_helper_fucom_ST0_FT0();
5903 gen_helper_fpop();
5904 break;
5905 case 0x33: /* de/3 */
5906 switch(rm) {
5907 case 1: /* fcompp */
5908 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5909 gen_helper_fcom_ST0_FT0();
5910 gen_helper_fpop();
5911 gen_helper_fpop();
5912 break;
5913 default:
5914 goto illegal_op;
5915 }
5916 break;
5917 case 0x38: /* ffreep sti, undocumented op */
5918 gen_helper_ffree_STN(tcg_const_i32(opreg));
5919 gen_helper_fpop();
5920 break;
5921 case 0x3c: /* df/4 */
5922 switch(rm) {
5923 case 0:
5924 gen_helper_fnstsw(cpu_tmp2_i32);
5925 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5926 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5927 break;
5928 default:
5929 goto illegal_op;
5930 }
5931 break;
5932 case 0x3d: /* fucomip */
5933 if (s->cc_op != CC_OP_DYNAMIC)
5934 gen_op_set_cc_op(s->cc_op);
5935 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5936 gen_helper_fucomi_ST0_FT0();
5937 gen_helper_fpop();
5938 s->cc_op = CC_OP_EFLAGS;
5939 break;
5940 case 0x3e: /* fcomip */
5941 if (s->cc_op != CC_OP_DYNAMIC)
5942 gen_op_set_cc_op(s->cc_op);
5943 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5944 gen_helper_fcomi_ST0_FT0();
5945 gen_helper_fpop();
5946 s->cc_op = CC_OP_EFLAGS;
5947 break;
5948 case 0x10 ... 0x13: /* fcmovxx */
5949 case 0x18 ... 0x1b:
5950 {
5951 int op1, l1;
5952 static const uint8_t fcmov_cc[8] = {
5953 (JCC_B << 1),
5954 (JCC_Z << 1),
5955 (JCC_BE << 1),
5956 (JCC_P << 1),
5957 };
5958 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5959 l1 = gen_new_label();
5960 gen_jcc1(s, s->cc_op, op1, l1);
5961 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
5962 gen_set_label(l1);
5963 }
5964 break;
5965 default:
5966 goto illegal_op;
5967 }
5968 }
5969 break;
5970 /************************/
5971 /* string ops */
5972
5973 case 0xa4: /* movsS */
5974 case 0xa5:
5975 if ((b & 1) == 0)
5976 ot = OT_BYTE;
5977 else
5978 ot = dflag + OT_WORD;
5979
5980 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5981 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5982 } else {
5983 gen_movs(s, ot);
5984 }
5985 break;
5986
5987 case 0xaa: /* stosS */
5988 case 0xab:
5989 if ((b & 1) == 0)
5990 ot = OT_BYTE;
5991 else
5992 ot = dflag + OT_WORD;
5993
5994 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5995 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5996 } else {
5997 gen_stos(s, ot);
5998 }
5999 break;
6000 case 0xac: /* lodsS */
6001 case 0xad:
6002 if ((b & 1) == 0)
6003 ot = OT_BYTE;
6004 else
6005 ot = dflag + OT_WORD;
6006 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6007 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6008 } else {
6009 gen_lods(s, ot);
6010 }
6011 break;
6012 case 0xae: /* scasS */
6013 case 0xaf:
6014 if ((b & 1) == 0)
6015 ot = OT_BYTE;
6016 else
6017 ot = dflag + OT_WORD;
6018 if (prefixes & PREFIX_REPNZ) {
6019 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6020 } else if (prefixes & PREFIX_REPZ) {
6021 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6022 } else {
6023 gen_scas(s, ot);
6024 s->cc_op = CC_OP_SUBB + ot;
6025 }
6026 break;
6027
6028 case 0xa6: /* cmpsS */
6029 case 0xa7:
6030 if ((b & 1) == 0)
6031 ot = OT_BYTE;
6032 else
6033 ot = dflag + OT_WORD;
6034 if (prefixes & PREFIX_REPNZ) {
6035 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6036 } else if (prefixes & PREFIX_REPZ) {
6037 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6038 } else {
6039 gen_cmps(s, ot);
6040 s->cc_op = CC_OP_SUBB + ot;
6041 }
6042 break;
6043 case 0x6c: /* insS */
6044 case 0x6d:
6045 if ((b & 1) == 0)
6046 ot = OT_BYTE;
6047 else
6048 ot = dflag ? OT_LONG : OT_WORD;
6049 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6050 gen_op_andl_T0_ffff();
6051 gen_check_io(s, ot, pc_start - s->cs_base,
6052 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6053 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6054 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6055 } else {
6056 gen_ins(s, ot);
6057 if (use_icount) {
6058 gen_jmp(s, s->pc - s->cs_base);
6059 }
6060 }
6061 break;
6062 case 0x6e: /* outsS */
6063 case 0x6f:
6064 if ((b & 1) == 0)
6065 ot = OT_BYTE;
6066 else
6067 ot = dflag ? OT_LONG : OT_WORD;
6068 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6069 gen_op_andl_T0_ffff();
6070 gen_check_io(s, ot, pc_start - s->cs_base,
6071 svm_is_rep(prefixes) | 4);
6072 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6073 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6074 } else {
6075 gen_outs(s, ot);
6076 if (use_icount) {
6077 gen_jmp(s, s->pc - s->cs_base);
6078 }
6079 }
6080 break;
6081
6082 /************************/
6083 /* port I/O */
6084
6085 case 0xe4:
6086 case 0xe5:
6087 if ((b & 1) == 0)
6088 ot = OT_BYTE;
6089 else
6090 ot = dflag ? OT_LONG : OT_WORD;
6091 val = ldub_code(s->pc++);
6092 gen_op_movl_T0_im(val);
6093 gen_check_io(s, ot, pc_start - s->cs_base,
6094 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6095 if (use_icount)
6096 gen_io_start();
6097 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6098 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6099 gen_op_mov_reg_T1(ot, R_EAX);
6100 if (use_icount) {
6101 gen_io_end();
6102 gen_jmp(s, s->pc - s->cs_base);
6103 }
6104 break;
6105 case 0xe6:
6106 case 0xe7:
6107 if ((b & 1) == 0)
6108 ot = OT_BYTE;
6109 else
6110 ot = dflag ? OT_LONG : OT_WORD;
6111 val = ldub_code(s->pc++);
6112 gen_op_movl_T0_im(val);
6113 gen_check_io(s, ot, pc_start - s->cs_base,
6114 svm_is_rep(prefixes));
6115 gen_op_mov_TN_reg(ot, 1, R_EAX);
6116
6117 if (use_icount)
6118 gen_io_start();
6119 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6120 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6121 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6122 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6123 if (use_icount) {
6124 gen_io_end();
6125 gen_jmp(s, s->pc - s->cs_base);
6126 }
6127 break;
6128 case 0xec:
6129 case 0xed:
6130 if ((b & 1) == 0)
6131 ot = OT_BYTE;
6132 else
6133 ot = dflag ? OT_LONG : OT_WORD;
6134 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6135 gen_op_andl_T0_ffff();
6136 gen_check_io(s, ot, pc_start - s->cs_base,
6137 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6138 if (use_icount)
6139 gen_io_start();
6140 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6141 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6142 gen_op_mov_reg_T1(ot, R_EAX);
6143 if (use_icount) {
6144 gen_io_end();
6145 gen_jmp(s, s->pc - s->cs_base);
6146 }
6147 break;
6148 case 0xee:
6149 case 0xef:
6150 if ((b & 1) == 0)
6151 ot = OT_BYTE;
6152 else
6153 ot = dflag ? OT_LONG : OT_WORD;
6154 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6155 gen_op_andl_T0_ffff();
6156 gen_check_io(s, ot, pc_start - s->cs_base,
6157 svm_is_rep(prefixes));
6158 gen_op_mov_TN_reg(ot, 1, R_EAX);
6159
6160 if (use_icount)
6161 gen_io_start();
6162 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6163 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6164 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6165 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6166 if (use_icount) {
6167 gen_io_end();
6168 gen_jmp(s, s->pc - s->cs_base);
6169 }
6170 break;
6171
6172 /************************/
6173 /* control */
6174 case 0xc2: /* ret im */
6175 val = ldsw_code(s->pc);
6176 s->pc += 2;
6177 gen_pop_T0(s);
6178 if (CODE64(s) && s->dflag)
6179 s->dflag = 2;
6180 gen_stack_update(s, val + (2 << s->dflag));
6181 if (s->dflag == 0)
6182 gen_op_andl_T0_ffff();
6183 gen_op_jmp_T0();
6184 gen_eob(s);
6185 break;
6186 case 0xc3: /* ret */
6187 gen_pop_T0(s);
6188 gen_pop_update(s);
6189 if (s->dflag == 0)
6190 gen_op_andl_T0_ffff();
6191 gen_op_jmp_T0();
6192 gen_eob(s);
6193 break;
6194 case 0xca: /* lret im */
6195 val = ldsw_code(s->pc);
6196 s->pc += 2;
6197 do_lret:
6198 if (s->pe && !s->vm86) {
6199 if (s->cc_op != CC_OP_DYNAMIC)
6200 gen_op_set_cc_op(s->cc_op);
6201 gen_jmp_im(pc_start - s->cs_base);
6202 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6203 tcg_const_i32(val));
6204 } else {
6205 gen_stack_A0(s);
6206 /* pop offset */
6207 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6208 if (s->dflag == 0)
6209 gen_op_andl_T0_ffff();
6210 /* NOTE: keeping EIP updated is not a problem in case of
6211 exception */
6212 gen_op_jmp_T0();
6213 /* pop selector */
6214 gen_op_addl_A0_im(2 << s->dflag);
6215 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6216 gen_op_movl_seg_T0_vm(R_CS);
6217 /* add stack offset */
6218 gen_stack_update(s, val + (4 << s->dflag));
6219 }
6220 gen_eob(s);
6221 break;
6222 case 0xcb: /* lret */
6223 val = 0;
6224 goto do_lret;
6225 case 0xcf: /* iret */
6226 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6227 if (!s->pe) {
6228 /* real mode */
6229 gen_helper_iret_real(tcg_const_i32(s->dflag));
6230 s->cc_op = CC_OP_EFLAGS;
6231 } else if (s->vm86) {
6232 if (s->iopl != 3) {
6233 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6234 } else {
6235 gen_helper_iret_real(tcg_const_i32(s->dflag));
6236 s->cc_op = CC_OP_EFLAGS;
6237 }
6238 } else {
6239 if (s->cc_op != CC_OP_DYNAMIC)
6240 gen_op_set_cc_op(s->cc_op);
6241 gen_jmp_im(pc_start - s->cs_base);
6242 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6243 tcg_const_i32(s->pc - s->cs_base));
6244 s->cc_op = CC_OP_EFLAGS;
6245 }
6246 gen_eob(s);
6247 break;
6248 case 0xe8: /* call im */
6249 {
6250 if (dflag)
6251 tval = (int32_t)insn_get(s, OT_LONG);
6252 else
6253 tval = (int16_t)insn_get(s, OT_WORD);
6254 next_eip = s->pc - s->cs_base;
6255 tval += next_eip;
6256 if (s->dflag == 0)
6257 tval &= 0xffff;
6258 else if(!CODE64(s))
6259 tval &= 0xffffffff;
6260 gen_movtl_T0_im(next_eip);
6261 gen_push_T0(s);
6262 gen_jmp(s, tval);
6263 }
6264 break;
6265 case 0x9a: /* lcall im */
6266 {
6267 unsigned int selector, offset;
6268
6269 if (CODE64(s))
6270 goto illegal_op;
6271 ot = dflag ? OT_LONG : OT_WORD;
6272 offset = insn_get(s, ot);
6273 selector = insn_get(s, OT_WORD);
6274
6275 gen_op_movl_T0_im(selector);
6276 gen_op_movl_T1_imu(offset);
6277 }
6278 goto do_lcall;
6279 case 0xe9: /* jmp im */
6280 if (dflag)
6281 tval = (int32_t)insn_get(s, OT_LONG);
6282 else
6283 tval = (int16_t)insn_get(s, OT_WORD);
6284 tval += s->pc - s->cs_base;
6285 if (s->dflag == 0)
6286 tval &= 0xffff;
6287 else if(!CODE64(s))
6288 tval &= 0xffffffff;
6289 gen_jmp(s, tval);
6290 break;
6291 case 0xea: /* ljmp im */
6292 {
6293 unsigned int selector, offset;
6294
6295 if (CODE64(s))
6296 goto illegal_op;
6297 ot = dflag ? OT_LONG : OT_WORD;
6298 offset = insn_get(s, ot);
6299 selector = insn_get(s, OT_WORD);
6300
6301 gen_op_movl_T0_im(selector);
6302 gen_op_movl_T1_imu(offset);
6303 }
6304 goto do_ljmp;
6305 case 0xeb: /* jmp Jb */
6306 tval = (int8_t)insn_get(s, OT_BYTE);
6307 tval += s->pc - s->cs_base;
6308 if (s->dflag == 0)
6309 tval &= 0xffff;
6310 gen_jmp(s, tval);
6311 break;
6312 case 0x70 ... 0x7f: /* jcc Jb */
6313 tval = (int8_t)insn_get(s, OT_BYTE);
6314 goto do_jcc;
6315 case 0x180 ... 0x18f: /* jcc Jv */
6316 if (dflag) {
6317 tval = (int32_t)insn_get(s, OT_LONG);
6318 } else {
6319 tval = (int16_t)insn_get(s, OT_WORD);
6320 }
6321 do_jcc:
6322 next_eip = s->pc - s->cs_base;
6323 tval += next_eip;
6324 if (s->dflag == 0)
6325 tval &= 0xffff;
6326 gen_jcc(s, b, tval, next_eip);
6327 break;
6328
6329 case 0x190 ... 0x19f: /* setcc Gv */
6330 modrm = ldub_code(s->pc++);
6331 gen_setcc(s, b);
6332 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6333 break;
6334 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6335 {
6336 int l1;
6337 TCGv t0;
6338
6339 ot = dflag + OT_WORD;
6340 modrm = ldub_code(s->pc++);
6341 reg = ((modrm >> 3) & 7) | rex_r;
6342 mod = (modrm >> 6) & 3;
6343 t0 = tcg_temp_local_new();
6344 if (mod != 3) {
6345 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6346 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6347 } else {
6348 rm = (modrm & 7) | REX_B(s);
6349 gen_op_mov_v_reg(ot, t0, rm);
6350 }
6351 #ifdef TARGET_X86_64
6352 if (ot == OT_LONG) {
6353 /* XXX: specific Intel behaviour ? */
6354 l1 = gen_new_label();
6355 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6356 tcg_gen_mov_tl(cpu_regs[reg], t0);
6357 gen_set_label(l1);
6358 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
6359 } else
6360 #endif
6361 {
6362 l1 = gen_new_label();
6363 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6364 gen_op_mov_reg_v(ot, reg, t0);
6365 gen_set_label(l1);
6366 }
6367 tcg_temp_free(t0);
6368 }
6369 break;
6370
6371 /************************/
6372 /* flags */
6373 case 0x9c: /* pushf */
6374 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6375 if (s->vm86 && s->iopl != 3) {
6376 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6377 } else {
6378 if (s->cc_op != CC_OP_DYNAMIC)
6379 gen_op_set_cc_op(s->cc_op);
6380 gen_helper_read_eflags(cpu_T[0]);
6381 gen_push_T0(s);
6382 }
6383 break;
6384 case 0x9d: /* popf */
6385 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6386 if (s->vm86 && s->iopl != 3) {
6387 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6388 } else {
6389 gen_pop_T0(s);
6390 if (s->cpl == 0) {
6391 if (s->dflag) {
6392 gen_helper_write_eflags(cpu_T[0],
6393 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6394 } else {
6395 gen_helper_write_eflags(cpu_T[0],
6396 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6397 }
6398 } else {
6399 if (s->cpl <= s->iopl) {
6400 if (s->dflag) {
6401 gen_helper_write_eflags(cpu_T[0],
6402 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6403 } else {
6404 gen_helper_write_eflags(cpu_T[0],
6405 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6406 }
6407 } else {
6408 if (s->dflag) {
6409 gen_helper_write_eflags(cpu_T[0],
6410 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6411 } else {
6412 gen_helper_write_eflags(cpu_T[0],
6413 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6414 }
6415 }
6416 }
6417 gen_pop_update(s);
6418 s->cc_op = CC_OP_EFLAGS;
6419 /* abort translation because TF flag may change */
6420 gen_jmp_im(s->pc - s->cs_base);
6421 gen_eob(s);
6422 }
6423 break;
6424 case 0x9e: /* sahf */
6425 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6426 goto illegal_op;
6427 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6428 if (s->cc_op != CC_OP_DYNAMIC)
6429 gen_op_set_cc_op(s->cc_op);
6430 gen_compute_eflags(cpu_cc_src);
6431 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6432 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6433 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6434 s->cc_op = CC_OP_EFLAGS;
6435 break;
6436 case 0x9f: /* lahf */
6437 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6438 goto illegal_op;
6439 if (s->cc_op != CC_OP_DYNAMIC)
6440 gen_op_set_cc_op(s->cc_op);
6441 gen_compute_eflags(cpu_T[0]);
6442 /* Note: gen_compute_eflags() only gives the condition codes */
6443 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6444 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6445 break;
6446 case 0xf5: /* cmc */
6447 if (s->cc_op != CC_OP_DYNAMIC)
6448 gen_op_set_cc_op(s->cc_op);
6449 gen_compute_eflags(cpu_cc_src);
6450 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6451 s->cc_op = CC_OP_EFLAGS;
6452 break;
6453 case 0xf8: /* clc */
6454 if (s->cc_op != CC_OP_DYNAMIC)
6455 gen_op_set_cc_op(s->cc_op);
6456 gen_compute_eflags(cpu_cc_src);
6457 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6458 s->cc_op = CC_OP_EFLAGS;
6459 break;
6460 case 0xf9: /* stc */
6461 if (s->cc_op != CC_OP_DYNAMIC)
6462 gen_op_set_cc_op(s->cc_op);
6463 gen_compute_eflags(cpu_cc_src);
6464 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6465 s->cc_op = CC_OP_EFLAGS;
6466 break;
6467 case 0xfc: /* cld */
6468 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6469 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6470 break;
6471 case 0xfd: /* std */
6472 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6473 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6474 break;
6475
6476 /************************/
6477 /* bit operations */
6478 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6479 ot = dflag + OT_WORD;
6480 modrm = ldub_code(s->pc++);
6481 op = (modrm >> 3) & 7;
6482 mod = (modrm >> 6) & 3;
6483 rm = (modrm & 7) | REX_B(s);
6484 if (mod != 3) {
6485 s->rip_offset = 1;
6486 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6487 gen_op_ld_T0_A0(ot + s->mem_index);
6488 } else {
6489 gen_op_mov_TN_reg(ot, 0, rm);
6490 }
6491 /* load shift */
6492 val = ldub_code(s->pc++);
6493 gen_op_movl_T1_im(val);
6494 if (op < 4)
6495 goto illegal_op;
6496 op -= 4;
6497 goto bt_op;
6498 case 0x1a3: /* bt Gv, Ev */
6499 op = 0;
6500 goto do_btx;
6501 case 0x1ab: /* bts */
6502 op = 1;
6503 goto do_btx;
6504 case 0x1b3: /* btr */
6505 op = 2;
6506 goto do_btx;
6507 case 0x1bb: /* btc */
6508 op = 3;
6509 do_btx:
6510 ot = dflag + OT_WORD;
6511 modrm = ldub_code(s->pc++);
6512 reg = ((modrm >> 3) & 7) | rex_r;
6513 mod = (modrm >> 6) & 3;
6514 rm = (modrm & 7) | REX_B(s);
6515 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6516 if (mod != 3) {
6517 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6518 /* specific case: we need to add a displacement */
6519 gen_exts(ot, cpu_T[1]);
6520 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6521 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6522 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6523 gen_op_ld_T0_A0(ot + s->mem_index);
6524 } else {
6525 gen_op_mov_TN_reg(ot, 0, rm);
6526 }
6527 bt_op:
6528 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6529 switch(op) {
6530 case 0:
6531 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6532 tcg_gen_movi_tl(cpu_cc_dst, 0);
6533 break;
6534 case 1:
6535 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6536 tcg_gen_movi_tl(cpu_tmp0, 1);
6537 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6538 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6539 break;
6540 case 2:
6541 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6542 tcg_gen_movi_tl(cpu_tmp0, 1);
6543 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6544 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6545 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6546 break;
6547 default:
6548 case 3:
6549 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6550 tcg_gen_movi_tl(cpu_tmp0, 1);
6551 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6552 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6553 break;
6554 }
6555 s->cc_op = CC_OP_SARB + ot;
6556 if (op != 0) {
6557 if (mod != 3)
6558 gen_op_st_T0_A0(ot + s->mem_index);
6559 else
6560 gen_op_mov_reg_T0(ot, rm);
6561 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6562 tcg_gen_movi_tl(cpu_cc_dst, 0);
6563 }
6564 break;
6565 case 0x1bc: /* bsf */
6566 case 0x1bd: /* bsr */
6567 {
6568 int label1;
6569 TCGv t0;
6570
6571 ot = dflag + OT_WORD;
6572 modrm = ldub_code(s->pc++);
6573 reg = ((modrm >> 3) & 7) | rex_r;
6574 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
6575 gen_extu(ot, cpu_T[0]);
6576 t0 = tcg_temp_local_new();
6577 tcg_gen_mov_tl(t0, cpu_T[0]);
6578 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6579 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6580 switch(ot) {
6581 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6582 tcg_const_i32(16)); break;
6583 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6584 tcg_const_i32(32)); break;
6585 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6586 tcg_const_i32(64)); break;
6587 }
6588 gen_op_mov_reg_T0(ot, reg);
6589 } else {
6590 label1 = gen_new_label();
6591 tcg_gen_movi_tl(cpu_cc_dst, 0);
6592 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6593 if (b & 1) {
6594 gen_helper_bsr(cpu_T[0], t0);
6595 } else {
6596 gen_helper_bsf(cpu_T[0], t0);
6597 }
6598 gen_op_mov_reg_T0(ot, reg);
6599 tcg_gen_movi_tl(cpu_cc_dst, 1);
6600 gen_set_label(label1);
6601 tcg_gen_discard_tl(cpu_cc_src);
6602 s->cc_op = CC_OP_LOGICB + ot;
6603 }
6604 tcg_temp_free(t0);
6605 }
6606 break;
6607 /************************/
6608 /* bcd */
6609 case 0x27: /* daa */
6610 if (CODE64(s))
6611 goto illegal_op;
6612 if (s->cc_op != CC_OP_DYNAMIC)
6613 gen_op_set_cc_op(s->cc_op);
6614 gen_helper_daa();
6615 s->cc_op = CC_OP_EFLAGS;
6616 break;
6617 case 0x2f: /* das */
6618 if (CODE64(s))
6619 goto illegal_op;
6620 if (s->cc_op != CC_OP_DYNAMIC)
6621 gen_op_set_cc_op(s->cc_op);
6622 gen_helper_das();
6623 s->cc_op = CC_OP_EFLAGS;
6624 break;
6625 case 0x37: /* aaa */
6626 if (CODE64(s))
6627 goto illegal_op;
6628 if (s->cc_op != CC_OP_DYNAMIC)
6629 gen_op_set_cc_op(s->cc_op);
6630 gen_helper_aaa();
6631 s->cc_op = CC_OP_EFLAGS;
6632 break;
6633 case 0x3f: /* aas */
6634 if (CODE64(s))
6635 goto illegal_op;
6636 if (s->cc_op != CC_OP_DYNAMIC)
6637 gen_op_set_cc_op(s->cc_op);
6638 gen_helper_aas();
6639 s->cc_op = CC_OP_EFLAGS;
6640 break;
6641 case 0xd4: /* aam */
6642 if (CODE64(s))
6643 goto illegal_op;
6644 val = ldub_code(s->pc++);
6645 if (val == 0) {
6646 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6647 } else {
6648 gen_helper_aam(tcg_const_i32(val));
6649 s->cc_op = CC_OP_LOGICB;
6650 }
6651 break;
6652 case 0xd5: /* aad */
6653 if (CODE64(s))
6654 goto illegal_op;
6655 val = ldub_code(s->pc++);
6656 gen_helper_aad(tcg_const_i32(val));
6657 s->cc_op = CC_OP_LOGICB;
6658 break;
6659 /************************/
6660 /* misc */
6661 case 0x90: /* nop */
6662 /* XXX: xchg + rex handling */
6663 /* XXX: correct lock test for all insn */
6664 if (prefixes & PREFIX_LOCK)
6665 goto illegal_op;
6666 if (prefixes & PREFIX_REPZ) {
6667 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6668 }
6669 break;
6670 case 0x9b: /* fwait */
6671 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6672 (HF_MP_MASK | HF_TS_MASK)) {
6673 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6674 } else {
6675 if (s->cc_op != CC_OP_DYNAMIC)
6676 gen_op_set_cc_op(s->cc_op);
6677 gen_jmp_im(pc_start - s->cs_base);
6678 gen_helper_fwait();
6679 }
6680 break;
6681 case 0xcc: /* int3 */
6682 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6683 break;
6684 case 0xcd: /* int N */
6685 val = ldub_code(s->pc++);
6686 if (s->vm86 && s->iopl != 3) {
6687 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6688 } else {
6689 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6690 }
6691 break;
6692 case 0xce: /* into */
6693 if (CODE64(s))
6694 goto illegal_op;
6695 if (s->cc_op != CC_OP_DYNAMIC)
6696 gen_op_set_cc_op(s->cc_op);
6697 gen_jmp_im(pc_start - s->cs_base);
6698 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6699 break;
6700 #ifdef WANT_ICEBP
6701 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6702 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6703 #if 1
6704 gen_debug(s, pc_start - s->cs_base);
6705 #else
6706 /* start debug */
6707 tb_flush(cpu_single_env);
6708 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6709 #endif
6710 break;
6711 #endif
6712 case 0xfa: /* cli */
6713 if (!s->vm86) {
6714 if (s->cpl <= s->iopl) {
6715 gen_helper_cli();
6716 } else {
6717 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6718 }
6719 } else {
6720 if (s->iopl == 3) {
6721 gen_helper_cli();
6722 } else {
6723 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6724 }
6725 }
6726 break;
6727 case 0xfb: /* sti */
6728 if (!s->vm86) {
6729 if (s->cpl <= s->iopl) {
6730 gen_sti:
6731 gen_helper_sti();
6732 /* interruptions are enabled only the first insn after sti */
6733 /* If several instructions disable interrupts, only the
6734 _first_ does it */
6735 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6736 gen_helper_set_inhibit_irq();
6737 /* give a chance to handle pending irqs */
6738 gen_jmp_im(s->pc - s->cs_base);
6739 gen_eob(s);
6740 } else {
6741 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6742 }
6743 } else {
6744 if (s->iopl == 3) {
6745 goto gen_sti;
6746 } else {
6747 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6748 }
6749 }
6750 break;
6751 case 0x62: /* bound */
6752 if (CODE64(s))
6753 goto illegal_op;
6754 ot = dflag ? OT_LONG : OT_WORD;
6755 modrm = ldub_code(s->pc++);
6756 reg = (modrm >> 3) & 7;
6757 mod = (modrm >> 6) & 3;
6758 if (mod == 3)
6759 goto illegal_op;
6760 gen_op_mov_TN_reg(ot, 0, reg);
6761 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6762 gen_jmp_im(pc_start - s->cs_base);
6763 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6764 if (ot == OT_WORD)
6765 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6766 else
6767 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6768 break;
6769 case 0x1c8 ... 0x1cf: /* bswap reg */
6770 reg = (b & 7) | REX_B(s);
6771 #ifdef TARGET_X86_64
6772 if (dflag == 2) {
6773 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6774 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6775 gen_op_mov_reg_T0(OT_QUAD, reg);
6776 } else
6777 #endif
6778 {
6779 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6780 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6781 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6782 gen_op_mov_reg_T0(OT_LONG, reg);
6783 }
6784 break;
6785 case 0xd6: /* salc */
6786 if (CODE64(s))
6787 goto illegal_op;
6788 if (s->cc_op != CC_OP_DYNAMIC)
6789 gen_op_set_cc_op(s->cc_op);
6790 gen_compute_eflags_c(cpu_T[0]);
6791 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6792 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6793 break;
6794 case 0xe0: /* loopnz */
6795 case 0xe1: /* loopz */
6796 case 0xe2: /* loop */
6797 case 0xe3: /* jecxz */
6798 {
6799 int l1, l2, l3;
6800
6801 tval = (int8_t)insn_get(s, OT_BYTE);
6802 next_eip = s->pc - s->cs_base;
6803 tval += next_eip;
6804 if (s->dflag == 0)
6805 tval &= 0xffff;
6806
6807 l1 = gen_new_label();
6808 l2 = gen_new_label();
6809 l3 = gen_new_label();
6810 b &= 3;
6811 switch(b) {
6812 case 0: /* loopnz */
6813 case 1: /* loopz */
6814 if (s->cc_op != CC_OP_DYNAMIC)
6815 gen_op_set_cc_op(s->cc_op);
6816 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6817 gen_op_jz_ecx(s->aflag, l3);
6818 gen_compute_eflags(cpu_tmp0);
6819 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6820 if (b == 0) {
6821 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6822 } else {
6823 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6824 }
6825 break;
6826 case 2: /* loop */
6827 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6828 gen_op_jnz_ecx(s->aflag, l1);
6829 break;
6830 default:
6831 case 3: /* jcxz */
6832 gen_op_jz_ecx(s->aflag, l1);
6833 break;
6834 }
6835
6836 gen_set_label(l3);
6837 gen_jmp_im(next_eip);
6838 tcg_gen_br(l2);
6839
6840 gen_set_label(l1);
6841 gen_jmp_im(tval);
6842 gen_set_label(l2);
6843 gen_eob(s);
6844 }
6845 break;
6846 case 0x130: /* wrmsr */
6847 case 0x132: /* rdmsr */
6848 if (s->cpl != 0) {
6849 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6850 } else {
6851 if (s->cc_op != CC_OP_DYNAMIC)
6852 gen_op_set_cc_op(s->cc_op);
6853 gen_jmp_im(pc_start - s->cs_base);
6854 if (b & 2) {
6855 gen_helper_rdmsr();
6856 } else {
6857 gen_helper_wrmsr();
6858 }
6859 }
6860 break;
6861 case 0x131: /* rdtsc */
6862 if (s->cc_op != CC_OP_DYNAMIC)
6863 gen_op_set_cc_op(s->cc_op);
6864 gen_jmp_im(pc_start - s->cs_base);
6865 if (use_icount)
6866 gen_io_start();
6867 gen_helper_rdtsc();
6868 if (use_icount) {
6869 gen_io_end();
6870 gen_jmp(s, s->pc - s->cs_base);
6871 }
6872 break;
6873 case 0x133: /* rdpmc */
6874 if (s->cc_op != CC_OP_DYNAMIC)
6875 gen_op_set_cc_op(s->cc_op);
6876 gen_jmp_im(pc_start - s->cs_base);
6877 gen_helper_rdpmc();
6878 break;
6879 case 0x134: /* sysenter */
6880 /* For Intel SYSENTER is valid on 64-bit */
6881 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6882 goto illegal_op;
6883 if (!s->pe) {
6884 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6885 } else {
6886 if (s->cc_op != CC_OP_DYNAMIC) {
6887 gen_op_set_cc_op(s->cc_op);
6888 s->cc_op = CC_OP_DYNAMIC;
6889 }
6890 gen_jmp_im(pc_start - s->cs_base);
6891 gen_helper_sysenter();
6892 gen_eob(s);
6893 }
6894 break;
6895 case 0x135: /* sysexit */
6896 /* For Intel SYSEXIT is valid on 64-bit */
6897 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6898 goto illegal_op;
6899 if (!s->pe) {
6900 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6901 } else {
6902 if (s->cc_op != CC_OP_DYNAMIC) {
6903 gen_op_set_cc_op(s->cc_op);
6904 s->cc_op = CC_OP_DYNAMIC;
6905 }
6906 gen_jmp_im(pc_start - s->cs_base);
6907 gen_helper_sysexit(tcg_const_i32(dflag));
6908 gen_eob(s);
6909 }
6910 break;
6911 #ifdef TARGET_X86_64
6912 case 0x105: /* syscall */
6913 /* XXX: is it usable in real mode ? */
6914 if (s->cc_op != CC_OP_DYNAMIC) {
6915 gen_op_set_cc_op(s->cc_op);
6916 s->cc_op = CC_OP_DYNAMIC;
6917 }
6918 gen_jmp_im(pc_start - s->cs_base);
6919 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
6920 gen_eob(s);
6921 break;
6922 case 0x107: /* sysret */
6923 if (!s->pe) {
6924 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6925 } else {
6926 if (s->cc_op != CC_OP_DYNAMIC) {
6927 gen_op_set_cc_op(s->cc_op);
6928 s->cc_op = CC_OP_DYNAMIC;
6929 }
6930 gen_jmp_im(pc_start - s->cs_base);
6931 gen_helper_sysret(tcg_const_i32(s->dflag));
6932 /* condition codes are modified only in long mode */
6933 if (s->lma)
6934 s->cc_op = CC_OP_EFLAGS;
6935 gen_eob(s);
6936 }
6937 break;
6938 #endif
6939 case 0x1a2: /* cpuid */
6940 if (s->cc_op != CC_OP_DYNAMIC)
6941 gen_op_set_cc_op(s->cc_op);
6942 gen_jmp_im(pc_start - s->cs_base);
6943 gen_helper_cpuid();
6944 break;
6945 case 0xf4: /* hlt */
6946 if (s->cpl != 0) {
6947 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6948 } else {
6949 if (s->cc_op != CC_OP_DYNAMIC)
6950 gen_op_set_cc_op(s->cc_op);
6951 gen_jmp_im(pc_start - s->cs_base);
6952 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
6953 s->is_jmp = 3;
6954 }
6955 break;
6956 case 0x100:
6957 modrm = ldub_code(s->pc++);
6958 mod = (modrm >> 6) & 3;
6959 op = (modrm >> 3) & 7;
6960 switch(op) {
6961 case 0: /* sldt */
6962 if (!s->pe || s->vm86)
6963 goto illegal_op;
6964 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6965 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6966 ot = OT_WORD;
6967 if (mod == 3)
6968 ot += s->dflag;
6969 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6970 break;
6971 case 2: /* lldt */
6972 if (!s->pe || s->vm86)
6973 goto illegal_op;
6974 if (s->cpl != 0) {
6975 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6976 } else {
6977 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6978 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6979 gen_jmp_im(pc_start - s->cs_base);
6980 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6981 gen_helper_lldt(cpu_tmp2_i32);
6982 }
6983 break;
6984 case 1: /* str */
6985 if (!s->pe || s->vm86)
6986 goto illegal_op;
6987 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6988 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6989 ot = OT_WORD;
6990 if (mod == 3)
6991 ot += s->dflag;
6992 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6993 break;
6994 case 3: /* ltr */
6995 if (!s->pe || s->vm86)
6996 goto illegal_op;
6997 if (s->cpl != 0) {
6998 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6999 } else {
7000 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7001 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7002 gen_jmp_im(pc_start - s->cs_base);
7003 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7004 gen_helper_ltr(cpu_tmp2_i32);
7005 }
7006 break;
7007 case 4: /* verr */
7008 case 5: /* verw */
7009 if (!s->pe || s->vm86)
7010 goto illegal_op;
7011 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7012 if (s->cc_op != CC_OP_DYNAMIC)
7013 gen_op_set_cc_op(s->cc_op);
7014 if (op == 4)
7015 gen_helper_verr(cpu_T[0]);
7016 else
7017 gen_helper_verw(cpu_T[0]);
7018 s->cc_op = CC_OP_EFLAGS;
7019 break;
7020 default:
7021 goto illegal_op;
7022 }
7023 break;
7024 case 0x101:
7025 modrm = ldub_code(s->pc++);
7026 mod = (modrm >> 6) & 3;
7027 op = (modrm >> 3) & 7;
7028 rm = modrm & 7;
7029 switch(op) {
7030 case 0: /* sgdt */
7031 if (mod == 3)
7032 goto illegal_op;
7033 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7034 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7035 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7036 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7037 gen_add_A0_im(s, 2);
7038 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7039 if (!s->dflag)
7040 gen_op_andl_T0_im(0xffffff);
7041 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7042 break;
7043 case 1:
7044 if (mod == 3) {
7045 switch (rm) {
7046 case 0: /* monitor */
7047 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7048 s->cpl != 0)
7049 goto illegal_op;
7050 if (s->cc_op != CC_OP_DYNAMIC)
7051 gen_op_set_cc_op(s->cc_op);
7052 gen_jmp_im(pc_start - s->cs_base);
7053 #ifdef TARGET_X86_64
7054 if (s->aflag == 2) {
7055 gen_op_movq_A0_reg(R_EAX);
7056 } else
7057 #endif
7058 {
7059 gen_op_movl_A0_reg(R_EAX);
7060 if (s->aflag == 0)
7061 gen_op_andl_A0_ffff();
7062 }
7063 gen_add_A0_ds_seg(s);
7064 gen_helper_monitor(cpu_A0);
7065 break;
7066 case 1: /* mwait */
7067 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7068 s->cpl != 0)
7069 goto illegal_op;
7070 if (s->cc_op != CC_OP_DYNAMIC) {
7071 gen_op_set_cc_op(s->cc_op);
7072 s->cc_op = CC_OP_DYNAMIC;
7073 }
7074 gen_jmp_im(pc_start - s->cs_base);
7075 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7076 gen_eob(s);
7077 break;
7078 default:
7079 goto illegal_op;
7080 }
7081 } else { /* sidt */
7082 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7083 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7084 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7085 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7086 gen_add_A0_im(s, 2);
7087 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7088 if (!s->dflag)
7089 gen_op_andl_T0_im(0xffffff);
7090 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7091 }
7092 break;
7093 case 2: /* lgdt */
7094 case 3: /* lidt */
7095 if (mod == 3) {
7096 if (s->cc_op != CC_OP_DYNAMIC)
7097 gen_op_set_cc_op(s->cc_op);
7098 gen_jmp_im(pc_start - s->cs_base);
7099 switch(rm) {
7100 case 0: /* VMRUN */
7101 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7102 goto illegal_op;
7103 if (s->cpl != 0) {
7104 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7105 break;
7106 } else {
7107 gen_helper_vmrun(tcg_const_i32(s->aflag),
7108 tcg_const_i32(s->pc - pc_start));
7109 tcg_gen_exit_tb(0);
7110 s->is_jmp = 3;
7111 }
7112 break;
7113 case 1: /* VMMCALL */
7114 if (!(s->flags & HF_SVME_MASK))
7115 goto illegal_op;
7116 gen_helper_vmmcall();
7117 break;
7118 case 2: /* VMLOAD */
7119 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7120 goto illegal_op;
7121 if (s->cpl != 0) {
7122 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7123 break;
7124 } else {
7125 gen_helper_vmload(tcg_const_i32(s->aflag));
7126 }
7127 break;
7128 case 3: /* VMSAVE */
7129 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7130 goto illegal_op;
7131 if (s->cpl != 0) {
7132 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7133 break;
7134 } else {
7135 gen_helper_vmsave(tcg_const_i32(s->aflag));
7136 }
7137 break;
7138 case 4: /* STGI */
7139 if ((!(s->flags & HF_SVME_MASK) &&
7140 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7141 !s->pe)
7142 goto illegal_op;
7143 if (s->cpl != 0) {
7144 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7145 break;
7146 } else {
7147 gen_helper_stgi();
7148 }
7149 break;
7150 case 5: /* CLGI */
7151 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7152 goto illegal_op;
7153 if (s->cpl != 0) {
7154 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7155 break;
7156 } else {
7157 gen_helper_clgi();
7158 }
7159 break;
7160 case 6: /* SKINIT */
7161 if ((!(s->flags & HF_SVME_MASK) &&
7162 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7163 !s->pe)
7164 goto illegal_op;
7165 gen_helper_skinit();
7166 break;
7167 case 7: /* INVLPGA */
7168 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7169 goto illegal_op;
7170 if (s->cpl != 0) {
7171 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7172 break;
7173 } else {
7174 gen_helper_invlpga(tcg_const_i32(s->aflag));
7175 }
7176 break;
7177 default:
7178 goto illegal_op;
7179 }
7180 } else if (s->cpl != 0) {
7181 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7182 } else {
7183 gen_svm_check_intercept(s, pc_start,
7184 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7185 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7186 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7187 gen_add_A0_im(s, 2);
7188 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7189 if (!s->dflag)
7190 gen_op_andl_T0_im(0xffffff);
7191 if (op == 2) {
7192 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7193 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7194 } else {
7195 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7196 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7197 }
7198 }
7199 break;
7200 case 4: /* smsw */
7201 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7202 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7203 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7204 #else
7205 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7206 #endif
7207 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7208 break;
7209 case 6: /* lmsw */
7210 if (s->cpl != 0) {
7211 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7212 } else {
7213 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7214 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7215 gen_helper_lmsw(cpu_T[0]);
7216 gen_jmp_im(s->pc - s->cs_base);
7217 gen_eob(s);
7218 }
7219 break;
7220 case 7:
7221 if (mod != 3) { /* invlpg */
7222 if (s->cpl != 0) {
7223 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7224 } else {
7225 if (s->cc_op != CC_OP_DYNAMIC)
7226 gen_op_set_cc_op(s->cc_op);
7227 gen_jmp_im(pc_start - s->cs_base);
7228 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7229 gen_helper_invlpg(cpu_A0);
7230 gen_jmp_im(s->pc - s->cs_base);
7231 gen_eob(s);
7232 }
7233 } else {
7234 switch (rm) {
7235 case 0: /* swapgs */
7236 #ifdef TARGET_X86_64
7237 if (CODE64(s)) {
7238 if (s->cpl != 0) {
7239 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7240 } else {
7241 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7242 offsetof(CPUX86State,segs[R_GS].base));
7243 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7244 offsetof(CPUX86State,kernelgsbase));
7245 tcg_gen_st_tl(cpu_T[1], cpu_env,
7246 offsetof(CPUX86State,segs[R_GS].base));
7247 tcg_gen_st_tl(cpu_T[0], cpu_env,
7248 offsetof(CPUX86State,kernelgsbase));
7249 }
7250 } else
7251 #endif
7252 {
7253 goto illegal_op;
7254 }
7255 break;
7256 case 1: /* rdtscp */
7257 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7258 goto illegal_op;
7259 if (s->cc_op != CC_OP_DYNAMIC)
7260 gen_op_set_cc_op(s->cc_op);
7261 gen_jmp_im(pc_start - s->cs_base);
7262 if (use_icount)
7263 gen_io_start();
7264 gen_helper_rdtscp();
7265 if (use_icount) {
7266 gen_io_end();
7267 gen_jmp(s, s->pc - s->cs_base);
7268 }
7269 break;
7270 default:
7271 goto illegal_op;
7272 }
7273 }
7274 break;
7275 default:
7276 goto illegal_op;
7277 }
7278 break;
7279 case 0x108: /* invd */
7280 case 0x109: /* wbinvd */
7281 if (s->cpl != 0) {
7282 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7283 } else {
7284 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7285 /* nothing to do */
7286 }
7287 break;
7288 case 0x63: /* arpl or movslS (x86_64) */
7289 #ifdef TARGET_X86_64
7290 if (CODE64(s)) {
7291 int d_ot;
7292 /* d_ot is the size of destination */
7293 d_ot = dflag + OT_WORD;
7294
7295 modrm = ldub_code(s->pc++);
7296 reg = ((modrm >> 3) & 7) | rex_r;
7297 mod = (modrm >> 6) & 3;
7298 rm = (modrm & 7) | REX_B(s);
7299
7300 if (mod == 3) {
7301 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7302 /* sign extend */
7303 if (d_ot == OT_QUAD)
7304 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7305 gen_op_mov_reg_T0(d_ot, reg);
7306 } else {
7307 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7308 if (d_ot == OT_QUAD) {
7309 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7310 } else {
7311 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7312 }
7313 gen_op_mov_reg_T0(d_ot, reg);
7314 }
7315 } else
7316 #endif
7317 {
7318 int label1;
7319 TCGv t0, t1, t2, a0;
7320
7321 if (!s->pe || s->vm86)
7322 goto illegal_op;
7323 t0 = tcg_temp_local_new();
7324 t1 = tcg_temp_local_new();
7325 t2 = tcg_temp_local_new();
7326 ot = OT_WORD;
7327 modrm = ldub_code(s->pc++);
7328 reg = (modrm >> 3) & 7;
7329 mod = (modrm >> 6) & 3;
7330 rm = modrm & 7;
7331 if (mod != 3) {
7332 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7333 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7334 a0 = tcg_temp_local_new();
7335 tcg_gen_mov_tl(a0, cpu_A0);
7336 } else {
7337 gen_op_mov_v_reg(ot, t0, rm);
7338 TCGV_UNUSED(a0);
7339 }
7340 gen_op_mov_v_reg(ot, t1, reg);
7341 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7342 tcg_gen_andi_tl(t1, t1, 3);
7343 tcg_gen_movi_tl(t2, 0);
7344 label1 = gen_new_label();
7345 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7346 tcg_gen_andi_tl(t0, t0, ~3);
7347 tcg_gen_or_tl(t0, t0, t1);
7348 tcg_gen_movi_tl(t2, CC_Z);
7349 gen_set_label(label1);
7350 if (mod != 3) {
7351 gen_op_st_v(ot + s->mem_index, t0, a0);
7352 tcg_temp_free(a0);
7353 } else {
7354 gen_op_mov_reg_v(ot, rm, t0);
7355 }
7356 if (s->cc_op != CC_OP_DYNAMIC)
7357 gen_op_set_cc_op(s->cc_op);
7358 gen_compute_eflags(cpu_cc_src);
7359 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7360 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7361 s->cc_op = CC_OP_EFLAGS;
7362 tcg_temp_free(t0);
7363 tcg_temp_free(t1);
7364 tcg_temp_free(t2);
7365 }
7366 break;
7367 case 0x102: /* lar */
7368 case 0x103: /* lsl */
7369 {
7370 int label1;
7371 TCGv t0;
7372 if (!s->pe || s->vm86)
7373 goto illegal_op;
7374 ot = dflag ? OT_LONG : OT_WORD;
7375 modrm = ldub_code(s->pc++);
7376 reg = ((modrm >> 3) & 7) | rex_r;
7377 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7378 t0 = tcg_temp_local_new();
7379 if (s->cc_op != CC_OP_DYNAMIC)
7380 gen_op_set_cc_op(s->cc_op);
7381 if (b == 0x102)
7382 gen_helper_lar(t0, cpu_T[0]);
7383 else
7384 gen_helper_lsl(t0, cpu_T[0]);
7385 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7386 label1 = gen_new_label();
7387 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7388 gen_op_mov_reg_v(ot, reg, t0);
7389 gen_set_label(label1);
7390 s->cc_op = CC_OP_EFLAGS;
7391 tcg_temp_free(t0);
7392 }
7393 break;
7394 case 0x118:
7395 modrm = ldub_code(s->pc++);
7396 mod = (modrm >> 6) & 3;
7397 op = (modrm >> 3) & 7;
7398 switch(op) {
7399 case 0: /* prefetchnta */
7400 case 1: /* prefetchnt0 */
7401 case 2: /* prefetchnt0 */
7402 case 3: /* prefetchnt0 */
7403 if (mod == 3)
7404 goto illegal_op;
7405 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7406 /* nothing more to do */
7407 break;
7408 default: /* nop (multi byte) */
7409 gen_nop_modrm(s, modrm);
7410 break;
7411 }
7412 break;
7413 case 0x119 ... 0x11f: /* nop (multi byte) */
7414 modrm = ldub_code(s->pc++);
7415 gen_nop_modrm(s, modrm);
7416 break;
7417 case 0x120: /* mov reg, crN */
7418 case 0x122: /* mov crN, reg */
7419 if (s->cpl != 0) {
7420 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7421 } else {
7422 modrm = ldub_code(s->pc++);
7423 if ((modrm & 0xc0) != 0xc0)
7424 goto illegal_op;
7425 rm = (modrm & 7) | REX_B(s);
7426 reg = ((modrm >> 3) & 7) | rex_r;
7427 if (CODE64(s))
7428 ot = OT_QUAD;
7429 else
7430 ot = OT_LONG;
7431 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7432 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7433 reg = 8;
7434 }
7435 switch(reg) {
7436 case 0:
7437 case 2:
7438 case 3:
7439 case 4:
7440 case 8:
7441 if (s->cc_op != CC_OP_DYNAMIC)
7442 gen_op_set_cc_op(s->cc_op);
7443 gen_jmp_im(pc_start - s->cs_base);
7444 if (b & 2) {
7445 gen_op_mov_TN_reg(ot, 0, rm);
7446 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7447 gen_jmp_im(s->pc - s->cs_base);
7448 gen_eob(s);
7449 } else {
7450 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7451 gen_op_mov_reg_T0(ot, rm);
7452 }
7453 break;
7454 default:
7455 goto illegal_op;
7456 }
7457 }
7458 break;
7459 case 0x121: /* mov reg, drN */
7460 case 0x123: /* mov drN, reg */
7461 if (s->cpl != 0) {
7462 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7463 } else {
7464 modrm = ldub_code(s->pc++);
7465 if ((modrm & 0xc0) != 0xc0)
7466 goto illegal_op;
7467 rm = (modrm & 7) | REX_B(s);
7468 reg = ((modrm >> 3) & 7) | rex_r;
7469 if (CODE64(s))
7470 ot = OT_QUAD;
7471 else
7472 ot = OT_LONG;
7473 /* XXX: do it dynamically with CR4.DE bit */
7474 if (reg == 4 || reg == 5 || reg >= 8)
7475 goto illegal_op;
7476 if (b & 2) {
7477 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7478 gen_op_mov_TN_reg(ot, 0, rm);
7479 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7480 gen_jmp_im(s->pc - s->cs_base);
7481 gen_eob(s);
7482 } else {
7483 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7484 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7485 gen_op_mov_reg_T0(ot, rm);
7486 }
7487 }
7488 break;
7489 case 0x106: /* clts */
7490 if (s->cpl != 0) {
7491 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7492 } else {
7493 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7494 gen_helper_clts();
7495 /* abort block because static cpu state changed */
7496 gen_jmp_im(s->pc - s->cs_base);
7497 gen_eob(s);
7498 }
7499 break;
7500 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7501 case 0x1c3: /* MOVNTI reg, mem */
7502 if (!(s->cpuid_features & CPUID_SSE2))
7503 goto illegal_op;
7504 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7505 modrm = ldub_code(s->pc++);
7506 mod = (modrm >> 6) & 3;
7507 if (mod == 3)
7508 goto illegal_op;
7509 reg = ((modrm >> 3) & 7) | rex_r;
7510 /* generate a generic store */
7511 gen_ldst_modrm(s, modrm, ot, reg, 1);
7512 break;
7513 case 0x1ae:
7514 modrm = ldub_code(s->pc++);
7515 mod = (modrm >> 6) & 3;
7516 op = (modrm >> 3) & 7;
7517 switch(op) {
7518 case 0: /* fxsave */
7519 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7520 (s->prefix & PREFIX_LOCK))
7521 goto illegal_op;
7522 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7523 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7524 break;
7525 }
7526 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7527 if (s->cc_op != CC_OP_DYNAMIC)
7528 gen_op_set_cc_op(s->cc_op);
7529 gen_jmp_im(pc_start - s->cs_base);
7530 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
7531 break;
7532 case 1: /* fxrstor */
7533 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7534 (s->prefix & PREFIX_LOCK))
7535 goto illegal_op;
7536 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7537 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7538 break;
7539 }
7540 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7541 if (s->cc_op != CC_OP_DYNAMIC)
7542 gen_op_set_cc_op(s->cc_op);
7543 gen_jmp_im(pc_start - s->cs_base);
7544 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
7545 break;
7546 case 2: /* ldmxcsr */
7547 case 3: /* stmxcsr */
7548 if (s->flags & HF_TS_MASK) {
7549 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7550 break;
7551 }
7552 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7553 mod == 3)
7554 goto illegal_op;
7555 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7556 if (op == 2) {
7557 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7558 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7559 } else {
7560 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7561 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7562 }
7563 break;
7564 case 5: /* lfence */
7565 case 6: /* mfence */
7566 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7567 goto illegal_op;
7568 break;
7569 case 7: /* sfence / clflush */
7570 if ((modrm & 0xc7) == 0xc0) {
7571 /* sfence */
7572 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7573 if (!(s->cpuid_features & CPUID_SSE))
7574 goto illegal_op;
7575 } else {
7576 /* clflush */
7577 if (!(s->cpuid_features & CPUID_CLFLUSH))
7578 goto illegal_op;
7579 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7580 }
7581 break;
7582 default:
7583 goto illegal_op;
7584 }
7585 break;
7586 case 0x10d: /* 3DNow! prefetch(w) */
7587 modrm = ldub_code(s->pc++);
7588 mod = (modrm >> 6) & 3;
7589 if (mod == 3)
7590 goto illegal_op;
7591 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7592 /* ignore for now */
7593 break;
7594 case 0x1aa: /* rsm */
7595 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7596 if (!(s->flags & HF_SMM_MASK))
7597 goto illegal_op;
7598 if (s->cc_op != CC_OP_DYNAMIC) {
7599 gen_op_set_cc_op(s->cc_op);
7600 s->cc_op = CC_OP_DYNAMIC;
7601 }
7602 gen_jmp_im(s->pc - s->cs_base);
7603 gen_helper_rsm();
7604 gen_eob(s);
7605 break;
7606 case 0x1b8: /* SSE4.2 popcnt */
7607 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7608 PREFIX_REPZ)
7609 goto illegal_op;
7610 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7611 goto illegal_op;
7612
7613 modrm = ldub_code(s->pc++);
7614 reg = ((modrm >> 3) & 7);
7615
7616 if (s->prefix & PREFIX_DATA)
7617 ot = OT_WORD;
7618 else if (s->dflag != 2)
7619 ot = OT_LONG;
7620 else
7621 ot = OT_QUAD;
7622
7623 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7624 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7625 gen_op_mov_reg_T0(ot, reg);
7626
7627 s->cc_op = CC_OP_EFLAGS;
7628 break;
7629 case 0x10e ... 0x10f:
7630 /* 3DNow! instructions, ignore prefixes */
7631 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7632 case 0x110 ... 0x117:
7633 case 0x128 ... 0x12f:
7634 case 0x138 ... 0x13a:
7635 case 0x150 ... 0x179:
7636 case 0x17c ... 0x17f:
7637 case 0x1c2:
7638 case 0x1c4 ... 0x1c6:
7639 case 0x1d0 ... 0x1fe:
7640 gen_sse(s, b, pc_start, rex_r);
7641 break;
7642 default:
7643 goto illegal_op;
7644 }
7645 /* lock generation */
7646 if (s->prefix & PREFIX_LOCK)
7647 gen_helper_unlock();
7648 return s->pc;
7649 illegal_op:
7650 if (s->prefix & PREFIX_LOCK)
7651 gen_helper_unlock();
7652 /* XXX: ensure that no lock was generated */
7653 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7654 return s->pc;
7655 }
7656
7657 void optimize_flags_init(void)
7658 {
7659 #if TCG_TARGET_REG_BITS == 32
7660 assert(sizeof(CCTable) == (1 << 3));
7661 #else
7662 assert(sizeof(CCTable) == (1 << 4));
7663 #endif
7664 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7665 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7666 offsetof(CPUState, cc_op), "cc_op");
7667 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7668 "cc_src");
7669 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7670 "cc_dst");
7671 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
7672 "cc_tmp");
7673
7674 #ifdef TARGET_X86_64
7675 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7676 offsetof(CPUState, regs[R_EAX]), "rax");
7677 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7678 offsetof(CPUState, regs[R_ECX]), "rcx");
7679 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7680 offsetof(CPUState, regs[R_EDX]), "rdx");
7681 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7682 offsetof(CPUState, regs[R_EBX]), "rbx");
7683 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7684 offsetof(CPUState, regs[R_ESP]), "rsp");
7685 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7686 offsetof(CPUState, regs[R_EBP]), "rbp");
7687 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7688 offsetof(CPUState, regs[R_ESI]), "rsi");
7689 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7690 offsetof(CPUState, regs[R_EDI]), "rdi");
7691 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7692 offsetof(CPUState, regs[8]), "r8");
7693 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7694 offsetof(CPUState, regs[9]), "r9");
7695 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7696 offsetof(CPUState, regs[10]), "r10");
7697 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7698 offsetof(CPUState, regs[11]), "r11");
7699 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7700 offsetof(CPUState, regs[12]), "r12");
7701 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7702 offsetof(CPUState, regs[13]), "r13");
7703 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7704 offsetof(CPUState, regs[14]), "r14");
7705 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7706 offsetof(CPUState, regs[15]), "r15");
7707 #else
7708 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7709 offsetof(CPUState, regs[R_EAX]), "eax");
7710 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7711 offsetof(CPUState, regs[R_ECX]), "ecx");
7712 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7713 offsetof(CPUState, regs[R_EDX]), "edx");
7714 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7715 offsetof(CPUState, regs[R_EBX]), "ebx");
7716 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7717 offsetof(CPUState, regs[R_ESP]), "esp");
7718 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7719 offsetof(CPUState, regs[R_EBP]), "ebp");
7720 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7721 offsetof(CPUState, regs[R_ESI]), "esi");
7722 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7723 offsetof(CPUState, regs[R_EDI]), "edi");
7724 #endif
7725
7726 /* register helpers */
7727 #define GEN_HELPER 2
7728 #include "helper.h"
7729 }
7730
7731 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7732 basic block 'tb'. If search_pc is TRUE, also generate PC
7733 information for each intermediate instruction. */
7734 static inline void gen_intermediate_code_internal(CPUState *env,
7735 TranslationBlock *tb,
7736 int search_pc)
7737 {
7738 DisasContext dc1, *dc = &dc1;
7739 target_ulong pc_ptr;
7740 uint16_t *gen_opc_end;
7741 CPUBreakpoint *bp;
7742 int j, lj, cflags;
7743 uint64_t flags;
7744 target_ulong pc_start;
7745 target_ulong cs_base;
7746 int num_insns;
7747 int max_insns;
7748
7749 /* generate intermediate code */
7750 pc_start = tb->pc;
7751 cs_base = tb->cs_base;
7752 flags = tb->flags;
7753 cflags = tb->cflags;
7754
7755 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7756 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7757 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7758 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7759 dc->f_st = 0;
7760 dc->vm86 = (flags >> VM_SHIFT) & 1;
7761 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7762 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7763 dc->tf = (flags >> TF_SHIFT) & 1;
7764 dc->singlestep_enabled = env->singlestep_enabled;
7765 dc->cc_op = CC_OP_DYNAMIC;
7766 dc->cs_base = cs_base;
7767 dc->tb = tb;
7768 dc->popl_esp_hack = 0;
7769 /* select memory access functions */
7770 dc->mem_index = 0;
7771 if (flags & HF_SOFTMMU_MASK) {
7772 if (dc->cpl == 3)
7773 dc->mem_index = 2 * 4;
7774 else
7775 dc->mem_index = 1 * 4;
7776 }
7777 dc->cpuid_features = env->cpuid_features;
7778 dc->cpuid_ext_features = env->cpuid_ext_features;
7779 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7780 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7781 #ifdef TARGET_X86_64
7782 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7783 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7784 #endif
7785 dc->flags = flags;
7786 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7787 (flags & HF_INHIBIT_IRQ_MASK)
7788 #ifndef CONFIG_SOFTMMU
7789 || (flags & HF_SOFTMMU_MASK)
7790 #endif
7791 );
7792 #if 0
7793 /* check addseg logic */
7794 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7795 printf("ERROR addseg\n");
7796 #endif
7797
7798 cpu_T[0] = tcg_temp_new();
7799 cpu_T[1] = tcg_temp_new();
7800 cpu_A0 = tcg_temp_new();
7801 cpu_T3 = tcg_temp_new();
7802
7803 cpu_tmp0 = tcg_temp_new();
7804 cpu_tmp1_i64 = tcg_temp_new_i64();
7805 cpu_tmp2_i32 = tcg_temp_new_i32();
7806 cpu_tmp3_i32 = tcg_temp_new_i32();
7807 cpu_tmp4 = tcg_temp_new();
7808 cpu_tmp5 = tcg_temp_new();
7809 cpu_ptr0 = tcg_temp_new_ptr();
7810 cpu_ptr1 = tcg_temp_new_ptr();
7811
7812 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7813
7814 dc->is_jmp = DISAS_NEXT;
7815 pc_ptr = pc_start;
7816 lj = -1;
7817 num_insns = 0;
7818 max_insns = tb->cflags & CF_COUNT_MASK;
7819 if (max_insns == 0)
7820 max_insns = CF_COUNT_MASK;
7821
7822 gen_icount_start();
7823 for(;;) {
7824 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7825 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7826 if (bp->pc == pc_ptr &&
7827 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7828 gen_debug(dc, pc_ptr - dc->cs_base);
7829 break;
7830 }
7831 }
7832 }
7833 if (search_pc) {
7834 j = gen_opc_ptr - gen_opc_buf;
7835 if (lj < j) {
7836 lj++;
7837 while (lj < j)
7838 gen_opc_instr_start[lj++] = 0;
7839 }
7840 gen_opc_pc[lj] = pc_ptr;
7841 gen_opc_cc_op[lj] = dc->cc_op;
7842 gen_opc_instr_start[lj] = 1;
7843 gen_opc_icount[lj] = num_insns;
7844 }
7845 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7846 gen_io_start();
7847
7848 pc_ptr = disas_insn(dc, pc_ptr);
7849 num_insns++;
7850 /* stop translation if indicated */
7851 if (dc->is_jmp)
7852 break;
7853 /* if single step mode, we generate only one instruction and
7854 generate an exception */
7855 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7856 the flag and abort the translation to give the irqs a
7857 change to be happen */
7858 if (dc->tf || dc->singlestep_enabled ||
7859 (flags & HF_INHIBIT_IRQ_MASK)) {
7860 gen_jmp_im(pc_ptr - dc->cs_base);
7861 gen_eob(dc);
7862 break;
7863 }
7864 /* if too long translation, stop generation too */
7865 if (gen_opc_ptr >= gen_opc_end ||
7866 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7867 num_insns >= max_insns) {
7868 gen_jmp_im(pc_ptr - dc->cs_base);
7869 gen_eob(dc);
7870 break;
7871 }
7872 if (singlestep) {
7873 gen_jmp_im(pc_ptr - dc->cs_base);
7874 gen_eob(dc);
7875 break;
7876 }
7877 }
7878 if (tb->cflags & CF_LAST_IO)
7879 gen_io_end();
7880 gen_icount_end(tb, num_insns);
7881 *gen_opc_ptr = INDEX_op_end;
7882 /* we don't forget to fill the last values */
7883 if (search_pc) {
7884 j = gen_opc_ptr - gen_opc_buf;
7885 lj++;
7886 while (lj <= j)
7887 gen_opc_instr_start[lj++] = 0;
7888 }
7889
7890 #ifdef DEBUG_DISAS
7891 log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP);
7892 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7893 int disas_flags;
7894 qemu_log("----------------\n");
7895 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7896 #ifdef TARGET_X86_64
7897 if (dc->code64)
7898 disas_flags = 2;
7899 else
7900 #endif
7901 disas_flags = !dc->code32;
7902 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7903 qemu_log("\n");
7904 }
7905 #endif
7906
7907 if (!search_pc) {
7908 tb->size = pc_ptr - pc_start;
7909 tb->icount = num_insns;
7910 }
7911 }
7912
7913 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7914 {
7915 gen_intermediate_code_internal(env, tb, 0);
7916 }
7917
7918 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7919 {
7920 gen_intermediate_code_internal(env, tb, 1);
7921 }
7922
7923 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7924 unsigned long searched_pc, int pc_pos, void *puc)
7925 {
7926 int cc_op;
7927 #ifdef DEBUG_DISAS
7928 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7929 int i;
7930 qemu_log("RESTORE:\n");
7931 for(i = 0;i <= pc_pos; i++) {
7932 if (gen_opc_instr_start[i]) {
7933 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7934 }
7935 }
7936 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7937 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7938 (uint32_t)tb->cs_base);
7939 }
7940 #endif
7941 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7942 cc_op = gen_opc_cc_op[pc_pos];
7943 if (cc_op != CC_OP_DYNAMIC)
7944 env->cc_op = cc_op;
7945 }
Anthony Liguori's QEMU queue