hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31
  32 typedef PCIHostState I440FXState;
  33
  34 typedef struct PIIX3State {
  35     PCIDevice dev;
  36     int pci_irq_levels[4];
  37     qemu_irq *pic;
  38 } PIIX3State;
  39
  40 struct PCII440FXState {
  41     PCIDevice dev;
  42     target_phys_addr_t isa_page_descs[384 / 4];
  43     uint8_t smm_enabled;
  44     PIIX3State *piix3;
  45 };
  46
  47 static void piix3_set_irq(void *opaque, int irq_num, int level);
  48
  49 /* return the global irq number corresponding to a given device irq
  50    pin. We could also use the bus number to have a more precise
  51    mapping. */
  52 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  53 {
  54     int slot_addend;
  55     slot_addend = (pci_dev->devfn >> 3) - 1;
  56     return (irq_num + slot_addend) & 3;
  57 }
  58
  59 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  60 {
  61     uint32_t addr;
  62
  63     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  64     switch(r) {
  65     case 3:
  66         /* RAM */
  67         cpu_register_physical_memory(start, end - start,
  68                                      start);
  69         break;
  70     case 1:
  71         /* ROM (XXX: not quite correct) */
  72         cpu_register_physical_memory(start, end - start,
  73                                      start | IO_MEM_ROM);
  74         break;
  75     case 2:
  76     case 0:
  77         /* XXX: should distinguish read/write cases */
  78         for(addr = start; addr < end; addr += 4096) {
  79             cpu_register_physical_memory(addr, 4096,
  80                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  81         }
  82         break;
  83     }
  84 }
  85
  86 static void i440fx_update_memory_mappings(PCII440FXState *d)
  87 {
  88     int i, r;
  89     uint32_t smram, addr;
  90
  91     update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
  92     for(i = 0; i < 12; i++) {
  93         r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
  94         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
  95     }
  96     smram = d->dev.config[0x72];
  97     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
  98         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
  99     } else {
 100         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 101             cpu_register_physical_memory(addr, 4096,
 102                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 103         }
 104     }
 105 }
 106
 107 void i440fx_set_smm(PCII440FXState *d, int val)
 108 {
 109     val = (val != 0);
 110     if (d->smm_enabled != val) {
 111         d->smm_enabled = val;
 112         i440fx_update_memory_mappings(d);
 113     }
 114 }
 115
 116
 117 /* XXX: suppress when better memory API. We make the assumption that
 118    no device (in particular the VGA) changes the memory mappings in
 119    the 0xa0000-0x100000 range */
 120 void i440fx_init_memory_mappings(PCII440FXState *d)
 121 {
 122     int i;
 123     for(i = 0; i < 96; i++) {
 124         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 125     }
 126 }
 127
 128 static void i440fx_write_config(PCIDevice *dev,
 129                                 uint32_t address, uint32_t val, int len)
 130 {
 131     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 132
 133     /* XXX: implement SMRAM.D_LOCK */
 134     pci_default_write_config(dev, address, val, len);
 135     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 136         i440fx_update_memory_mappings(d);
 137 }
 138
 139 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 140 {
 141     PCII440FXState *d = opaque;
 142     int ret, i;
 143
 144     ret = pci_device_load(&d->dev, f);
 145     if (ret < 0)
 146         return ret;
 147     i440fx_update_memory_mappings(d);
 148     qemu_get_8s(f, &d->smm_enabled);
 149
 150     if (version_id == 2)
 151         for (i = 0; i < 4; i++)
 152             d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 153
 154     return 0;
 155 }
 156
 157 static int i440fx_post_load(void *opaque, int version_id)
 158 {
 159     PCII440FXState *d = opaque;
 160
 161     i440fx_update_memory_mappings(d);
 162     return 0;
 163 }
 164
 165 static const VMStateDescription vmstate_i440fx = {
 166     .name = "I440FX",
 167     .version_id = 3,
 168     .minimum_version_id = 3,
 169     .minimum_version_id_old = 1,
 170     .load_state_old = i440fx_load_old,
 171     .post_load = i440fx_post_load,
 172     .fields      = (VMStateField []) {
 173         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 174         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 175         VMSTATE_END_OF_LIST()
 176     }
 177 };
 178
 179 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 180 {
 181     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 182
 183     pci_host_config_register_ioport(0xcf8, s);
 184
 185     pci_host_data_register_ioport(0xcfc, s);
 186     return 0;
 187 }
 188
 189 static int i440fx_initfn(PCIDevice *dev)
 190 {
 191     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 192
 193     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 194     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 195     d->dev.config[0x08] = 0x02; // revision
 196     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 197     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 198
 199     d->dev.config[0x72] = 0x02; /* SMRAM */
 200
 201     vmstate_register(0, &vmstate_i440fx, d);
 202     return 0;
 203 }
 204
 205 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 206 {
 207     DeviceState *dev;
 208     PCIBus *b;
 209     PCIDevice *d;
 210     I440FXState *s;
 211     PIIX3State *piix3;
 212
 213     dev = qdev_create(NULL, "i440FX-pcihost");
 214     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 215     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 216     s->bus = b;
 217     qdev_init_nofail(dev);
 218
 219     d = pci_create_simple(b, 0, "i440FX");
 220     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 221
 222     piix3 = DO_UPCAST(PIIX3State, dev,
 223                                  pci_create_simple(b, -1, "PIIX3"));
 224     piix3->pic = pic;
 225     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
 226     (*pi440fx_state)->piix3 = piix3;
 227
 228     *piix3_devfn = piix3->dev.devfn;
 229
 230     return b;
 231 }
 232
 233 /* PIIX3 PCI to ISA bridge */
 234
 235 static void piix3_set_irq(void *opaque, int irq_num, int level)
 236 {
 237     int i, pic_irq, pic_level;
 238     PIIX3State *piix3 = opaque;
 239
 240     piix3->pci_irq_levels[irq_num] = level;
 241
 242     /* now we change the pic irq level according to the piix irq mappings */
 243     /* XXX: optimize */
 244     pic_irq = piix3->dev.config[0x60 + irq_num];
 245     if (pic_irq < 16) {
 246         /* The pic level is the logical OR of all the PCI irqs mapped
 247            to it */
 248         pic_level = 0;
 249         for (i = 0; i < 4; i++) {
 250             if (pic_irq == piix3->dev.config[0x60 + i])
 251                 pic_level |= piix3->pci_irq_levels[i];
 252         }
 253         qemu_set_irq(piix3->pic[pic_irq], pic_level);
 254     }
 255 }
 256
 257 static void piix3_reset(void *opaque)
 258 {
 259     PIIX3State *d = opaque;
 260     uint8_t *pci_conf = d->dev.config;
 261
 262     pci_conf[0x04] = 0x07; // master, memory and I/O
 263     pci_conf[0x05] = 0x00;
 264     pci_conf[0x06] = 0x00;
 265     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 266     pci_conf[0x4c] = 0x4d;
 267     pci_conf[0x4e] = 0x03;
 268     pci_conf[0x4f] = 0x00;
 269     pci_conf[0x60] = 0x80;
 270     pci_conf[0x61] = 0x80;
 271     pci_conf[0x62] = 0x80;
 272     pci_conf[0x63] = 0x80;
 273     pci_conf[0x69] = 0x02;
 274     pci_conf[0x70] = 0x80;
 275     pci_conf[0x76] = 0x0c;
 276     pci_conf[0x77] = 0x0c;
 277     pci_conf[0x78] = 0x02;
 278     pci_conf[0x79] = 0x00;
 279     pci_conf[0x80] = 0x00;
 280     pci_conf[0x82] = 0x00;
 281     pci_conf[0xa0] = 0x08;
 282     pci_conf[0xa2] = 0x00;
 283     pci_conf[0xa3] = 0x00;
 284     pci_conf[0xa4] = 0x00;
 285     pci_conf[0xa5] = 0x00;
 286     pci_conf[0xa6] = 0x00;
 287     pci_conf[0xa7] = 0x00;
 288     pci_conf[0xa8] = 0x0f;
 289     pci_conf[0xaa] = 0x00;
 290     pci_conf[0xab] = 0x00;
 291     pci_conf[0xac] = 0x00;
 292     pci_conf[0xae] = 0x00;
 293
 294     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 295 }
 296
 297 static const VMStateDescription vmstate_piix3 = {
 298     .name = "PIIX3",
 299     .version_id = 3,
 300     .minimum_version_id = 2,
 301     .minimum_version_id_old = 2,
 302     .fields      = (VMStateField []) {
 303         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 304         VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
 305         VMSTATE_END_OF_LIST()
 306     }
 307 };
 308
 309 static int piix3_initfn(PCIDevice *dev)
 310 {
 311     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 312     uint8_t *pci_conf;
 313
 314     isa_bus_new(&d->dev.qdev);
 315     vmstate_register(0, &vmstate_piix3, d);
 316
 317     pci_conf = d->dev.config;
 318     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 319     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 320     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 321     pci_conf[PCI_HEADER_TYPE] =
 322         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 323
 324     qemu_register_reset(piix3_reset, d);
 325     return 0;
 326 }
 327
 328 static PCIDeviceInfo i440fx_info[] = {
 329     {
 330         .qdev.name    = "i440FX",
 331         .qdev.desc    = "Host bridge",
 332         .qdev.size    = sizeof(PCII440FXState),
 333         .qdev.no_user = 1,
 334         .init         = i440fx_initfn,
 335         .config_write = i440fx_write_config,
 336     },{
 337         .qdev.name    = "PIIX3",
 338         .qdev.desc    = "ISA bridge",
 339         .qdev.size    = sizeof(PIIX3State),
 340         .qdev.no_user = 1,
 341         .init         = piix3_initfn,
 342     },{
 343         /* end of list */
 344     }
 345 };
 346
 347 static SysBusDeviceInfo i440fx_pcihost_info = {
 348     .init         = i440fx_pcihost_initfn,
 349     .qdev.name    = "i440FX-pcihost",
 350     .qdev.size    = sizeof(I440FXState),
 351     .qdev.no_user = 1,
 352 };
 353
 354 static void i440fx_register(void)
 355 {
 356     sysbus_register_withprop(&i440fx_pcihost_info);
 357     pci_qdev_register_many(i440fx_info);
 358 }
 359 device_init(i440fx_register);