hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "devices.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "pci.h"
  32 #include "sh_pci.h"
  33 #include "net.h"
  34 #include "sh7750_regs.h"
  35 #include "ide.h"
  36 #include "loader.h"
  37 #include "usb.h"
  38 #include "flash.h"
  39
  40 #define FLASH_BASE 0x00000000
  41 #define FLASH_SIZE 0x02000000
  42
  43 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  44 #define SDRAM_SIZE 0x04000000
  45
  46 #define SM501_VRAM_SIZE 0x800000
  47
  48 #define BOOT_PARAMS_OFFSET 0x0010000
  49 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  50 #define LINUX_LOAD_OFFSET  0x0800000
  51 #define INITRD_LOAD_OFFSET 0x1800000
  52
  53 #define PA_IRLMSK       0x00
  54 #define PA_POWOFF       0x30
  55 #define PA_VERREG       0x32
  56 #define PA_OUTPORT      0x36
  57
  58 typedef struct {
  59     uint16_t bcr;
  60     uint16_t irlmsk;
  61     uint16_t irlmon;
  62     uint16_t cfctl;
  63     uint16_t cfpow;
  64     uint16_t dispctl;
  65     uint16_t sdmpow;
  66     uint16_t rtcce;
  67     uint16_t pcicd;
  68     uint16_t voyagerrts;
  69     uint16_t cfrst;
  70     uint16_t admrts;
  71     uint16_t extrst;
  72     uint16_t cfcdintclr;
  73     uint16_t keyctlclr;
  74     uint16_t pad0;
  75     uint16_t pad1;
  76     uint16_t verreg;
  77     uint16_t inport;
  78     uint16_t outport;
  79     uint16_t bverreg;
  80
  81 /* output pin */
  82     qemu_irq irl;
  83 } r2d_fpga_t;
  84
  85 enum r2d_fpga_irq {
  86     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  87     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  88     NR_IRQS
  89 };
  90
  91 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  92     [CF_IDE]    = {  1, 1<<9 },
  93     [CF_CD]     = {  2, 1<<8 },
  94     [PCI_INTA]  = {  9, 1<<14 },
  95     [PCI_INTB]  = { 10, 1<<13 },
  96     [PCI_INTC]  = {  3, 1<<12 },
  97     [PCI_INTD]  = {  0, 1<<11 },
  98     [SM501]     = {  4, 1<<10 },
  99     [KEY]       = {  5, 1<<6 },
 100     [RTC_A]     = {  6, 1<<5 },
 101     [RTC_T]     = {  7, 1<<4 },
 102     [SDCARD]    = {  8, 1<<7 },
 103     [EXT]       = { 11, 1<<0 },
 104     [TP]        = { 12, 1<<15 },
 105 };
 106
 107 static void update_irl(r2d_fpga_t *fpga)
 108 {
 109     int i, irl = 15;
 110     for (i = 0; i < NR_IRQS; i++)
 111         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 112             if (irqtab[i].irl < irl)
 113                 irl = irqtab[i].irl;
 114     qemu_set_irq(fpga->irl, irl ^ 15);
 115 }
 116
 117 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 118 {
 119     r2d_fpga_t *fpga = opaque;
 120     if (level)
 121         fpga->irlmon |= irqtab[n].msk;
 122     else
 123         fpga->irlmon &= ~irqtab[n].msk;
 124     update_irl(fpga);
 125 }
 126
 127 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 128 {
 129     r2d_fpga_t *s = opaque;
 130
 131     switch (addr) {
 132     case PA_IRLMSK:
 133         return s->irlmsk;
 134     case PA_OUTPORT:
 135         return s->outport;
 136     case PA_POWOFF:
 137         return 0x00;
 138     case PA_VERREG:
 139         return 0x10;
 140     }
 141
 142     return 0;
 143 }
 144
 145 static void
 146 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 147 {
 148     r2d_fpga_t *s = opaque;
 149
 150     switch (addr) {
 151     case PA_IRLMSK:
 152         s->irlmsk = value;
 153         update_irl(s);
 154         break;
 155     case PA_OUTPORT:
 156         s->outport = value;
 157         break;
 158     case PA_POWOFF:
 159         if (value & 1) {
 160             qemu_system_shutdown_request();
 161         }
 162         break;
 163     case PA_VERREG:
 164         /* Discard writes */
 165         break;
 166     }
 167 }
 168
 169 static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
 170     r2d_fpga_read,
 171     r2d_fpga_read,
 172     NULL,
 173 };
 174
 175 static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
 176     r2d_fpga_write,
 177     r2d_fpga_write,
 178     NULL,
 179 };
 180
 181 static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 182 {
 183     int iomemtype;
 184     r2d_fpga_t *s;
 185
 186     s = qemu_mallocz(sizeof(r2d_fpga_t));
 187
 188     s->irl = irl;
 189
 190     iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
 191                                        r2d_fpga_writefn, s);
 192     cpu_register_physical_memory(base, 0x40, iomemtype);
 193     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 194 }
 195
 196 static void r2d_pci_set_irq(void *opaque, int n, int l)
 197 {
 198     qemu_irq *p = opaque;
 199
 200     qemu_set_irq(p[n], l);
 201 }
 202
 203 static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
 204 {
 205     const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
 206     return intx[d->devfn >> 3];
 207 }
 208
 209 static struct __attribute__((__packed__))
 210 {
 211     int mount_root_rdonly;
 212     int ramdisk_flags;
 213     int orig_root_dev;
 214     int loader_type;
 215     int initrd_start;
 216     int initrd_size;
 217
 218     char pad[232];
 219
 220     char kernel_cmdline[256];
 221 } boot_params;
 222
 223 static void r2d_init(ram_addr_t ram_size,
 224               const char *boot_device,
 225               const char *kernel_filename, const char *kernel_cmdline,
 226               const char *initrd_filename, const char *cpu_model)
 227 {
 228     CPUState *env;
 229     struct SH7750State *s;
 230     ram_addr_t sdram_addr;
 231     qemu_irq *irq;
 232     DriveInfo *dinfo;
 233     int i;
 234
 235     if (!cpu_model)
 236         cpu_model = "SH7751R";
 237
 238     env = cpu_init(cpu_model);
 239     if (!env) {
 240         fprintf(stderr, "Unable to find CPU definition\n");
 241         exit(1);
 242     }
 243
 244     /* Allocate memory space */
 245     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
 246     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
 247     /* Register peripherals */
 248     s = sh7750_init(env);
 249     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
 250     sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
 251
 252     sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
 253
 254     /* onboard CF (True IDE mode, Master only). */
 255     dinfo = drive_get(IF_IDE, 0, 0);
 256     mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
 257                   dinfo, NULL);
 258
 259     /* onboard flash memory */
 260     pflash_cfi02_register(0x0, qemu_ram_alloc(FLASH_SIZE),
 261                           dinfo ? dinfo->bdrv : NULL, (16 * 1024),
 262                           FLASH_SIZE >> 16,
 263                           1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
 264                           0x555, 0x2aa, 0);
 265
 266     /* NIC: rtl8139 on-board, and 2 slots. */
 267     for (i = 0; i < nb_nics; i++)
 268         pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
 269
 270     /* USB keyboard */
 271     usbdevice_create("keyboard");
 272
 273     /* Todo: register on board registers */
 274     memset(&boot_params, 0, sizeof(boot_params));
 275
 276     if (kernel_filename) {
 277         int kernel_size;
 278
 279         kernel_size = load_image_targphys(kernel_filename,
 280                                           SDRAM_BASE + LINUX_LOAD_OFFSET,
 281                                           INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
 282         if (kernel_size < 0) {
 283           fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 284           exit(1);
 285         }
 286
 287         /* initialization which should be done by firmware */
 288         stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
 289         stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 290         env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
 291     }
 292
 293     if (initrd_filename) {
 294         int initrd_size;
 295
 296         initrd_size = load_image_targphys(initrd_filename,
 297                                           SDRAM_BASE + INITRD_LOAD_OFFSET,
 298                                           SDRAM_SIZE - INITRD_LOAD_OFFSET);
 299
 300         if (initrd_size < 0) {
 301           fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
 302           exit(1);
 303         }
 304
 305         /* initialization which should be done by firmware */
 306         boot_params.loader_type = 1;
 307         boot_params.initrd_start = INITRD_LOAD_OFFSET;
 308         boot_params.initrd_size = initrd_size;
 309     }
 310
 311     if (kernel_cmdline) {
 312         strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 313                 sizeof(boot_params.kernel_cmdline));
 314     }
 315
 316     rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
 317                        SDRAM_BASE + BOOT_PARAMS_OFFSET);
 318 }
 319
 320 static QEMUMachine r2d_machine = {
 321     .name = "r2d",
 322     .desc = "r2d-plus board",
 323     .init = r2d_init,
 324 };
 325
 326 static void r2d_machine_init(void)
 327 {
 328     qemu_register_machine(&r2d_machine);
 329 }
 330
 331 machine_init(r2d_machine_init);