target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUState struct CPUX86State
  46
  47 #include "cpu-defs.h"
  48
  49 #include "softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  89 #define DESC_A_MASK     (1 << 8)
  90
  91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  94
  95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  97
  98 #define DESC_TSS_BUSY_MASK (1 << 9)
  99
 100 /* eflags masks */
 101 #define CC_C    0x0001
 102 #define CC_P    0x0004
 103 #define CC_A    0x0010
 104 #define CC_Z    0x0040
 105 #define CC_S    0x0080
 106 #define CC_O    0x0800
 107
 108 #define TF_SHIFT   8
 109 #define IOPL_SHIFT 12
 110 #define VM_SHIFT   17
 111
 112 #define TF_MASK                 0x00000100
 113 #define IF_MASK                 0x00000200
 114 #define DF_MASK                 0x00000400
 115 #define IOPL_MASK               0x00003000
 116 #define NT_MASK                 0x00004000
 117 #define RF_MASK                 0x00010000
 118 #define VM_MASK                 0x00020000
 119 #define AC_MASK                 0x00040000
 120 #define VIF_MASK                0x00080000
 121 #define VIP_MASK                0x00100000
 122 #define ID_MASK                 0x00200000
 123
 124 /* hidden flags - used internally by qemu to represent additional cpu
 125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 126    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
 127    position to ease oring with eflags. */
 128 /* current cpl */
 129 #define HF_CPL_SHIFT         0
 130 /* true if soft mmu is being used */
 131 #define HF_SOFTMMU_SHIFT     2
 132 /* true if hardware interrupts must be disabled for next instruction */
 133 #define HF_INHIBIT_IRQ_SHIFT 3
 134 /* 16 or 32 segments */
 135 #define HF_CS32_SHIFT        4
 136 #define HF_SS32_SHIFT        5
 137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 138 #define HF_ADDSEG_SHIFT      6
 139 /* copy of CR0.PE (protected mode) */
 140 #define HF_PE_SHIFT          7
 141 #define HF_TF_SHIFT          8 /* must be same as eflags */
 142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 143 #define HF_EM_SHIFT         10
 144 #define HF_TS_SHIFT         11
 145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 148 #define HF_RF_SHIFT         16 /* must be same as eflags */
 149 #define HF_VM_SHIFT         17 /* must be same as eflags */
 150 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 151 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 152 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 153 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 154
 155 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 156 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 157 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 158 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 159 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 160 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 161 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 162 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 163 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 164 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 165 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 166 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 167 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 168 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 169 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 170 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 171 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 172 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 173 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 174 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 175
 176 /* hflags2 */
 177
 178 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 179 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 180 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 181 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 182
 183 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 184 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 185 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 186 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 187
 188 #define CR0_PE_SHIFT 0
 189 #define CR0_MP_SHIFT 1
 190
 191 #define CR0_PE_MASK  (1 << 0)
 192 #define CR0_MP_MASK  (1 << 1)
 193 #define CR0_EM_MASK  (1 << 2)
 194 #define CR0_TS_MASK  (1 << 3)
 195 #define CR0_ET_MASK  (1 << 4)
 196 #define CR0_NE_MASK  (1 << 5)
 197 #define CR0_WP_MASK  (1 << 16)
 198 #define CR0_AM_MASK  (1 << 18)
 199 #define CR0_PG_MASK  (1 << 31)
 200
 201 #define CR4_VME_MASK  (1 << 0)
 202 #define CR4_PVI_MASK  (1 << 1)
 203 #define CR4_TSD_MASK  (1 << 2)
 204 #define CR4_DE_MASK   (1 << 3)
 205 #define CR4_PSE_MASK  (1 << 4)
 206 #define CR4_PAE_MASK  (1 << 5)
 207 #define CR4_PGE_MASK  (1 << 7)
 208 #define CR4_PCE_MASK  (1 << 8)
 209 #define CR4_OSFXSR_SHIFT 9
 210 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 211 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 212
 213 #define DR6_BD          (1 << 13)
 214 #define DR6_BS          (1 << 14)
 215 #define DR6_BT          (1 << 15)
 216 #define DR6_FIXED_1     0xffff0ff0
 217
 218 #define DR7_GD          (1 << 13)
 219 #define DR7_TYPE_SHIFT  16
 220 #define DR7_LEN_SHIFT   18
 221 #define DR7_FIXED_1     0x00000400
 222
 223 #define PG_PRESENT_BIT  0
 224 #define PG_RW_BIT       1
 225 #define PG_USER_BIT     2
 226 #define PG_PWT_BIT      3
 227 #define PG_PCD_BIT      4
 228 #define PG_ACCESSED_BIT 5
 229 #define PG_DIRTY_BIT    6
 230 #define PG_PSE_BIT      7
 231 #define PG_GLOBAL_BIT   8
 232 #define PG_NX_BIT       63
 233
 234 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 235 #define PG_RW_MASK       (1 << PG_RW_BIT)
 236 #define PG_USER_MASK     (1 << PG_USER_BIT)
 237 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 238 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 239 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 240 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 241 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 242 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 243 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 244
 245 #define PG_ERROR_W_BIT     1
 246
 247 #define PG_ERROR_P_MASK    0x01
 248 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 249 #define PG_ERROR_U_MASK    0x04
 250 #define PG_ERROR_RSVD_MASK 0x08
 251 #define PG_ERROR_I_D_MASK  0x10
 252
 253 #define MSR_IA32_TSC                    0x10
 254 #define MSR_IA32_APICBASE               0x1b
 255 #define MSR_IA32_APICBASE_BSP           (1<<8)
 256 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 257 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 258
 259 #define MSR_MTRRcap                     0xfe
 260 #define MSR_MTRRcap_VCNT                8
 261 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 262 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 263
 264 #define MSR_IA32_SYSENTER_CS            0x174
 265 #define MSR_IA32_SYSENTER_ESP           0x175
 266 #define MSR_IA32_SYSENTER_EIP           0x176
 267
 268 #define MSR_MCG_CAP                     0x179
 269 #define MSR_MCG_STATUS                  0x17a
 270 #define MSR_MCG_CTL                     0x17b
 271
 272 #define MSR_IA32_PERF_STATUS            0x198
 273
 274 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 275 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 276
 277 #define MSR_MTRRfix64K_00000            0x250
 278 #define MSR_MTRRfix16K_80000            0x258
 279 #define MSR_MTRRfix16K_A0000            0x259
 280 #define MSR_MTRRfix4K_C0000             0x268
 281 #define MSR_MTRRfix4K_C8000             0x269
 282 #define MSR_MTRRfix4K_D0000             0x26a
 283 #define MSR_MTRRfix4K_D8000             0x26b
 284 #define MSR_MTRRfix4K_E0000             0x26c
 285 #define MSR_MTRRfix4K_E8000             0x26d
 286 #define MSR_MTRRfix4K_F0000             0x26e
 287 #define MSR_MTRRfix4K_F8000             0x26f
 288
 289 #define MSR_PAT                         0x277
 290
 291 #define MSR_MTRRdefType                 0x2ff
 292
 293 #define MSR_EFER                        0xc0000080
 294
 295 #define MSR_EFER_SCE   (1 << 0)
 296 #define MSR_EFER_LME   (1 << 8)
 297 #define MSR_EFER_LMA   (1 << 10)
 298 #define MSR_EFER_NXE   (1 << 11)
 299 #define MSR_EFER_SVME  (1 << 12)
 300 #define MSR_EFER_FFXSR (1 << 14)
 301
 302 #define MSR_STAR                        0xc0000081
 303 #define MSR_LSTAR                       0xc0000082
 304 #define MSR_CSTAR                       0xc0000083
 305 #define MSR_FMASK                       0xc0000084
 306 #define MSR_FSBASE                      0xc0000100
 307 #define MSR_GSBASE                      0xc0000101
 308 #define MSR_KERNELGSBASE                0xc0000102
 309
 310 #define MSR_VM_HSAVE_PA                 0xc0010117
 311
 312 /* cpuid_features bits */
 313 #define CPUID_FP87 (1 << 0)
 314 #define CPUID_VME  (1 << 1)
 315 #define CPUID_DE   (1 << 2)
 316 #define CPUID_PSE  (1 << 3)
 317 #define CPUID_TSC  (1 << 4)
 318 #define CPUID_MSR  (1 << 5)
 319 #define CPUID_PAE  (1 << 6)
 320 #define CPUID_MCE  (1 << 7)
 321 #define CPUID_CX8  (1 << 8)
 322 #define CPUID_APIC (1 << 9)
 323 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 324 #define CPUID_MTRR (1 << 12)
 325 #define CPUID_PGE  (1 << 13)
 326 #define CPUID_MCA  (1 << 14)
 327 #define CPUID_CMOV (1 << 15)
 328 #define CPUID_PAT  (1 << 16)
 329 #define CPUID_PSE36   (1 << 17)
 330 #define CPUID_PN   (1 << 18)
 331 #define CPUID_CLFLUSH (1 << 19)
 332 #define CPUID_DTS (1 << 21)
 333 #define CPUID_ACPI (1 << 22)
 334 #define CPUID_MMX  (1 << 23)
 335 #define CPUID_FXSR (1 << 24)
 336 #define CPUID_SSE  (1 << 25)
 337 #define CPUID_SSE2 (1 << 26)
 338 #define CPUID_SS (1 << 27)
 339 #define CPUID_HT (1 << 28)
 340 #define CPUID_TM (1 << 29)
 341 #define CPUID_IA64 (1 << 30)
 342 #define CPUID_PBE (1 << 31)
 343
 344 #define CPUID_EXT_SSE3     (1 << 0)
 345 #define CPUID_EXT_DTES64   (1 << 2)
 346 #define CPUID_EXT_MONITOR  (1 << 3)
 347 #define CPUID_EXT_DSCPL    (1 << 4)
 348 #define CPUID_EXT_VMX      (1 << 5)
 349 #define CPUID_EXT_SMX      (1 << 6)
 350 #define CPUID_EXT_EST      (1 << 7)
 351 #define CPUID_EXT_TM2      (1 << 8)
 352 #define CPUID_EXT_SSSE3    (1 << 9)
 353 #define CPUID_EXT_CID      (1 << 10)
 354 #define CPUID_EXT_CX16     (1 << 13)
 355 #define CPUID_EXT_XTPR     (1 << 14)
 356 #define CPUID_EXT_PDCM     (1 << 15)
 357 #define CPUID_EXT_DCA      (1 << 18)
 358 #define CPUID_EXT_SSE41    (1 << 19)
 359 #define CPUID_EXT_SSE42    (1 << 20)
 360 #define CPUID_EXT_X2APIC   (1 << 21)
 361 #define CPUID_EXT_MOVBE    (1 << 22)
 362 #define CPUID_EXT_POPCNT   (1 << 23)
 363 #define CPUID_EXT_XSAVE    (1 << 26)
 364 #define CPUID_EXT_OSXSAVE  (1 << 27)
 365
 366 #define CPUID_EXT2_SYSCALL (1 << 11)
 367 #define CPUID_EXT2_MP      (1 << 19)
 368 #define CPUID_EXT2_NX      (1 << 20)
 369 #define CPUID_EXT2_MMXEXT  (1 << 22)
 370 #define CPUID_EXT2_FFXSR   (1 << 25)
 371 #define CPUID_EXT2_PDPE1GB (1 << 26)
 372 #define CPUID_EXT2_RDTSCP  (1 << 27)
 373 #define CPUID_EXT2_LM      (1 << 29)
 374 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 375 #define CPUID_EXT2_3DNOW   (1 << 31)
 376
 377 #define CPUID_EXT3_LAHF_LM (1 << 0)
 378 #define CPUID_EXT3_CMP_LEG (1 << 1)
 379 #define CPUID_EXT3_SVM     (1 << 2)
 380 #define CPUID_EXT3_EXTAPIC (1 << 3)
 381 #define CPUID_EXT3_CR8LEG  (1 << 4)
 382 #define CPUID_EXT3_ABM     (1 << 5)
 383 #define CPUID_EXT3_SSE4A   (1 << 6)
 384 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 385 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 386 #define CPUID_EXT3_OSVW    (1 << 9)
 387 #define CPUID_EXT3_IBS     (1 << 10)
 388 #define CPUID_EXT3_SKINIT  (1 << 12)
 389
 390 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 391 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 392 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 393
 394 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 395 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 396 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 397
 398 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 399 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 400
 401 #define EXCP00_DIVZ     0
 402 #define EXCP01_DB       1
 403 #define EXCP02_NMI      2
 404 #define EXCP03_INT3     3
 405 #define EXCP04_INTO     4
 406 #define EXCP05_BOUND    5
 407 #define EXCP06_ILLOP    6
 408 #define EXCP07_PREX     7
 409 #define EXCP08_DBLE     8
 410 #define EXCP09_XERR     9
 411 #define EXCP0A_TSS      10
 412 #define EXCP0B_NOSEG    11
 413 #define EXCP0C_STACK    12
 414 #define EXCP0D_GPF      13
 415 #define EXCP0E_PAGE     14
 416 #define EXCP10_COPR     16
 417 #define EXCP11_ALGN     17
 418 #define EXCP12_MCHK     18
 419
 420 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 421                                  for syscall instruction */
 422
 423 enum {
 424     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 425     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 426
 427     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 428     CC_OP_MULW,
 429     CC_OP_MULL,
 430     CC_OP_MULQ,
 431
 432     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 433     CC_OP_ADDW,
 434     CC_OP_ADDL,
 435     CC_OP_ADDQ,
 436
 437     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 438     CC_OP_ADCW,
 439     CC_OP_ADCL,
 440     CC_OP_ADCQ,
 441
 442     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 443     CC_OP_SUBW,
 444     CC_OP_SUBL,
 445     CC_OP_SUBQ,
 446
 447     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 448     CC_OP_SBBW,
 449     CC_OP_SBBL,
 450     CC_OP_SBBQ,
 451
 452     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 453     CC_OP_LOGICW,
 454     CC_OP_LOGICL,
 455     CC_OP_LOGICQ,
 456
 457     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 458     CC_OP_INCW,
 459     CC_OP_INCL,
 460     CC_OP_INCQ,
 461
 462     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 463     CC_OP_DECW,
 464     CC_OP_DECL,
 465     CC_OP_DECQ,
 466
 467     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 468     CC_OP_SHLW,
 469     CC_OP_SHLL,
 470     CC_OP_SHLQ,
 471
 472     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 473     CC_OP_SARW,
 474     CC_OP_SARL,
 475     CC_OP_SARQ,
 476
 477     CC_OP_NB,
 478 };
 479
 480 #ifdef FLOATX80
 481 #define USE_X86LDOUBLE
 482 #endif
 483
 484 #ifdef USE_X86LDOUBLE
 485 typedef floatx80 CPU86_LDouble;
 486 #else
 487 typedef float64 CPU86_LDouble;
 488 #endif
 489
 490 typedef struct SegmentCache {
 491     uint32_t selector;
 492     target_ulong base;
 493     uint32_t limit;
 494     uint32_t flags;
 495 } SegmentCache;
 496
 497 typedef union {
 498     uint8_t _b[16];
 499     uint16_t _w[8];
 500     uint32_t _l[4];
 501     uint64_t _q[2];
 502     float32 _s[4];
 503     float64 _d[2];
 504 } XMMReg;
 505
 506 typedef union {
 507     uint8_t _b[8];
 508     uint16_t _w[4];
 509     uint32_t _l[2];
 510     float32 _s[2];
 511     uint64_t q;
 512 } MMXReg;
 513
 514 #ifdef WORDS_BIGENDIAN
 515 #define XMM_B(n) _b[15 - (n)]
 516 #define XMM_W(n) _w[7 - (n)]
 517 #define XMM_L(n) _l[3 - (n)]
 518 #define XMM_S(n) _s[3 - (n)]
 519 #define XMM_Q(n) _q[1 - (n)]
 520 #define XMM_D(n) _d[1 - (n)]
 521
 522 #define MMX_B(n) _b[7 - (n)]
 523 #define MMX_W(n) _w[3 - (n)]
 524 #define MMX_L(n) _l[1 - (n)]
 525 #define MMX_S(n) _s[1 - (n)]
 526 #else
 527 #define XMM_B(n) _b[n]
 528 #define XMM_W(n) _w[n]
 529 #define XMM_L(n) _l[n]
 530 #define XMM_S(n) _s[n]
 531 #define XMM_Q(n) _q[n]
 532 #define XMM_D(n) _d[n]
 533
 534 #define MMX_B(n) _b[n]
 535 #define MMX_W(n) _w[n]
 536 #define MMX_L(n) _l[n]
 537 #define MMX_S(n) _s[n]
 538 #endif
 539 #define MMX_Q(n) q
 540
 541 #ifdef TARGET_X86_64
 542 #define CPU_NB_REGS 16
 543 #else
 544 #define CPU_NB_REGS 8
 545 #endif
 546
 547 #define NB_MMU_MODES 2
 548
 549 typedef struct CPUX86State {
 550     /* standard registers */
 551     target_ulong regs[CPU_NB_REGS];
 552     target_ulong eip;
 553     target_ulong eflags; /* eflags register. During CPU emulation, CC
 554                         flags and DF are set to zero because they are
 555                         stored elsewhere */
 556
 557     /* emulator internal eflags handling */
 558     target_ulong cc_src;
 559     target_ulong cc_dst;
 560     uint32_t cc_op;
 561     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 562     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 563                         are known at translation time. */
 564     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 565
 566     /* segments */
 567     SegmentCache segs[6]; /* selector values */
 568     SegmentCache ldt;
 569     SegmentCache tr;
 570     SegmentCache gdt; /* only base and limit are used */
 571     SegmentCache idt; /* only base and limit are used */
 572
 573     target_ulong cr[5]; /* NOTE: cr1 is unused */
 574     uint64_t a20_mask;
 575
 576     /* FPU state */
 577     unsigned int fpstt; /* top of stack index */
 578     unsigned int fpus;
 579     unsigned int fpuc;
 580     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 581     union {
 582 #ifdef USE_X86LDOUBLE
 583         CPU86_LDouble d __attribute__((aligned(16)));
 584 #else
 585         CPU86_LDouble d;
 586 #endif
 587         MMXReg mmx;
 588     } fpregs[8];
 589
 590     /* emulator internal variables */
 591     float_status fp_status;
 592     CPU86_LDouble ft0;
 593
 594     float_status mmx_status; /* for 3DNow! float ops */
 595     float_status sse_status;
 596     uint32_t mxcsr;
 597     XMMReg xmm_regs[CPU_NB_REGS];
 598     XMMReg xmm_t0;
 599     MMXReg mmx_t0;
 600     target_ulong cc_tmp; /* temporary for rcr/rcl */
 601
 602     /* sysenter registers */
 603     uint32_t sysenter_cs;
 604     target_ulong sysenter_esp;
 605     target_ulong sysenter_eip;
 606     uint64_t efer;
 607     uint64_t star;
 608
 609     uint64_t vm_hsave;
 610     uint64_t vm_vmcb;
 611     uint64_t tsc_offset;
 612     uint64_t intercept;
 613     uint16_t intercept_cr_read;
 614     uint16_t intercept_cr_write;
 615     uint16_t intercept_dr_read;
 616     uint16_t intercept_dr_write;
 617     uint32_t intercept_exceptions;
 618     uint8_t v_tpr;
 619
 620 #ifdef TARGET_X86_64
 621     target_ulong lstar;
 622     target_ulong cstar;
 623     target_ulong fmask;
 624     target_ulong kernelgsbase;
 625 #endif
 626
 627     uint64_t tsc;
 628
 629     uint64_t pat;
 630
 631     /* exception/interrupt handling */
 632     int error_code;
 633     int exception_is_int;
 634     target_ulong exception_next_eip;
 635     target_ulong dr[8]; /* debug registers */
 636     union {
 637         CPUBreakpoint *cpu_breakpoint[4];
 638         CPUWatchpoint *cpu_watchpoint[4];
 639     }; /* break/watchpoints for dr[0..3] */
 640     uint32_t smbase;
 641     int old_exception;  /* exception in flight */
 642
 643     CPU_COMMON
 644
 645     /* processor features (e.g. for CPUID insn) */
 646     uint32_t cpuid_level;
 647     uint32_t cpuid_vendor1;
 648     uint32_t cpuid_vendor2;
 649     uint32_t cpuid_vendor3;
 650     uint32_t cpuid_version;
 651     uint32_t cpuid_features;
 652     uint32_t cpuid_ext_features;
 653     uint32_t cpuid_xlevel;
 654     uint32_t cpuid_model[12];
 655     uint32_t cpuid_ext2_features;
 656     uint32_t cpuid_ext3_features;
 657     uint32_t cpuid_apic_id;
 658
 659     /* MTRRs */
 660     uint64_t mtrr_fixed[11];
 661     uint64_t mtrr_deftype;
 662     struct {
 663         uint64_t base;
 664         uint64_t mask;
 665     } mtrr_var[8];
 666
 667 #ifdef CONFIG_KQEMU
 668     int kqemu_enabled;
 669     int last_io_time;
 670 #endif
 671
 672     /* For KVM */
 673     uint64_t interrupt_bitmap[256 / 64];
 674     uint32_t mp_state;
 675
 676     /* in order to simplify APIC support, we leave this pointer to the
 677        user */
 678     struct APICState *apic_state;
 679 } CPUX86State;
 680
 681 CPUX86State *cpu_x86_init(const char *cpu_model);
 682 int cpu_x86_exec(CPUX86State *s);
 683 void cpu_x86_close(CPUX86State *s);
 684 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 685                                                  ...));
 686 int cpu_get_pic_interrupt(CPUX86State *s);
 687 /* MSDOS compatibility mode FPU exception support */
 688 void cpu_set_ferr(CPUX86State *s);
 689
 690 /* this function must always be used to load data in the segment
 691    cache: it synchronizes the hflags with the segment cache values */
 692 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 693                                           int seg_reg, unsigned int selector,
 694                                           target_ulong base,
 695                                           unsigned int limit,
 696                                           unsigned int flags)
 697 {
 698     SegmentCache *sc;
 699     unsigned int new_hflags;
 700
 701     sc = &env->segs[seg_reg];
 702     sc->selector = selector;
 703     sc->base = base;
 704     sc->limit = limit;
 705     sc->flags = flags;
 706
 707     /* update the hidden flags */
 708     {
 709         if (seg_reg == R_CS) {
 710 #ifdef TARGET_X86_64
 711             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 712                 /* long mode */
 713                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 714                 env->hflags &= ~(HF_ADDSEG_MASK);
 715             } else
 716 #endif
 717             {
 718                 /* legacy / compatibility case */
 719                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 720                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 721                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 722                     new_hflags;
 723             }
 724         }
 725         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 726             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 727         if (env->hflags & HF_CS64_MASK) {
 728             /* zero base assumed for DS, ES and SS in long mode */
 729         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 730                    (env->eflags & VM_MASK) ||
 731                    !(env->hflags & HF_CS32_MASK)) {
 732             /* XXX: try to avoid this test. The problem comes from the
 733                fact that is real mode or vm86 mode we only modify the
 734                'base' and 'selector' fields of the segment cache to go
 735                faster. A solution may be to force addseg to one in
 736                translate-i386.c. */
 737             new_hflags |= HF_ADDSEG_MASK;
 738         } else {
 739             new_hflags |= ((env->segs[R_DS].base |
 740                             env->segs[R_ES].base |
 741                             env->segs[R_SS].base) != 0) <<
 742                 HF_ADDSEG_SHIFT;
 743         }
 744         env->hflags = (env->hflags &
 745                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 746     }
 747 }
 748
 749 /* wrapper, just in case memory mappings must be changed */
 750 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 751 {
 752 #if HF_CPL_MASK == 3
 753     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 754 #else
 755 #error HF_CPL_MASK is hardcoded
 756 #endif
 757 }
 758
 759 /* op_helper.c */
 760 /* used for debug or cpu save/restore */
 761 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 762 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 763
 764 /* cpu-exec.c */
 765 /* the following helpers are only usable in user mode simulation as
 766    they can trigger unexpected exceptions */
 767 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 768 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 769 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 770
 771 /* you can call this signal handler from your SIGBUS and SIGSEGV
 772    signal handlers to inform the virtual CPU of exceptions. non zero
 773    is returned if the signal was handled by the virtual CPU.  */
 774 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 775                            void *puc);
 776
 777 /* helper.c */
 778 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 779                              int is_write, int mmu_idx, int is_softmmu);
 780 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 781 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
 782                    uint32_t *eax, uint32_t *ebx,
 783                    uint32_t *ecx, uint32_t *edx);
 784
 785 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
 786 {
 787     return (dr7 >> (index * 2)) & 3;
 788 }
 789
 790 static inline int hw_breakpoint_type(unsigned long dr7, int index)
 791 {
 792     return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
 793 }
 794
 795 static inline int hw_breakpoint_len(unsigned long dr7, int index)
 796 {
 797     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
 798     return (len == 2) ? 8 : len + 1;
 799 }
 800
 801 void hw_breakpoint_insert(CPUX86State *env, int index);
 802 void hw_breakpoint_remove(CPUX86State *env, int index);
 803 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
 804
 805 /* will be suppressed */
 806 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 807 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
 808 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 809
 810 /* hw/apic.c */
 811 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 812 uint64_t cpu_get_apic_base(CPUX86State *env);
 813 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 814 #ifndef NO_CPU_IO_DEFS
 815 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 816 #endif
 817
 818 /* hw/pc.c */
 819 void cpu_smm_update(CPUX86State *env);
 820 uint64_t cpu_get_tsc(CPUX86State *env);
 821
 822 /* used to debug */
 823 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 824 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 825
 826 #ifdef CONFIG_KQEMU
 827 static inline int cpu_get_time_fast(void)
 828 {
 829     int low, high;
 830     asm volatile("rdtsc" : "=a" (low), "=d" (high));
 831     return low;
 832 }
 833 #endif
 834
 835 #define TARGET_PAGE_BITS 12
 836
 837 #define cpu_init cpu_x86_init
 838 #define cpu_exec cpu_x86_exec
 839 #define cpu_gen_code cpu_x86_gen_code
 840 #define cpu_signal_handler cpu_x86_signal_handler
 841 #define cpu_list x86_cpu_list
 842
 843 #define CPU_SAVE_VERSION 9
 844
 845 /* MMU modes definitions */
 846 #define MMU_MODE0_SUFFIX _kernel
 847 #define MMU_MODE1_SUFFIX _user
 848 #define MMU_USER_IDX 1
 849 static inline int cpu_mmu_index (CPUState *env)
 850 {
 851     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 852 }
 853
 854 /* translate.c */
 855 void optimize_flags_init(void);
 856
 857 typedef struct CCTable {
 858     int (*compute_all)(void); /* return all the flags */
 859     int (*compute_c)(void);  /* return the C flag */
 860 } CCTable;
 861
 862 #if defined(CONFIG_USER_ONLY)
 863 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 864 {
 865     if (newsp)
 866         env->regs[R_ESP] = newsp;
 867     env->regs[R_EAX] = 0;
 868 }
 869 #endif
 870
 871 #include "cpu-all.h"
 872 #include "exec-all.h"
 873
 874 #include "svm.h"
 875
 876 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 877 {
 878     env->eip = tb->pc - tb->cs_base;
 879 }
 880
 881 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 882                                         target_ulong *cs_base, int *flags)
 883 {
 884     *cs_base = env->segs[R_CS].base;
 885     *pc = *cs_base + env->eip;
 886     *flags = env->hflags |
 887         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
 888 }
 889
 890 #endif /* CPU_I386_H */