2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
39 #include "mc146818rtc.h"
41 //#define HARD_DEBUG_PPC_IO
42 //#define DEBUG_PPC_IO
44 /* SMP is not enabled, for now */
49 #define BIOS_SIZE (1024 * 1024)
50 #define BIOS_FILENAME "ppc_rom.bin"
51 #define KERNEL_LOAD_ADDR 0x01000000
52 #define INITRD_LOAD_ADDR 0x01800000
54 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
58 #if defined (HARD_DEBUG_PPC_IO)
59 #define PPC_IO_DPRINTF(fmt, ...) \
61 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
62 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
64 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
67 #elif defined (DEBUG_PPC_IO)
68 #define PPC_IO_DPRINTF(fmt, ...) \
69 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
71 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
74 /* Constants for devices init */
75 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
76 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
77 static const int ide_irq
[2] = { 13, 13 };
79 #define NE2000_NB_MAX 6
81 static uint32_t ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
82 static int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
84 //static PITState *pit;
86 /* ISA IO ports bridge */
87 #define PPC_IO_BASE 0x80000000
90 /* Speaker port 0x61 */
91 static int speaker_data_on
;
92 static int dummy_refresh_clock
;
95 static void speaker_ioport_write (void *opaque
, uint32_t addr
, uint32_t val
)
98 speaker_data_on
= (val
>> 1) & 1;
99 pit_set_gate(pit
, 2, val
& 1);
103 static uint32_t speaker_ioport_read (void *opaque
, uint32_t addr
)
107 out
= pit_get_out(pit
, 2, qemu_get_clock(vm_clock
));
108 dummy_refresh_clock
^= 1;
109 return (speaker_data_on
<< 1) | pit_get_gate(pit
, 2) | (out
<< 5) |
110 (dummy_refresh_clock
<< 4);
115 /* PCI intack register */
116 /* Read-only register (?) */
117 static void _PPC_intack_write (void *opaque
,
118 target_phys_addr_t addr
, uint32_t value
)
121 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
126 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr
)
130 if ((addr
& 0xf) == 0)
131 retval
= pic_intack_read(isa_pic
);
133 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
140 static uint32_t PPC_intack_readb (void *opaque
, target_phys_addr_t addr
)
142 return _PPC_intack_read(addr
);
145 static uint32_t PPC_intack_readw (void *opaque
, target_phys_addr_t addr
)
147 #ifdef TARGET_WORDS_BIGENDIAN
148 return bswap16(_PPC_intack_read(addr
));
150 return _PPC_intack_read(addr
);
154 static uint32_t PPC_intack_readl (void *opaque
, target_phys_addr_t addr
)
156 #ifdef TARGET_WORDS_BIGENDIAN
157 return bswap32(_PPC_intack_read(addr
));
159 return _PPC_intack_read(addr
);
163 static CPUWriteMemoryFunc
* const PPC_intack_write
[] = {
169 static CPUReadMemoryFunc
* const PPC_intack_read
[] = {
175 /* PowerPC control and status registers */
181 /* Control and status */
186 /* General purpose registers */
199 /* Error diagnostic */
202 static void PPC_XCSR_writeb (void *opaque
,
203 target_phys_addr_t addr
, uint32_t value
)
205 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
209 static void PPC_XCSR_writew (void *opaque
,
210 target_phys_addr_t addr
, uint32_t value
)
212 #ifdef TARGET_WORDS_BIGENDIAN
213 value
= bswap16(value
);
215 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
219 static void PPC_XCSR_writel (void *opaque
,
220 target_phys_addr_t addr
, uint32_t value
)
222 #ifdef TARGET_WORDS_BIGENDIAN
223 value
= bswap32(value
);
225 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
229 static uint32_t PPC_XCSR_readb (void *opaque
, target_phys_addr_t addr
)
233 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
239 static uint32_t PPC_XCSR_readw (void *opaque
, target_phys_addr_t addr
)
243 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
245 #ifdef TARGET_WORDS_BIGENDIAN
246 retval
= bswap16(retval
);
252 static uint32_t PPC_XCSR_readl (void *opaque
, target_phys_addr_t addr
)
256 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
258 #ifdef TARGET_WORDS_BIGENDIAN
259 retval
= bswap32(retval
);
265 static CPUWriteMemoryFunc
* const PPC_XCSR_write
[] = {
271 static CPUReadMemoryFunc
* const PPC_XCSR_read
[] = {
278 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
279 typedef struct sysctrl_t
{
290 STATE_HARDFILE
= 0x01,
293 static sysctrl_t
*sysctrl
;
295 static void PREP_io_write (void *opaque
, uint32_t addr
, uint32_t val
)
297 sysctrl_t
*sysctrl
= opaque
;
299 PPC_IO_DPRINTF("0x%08" PRIx32
" => 0x%02" PRIx32
"\n", addr
- PPC_IO_BASE
,
301 sysctrl
->fake_io
[addr
- 0x0398] = val
;
304 static uint32_t PREP_io_read (void *opaque
, uint32_t addr
)
306 sysctrl_t
*sysctrl
= opaque
;
308 PPC_IO_DPRINTF("0x%08" PRIx32
" <= 0x%02" PRIx32
"\n", addr
- PPC_IO_BASE
,
309 sysctrl
->fake_io
[addr
- 0x0398]);
310 return sysctrl
->fake_io
[addr
- 0x0398];
313 static void PREP_io_800_writeb (void *opaque
, uint32_t addr
, uint32_t val
)
315 sysctrl_t
*sysctrl
= opaque
;
317 PPC_IO_DPRINTF("0x%08" PRIx32
" => 0x%02" PRIx32
"\n",
318 addr
- PPC_IO_BASE
, val
);
321 /* Special port 92 */
322 /* Check soft reset asked */
324 qemu_irq_raise(sysctrl
->reset_irq
);
326 qemu_irq_lower(sysctrl
->reset_irq
);
336 /* Motorola CPU configuration register : read-only */
339 /* Motorola base module feature register : read-only */
342 /* Motorola base module status register : read-only */
345 /* Hardfile light register */
347 sysctrl
->state
|= STATE_HARDFILE
;
349 sysctrl
->state
&= ~STATE_HARDFILE
;
352 /* Password protect 1 register */
353 if (sysctrl
->nvram
!= NULL
)
354 m48t59_toggle_lock(sysctrl
->nvram
, 1);
357 /* Password protect 2 register */
358 if (sysctrl
->nvram
!= NULL
)
359 m48t59_toggle_lock(sysctrl
->nvram
, 2);
362 /* L2 invalidate register */
363 // tlb_flush(first_cpu, 1);
366 /* system control register */
367 sysctrl
->syscontrol
= val
& 0x0F;
370 /* I/O map type register */
371 sysctrl
->contiguous_map
= val
& 0x01;
374 printf("ERROR: unaffected IO port write: %04" PRIx32
375 " => %02" PRIx32
"\n", addr
, val
);
380 static uint32_t PREP_io_800_readb (void *opaque
, uint32_t addr
)
382 sysctrl_t
*sysctrl
= opaque
;
383 uint32_t retval
= 0xFF;
387 /* Special port 92 */
391 /* Motorola CPU configuration register */
392 retval
= 0xEF; /* MPC750 */
395 /* Motorola Base module feature register */
396 retval
= 0xAD; /* No ESCC, PMC slot neither ethernet */
399 /* Motorola base module status register */
400 retval
= 0xE0; /* Standard MPC750 */
403 /* Equipment present register:
405 * no upgrade processor
406 * no cards in PCI slots
412 /* Motorola base module extended feature register */
413 retval
= 0x39; /* No USB, CF and PCI bridge. NVRAM present */
416 /* L2 invalidate: don't care */
423 /* system control register
424 * 7 - 6 / 1 - 0: L2 cache enable
426 retval
= sysctrl
->syscontrol
;
430 retval
= 0x03; /* no L2 cache */
433 /* I/O map type register */
434 retval
= sysctrl
->contiguous_map
;
437 printf("ERROR: unaffected IO port: %04" PRIx32
" read\n", addr
);
440 PPC_IO_DPRINTF("0x%08" PRIx32
" <= 0x%02" PRIx32
"\n",
441 addr
- PPC_IO_BASE
, retval
);
446 static inline target_phys_addr_t
prep_IO_address(sysctrl_t
*sysctrl
,
447 target_phys_addr_t addr
)
449 if (sysctrl
->contiguous_map
== 0) {
450 /* 64 KB contiguous space for IOs */
453 /* 8 MB non-contiguous space for IOs */
454 addr
= (addr
& 0x1F) | ((addr
& 0x007FFF000) >> 7);
460 static void PPC_prep_io_writeb (void *opaque
, target_phys_addr_t addr
,
463 sysctrl_t
*sysctrl
= opaque
;
465 addr
= prep_IO_address(sysctrl
, addr
);
466 cpu_outb(addr
, value
);
469 static uint32_t PPC_prep_io_readb (void *opaque
, target_phys_addr_t addr
)
471 sysctrl_t
*sysctrl
= opaque
;
474 addr
= prep_IO_address(sysctrl
, addr
);
480 static void PPC_prep_io_writew (void *opaque
, target_phys_addr_t addr
,
483 sysctrl_t
*sysctrl
= opaque
;
485 addr
= prep_IO_address(sysctrl
, addr
);
486 #ifdef TARGET_WORDS_BIGENDIAN
487 value
= bswap16(value
);
489 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", addr
, value
);
490 cpu_outw(addr
, value
);
493 static uint32_t PPC_prep_io_readw (void *opaque
, target_phys_addr_t addr
)
495 sysctrl_t
*sysctrl
= opaque
;
498 addr
= prep_IO_address(sysctrl
, addr
);
500 #ifdef TARGET_WORDS_BIGENDIAN
503 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" <= 0x%08" PRIx32
"\n", addr
, ret
);
508 static void PPC_prep_io_writel (void *opaque
, target_phys_addr_t addr
,
511 sysctrl_t
*sysctrl
= opaque
;
513 addr
= prep_IO_address(sysctrl
, addr
);
514 #ifdef TARGET_WORDS_BIGENDIAN
515 value
= bswap32(value
);
517 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", addr
, value
);
518 cpu_outl(addr
, value
);
521 static uint32_t PPC_prep_io_readl (void *opaque
, target_phys_addr_t addr
)
523 sysctrl_t
*sysctrl
= opaque
;
526 addr
= prep_IO_address(sysctrl
, addr
);
528 #ifdef TARGET_WORDS_BIGENDIAN
531 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" <= 0x%08" PRIx32
"\n", addr
, ret
);
536 static CPUWriteMemoryFunc
* const PPC_prep_io_write
[] = {
542 static CPUReadMemoryFunc
* const PPC_prep_io_read
[] = {
548 #define NVRAM_SIZE 0x2000
550 static void cpu_request_exit(void *opaque
, int irq
, int level
)
552 CPUState
*env
= cpu_single_env
;
559 /* PowerPC PREP hardware initialisation */
560 static void ppc_prep_init (QEMUMachine
*machine
, QemuOpts
*opts
)
562 ram_addr_t ram_size
= qemu_opt_get_number(opts
, "ram_size", 0);
563 const char *boot_device
= qemu_opt_get(opts
, "boot_device");
564 const char *kernel_filename
= qemu_opt_get(opts
, "kernel");
565 const char *kernel_cmdline
= qemu_opt_get(opts
, "cmdline");
566 const char *initrd_filename
= qemu_opt_get(opts
, "initrd");
567 const char *cpu_model
= qemu_opt_get(opts
, "cpu");
568 CPUState
*env
= NULL
, *envs
[MAX_CPUS
];
573 int linux_boot
, i
, nb_nics1
, bios_size
;
574 ram_addr_t ram_offset
, bios_offset
;
575 uint32_t kernel_base
, kernel_size
, initrd_base
, initrd_size
;
578 qemu_irq
*cpu_exit_irq
;
580 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
581 DriveInfo
*fd
[MAX_FD
];
583 sysctrl
= qemu_mallocz(sizeof(sysctrl_t
));
585 linux_boot
= (kernel_filename
!= NULL
);
588 if (cpu_model
== NULL
)
590 for (i
= 0; i
< smp_cpus
; i
++) {
591 env
= cpu_init(cpu_model
);
593 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
596 if (env
->flags
& POWERPC_FLAG_RTC_CLK
) {
597 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
598 cpu_ppc_tb_init(env
, 7812500UL);
600 /* Set time-base frequency to 100 Mhz */
601 cpu_ppc_tb_init(env
, 100UL * 1000UL * 1000UL);
603 qemu_register_reset((QEMUResetHandler
*)&cpu_reset
, env
);
608 ram_offset
= qemu_ram_alloc(ram_size
);
609 cpu_register_physical_memory(0, ram_size
, ram_offset
);
611 /* allocate and load BIOS */
612 bios_offset
= qemu_ram_alloc(BIOS_SIZE
);
613 if (bios_name
== NULL
)
614 bios_name
= BIOS_FILENAME
;
615 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
617 bios_size
= get_image_size(filename
);
621 if (bios_size
> 0 && bios_size
<= BIOS_SIZE
) {
622 target_phys_addr_t bios_addr
;
623 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
624 bios_addr
= (uint32_t)(-bios_size
);
625 cpu_register_physical_memory(bios_addr
, bios_size
,
626 bios_offset
| IO_MEM_ROM
);
627 bios_size
= load_image_targphys(filename
, bios_addr
, bios_size
);
629 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
630 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name
);
635 if (env
->nip
< 0xFFF80000 && bios_size
< 0x00100000) {
636 hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
640 kernel_base
= KERNEL_LOAD_ADDR
;
641 /* now we can load the kernel */
642 kernel_size
= load_image_targphys(kernel_filename
, kernel_base
,
643 ram_size
- kernel_base
);
644 if (kernel_size
< 0) {
645 hw_error("qemu: could not load kernel '%s'\n", kernel_filename
);
649 if (initrd_filename
) {
650 initrd_base
= INITRD_LOAD_ADDR
;
651 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
652 ram_size
- initrd_base
);
653 if (initrd_size
< 0) {
654 hw_error("qemu: could not load initial ram disk '%s'\n",
661 ppc_boot_device
= 'm';
667 ppc_boot_device
= '\0';
668 /* For now, OHW cannot boot from the network. */
669 for (i
= 0; boot_device
[i
] != '\0'; i
++) {
670 if (boot_device
[i
] >= 'a' && boot_device
[i
] <= 'f') {
671 ppc_boot_device
= boot_device
[i
];
675 if (ppc_boot_device
== '\0') {
676 fprintf(stderr
, "No valid boot device for Mac99 machine\n");
681 isa_mem_base
= 0xc0000000;
682 if (PPC_INPUT(env
) != PPC_FLAGS_INPUT_6xx
) {
683 hw_error("Only 6xx bus is supported on PREP machine\n");
685 i8259
= i8259_init(first_cpu
->irq_inputs
[PPC6xx_INPUT_INT
]);
686 pci_bus
= pci_prep_init(i8259
);
687 /* Hmm, prep has no pci-isa bridge ??? */
690 // pci_bus = i440fx_init();
691 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
692 PPC_io_memory
= cpu_register_io_memory(PPC_prep_io_read
,
693 PPC_prep_io_write
, sysctrl
);
694 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory
);
696 /* init basic PC hardware */
697 pci_vga_init(pci_bus
, 0, 0);
698 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
699 // pit = pit_init(0x40, i8259[0]);
703 serial_isa_init(0, serial_hds
[0]);
705 if (nb_nics1
> NE2000_NB_MAX
)
706 nb_nics1
= NE2000_NB_MAX
;
707 for(i
= 0; i
< nb_nics1
; i
++) {
708 if (nd_table
[i
].model
== NULL
) {
709 nd_table
[i
].model
= qemu_strdup("ne2k_isa");
711 if (strcmp(nd_table
[i
].model
, "ne2k_isa") == 0) {
712 isa_ne2000_init(ne2000_io
[i
], ne2000_irq
[i
], &nd_table
[i
]);
714 pci_nic_init_nofail(&nd_table
[i
], "ne2k_pci", NULL
);
718 if (drive_get_max_bus(IF_IDE
) >= MAX_IDE_BUS
) {
719 fprintf(stderr
, "qemu: too many IDE bus\n");
723 for(i
= 0; i
< MAX_IDE_BUS
* MAX_IDE_DEVS
; i
++) {
724 hd
[i
] = drive_get(IF_IDE
, i
/ MAX_IDE_DEVS
, i
% MAX_IDE_DEVS
);
727 for(i
= 0; i
< MAX_IDE_BUS
; i
++) {
728 isa_ide_init(ide_iobase
[i
], ide_iobase2
[i
], ide_irq
[i
],
732 isa_create_simple("i8042");
734 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
735 DMA_init(1, cpu_exit_irq
);
739 for(i
= 0; i
< MAX_FD
; i
++) {
740 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
744 /* Register speaker port */
745 register_ioport_read(0x61, 1, 1, speaker_ioport_read
, NULL
);
746 register_ioport_write(0x61, 1, 1, speaker_ioport_write
, NULL
);
747 /* Register fake IO ports for PREP */
748 sysctrl
->reset_irq
= first_cpu
->irq_inputs
[PPC6xx_INPUT_HRESET
];
749 register_ioport_read(0x398, 2, 1, &PREP_io_read
, sysctrl
);
750 register_ioport_write(0x398, 2, 1, &PREP_io_write
, sysctrl
);
751 /* System control ports */
752 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb
, sysctrl
);
753 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb
, sysctrl
);
754 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb
, sysctrl
);
755 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb
, sysctrl
);
756 /* PCI intack location */
757 PPC_io_memory
= cpu_register_io_memory(PPC_intack_read
,
758 PPC_intack_write
, NULL
);
759 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory
);
760 /* PowerPC control and status register group */
762 PPC_io_memory
= cpu_register_io_memory(PPC_XCSR_read
, PPC_XCSR_write
,
764 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory
);
768 usb_ohci_init_pci(pci_bus
, -1);
771 m48t59
= m48t59_init(i8259
[8], 0, 0x0074, NVRAM_SIZE
, 59);
774 sysctrl
->nvram
= m48t59
;
776 /* Initialise NVRAM */
777 nvram
.opaque
= m48t59
;
778 nvram
.read_fn
= &m48t59_read
;
779 nvram
.write_fn
= &m48t59_write
;
780 PPC_NVRAM_set_params(&nvram
, NVRAM_SIZE
, "PREP", ram_size
, ppc_boot_device
,
781 kernel_base
, kernel_size
,
783 initrd_base
, initrd_size
,
784 /* XXX: need an option to load a NVRAM image */
786 graphic_width
, graphic_height
, graphic_depth
);
788 /* Special port to get debug messages from Open-Firmware */
789 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write
, NULL
);
792 static QEMUMachine prep_machine
= {
794 .desc
= "PowerPC PREP platform",
795 .init
= ppc_prep_init
,
796 .max_cpus
= MAX_CPUS
,
799 static void prep_machine_init(void)
801 qemu_register_machine(&prep_machine
);
804 machine_init(prep_machine_init
);