hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34
  35 #define BIOS_FILENAME "ppc405_rom.bin"
  36 #define BIOS_SIZE (2048 * 1024)
  37
  38 #define KERNEL_LOAD_ADDR 0x00000000
  39 #define INITRD_LOAD_ADDR 0x01800000
  40
  41 #define USE_FLASH_BIOS
  42
  43 #define DEBUG_BOARD_INIT
  44
  45 /*****************************************************************************/
  46 /* PPC405EP reference board (IBM) */
  47 /* Standalone board with:
  48  * - PowerPC 405EP CPU
  49  * - SDRAM (0x00000000)
  50  * - Flash (0xFFF80000)
  51  * - SRAM  (0xFFF00000)
  52  * - NVRAM (0xF0000000)
  53  * - FPGA  (0xF0300000)
  54  */
  55 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  56 struct ref405ep_fpga_t {
  57     uint8_t reg0;
  58     uint8_t reg1;
  59 };
  60
  61 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  62 {
  63     ref405ep_fpga_t *fpga;
  64     uint32_t ret;
  65
  66     fpga = opaque;
  67     switch (addr) {
  68     case 0x0:
  69         ret = fpga->reg0;
  70         break;
  71     case 0x1:
  72         ret = fpga->reg1;
  73         break;
  74     default:
  75         ret = 0;
  76         break;
  77     }
  78
  79     return ret;
  80 }
  81
  82 static void ref405ep_fpga_writeb (void *opaque,
  83                                   target_phys_addr_t addr, uint32_t value)
  84 {
  85     ref405ep_fpga_t *fpga;
  86
  87     fpga = opaque;
  88     switch (addr) {
  89     case 0x0:
  90         /* Read only */
  91         break;
  92     case 0x1:
  93         fpga->reg1 = value;
  94         break;
  95     default:
  96         break;
  97     }
  98 }
  99
 100 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 101 {
 102     uint32_t ret;
 103
 104     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 105     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 106
 107     return ret;
 108 }
 109
 110 static void ref405ep_fpga_writew (void *opaque,
 111                                   target_phys_addr_t addr, uint32_t value)
 112 {
 113     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 114     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 115 }
 116
 117 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 118 {
 119     uint32_t ret;
 120
 121     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 122     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 125
 126     return ret;
 127 }
 128
 129 static void ref405ep_fpga_writel (void *opaque,
 130                                   target_phys_addr_t addr, uint32_t value)
 131 {
 132     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 133     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 136 }
 137
 138 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
 139     &ref405ep_fpga_readb,
 140     &ref405ep_fpga_readw,
 141     &ref405ep_fpga_readl,
 142 };
 143
 144 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
 145     &ref405ep_fpga_writeb,
 146     &ref405ep_fpga_writew,
 147     &ref405ep_fpga_writel,
 148 };
 149
 150 static void ref405ep_fpga_reset (void *opaque)
 151 {
 152     ref405ep_fpga_t *fpga;
 153
 154     fpga = opaque;
 155     fpga->reg0 = 0x00;
 156     fpga->reg1 = 0x0F;
 157 }
 158
 159 static void ref405ep_fpga_init (uint32_t base)
 160 {
 161     ref405ep_fpga_t *fpga;
 162     int fpga_memory;
 163
 164     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 165     fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
 166                                          ref405ep_fpga_write, fpga);
 167     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 168     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 169 }
 170
 171 static void ref405ep_init (QEMUMachine *machine, QemuOpts *opts)
 172 {
 173     ram_addr_t ram_size = qemu_opt_get_number(opts, "ram_size", 0);
 174     const char *kernel_filename = qemu_opt_get(opts, "kernel");
 175     const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
 176     const char *initrd_filename = qemu_opt_get(opts, "initrd");
 177     char *filename;
 178     ppc4xx_bd_info_t bd;
 179     CPUPPCState *env;
 180     qemu_irq *pic;
 181     ram_addr_t sram_offset, bios_offset, bdloc;
 182     target_phys_addr_t ram_bases[2], ram_sizes[2];
 183     target_ulong sram_size, bios_size;
 184     //int phy_addr = 0;
 185     //static int phy_addr = 1;
 186     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 187     int linux_boot;
 188     int fl_idx, fl_sectors, len;
 189     DriveInfo *dinfo;
 190
 191     /* XXX: fix this */
 192     ram_bases[0] = qemu_ram_alloc(0x08000000);
 193     ram_sizes[0] = 0x08000000;
 194     ram_bases[1] = 0x00000000;
 195     ram_sizes[1] = 0x00000000;
 196     ram_size = 128 * 1024 * 1024;
 197 #ifdef DEBUG_BOARD_INIT
 198     printf("%s: register cpu\n", __func__);
 199 #endif
 200     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 201                         kernel_filename == NULL ? 0 : 1);
 202     /* allocate SRAM */
 203     sram_size = 512 * 1024;
 204     sram_offset = qemu_ram_alloc(sram_size);
 205 #ifdef DEBUG_BOARD_INIT
 206     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 207 #endif
 208     cpu_register_physical_memory(0xFFF00000, sram_size,
 209                                  sram_offset | IO_MEM_RAM);
 210     /* allocate and load BIOS */
 211 #ifdef DEBUG_BOARD_INIT
 212     printf("%s: register BIOS\n", __func__);
 213 #endif
 214     fl_idx = 0;
 215 #ifdef USE_FLASH_BIOS
 216     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 217     if (dinfo) {
 218         bios_size = bdrv_getlength(dinfo->bdrv);
 219         bios_offset = qemu_ram_alloc(bios_size);
 220         fl_sectors = (bios_size + 65535) >> 16;
 221 #ifdef DEBUG_BOARD_INIT
 222         printf("Register parallel flash %d size " TARGET_FMT_lx
 223                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 224                fl_idx, bios_size, bios_offset, -bios_size,
 225                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 226 #endif
 227         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 228                               dinfo->bdrv, 65536, fl_sectors, 1,
 229                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 230                               1);
 231         fl_idx++;
 232     } else
 233 #endif
 234     {
 235 #ifdef DEBUG_BOARD_INIT
 236         printf("Load BIOS from file\n");
 237 #endif
 238         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 239         if (bios_name == NULL)
 240             bios_name = BIOS_FILENAME;
 241         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 242         if (filename) {
 243             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 244             qemu_free(filename);
 245         } else {
 246             bios_size = -1;
 247         }
 248         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 249             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 250                     bios_name);
 251             exit(1);
 252         }
 253         bios_size = (bios_size + 0xfff) & ~0xfff;
 254         cpu_register_physical_memory((uint32_t)(-bios_size),
 255                                      bios_size, bios_offset | IO_MEM_ROM);
 256     }
 257     /* Register FPGA */
 258 #ifdef DEBUG_BOARD_INIT
 259     printf("%s: register FPGA\n", __func__);
 260 #endif
 261     ref405ep_fpga_init(0xF0300000);
 262     /* Register NVRAM */
 263 #ifdef DEBUG_BOARD_INIT
 264     printf("%s: register NVRAM\n", __func__);
 265 #endif
 266     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 267     /* Load kernel */
 268     linux_boot = (kernel_filename != NULL);
 269     if (linux_boot) {
 270 #ifdef DEBUG_BOARD_INIT
 271         printf("%s: load kernel\n", __func__);
 272 #endif
 273         memset(&bd, 0, sizeof(bd));
 274         bd.bi_memstart = 0x00000000;
 275         bd.bi_memsize = ram_size;
 276         bd.bi_flashstart = -bios_size;
 277         bd.bi_flashsize = -bios_size;
 278         bd.bi_flashoffset = 0;
 279         bd.bi_sramstart = 0xFFF00000;
 280         bd.bi_sramsize = sram_size;
 281         bd.bi_bootflags = 0;
 282         bd.bi_intfreq = 133333333;
 283         bd.bi_busfreq = 33333333;
 284         bd.bi_baudrate = 115200;
 285         bd.bi_s_version[0] = 'Q';
 286         bd.bi_s_version[1] = 'M';
 287         bd.bi_s_version[2] = 'U';
 288         bd.bi_s_version[3] = '\0';
 289         bd.bi_r_version[0] = 'Q';
 290         bd.bi_r_version[1] = 'E';
 291         bd.bi_r_version[2] = 'M';
 292         bd.bi_r_version[3] = 'U';
 293         bd.bi_r_version[4] = '\0';
 294         bd.bi_procfreq = 133333333;
 295         bd.bi_plb_busfreq = 33333333;
 296         bd.bi_pci_busfreq = 33333333;
 297         bd.bi_opbfreq = 33333333;
 298         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 299         env->gpr[3] = bdloc;
 300         kernel_base = KERNEL_LOAD_ADDR;
 301         /* now we can load the kernel */
 302         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 303                                           ram_size - kernel_base);
 304         if (kernel_size < 0) {
 305             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 306                     kernel_filename);
 307             exit(1);
 308         }
 309         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
 310                kernel_size, kernel_base);
 311         /* load initrd */
 312         if (initrd_filename) {
 313             initrd_base = INITRD_LOAD_ADDR;
 314             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 315                                               ram_size - initrd_base);
 316             if (initrd_size < 0) {
 317                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 318                         initrd_filename);
 319                 exit(1);
 320             }
 321         } else {
 322             initrd_base = 0;
 323             initrd_size = 0;
 324         }
 325         env->gpr[4] = initrd_base;
 326         env->gpr[5] = initrd_size;
 327         if (kernel_cmdline != NULL) {
 328             len = strlen(kernel_cmdline);
 329             bdloc -= ((len + 255) & ~255);
 330             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 331             env->gpr[6] = bdloc;
 332             env->gpr[7] = bdloc + len;
 333         } else {
 334             env->gpr[6] = 0;
 335             env->gpr[7] = 0;
 336         }
 337         env->nip = KERNEL_LOAD_ADDR;
 338     } else {
 339         kernel_base = 0;
 340         kernel_size = 0;
 341         initrd_base = 0;
 342         initrd_size = 0;
 343         bdloc = 0;
 344     }
 345 #ifdef DEBUG_BOARD_INIT
 346     printf("%s: Done\n", __func__);
 347 #endif
 348     printf("bdloc %016lx\n", (unsigned long)bdloc);
 349 }
 350
 351 static QEMUMachine ref405ep_machine = {
 352     .name = "ref405ep",
 353     .desc = "ref405ep",
 354     .init = ref405ep_init,
 355 };
 356
 357 /*****************************************************************************/
 358 /* AMCC Taihu evaluation board */
 359 /* - PowerPC 405EP processor
 360  * - SDRAM               128 MB at 0x00000000
 361  * - Boot flash          2 MB   at 0xFFE00000
 362  * - Application flash   32 MB  at 0xFC000000
 363  * - 2 serial ports
 364  * - 2 ethernet PHY
 365  * - 1 USB 1.1 device    0x50000000
 366  * - 1 LCD display       0x50100000
 367  * - 1 CPLD              0x50100000
 368  * - 1 I2C EEPROM
 369  * - 1 I2C thermal sensor
 370  * - a set of LEDs
 371  * - bit-bang SPI port using GPIOs
 372  * - 1 EBC interface connector 0 0x50200000
 373  * - 1 cardbus controller + expansion slot.
 374  * - 1 PCI expansion slot.
 375  */
 376 typedef struct taihu_cpld_t taihu_cpld_t;
 377 struct taihu_cpld_t {
 378     uint8_t reg0;
 379     uint8_t reg1;
 380 };
 381
 382 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 383 {
 384     taihu_cpld_t *cpld;
 385     uint32_t ret;
 386
 387     cpld = opaque;
 388     switch (addr) {
 389     case 0x0:
 390         ret = cpld->reg0;
 391         break;
 392     case 0x1:
 393         ret = cpld->reg1;
 394         break;
 395     default:
 396         ret = 0;
 397         break;
 398     }
 399
 400     return ret;
 401 }
 402
 403 static void taihu_cpld_writeb (void *opaque,
 404                                target_phys_addr_t addr, uint32_t value)
 405 {
 406     taihu_cpld_t *cpld;
 407
 408     cpld = opaque;
 409     switch (addr) {
 410     case 0x0:
 411         /* Read only */
 412         break;
 413     case 0x1:
 414         cpld->reg1 = value;
 415         break;
 416     default:
 417         break;
 418     }
 419 }
 420
 421 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 422 {
 423     uint32_t ret;
 424
 425     ret = taihu_cpld_readb(opaque, addr) << 8;
 426     ret |= taihu_cpld_readb(opaque, addr + 1);
 427
 428     return ret;
 429 }
 430
 431 static void taihu_cpld_writew (void *opaque,
 432                                target_phys_addr_t addr, uint32_t value)
 433 {
 434     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 435     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 436 }
 437
 438 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 439 {
 440     uint32_t ret;
 441
 442     ret = taihu_cpld_readb(opaque, addr) << 24;
 443     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 444     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 445     ret |= taihu_cpld_readb(opaque, addr + 3);
 446
 447     return ret;
 448 }
 449
 450 static void taihu_cpld_writel (void *opaque,
 451                                target_phys_addr_t addr, uint32_t value)
 452 {
 453     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 454     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 455     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 456     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 457 }
 458
 459 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
 460     &taihu_cpld_readb,
 461     &taihu_cpld_readw,
 462     &taihu_cpld_readl,
 463 };
 464
 465 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
 466     &taihu_cpld_writeb,
 467     &taihu_cpld_writew,
 468     &taihu_cpld_writel,
 469 };
 470
 471 static void taihu_cpld_reset (void *opaque)
 472 {
 473     taihu_cpld_t *cpld;
 474
 475     cpld = opaque;
 476     cpld->reg0 = 0x01;
 477     cpld->reg1 = 0x80;
 478 }
 479
 480 static void taihu_cpld_init (uint32_t base)
 481 {
 482     taihu_cpld_t *cpld;
 483     int cpld_memory;
 484
 485     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 486     cpld_memory = cpu_register_io_memory(taihu_cpld_read,
 487                                          taihu_cpld_write, cpld);
 488     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 489     qemu_register_reset(&taihu_cpld_reset, cpld);
 490 }
 491
 492 static void taihu_405ep_init(QEMUMachine *machine, QemuOpts *opts)
 493 {
 494     ram_addr_t ram_size = qemu_opt_get_number(opts, "ram_size", 0);
 495     const char *kernel_filename = qemu_opt_get(opts, "kernel");
 496     const char *initrd_filename = qemu_opt_get(opts, "initrd");
 497     char *filename;
 498     CPUPPCState *env;
 499     qemu_irq *pic;
 500     ram_addr_t bios_offset;
 501     target_phys_addr_t ram_bases[2], ram_sizes[2];
 502     target_ulong bios_size;
 503     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 504     int linux_boot;
 505     int fl_idx, fl_sectors;
 506     DriveInfo *dinfo;
 507
 508     /* RAM is soldered to the board so the size cannot be changed */
 509     ram_bases[0] = qemu_ram_alloc(0x04000000);
 510     ram_sizes[0] = 0x04000000;
 511     ram_bases[1] = qemu_ram_alloc(0x04000000);
 512     ram_sizes[1] = 0x04000000;
 513     ram_size = 0x08000000;
 514 #ifdef DEBUG_BOARD_INIT
 515     printf("%s: register cpu\n", __func__);
 516 #endif
 517     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 518                         kernel_filename == NULL ? 0 : 1);
 519     /* allocate and load BIOS */
 520 #ifdef DEBUG_BOARD_INIT
 521     printf("%s: register BIOS\n", __func__);
 522 #endif
 523     fl_idx = 0;
 524 #if defined(USE_FLASH_BIOS)
 525     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 526     if (dinfo) {
 527         bios_size = bdrv_getlength(dinfo->bdrv);
 528         /* XXX: should check that size is 2MB */
 529         //        bios_size = 2 * 1024 * 1024;
 530         fl_sectors = (bios_size + 65535) >> 16;
 531         bios_offset = qemu_ram_alloc(bios_size);
 532 #ifdef DEBUG_BOARD_INIT
 533         printf("Register parallel flash %d size " TARGET_FMT_lx
 534                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 535                fl_idx, bios_size, bios_offset, -bios_size,
 536                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 537 #endif
 538         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 539                               dinfo->bdrv, 65536, fl_sectors, 1,
 540                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 541                               1);
 542         fl_idx++;
 543     } else
 544 #endif
 545     {
 546 #ifdef DEBUG_BOARD_INIT
 547         printf("Load BIOS from file\n");
 548 #endif
 549         if (bios_name == NULL)
 550             bios_name = BIOS_FILENAME;
 551         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 552         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 553         if (filename) {
 554             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 555         } else {
 556             bios_size = -1;
 557         }
 558         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 559             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 560                     bios_name);
 561             exit(1);
 562         }
 563         bios_size = (bios_size + 0xfff) & ~0xfff;
 564         cpu_register_physical_memory((uint32_t)(-bios_size),
 565                                      bios_size, bios_offset | IO_MEM_ROM);
 566     }
 567     /* Register Linux flash */
 568     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 569     if (dinfo) {
 570         bios_size = bdrv_getlength(dinfo->bdrv);
 571         /* XXX: should check that size is 32MB */
 572         bios_size = 32 * 1024 * 1024;
 573         fl_sectors = (bios_size + 65535) >> 16;
 574 #ifdef DEBUG_BOARD_INIT
 575         printf("Register parallel flash %d size " TARGET_FMT_lx
 576                " at offset %08lx  addr " TARGET_FMT_lx " '%s'\n",
 577                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 578                bdrv_get_device_name(dinfo->bdrv));
 579 #endif
 580         bios_offset = qemu_ram_alloc(bios_size);
 581         pflash_cfi02_register(0xfc000000, bios_offset,
 582                               dinfo->bdrv, 65536, fl_sectors, 1,
 583                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 584                               1);
 585         fl_idx++;
 586     }
 587     /* Register CLPD & LCD display */
 588 #ifdef DEBUG_BOARD_INIT
 589     printf("%s: register CPLD\n", __func__);
 590 #endif
 591     taihu_cpld_init(0x50100000);
 592     /* Load kernel */
 593     linux_boot = (kernel_filename != NULL);
 594     if (linux_boot) {
 595 #ifdef DEBUG_BOARD_INIT
 596         printf("%s: load kernel\n", __func__);
 597 #endif
 598         kernel_base = KERNEL_LOAD_ADDR;
 599         /* now we can load the kernel */
 600         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 601                                           ram_size - kernel_base);
 602         if (kernel_size < 0) {
 603             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 604                     kernel_filename);
 605             exit(1);
 606         }
 607         /* load initrd */
 608         if (initrd_filename) {
 609             initrd_base = INITRD_LOAD_ADDR;
 610             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 611                                               ram_size - initrd_base);
 612             if (initrd_size < 0) {
 613                 fprintf(stderr,
 614                         "qemu: could not load initial ram disk '%s'\n",
 615                         initrd_filename);
 616                 exit(1);
 617             }
 618         } else {
 619             initrd_base = 0;
 620             initrd_size = 0;
 621         }
 622     } else {
 623         kernel_base = 0;
 624         kernel_size = 0;
 625         initrd_base = 0;
 626         initrd_size = 0;
 627     }
 628 #ifdef DEBUG_BOARD_INIT
 629     printf("%s: Done\n", __func__);
 630 #endif
 631 }
 632
 633 static QEMUMachine taihu_machine = {
 634     .name = "taihu",
 635     .desc = "taihu",
 636     .init = taihu_405ep_init,
 637 };
 638
 639 static void ppc405_machine_init(void)
 640 {
 641     qemu_register_machine(&ref405ep_machine);
 642     qemu_register_machine(&taihu_machine);
 643 }
 644
 645 machine_init(ppc405_machine_init);