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Fix -device help and documentation
[qemu/aliguori-queue.git] / target-mips / op_helper.c
blob2bfdd5002f62188b50bf6d0c7dd78665920ce81c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "exec.h"
21
22 #include "host-utils.h"
23
24 #include "helper.h"
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
27
28 void helper_raise_exception_err (uint32_t exception, int error_code)
29 {
30 #if 1
31 if (exception < 0x100)
32 qemu_log("%s: %d %d\n", __func__, exception, error_code);
33 #endif
34 env->exception_index = exception;
35 env->error_code = error_code;
36 cpu_loop_exit();
37 }
38
39 void helper_raise_exception (uint32_t exception)
40 {
41 helper_raise_exception_err(exception, 0);
42 }
43
44 void helper_interrupt_restart (void)
45 {
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
52 helper_raise_exception(EXCP_EXT_INTERRUPT);
53 }
54 }
55
56 #if !defined(CONFIG_USER_ONLY)
57 static void do_restore_state (void *pc_ptr)
58 {
59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
66 }
67 #endif
68
69 #if defined(CONFIG_USER_ONLY)
70 #define HELPER_LD(name, insn, type) \
71 static inline type do_##name(target_ulong addr, int mem_idx) \
72 { \
73 return (type) insn##_raw(addr); \
74 }
75 #else
76 #define HELPER_LD(name, insn, type) \
77 static inline type do_##name(target_ulong addr, int mem_idx) \
78 { \
79 switch (mem_idx) \
80 { \
81 case 0: return (type) insn##_kernel(addr); break; \
82 case 1: return (type) insn##_super(addr); break; \
83 default: \
84 case 2: return (type) insn##_user(addr); break; \
85 } \
86 }
87 #endif
88 HELPER_LD(lbu, ldub, uint8_t)
89 HELPER_LD(lw, ldl, int32_t)
90 #ifdef TARGET_MIPS64
91 HELPER_LD(ld, ldq, int64_t)
92 #endif
93 #undef HELPER_LD
94
95 #if defined(CONFIG_USER_ONLY)
96 #define HELPER_ST(name, insn, type) \
97 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
98 { \
99 insn##_raw(addr, val); \
100 }
101 #else
102 #define HELPER_ST(name, insn, type) \
103 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
104 { \
105 switch (mem_idx) \
106 { \
107 case 0: insn##_kernel(addr, val); break; \
108 case 1: insn##_super(addr, val); break; \
109 default: \
110 case 2: insn##_user(addr, val); break; \
111 } \
112 }
113 #endif
114 HELPER_ST(sb, stb, uint8_t)
115 HELPER_ST(sw, stl, uint32_t)
116 #ifdef TARGET_MIPS64
117 HELPER_ST(sd, stq, uint64_t)
118 #endif
119 #undef HELPER_ST
120
121 target_ulong helper_clo (target_ulong arg1)
122 {
123 return clo32(arg1);
124 }
125
126 target_ulong helper_clz (target_ulong arg1)
127 {
128 return clz32(arg1);
129 }
130
131 #if defined(TARGET_MIPS64)
132 target_ulong helper_dclo (target_ulong arg1)
133 {
134 return clo64(arg1);
135 }
136
137 target_ulong helper_dclz (target_ulong arg1)
138 {
139 return clz64(arg1);
140 }
141 #endif /* TARGET_MIPS64 */
142
143 /* 64 bits arithmetic for 32 bits hosts */
144 static inline uint64_t get_HILO (void)
145 {
146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
147 }
148
149 static inline void set_HILO (uint64_t HILO)
150 {
151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
153 }
154
155 static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
156 {
157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
159 }
160
161 static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
162 {
163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
165 }
166
167 /* Multiplication variants of the vr54xx. */
168 target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
169 {
170 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
171
172 return arg1;
173 }
174
175 target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
176 {
177 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
178
179 return arg1;
180 }
181
182 target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
183 {
184 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
185
186 return arg1;
187 }
188
189 target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
190 {
191 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
192
193 return arg1;
194 }
195
196 target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
197 {
198 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
199
200 return arg1;
201 }
202
203 target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
204 {
205 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
206
207 return arg1;
208 }
209
210 target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
211 {
212 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
213
214 return arg1;
215 }
216
217 target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
218 {
219 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
220
221 return arg1;
222 }
223
224 target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
225 {
226 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
227
228 return arg1;
229 }
230
231 target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
232 {
233 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
234
235 return arg1;
236 }
237
238 target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
239 {
240 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
241
242 return arg1;
243 }
244
245 target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
246 {
247 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
248
249 return arg1;
250 }
251
252 target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
253 {
254 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
255
256 return arg1;
257 }
258
259 target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
260 {
261 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
262
263 return arg1;
264 }
265
266 #ifdef TARGET_MIPS64
267 void helper_dmult (target_ulong arg1, target_ulong arg2)
268 {
269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
270 }
271
272 void helper_dmultu (target_ulong arg1, target_ulong arg2)
273 {
274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
275 }
276 #endif
277
278 #ifndef CONFIG_USER_ONLY
279
280 static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
281 {
282 target_phys_addr_t lladdr;
283
284 lladdr = cpu_mips_translate_address(env, address, rw);
285
286 if (lladdr == -1LL) {
287 cpu_loop_exit();
288 } else {
289 return lladdr;
290 }
291 }
292
293 #define HELPER_LD_ATOMIC(name, insn) \
294 target_ulong helper_##name(target_ulong arg, int mem_idx) \
295 { \
296 env->lladdr = do_translate_address(arg, 0); \
297 env->llval = do_##insn(arg, mem_idx); \
298 return env->llval; \
299 }
300 HELPER_LD_ATOMIC(ll, lw)
301 #ifdef TARGET_MIPS64
302 HELPER_LD_ATOMIC(lld, ld)
303 #endif
304 #undef HELPER_LD_ATOMIC
305
306 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
307 target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
308 { \
309 target_long tmp; \
310 \
311 if (arg2 & almask) { \
312 env->CP0_BadVAddr = arg2; \
313 helper_raise_exception(EXCP_AdES); \
314 } \
315 if (do_translate_address(arg2, 1) == env->lladdr) { \
316 tmp = do_##ld_insn(arg2, mem_idx); \
317 if (tmp == env->llval) { \
318 do_##st_insn(arg2, arg1, mem_idx); \
319 return 1; \
320 } \
321 } \
322 return 0; \
323 }
324 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
325 #ifdef TARGET_MIPS64
326 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
327 #endif
328 #undef HELPER_ST_ATOMIC
329 #endif
330
331 #ifdef TARGET_WORDS_BIGENDIAN
332 #define GET_LMASK(v) ((v) & 3)
333 #define GET_OFFSET(addr, offset) (addr + (offset))
334 #else
335 #define GET_LMASK(v) (((v) & 3) ^ 3)
336 #define GET_OFFSET(addr, offset) (addr - (offset))
337 #endif
338
339 target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
340 {
341 target_ulong tmp;
342
343 tmp = do_lbu(arg2, mem_idx);
344 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
345
346 if (GET_LMASK(arg2) <= 2) {
347 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
348 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
349 }
350
351 if (GET_LMASK(arg2) <= 1) {
352 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
353 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
354 }
355
356 if (GET_LMASK(arg2) == 0) {
357 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
358 arg1 = (arg1 & 0xFFFFFF00) | tmp;
359 }
360 return (int32_t)arg1;
361 }
362
363 target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
364 {
365 target_ulong tmp;
366
367 tmp = do_lbu(arg2, mem_idx);
368 arg1 = (arg1 & 0xFFFFFF00) | tmp;
369
370 if (GET_LMASK(arg2) >= 1) {
371 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
372 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
373 }
374
375 if (GET_LMASK(arg2) >= 2) {
376 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
377 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
378 }
379
380 if (GET_LMASK(arg2) == 3) {
381 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
382 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
383 }
384 return (int32_t)arg1;
385 }
386
387 void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
388 {
389 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
390
391 if (GET_LMASK(arg2) <= 2)
392 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
393
394 if (GET_LMASK(arg2) <= 1)
395 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
396
397 if (GET_LMASK(arg2) == 0)
398 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
399 }
400
401 void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
402 {
403 do_sb(arg2, (uint8_t)arg1, mem_idx);
404
405 if (GET_LMASK(arg2) >= 1)
406 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
407
408 if (GET_LMASK(arg2) >= 2)
409 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
410
411 if (GET_LMASK(arg2) == 3)
412 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
413 }
414
415 #if defined(TARGET_MIPS64)
416 /* "half" load and stores. We must do the memory access inline,
417 or fault handling won't work. */
418
419 #ifdef TARGET_WORDS_BIGENDIAN
420 #define GET_LMASK64(v) ((v) & 7)
421 #else
422 #define GET_LMASK64(v) (((v) & 7) ^ 7)
423 #endif
424
425 target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
426 {
427 uint64_t tmp;
428
429 tmp = do_lbu(arg2, mem_idx);
430 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
431
432 if (GET_LMASK64(arg2) <= 6) {
433 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
434 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
435 }
436
437 if (GET_LMASK64(arg2) <= 5) {
438 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
439 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
440 }
441
442 if (GET_LMASK64(arg2) <= 4) {
443 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
444 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
445 }
446
447 if (GET_LMASK64(arg2) <= 3) {
448 tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
449 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
450 }
451
452 if (GET_LMASK64(arg2) <= 2) {
453 tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
454 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
455 }
456
457 if (GET_LMASK64(arg2) <= 1) {
458 tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
459 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
460 }
461
462 if (GET_LMASK64(arg2) == 0) {
463 tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
464 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
465 }
466
467 return arg1;
468 }
469
470 target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
471 {
472 uint64_t tmp;
473
474 tmp = do_lbu(arg2, mem_idx);
475 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
476
477 if (GET_LMASK64(arg2) >= 1) {
478 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
479 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
480 }
481
482 if (GET_LMASK64(arg2) >= 2) {
483 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
484 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
485 }
486
487 if (GET_LMASK64(arg2) >= 3) {
488 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
489 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
490 }
491
492 if (GET_LMASK64(arg2) >= 4) {
493 tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
494 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
495 }
496
497 if (GET_LMASK64(arg2) >= 5) {
498 tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
499 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
500 }
501
502 if (GET_LMASK64(arg2) >= 6) {
503 tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
504 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
505 }
506
507 if (GET_LMASK64(arg2) == 7) {
508 tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
509 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
510 }
511
512 return arg1;
513 }
514
515 void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
516 {
517 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
518
519 if (GET_LMASK64(arg2) <= 6)
520 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
521
522 if (GET_LMASK64(arg2) <= 5)
523 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
524
525 if (GET_LMASK64(arg2) <= 4)
526 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
527
528 if (GET_LMASK64(arg2) <= 3)
529 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
530
531 if (GET_LMASK64(arg2) <= 2)
532 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
533
534 if (GET_LMASK64(arg2) <= 1)
535 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
536
537 if (GET_LMASK64(arg2) <= 0)
538 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
539 }
540
541 void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
542 {
543 do_sb(arg2, (uint8_t)arg1, mem_idx);
544
545 if (GET_LMASK64(arg2) >= 1)
546 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
547
548 if (GET_LMASK64(arg2) >= 2)
549 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
550
551 if (GET_LMASK64(arg2) >= 3)
552 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
553
554 if (GET_LMASK64(arg2) >= 4)
555 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
556
557 if (GET_LMASK64(arg2) >= 5)
558 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
559
560 if (GET_LMASK64(arg2) >= 6)
561 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
562
563 if (GET_LMASK64(arg2) == 7)
564 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
565 }
566 #endif /* TARGET_MIPS64 */
567
568 #ifndef CONFIG_USER_ONLY
569 /* CP0 helpers */
570 target_ulong helper_mfc0_mvpcontrol (void)
571 {
572 return env->mvp->CP0_MVPControl;
573 }
574
575 target_ulong helper_mfc0_mvpconf0 (void)
576 {
577 return env->mvp->CP0_MVPConf0;
578 }
579
580 target_ulong helper_mfc0_mvpconf1 (void)
581 {
582 return env->mvp->CP0_MVPConf1;
583 }
584
585 target_ulong helper_mfc0_random (void)
586 {
587 return (int32_t)cpu_mips_get_random(env);
588 }
589
590 target_ulong helper_mfc0_tcstatus (void)
591 {
592 return env->active_tc.CP0_TCStatus;
593 }
594
595 target_ulong helper_mftc0_tcstatus(void)
596 {
597 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
598
599 if (other_tc == env->current_tc)
600 return env->active_tc.CP0_TCStatus;
601 else
602 return env->tcs[other_tc].CP0_TCStatus;
603 }
604
605 target_ulong helper_mfc0_tcbind (void)
606 {
607 return env->active_tc.CP0_TCBind;
608 }
609
610 target_ulong helper_mftc0_tcbind(void)
611 {
612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
613
614 if (other_tc == env->current_tc)
615 return env->active_tc.CP0_TCBind;
616 else
617 return env->tcs[other_tc].CP0_TCBind;
618 }
619
620 target_ulong helper_mfc0_tcrestart (void)
621 {
622 return env->active_tc.PC;
623 }
624
625 target_ulong helper_mftc0_tcrestart(void)
626 {
627 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
628
629 if (other_tc == env->current_tc)
630 return env->active_tc.PC;
631 else
632 return env->tcs[other_tc].PC;
633 }
634
635 target_ulong helper_mfc0_tchalt (void)
636 {
637 return env->active_tc.CP0_TCHalt;
638 }
639
640 target_ulong helper_mftc0_tchalt(void)
641 {
642 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
643
644 if (other_tc == env->current_tc)
645 return env->active_tc.CP0_TCHalt;
646 else
647 return env->tcs[other_tc].CP0_TCHalt;
648 }
649
650 target_ulong helper_mfc0_tccontext (void)
651 {
652 return env->active_tc.CP0_TCContext;
653 }
654
655 target_ulong helper_mftc0_tccontext(void)
656 {
657 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
658
659 if (other_tc == env->current_tc)
660 return env->active_tc.CP0_TCContext;
661 else
662 return env->tcs[other_tc].CP0_TCContext;
663 }
664
665 target_ulong helper_mfc0_tcschedule (void)
666 {
667 return env->active_tc.CP0_TCSchedule;
668 }
669
670 target_ulong helper_mftc0_tcschedule(void)
671 {
672 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
673
674 if (other_tc == env->current_tc)
675 return env->active_tc.CP0_TCSchedule;
676 else
677 return env->tcs[other_tc].CP0_TCSchedule;
678 }
679
680 target_ulong helper_mfc0_tcschefback (void)
681 {
682 return env->active_tc.CP0_TCScheFBack;
683 }
684
685 target_ulong helper_mftc0_tcschefback(void)
686 {
687 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
688
689 if (other_tc == env->current_tc)
690 return env->active_tc.CP0_TCScheFBack;
691 else
692 return env->tcs[other_tc].CP0_TCScheFBack;
693 }
694
695 target_ulong helper_mfc0_count (void)
696 {
697 return (int32_t)cpu_mips_get_count(env);
698 }
699
700 target_ulong helper_mftc0_entryhi(void)
701 {
702 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
703 int32_t tcstatus;
704
705 if (other_tc == env->current_tc)
706 tcstatus = env->active_tc.CP0_TCStatus;
707 else
708 tcstatus = env->tcs[other_tc].CP0_TCStatus;
709
710 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
711 }
712
713 target_ulong helper_mftc0_status(void)
714 {
715 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
716 target_ulong t0;
717 int32_t tcstatus;
718
719 if (other_tc == env->current_tc)
720 tcstatus = env->active_tc.CP0_TCStatus;
721 else
722 tcstatus = env->tcs[other_tc].CP0_TCStatus;
723
724 t0 = env->CP0_Status & ~0xf1000018;
725 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
726 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
727 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
728
729 return t0;
730 }
731
732 target_ulong helper_mfc0_lladdr (void)
733 {
734 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
735 }
736
737 target_ulong helper_mfc0_watchlo (uint32_t sel)
738 {
739 return (int32_t)env->CP0_WatchLo[sel];
740 }
741
742 target_ulong helper_mfc0_watchhi (uint32_t sel)
743 {
744 return env->CP0_WatchHi[sel];
745 }
746
747 target_ulong helper_mfc0_debug (void)
748 {
749 target_ulong t0 = env->CP0_Debug;
750 if (env->hflags & MIPS_HFLAG_DM)
751 t0 |= 1 << CP0DB_DM;
752
753 return t0;
754 }
755
756 target_ulong helper_mftc0_debug(void)
757 {
758 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
759 int32_t tcstatus;
760
761 if (other_tc == env->current_tc)
762 tcstatus = env->active_tc.CP0_Debug_tcstatus;
763 else
764 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
765
766 /* XXX: Might be wrong, check with EJTAG spec. */
767 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
768 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
769 }
770
771 #if defined(TARGET_MIPS64)
772 target_ulong helper_dmfc0_tcrestart (void)
773 {
774 return env->active_tc.PC;
775 }
776
777 target_ulong helper_dmfc0_tchalt (void)
778 {
779 return env->active_tc.CP0_TCHalt;
780 }
781
782 target_ulong helper_dmfc0_tccontext (void)
783 {
784 return env->active_tc.CP0_TCContext;
785 }
786
787 target_ulong helper_dmfc0_tcschedule (void)
788 {
789 return env->active_tc.CP0_TCSchedule;
790 }
791
792 target_ulong helper_dmfc0_tcschefback (void)
793 {
794 return env->active_tc.CP0_TCScheFBack;
795 }
796
797 target_ulong helper_dmfc0_lladdr (void)
798 {
799 return env->lladdr >> env->CP0_LLAddr_shift;
800 }
801
802 target_ulong helper_dmfc0_watchlo (uint32_t sel)
803 {
804 return env->CP0_WatchLo[sel];
805 }
806 #endif /* TARGET_MIPS64 */
807
808 void helper_mtc0_index (target_ulong arg1)
809 {
810 int num = 1;
811 unsigned int tmp = env->tlb->nb_tlb;
812
813 do {
814 tmp >>= 1;
815 num <<= 1;
816 } while (tmp);
817 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
818 }
819
820 void helper_mtc0_mvpcontrol (target_ulong arg1)
821 {
822 uint32_t mask = 0;
823 uint32_t newval;
824
825 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
826 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
827 (1 << CP0MVPCo_EVP);
828 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
829 mask |= (1 << CP0MVPCo_STLB);
830 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
831
832 // TODO: Enable/disable shared TLB, enable/disable VPEs.
833
834 env->mvp->CP0_MVPControl = newval;
835 }
836
837 void helper_mtc0_vpecontrol (target_ulong arg1)
838 {
839 uint32_t mask;
840 uint32_t newval;
841
842 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
843 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
844 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
845
846 /* Yield scheduler intercept not implemented. */
847 /* Gating storage scheduler intercept not implemented. */
848
849 // TODO: Enable/disable TCs.
850
851 env->CP0_VPEControl = newval;
852 }
853
854 void helper_mtc0_vpeconf0 (target_ulong arg1)
855 {
856 uint32_t mask = 0;
857 uint32_t newval;
858
859 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
860 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
861 mask |= (0xff << CP0VPEC0_XTC);
862 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
863 }
864 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
865
866 // TODO: TC exclusive handling due to ERL/EXL.
867
868 env->CP0_VPEConf0 = newval;
869 }
870
871 void helper_mtc0_vpeconf1 (target_ulong arg1)
872 {
873 uint32_t mask = 0;
874 uint32_t newval;
875
876 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
877 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
878 (0xff << CP0VPEC1_NCP1);
879 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
880
881 /* UDI not implemented. */
882 /* CP2 not implemented. */
883
884 // TODO: Handle FPU (CP1) binding.
885
886 env->CP0_VPEConf1 = newval;
887 }
888
889 void helper_mtc0_yqmask (target_ulong arg1)
890 {
891 /* Yield qualifier inputs not implemented. */
892 env->CP0_YQMask = 0x00000000;
893 }
894
895 void helper_mtc0_vpeopt (target_ulong arg1)
896 {
897 env->CP0_VPEOpt = arg1 & 0x0000ffff;
898 }
899
900 void helper_mtc0_entrylo0 (target_ulong arg1)
901 {
902 /* Large physaddr (PABITS) not implemented */
903 /* 1k pages not implemented */
904 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
905 }
906
907 void helper_mtc0_tcstatus (target_ulong arg1)
908 {
909 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
910 uint32_t newval;
911
912 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
913
914 // TODO: Sync with CP0_Status.
915
916 env->active_tc.CP0_TCStatus = newval;
917 }
918
919 void helper_mttc0_tcstatus (target_ulong arg1)
920 {
921 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
922
923 // TODO: Sync with CP0_Status.
924
925 if (other_tc == env->current_tc)
926 env->active_tc.CP0_TCStatus = arg1;
927 else
928 env->tcs[other_tc].CP0_TCStatus = arg1;
929 }
930
931 void helper_mtc0_tcbind (target_ulong arg1)
932 {
933 uint32_t mask = (1 << CP0TCBd_TBE);
934 uint32_t newval;
935
936 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
937 mask |= (1 << CP0TCBd_CurVPE);
938 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
939 env->active_tc.CP0_TCBind = newval;
940 }
941
942 void helper_mttc0_tcbind (target_ulong arg1)
943 {
944 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
945 uint32_t mask = (1 << CP0TCBd_TBE);
946 uint32_t newval;
947
948 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
949 mask |= (1 << CP0TCBd_CurVPE);
950 if (other_tc == env->current_tc) {
951 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
952 env->active_tc.CP0_TCBind = newval;
953 } else {
954 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
955 env->tcs[other_tc].CP0_TCBind = newval;
956 }
957 }
958
959 void helper_mtc0_tcrestart (target_ulong arg1)
960 {
961 env->active_tc.PC = arg1;
962 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
963 env->lladdr = 0ULL;
964 /* MIPS16 not implemented. */
965 }
966
967 void helper_mttc0_tcrestart (target_ulong arg1)
968 {
969 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
970
971 if (other_tc == env->current_tc) {
972 env->active_tc.PC = arg1;
973 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
974 env->lladdr = 0ULL;
975 /* MIPS16 not implemented. */
976 } else {
977 env->tcs[other_tc].PC = arg1;
978 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
979 env->lladdr = 0ULL;
980 /* MIPS16 not implemented. */
981 }
982 }
983
984 void helper_mtc0_tchalt (target_ulong arg1)
985 {
986 env->active_tc.CP0_TCHalt = arg1 & 0x1;
987
988 // TODO: Halt TC / Restart (if allocated+active) TC.
989 }
990
991 void helper_mttc0_tchalt (target_ulong arg1)
992 {
993 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
994
995 // TODO: Halt TC / Restart (if allocated+active) TC.
996
997 if (other_tc == env->current_tc)
998 env->active_tc.CP0_TCHalt = arg1;
999 else
1000 env->tcs[other_tc].CP0_TCHalt = arg1;
1001 }
1002
1003 void helper_mtc0_tccontext (target_ulong arg1)
1004 {
1005 env->active_tc.CP0_TCContext = arg1;
1006 }
1007
1008 void helper_mttc0_tccontext (target_ulong arg1)
1009 {
1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1011
1012 if (other_tc == env->current_tc)
1013 env->active_tc.CP0_TCContext = arg1;
1014 else
1015 env->tcs[other_tc].CP0_TCContext = arg1;
1016 }
1017
1018 void helper_mtc0_tcschedule (target_ulong arg1)
1019 {
1020 env->active_tc.CP0_TCSchedule = arg1;
1021 }
1022
1023 void helper_mttc0_tcschedule (target_ulong arg1)
1024 {
1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1026
1027 if (other_tc == env->current_tc)
1028 env->active_tc.CP0_TCSchedule = arg1;
1029 else
1030 env->tcs[other_tc].CP0_TCSchedule = arg1;
1031 }
1032
1033 void helper_mtc0_tcschefback (target_ulong arg1)
1034 {
1035 env->active_tc.CP0_TCScheFBack = arg1;
1036 }
1037
1038 void helper_mttc0_tcschefback (target_ulong arg1)
1039 {
1040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1041
1042 if (other_tc == env->current_tc)
1043 env->active_tc.CP0_TCScheFBack = arg1;
1044 else
1045 env->tcs[other_tc].CP0_TCScheFBack = arg1;
1046 }
1047
1048 void helper_mtc0_entrylo1 (target_ulong arg1)
1049 {
1050 /* Large physaddr (PABITS) not implemented */
1051 /* 1k pages not implemented */
1052 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1053 }
1054
1055 void helper_mtc0_context (target_ulong arg1)
1056 {
1057 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1058 }
1059
1060 void helper_mtc0_pagemask (target_ulong arg1)
1061 {
1062 /* 1k pages not implemented */
1063 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1064 }
1065
1066 void helper_mtc0_pagegrain (target_ulong arg1)
1067 {
1068 /* SmartMIPS not implemented */
1069 /* Large physaddr (PABITS) not implemented */
1070 /* 1k pages not implemented */
1071 env->CP0_PageGrain = 0;
1072 }
1073
1074 void helper_mtc0_wired (target_ulong arg1)
1075 {
1076 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1077 }
1078
1079 void helper_mtc0_srsconf0 (target_ulong arg1)
1080 {
1081 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1082 }
1083
1084 void helper_mtc0_srsconf1 (target_ulong arg1)
1085 {
1086 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1087 }
1088
1089 void helper_mtc0_srsconf2 (target_ulong arg1)
1090 {
1091 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1092 }
1093
1094 void helper_mtc0_srsconf3 (target_ulong arg1)
1095 {
1096 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1097 }
1098
1099 void helper_mtc0_srsconf4 (target_ulong arg1)
1100 {
1101 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1102 }
1103
1104 void helper_mtc0_hwrena (target_ulong arg1)
1105 {
1106 env->CP0_HWREna = arg1 & 0x0000000F;
1107 }
1108
1109 void helper_mtc0_count (target_ulong arg1)
1110 {
1111 cpu_mips_store_count(env, arg1);
1112 }
1113
1114 void helper_mtc0_entryhi (target_ulong arg1)
1115 {
1116 target_ulong old, val;
1117
1118 /* 1k pages not implemented */
1119 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1120 #if defined(TARGET_MIPS64)
1121 val &= env->SEGMask;
1122 #endif
1123 old = env->CP0_EntryHi;
1124 env->CP0_EntryHi = val;
1125 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1126 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1127 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1128 }
1129 /* If the ASID changes, flush qemu's TLB. */
1130 if ((old & 0xFF) != (val & 0xFF))
1131 cpu_mips_tlb_flush(env, 1);
1132 }
1133
1134 void helper_mttc0_entryhi(target_ulong arg1)
1135 {
1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1137 int32_t tcstatus;
1138
1139 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
1140 if (other_tc == env->current_tc) {
1141 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1142 env->active_tc.CP0_TCStatus = tcstatus;
1143 } else {
1144 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1145 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1146 }
1147 }
1148
1149 void helper_mtc0_compare (target_ulong arg1)
1150 {
1151 cpu_mips_store_compare(env, arg1);
1152 }
1153
1154 void helper_mtc0_status (target_ulong arg1)
1155 {
1156 uint32_t val, old;
1157 uint32_t mask = env->CP0_Status_rw_bitmask;
1158
1159 val = arg1 & mask;
1160 old = env->CP0_Status;
1161 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1162 compute_hflags(env);
1163 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1164 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1165 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1166 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1167 env->CP0_Cause);
1168 switch (env->hflags & MIPS_HFLAG_KSU) {
1169 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1170 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1171 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1172 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1173 }
1174 }
1175 cpu_mips_update_irq(env);
1176 }
1177
1178 void helper_mttc0_status(target_ulong arg1)
1179 {
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1182
1183 env->CP0_Status = arg1 & ~0xf1000018;
1184 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1185 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1186 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1187 if (other_tc == env->current_tc)
1188 env->active_tc.CP0_TCStatus = tcstatus;
1189 else
1190 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1191 }
1192
1193 void helper_mtc0_intctl (target_ulong arg1)
1194 {
1195 /* vectored interrupts not implemented, no performance counters. */
1196 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1197 }
1198
1199 void helper_mtc0_srsctl (target_ulong arg1)
1200 {
1201 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1202 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1203 }
1204
1205 void helper_mtc0_cause (target_ulong arg1)
1206 {
1207 uint32_t mask = 0x00C00300;
1208 uint32_t old = env->CP0_Cause;
1209
1210 if (env->insn_flags & ISA_MIPS32R2)
1211 mask |= 1 << CP0Ca_DC;
1212
1213 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1214
1215 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1216 if (env->CP0_Cause & (1 << CP0Ca_DC))
1217 cpu_mips_stop_count(env);
1218 else
1219 cpu_mips_start_count(env);
1220 }
1221
1222 /* Handle the software interrupt as an hardware one, as they
1223 are very similar */
1224 if (arg1 & CP0Ca_IP_mask) {
1225 cpu_mips_update_irq(env);
1226 }
1227 }
1228
1229 void helper_mtc0_ebase (target_ulong arg1)
1230 {
1231 /* vectored interrupts not implemented */
1232 /* Multi-CPU not implemented */
1233 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1234 }
1235
1236 void helper_mtc0_config0 (target_ulong arg1)
1237 {
1238 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1239 }
1240
1241 void helper_mtc0_config2 (target_ulong arg1)
1242 {
1243 /* tertiary/secondary caches not implemented */
1244 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1245 }
1246
1247 void helper_mtc0_lladdr (target_ulong arg1)
1248 {
1249 target_long mask = env->CP0_LLAddr_rw_bitmask;
1250 arg1 = arg1 << env->CP0_LLAddr_shift;
1251 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1252 }
1253
1254 void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
1255 {
1256 /* Watch exceptions for instructions, data loads, data stores
1257 not implemented. */
1258 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1259 }
1260
1261 void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
1262 {
1263 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1264 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1265 }
1266
1267 void helper_mtc0_xcontext (target_ulong arg1)
1268 {
1269 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1270 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1271 }
1272
1273 void helper_mtc0_framemask (target_ulong arg1)
1274 {
1275 env->CP0_Framemask = arg1; /* XXX */
1276 }
1277
1278 void helper_mtc0_debug (target_ulong arg1)
1279 {
1280 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1281 if (arg1 & (1 << CP0DB_DM))
1282 env->hflags |= MIPS_HFLAG_DM;
1283 else
1284 env->hflags &= ~MIPS_HFLAG_DM;
1285 }
1286
1287 void helper_mttc0_debug(target_ulong arg1)
1288 {
1289 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1290 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1291
1292 /* XXX: Might be wrong, check with EJTAG spec. */
1293 if (other_tc == env->current_tc)
1294 env->active_tc.CP0_Debug_tcstatus = val;
1295 else
1296 env->tcs[other_tc].CP0_Debug_tcstatus = val;
1297 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1298 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1299 }
1300
1301 void helper_mtc0_performance0 (target_ulong arg1)
1302 {
1303 env->CP0_Performance0 = arg1 & 0x000007ff;
1304 }
1305
1306 void helper_mtc0_taglo (target_ulong arg1)
1307 {
1308 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1309 }
1310
1311 void helper_mtc0_datalo (target_ulong arg1)
1312 {
1313 env->CP0_DataLo = arg1; /* XXX */
1314 }
1315
1316 void helper_mtc0_taghi (target_ulong arg1)
1317 {
1318 env->CP0_TagHi = arg1; /* XXX */
1319 }
1320
1321 void helper_mtc0_datahi (target_ulong arg1)
1322 {
1323 env->CP0_DataHi = arg1; /* XXX */
1324 }
1325
1326 /* MIPS MT functions */
1327 target_ulong helper_mftgpr(uint32_t sel)
1328 {
1329 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1330
1331 if (other_tc == env->current_tc)
1332 return env->active_tc.gpr[sel];
1333 else
1334 return env->tcs[other_tc].gpr[sel];
1335 }
1336
1337 target_ulong helper_mftlo(uint32_t sel)
1338 {
1339 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1340
1341 if (other_tc == env->current_tc)
1342 return env->active_tc.LO[sel];
1343 else
1344 return env->tcs[other_tc].LO[sel];
1345 }
1346
1347 target_ulong helper_mfthi(uint32_t sel)
1348 {
1349 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1350
1351 if (other_tc == env->current_tc)
1352 return env->active_tc.HI[sel];
1353 else
1354 return env->tcs[other_tc].HI[sel];
1355 }
1356
1357 target_ulong helper_mftacx(uint32_t sel)
1358 {
1359 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1360
1361 if (other_tc == env->current_tc)
1362 return env->active_tc.ACX[sel];
1363 else
1364 return env->tcs[other_tc].ACX[sel];
1365 }
1366
1367 target_ulong helper_mftdsp(void)
1368 {
1369 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1370
1371 if (other_tc == env->current_tc)
1372 return env->active_tc.DSPControl;
1373 else
1374 return env->tcs[other_tc].DSPControl;
1375 }
1376
1377 void helper_mttgpr(target_ulong arg1, uint32_t sel)
1378 {
1379 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1380
1381 if (other_tc == env->current_tc)
1382 env->active_tc.gpr[sel] = arg1;
1383 else
1384 env->tcs[other_tc].gpr[sel] = arg1;
1385 }
1386
1387 void helper_mttlo(target_ulong arg1, uint32_t sel)
1388 {
1389 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1390
1391 if (other_tc == env->current_tc)
1392 env->active_tc.LO[sel] = arg1;
1393 else
1394 env->tcs[other_tc].LO[sel] = arg1;
1395 }
1396
1397 void helper_mtthi(target_ulong arg1, uint32_t sel)
1398 {
1399 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1400
1401 if (other_tc == env->current_tc)
1402 env->active_tc.HI[sel] = arg1;
1403 else
1404 env->tcs[other_tc].HI[sel] = arg1;
1405 }
1406
1407 void helper_mttacx(target_ulong arg1, uint32_t sel)
1408 {
1409 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1410
1411 if (other_tc == env->current_tc)
1412 env->active_tc.ACX[sel] = arg1;
1413 else
1414 env->tcs[other_tc].ACX[sel] = arg1;
1415 }
1416
1417 void helper_mttdsp(target_ulong arg1)
1418 {
1419 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1420
1421 if (other_tc == env->current_tc)
1422 env->active_tc.DSPControl = arg1;
1423 else
1424 env->tcs[other_tc].DSPControl = arg1;
1425 }
1426
1427 /* MIPS MT functions */
1428 target_ulong helper_dmt(target_ulong arg1)
1429 {
1430 // TODO
1431 arg1 = 0;
1432 // rt = arg1
1433
1434 return arg1;
1435 }
1436
1437 target_ulong helper_emt(target_ulong arg1)
1438 {
1439 // TODO
1440 arg1 = 0;
1441 // rt = arg1
1442
1443 return arg1;
1444 }
1445
1446 target_ulong helper_dvpe(target_ulong arg1)
1447 {
1448 // TODO
1449 arg1 = 0;
1450 // rt = arg1
1451
1452 return arg1;
1453 }
1454
1455 target_ulong helper_evpe(target_ulong arg1)
1456 {
1457 // TODO
1458 arg1 = 0;
1459 // rt = arg1
1460
1461 return arg1;
1462 }
1463 #endif /* !CONFIG_USER_ONLY */
1464
1465 void helper_fork(target_ulong arg1, target_ulong arg2)
1466 {
1467 // arg1 = rt, arg2 = rs
1468 arg1 = 0;
1469 // TODO: store to TC register
1470 }
1471
1472 target_ulong helper_yield(target_ulong arg1)
1473 {
1474 if (arg1 < 0) {
1475 /* No scheduling policy implemented. */
1476 if (arg1 != -2) {
1477 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1478 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1481 helper_raise_exception(EXCP_THREAD);
1482 }
1483 }
1484 } else if (arg1 == 0) {
1485 if (0 /* TODO: TC underflow */) {
1486 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1487 helper_raise_exception(EXCP_THREAD);
1488 } else {
1489 // TODO: Deallocate TC
1490 }
1491 } else if (arg1 > 0) {
1492 /* Yield qualifier inputs not implemented. */
1493 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1494 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1495 helper_raise_exception(EXCP_THREAD);
1496 }
1497 return env->CP0_YQMask;
1498 }
1499
1500 #ifndef CONFIG_USER_ONLY
1501 /* TLB management */
1502 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1503 {
1504 /* Flush qemu's TLB and discard all shadowed entries. */
1505 tlb_flush (env, flush_global);
1506 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1507 }
1508
1509 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
1510 {
1511 /* Discard entries from env->tlb[first] onwards. */
1512 while (env->tlb->tlb_in_use > first) {
1513 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1514 }
1515 }
1516
1517 static void r4k_fill_tlb (int idx)
1518 {
1519 r4k_tlb_t *tlb;
1520
1521 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1522 tlb = &env->tlb->mmu.r4k.tlb[idx];
1523 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1524 #if defined(TARGET_MIPS64)
1525 tlb->VPN &= env->SEGMask;
1526 #endif
1527 tlb->ASID = env->CP0_EntryHi & 0xFF;
1528 tlb->PageMask = env->CP0_PageMask;
1529 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1530 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1531 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1532 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1533 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1534 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1535 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1536 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1537 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1538 }
1539
1540 void r4k_helper_tlbwi (void)
1541 {
1542 int idx;
1543
1544 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1545
1546 /* Discard cached TLB entries. We could avoid doing this if the
1547 tlbwi is just upgrading access permissions on the current entry;
1548 that might be a further win. */
1549 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1550
1551 r4k_invalidate_tlb(env, idx, 0);
1552 r4k_fill_tlb(idx);
1553 }
1554
1555 void r4k_helper_tlbwr (void)
1556 {
1557 int r = cpu_mips_get_random(env);
1558
1559 r4k_invalidate_tlb(env, r, 1);
1560 r4k_fill_tlb(r);
1561 }
1562
1563 void r4k_helper_tlbp (void)
1564 {
1565 r4k_tlb_t *tlb;
1566 target_ulong mask;
1567 target_ulong tag;
1568 target_ulong VPN;
1569 uint8_t ASID;
1570 int i;
1571
1572 ASID = env->CP0_EntryHi & 0xFF;
1573 for (i = 0; i < env->tlb->nb_tlb; i++) {
1574 tlb = &env->tlb->mmu.r4k.tlb[i];
1575 /* 1k pages are not supported. */
1576 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1577 tag = env->CP0_EntryHi & ~mask;
1578 VPN = tlb->VPN & ~mask;
1579 /* Check ASID, virtual page number & size */
1580 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1581 /* TLB match */
1582 env->CP0_Index = i;
1583 break;
1584 }
1585 }
1586 if (i == env->tlb->nb_tlb) {
1587 /* No match. Discard any shadow entries, if any of them match. */
1588 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1589 tlb = &env->tlb->mmu.r4k.tlb[i];
1590 /* 1k pages are not supported. */
1591 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1592 tag = env->CP0_EntryHi & ~mask;
1593 VPN = tlb->VPN & ~mask;
1594 /* Check ASID, virtual page number & size */
1595 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1596 r4k_mips_tlb_flush_extra (env, i);
1597 break;
1598 }
1599 }
1600
1601 env->CP0_Index |= 0x80000000;
1602 }
1603 }
1604
1605 void r4k_helper_tlbr (void)
1606 {
1607 r4k_tlb_t *tlb;
1608 uint8_t ASID;
1609 int idx;
1610
1611 ASID = env->CP0_EntryHi & 0xFF;
1612 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1613 tlb = &env->tlb->mmu.r4k.tlb[idx];
1614
1615 /* If this will change the current ASID, flush qemu's TLB. */
1616 if (ASID != tlb->ASID)
1617 cpu_mips_tlb_flush (env, 1);
1618
1619 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1620
1621 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1622 env->CP0_PageMask = tlb->PageMask;
1623 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1624 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1625 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1626 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1627 }
1628
1629 void helper_tlbwi(void)
1630 {
1631 env->tlb->helper_tlbwi();
1632 }
1633
1634 void helper_tlbwr(void)
1635 {
1636 env->tlb->helper_tlbwr();
1637 }
1638
1639 void helper_tlbp(void)
1640 {
1641 env->tlb->helper_tlbp();
1642 }
1643
1644 void helper_tlbr(void)
1645 {
1646 env->tlb->helper_tlbr();
1647 }
1648
1649 /* Specials */
1650 target_ulong helper_di (void)
1651 {
1652 target_ulong t0 = env->CP0_Status;
1653
1654 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1655 cpu_mips_update_irq(env);
1656
1657 return t0;
1658 }
1659
1660 target_ulong helper_ei (void)
1661 {
1662 target_ulong t0 = env->CP0_Status;
1663
1664 env->CP0_Status = t0 | (1 << CP0St_IE);
1665 cpu_mips_update_irq(env);
1666
1667 return t0;
1668 }
1669
1670 static void debug_pre_eret (void)
1671 {
1672 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1673 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1674 env->active_tc.PC, env->CP0_EPC);
1675 if (env->CP0_Status & (1 << CP0St_ERL))
1676 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1677 if (env->hflags & MIPS_HFLAG_DM)
1678 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1679 qemu_log("\n");
1680 }
1681 }
1682
1683 static void debug_post_eret (void)
1684 {
1685 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1686 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1687 env->active_tc.PC, env->CP0_EPC);
1688 if (env->CP0_Status & (1 << CP0St_ERL))
1689 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1690 if (env->hflags & MIPS_HFLAG_DM)
1691 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1692 switch (env->hflags & MIPS_HFLAG_KSU) {
1693 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1694 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1695 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1696 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1697 }
1698 }
1699 }
1700
1701 static void set_pc (target_ulong error_pc)
1702 {
1703 env->active_tc.PC = error_pc & ~(target_ulong)1;
1704 if (error_pc & 1) {
1705 env->hflags |= MIPS_HFLAG_M16;
1706 } else {
1707 env->hflags &= ~(MIPS_HFLAG_M16);
1708 }
1709 }
1710
1711 void helper_eret (void)
1712 {
1713 debug_pre_eret();
1714 if (env->CP0_Status & (1 << CP0St_ERL)) {
1715 set_pc(env->CP0_ErrorEPC);
1716 env->CP0_Status &= ~(1 << CP0St_ERL);
1717 } else {
1718 set_pc(env->CP0_EPC);
1719 env->CP0_Status &= ~(1 << CP0St_EXL);
1720 }
1721 compute_hflags(env);
1722 debug_post_eret();
1723 env->lladdr = 1;
1724 }
1725
1726 void helper_deret (void)
1727 {
1728 debug_pre_eret();
1729 set_pc(env->CP0_DEPC);
1730
1731 env->hflags &= MIPS_HFLAG_DM;
1732 compute_hflags(env);
1733 debug_post_eret();
1734 env->lladdr = 1;
1735 }
1736 #endif /* !CONFIG_USER_ONLY */
1737
1738 target_ulong helper_rdhwr_cpunum(void)
1739 {
1740 if ((env->hflags & MIPS_HFLAG_CP0) ||
1741 (env->CP0_HWREna & (1 << 0)))
1742 return env->CP0_EBase & 0x3ff;
1743 else
1744 helper_raise_exception(EXCP_RI);
1745
1746 return 0;
1747 }
1748
1749 target_ulong helper_rdhwr_synci_step(void)
1750 {
1751 if ((env->hflags & MIPS_HFLAG_CP0) ||
1752 (env->CP0_HWREna & (1 << 1)))
1753 return env->SYNCI_Step;
1754 else
1755 helper_raise_exception(EXCP_RI);
1756
1757 return 0;
1758 }
1759
1760 target_ulong helper_rdhwr_cc(void)
1761 {
1762 if ((env->hflags & MIPS_HFLAG_CP0) ||
1763 (env->CP0_HWREna & (1 << 2)))
1764 return env->CP0_Count;
1765 else
1766 helper_raise_exception(EXCP_RI);
1767
1768 return 0;
1769 }
1770
1771 target_ulong helper_rdhwr_ccres(void)
1772 {
1773 if ((env->hflags & MIPS_HFLAG_CP0) ||
1774 (env->CP0_HWREna & (1 << 3)))
1775 return env->CCRes;
1776 else
1777 helper_raise_exception(EXCP_RI);
1778
1779 return 0;
1780 }
1781
1782 void helper_pmon (int function)
1783 {
1784 function /= 2;
1785 switch (function) {
1786 case 2: /* TODO: char inbyte(int waitflag); */
1787 if (env->active_tc.gpr[4] == 0)
1788 env->active_tc.gpr[2] = -1;
1789 /* Fall through */
1790 case 11: /* TODO: char inbyte (void); */
1791 env->active_tc.gpr[2] = -1;
1792 break;
1793 case 3:
1794 case 12:
1795 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1796 break;
1797 case 17:
1798 break;
1799 case 158:
1800 {
1801 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
1802 printf("%s", fmt);
1803 }
1804 break;
1805 }
1806 }
1807
1808 void helper_wait (void)
1809 {
1810 env->halted = 1;
1811 helper_raise_exception(EXCP_HLT);
1812 }
1813
1814 #if !defined(CONFIG_USER_ONLY)
1815
1816 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1817
1818 #define MMUSUFFIX _mmu
1819 #define ALIGNED_ONLY
1820
1821 #define SHIFT 0
1822 #include "softmmu_template.h"
1823
1824 #define SHIFT 1
1825 #include "softmmu_template.h"
1826
1827 #define SHIFT 2
1828 #include "softmmu_template.h"
1829
1830 #define SHIFT 3
1831 #include "softmmu_template.h"
1832
1833 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1834 {
1835 env->CP0_BadVAddr = addr;
1836 do_restore_state (retaddr);
1837 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1838 }
1839
1840 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1841 {
1842 TranslationBlock *tb;
1843 CPUState *saved_env;
1844 unsigned long pc;
1845 int ret;
1846
1847 /* XXX: hack to restore env in all cases, even if not called from
1848 generated code */
1849 saved_env = env;
1850 env = cpu_single_env;
1851 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1852 if (ret) {
1853 if (retaddr) {
1854 /* now we have a real cpu fault */
1855 pc = (unsigned long)retaddr;
1856 tb = tb_find_pc(pc);
1857 if (tb) {
1858 /* the PC is inside the translated code. It means that we have
1859 a virtual CPU fault */
1860 cpu_restore_state(tb, env, pc, NULL);
1861 }
1862 }
1863 helper_raise_exception_err(env->exception_index, env->error_code);
1864 }
1865 env = saved_env;
1866 }
1867
1868 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1869 int unused, int size)
1870 {
1871 if (is_exec)
1872 helper_raise_exception(EXCP_IBE);
1873 else
1874 helper_raise_exception(EXCP_DBE);
1875 }
1876 #endif /* !CONFIG_USER_ONLY */
1877
1878 /* Complex FPU operations which may need stack space. */
1879
1880 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1881 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1882 #define FLOAT_TWO32 make_float32(1 << 30)
1883 #define FLOAT_TWO64 make_float64(1ULL << 62)
1884 #define FLOAT_QNAN32 0x7fbfffff
1885 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1886 #define FLOAT_SNAN32 0x7fffffff
1887 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1888
1889 /* convert MIPS rounding mode in FCR31 to IEEE library */
1890 static unsigned int ieee_rm[] = {
1891 float_round_nearest_even,
1892 float_round_to_zero,
1893 float_round_up,
1894 float_round_down
1895 };
1896
1897 #define RESTORE_ROUNDING_MODE \
1898 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1899
1900 #define RESTORE_FLUSH_MODE \
1901 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
1902
1903 target_ulong helper_cfc1 (uint32_t reg)
1904 {
1905 target_ulong arg1;
1906
1907 switch (reg) {
1908 case 0:
1909 arg1 = (int32_t)env->active_fpu.fcr0;
1910 break;
1911 case 25:
1912 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1913 break;
1914 case 26:
1915 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
1916 break;
1917 case 28:
1918 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
1919 break;
1920 default:
1921 arg1 = (int32_t)env->active_fpu.fcr31;
1922 break;
1923 }
1924
1925 return arg1;
1926 }
1927
1928 void helper_ctc1 (target_ulong arg1, uint32_t reg)
1929 {
1930 switch(reg) {
1931 case 25:
1932 if (arg1 & 0xffffff00)
1933 return;
1934 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
1935 ((arg1 & 0x1) << 23);
1936 break;
1937 case 26:
1938 if (arg1 & 0x007c0000)
1939 return;
1940 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
1941 break;
1942 case 28:
1943 if (arg1 & 0x007c0000)
1944 return;
1945 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
1946 ((arg1 & 0x4) << 22);
1947 break;
1948 case 31:
1949 if (arg1 & 0x007c0000)
1950 return;
1951 env->active_fpu.fcr31 = arg1;
1952 break;
1953 default:
1954 return;
1955 }
1956 /* set rounding mode */
1957 RESTORE_ROUNDING_MODE;
1958 /* set flush-to-zero mode */
1959 RESTORE_FLUSH_MODE;
1960 set_float_exception_flags(0, &env->active_fpu.fp_status);
1961 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
1962 helper_raise_exception(EXCP_FPE);
1963 }
1964
1965 static inline char ieee_ex_to_mips(char xcpt)
1966 {
1967 return (xcpt & float_flag_inexact) >> 5 |
1968 (xcpt & float_flag_underflow) >> 3 |
1969 (xcpt & float_flag_overflow) >> 1 |
1970 (xcpt & float_flag_divbyzero) << 1 |
1971 (xcpt & float_flag_invalid) << 4;
1972 }
1973
1974 static inline char mips_ex_to_ieee(char xcpt)
1975 {
1976 return (xcpt & FP_INEXACT) << 5 |
1977 (xcpt & FP_UNDERFLOW) << 3 |
1978 (xcpt & FP_OVERFLOW) << 1 |
1979 (xcpt & FP_DIV0) >> 1 |
1980 (xcpt & FP_INVALID) >> 4;
1981 }
1982
1983 static inline void update_fcr31(void)
1984 {
1985 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
1986
1987 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
1988 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
1989 helper_raise_exception(EXCP_FPE);
1990 else
1991 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
1992 }
1993
1994 /* Float support.
1995 Single precition routines have a "s" suffix, double precision a
1996 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
1997 paired single lower "pl", paired single upper "pu". */
1998
1999 /* unary operations, modifying fp status */
2000 uint64_t helper_float_sqrt_d(uint64_t fdt0)
2001 {
2002 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2003 }
2004
2005 uint32_t helper_float_sqrt_s(uint32_t fst0)
2006 {
2007 return float32_sqrt(fst0, &env->active_fpu.fp_status);
2008 }
2009
2010 uint64_t helper_float_cvtd_s(uint32_t fst0)
2011 {
2012 uint64_t fdt2;
2013
2014 set_float_exception_flags(0, &env->active_fpu.fp_status);
2015 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2016 update_fcr31();
2017 return fdt2;
2018 }
2019
2020 uint64_t helper_float_cvtd_w(uint32_t wt0)
2021 {
2022 uint64_t fdt2;
2023
2024 set_float_exception_flags(0, &env->active_fpu.fp_status);
2025 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2026 update_fcr31();
2027 return fdt2;
2028 }
2029
2030 uint64_t helper_float_cvtd_l(uint64_t dt0)
2031 {
2032 uint64_t fdt2;
2033
2034 set_float_exception_flags(0, &env->active_fpu.fp_status);
2035 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2036 update_fcr31();
2037 return fdt2;
2038 }
2039
2040 uint64_t helper_float_cvtl_d(uint64_t fdt0)
2041 {
2042 uint64_t dt2;
2043
2044 set_float_exception_flags(0, &env->active_fpu.fp_status);
2045 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2046 update_fcr31();
2047 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2048 dt2 = FLOAT_SNAN64;
2049 return dt2;
2050 }
2051
2052 uint64_t helper_float_cvtl_s(uint32_t fst0)
2053 {
2054 uint64_t dt2;
2055
2056 set_float_exception_flags(0, &env->active_fpu.fp_status);
2057 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2058 update_fcr31();
2059 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2060 dt2 = FLOAT_SNAN64;
2061 return dt2;
2062 }
2063
2064 uint64_t helper_float_cvtps_pw(uint64_t dt0)
2065 {
2066 uint32_t fst2;
2067 uint32_t fsth2;
2068
2069 set_float_exception_flags(0, &env->active_fpu.fp_status);
2070 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2071 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2072 update_fcr31();
2073 return ((uint64_t)fsth2 << 32) | fst2;
2074 }
2075
2076 uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
2077 {
2078 uint32_t wt2;
2079 uint32_t wth2;
2080
2081 set_float_exception_flags(0, &env->active_fpu.fp_status);
2082 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2083 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2084 update_fcr31();
2085 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2086 wt2 = FLOAT_SNAN32;
2087 wth2 = FLOAT_SNAN32;
2088 }
2089 return ((uint64_t)wth2 << 32) | wt2;
2090 }
2091
2092 uint32_t helper_float_cvts_d(uint64_t fdt0)
2093 {
2094 uint32_t fst2;
2095
2096 set_float_exception_flags(0, &env->active_fpu.fp_status);
2097 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2098 update_fcr31();
2099 return fst2;
2100 }
2101
2102 uint32_t helper_float_cvts_w(uint32_t wt0)
2103 {
2104 uint32_t fst2;
2105
2106 set_float_exception_flags(0, &env->active_fpu.fp_status);
2107 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2108 update_fcr31();
2109 return fst2;
2110 }
2111
2112 uint32_t helper_float_cvts_l(uint64_t dt0)
2113 {
2114 uint32_t fst2;
2115
2116 set_float_exception_flags(0, &env->active_fpu.fp_status);
2117 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2118 update_fcr31();
2119 return fst2;
2120 }
2121
2122 uint32_t helper_float_cvts_pl(uint32_t wt0)
2123 {
2124 uint32_t wt2;
2125
2126 set_float_exception_flags(0, &env->active_fpu.fp_status);
2127 wt2 = wt0;
2128 update_fcr31();
2129 return wt2;
2130 }
2131
2132 uint32_t helper_float_cvts_pu(uint32_t wth0)
2133 {
2134 uint32_t wt2;
2135
2136 set_float_exception_flags(0, &env->active_fpu.fp_status);
2137 wt2 = wth0;
2138 update_fcr31();
2139 return wt2;
2140 }
2141
2142 uint32_t helper_float_cvtw_s(uint32_t fst0)
2143 {
2144 uint32_t wt2;
2145
2146 set_float_exception_flags(0, &env->active_fpu.fp_status);
2147 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2148 update_fcr31();
2149 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2150 wt2 = FLOAT_SNAN32;
2151 return wt2;
2152 }
2153
2154 uint32_t helper_float_cvtw_d(uint64_t fdt0)
2155 {
2156 uint32_t wt2;
2157
2158 set_float_exception_flags(0, &env->active_fpu.fp_status);
2159 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2160 update_fcr31();
2161 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2162 wt2 = FLOAT_SNAN32;
2163 return wt2;
2164 }
2165
2166 uint64_t helper_float_roundl_d(uint64_t fdt0)
2167 {
2168 uint64_t dt2;
2169
2170 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2171 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2172 RESTORE_ROUNDING_MODE;
2173 update_fcr31();
2174 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2175 dt2 = FLOAT_SNAN64;
2176 return dt2;
2177 }
2178
2179 uint64_t helper_float_roundl_s(uint32_t fst0)
2180 {
2181 uint64_t dt2;
2182
2183 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2184 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2185 RESTORE_ROUNDING_MODE;
2186 update_fcr31();
2187 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2188 dt2 = FLOAT_SNAN64;
2189 return dt2;
2190 }
2191
2192 uint32_t helper_float_roundw_d(uint64_t fdt0)
2193 {
2194 uint32_t wt2;
2195
2196 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2197 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2198 RESTORE_ROUNDING_MODE;
2199 update_fcr31();
2200 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2201 wt2 = FLOAT_SNAN32;
2202 return wt2;
2203 }
2204
2205 uint32_t helper_float_roundw_s(uint32_t fst0)
2206 {
2207 uint32_t wt2;
2208
2209 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2210 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2211 RESTORE_ROUNDING_MODE;
2212 update_fcr31();
2213 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2214 wt2 = FLOAT_SNAN32;
2215 return wt2;
2216 }
2217
2218 uint64_t helper_float_truncl_d(uint64_t fdt0)
2219 {
2220 uint64_t dt2;
2221
2222 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2223 update_fcr31();
2224 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2225 dt2 = FLOAT_SNAN64;
2226 return dt2;
2227 }
2228
2229 uint64_t helper_float_truncl_s(uint32_t fst0)
2230 {
2231 uint64_t dt2;
2232
2233 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2234 update_fcr31();
2235 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2236 dt2 = FLOAT_SNAN64;
2237 return dt2;
2238 }
2239
2240 uint32_t helper_float_truncw_d(uint64_t fdt0)
2241 {
2242 uint32_t wt2;
2243
2244 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2245 update_fcr31();
2246 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2247 wt2 = FLOAT_SNAN32;
2248 return wt2;
2249 }
2250
2251 uint32_t helper_float_truncw_s(uint32_t fst0)
2252 {
2253 uint32_t wt2;
2254
2255 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2256 update_fcr31();
2257 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2258 wt2 = FLOAT_SNAN32;
2259 return wt2;
2260 }
2261
2262 uint64_t helper_float_ceill_d(uint64_t fdt0)
2263 {
2264 uint64_t dt2;
2265
2266 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2267 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2268 RESTORE_ROUNDING_MODE;
2269 update_fcr31();
2270 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2271 dt2 = FLOAT_SNAN64;
2272 return dt2;
2273 }
2274
2275 uint64_t helper_float_ceill_s(uint32_t fst0)
2276 {
2277 uint64_t dt2;
2278
2279 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2280 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2281 RESTORE_ROUNDING_MODE;
2282 update_fcr31();
2283 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2284 dt2 = FLOAT_SNAN64;
2285 return dt2;
2286 }
2287
2288 uint32_t helper_float_ceilw_d(uint64_t fdt0)
2289 {
2290 uint32_t wt2;
2291
2292 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2293 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2294 RESTORE_ROUNDING_MODE;
2295 update_fcr31();
2296 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2297 wt2 = FLOAT_SNAN32;
2298 return wt2;
2299 }
2300
2301 uint32_t helper_float_ceilw_s(uint32_t fst0)
2302 {
2303 uint32_t wt2;
2304
2305 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2306 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2307 RESTORE_ROUNDING_MODE;
2308 update_fcr31();
2309 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2310 wt2 = FLOAT_SNAN32;
2311 return wt2;
2312 }
2313
2314 uint64_t helper_float_floorl_d(uint64_t fdt0)
2315 {
2316 uint64_t dt2;
2317
2318 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2319 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2320 RESTORE_ROUNDING_MODE;
2321 update_fcr31();
2322 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2323 dt2 = FLOAT_SNAN64;
2324 return dt2;
2325 }
2326
2327 uint64_t helper_float_floorl_s(uint32_t fst0)
2328 {
2329 uint64_t dt2;
2330
2331 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2332 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2333 RESTORE_ROUNDING_MODE;
2334 update_fcr31();
2335 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2336 dt2 = FLOAT_SNAN64;
2337 return dt2;
2338 }
2339
2340 uint32_t helper_float_floorw_d(uint64_t fdt0)
2341 {
2342 uint32_t wt2;
2343
2344 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2345 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2346 RESTORE_ROUNDING_MODE;
2347 update_fcr31();
2348 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2349 wt2 = FLOAT_SNAN32;
2350 return wt2;
2351 }
2352
2353 uint32_t helper_float_floorw_s(uint32_t fst0)
2354 {
2355 uint32_t wt2;
2356
2357 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2358 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2359 RESTORE_ROUNDING_MODE;
2360 update_fcr31();
2361 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2362 wt2 = FLOAT_SNAN32;
2363 return wt2;
2364 }
2365
2366 /* unary operations, not modifying fp status */
2367 #define FLOAT_UNOP(name) \
2368 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2369 { \
2370 return float64_ ## name(fdt0); \
2371 } \
2372 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2373 { \
2374 return float32_ ## name(fst0); \
2375 } \
2376 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2377 { \
2378 uint32_t wt0; \
2379 uint32_t wth0; \
2380 \
2381 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2382 wth0 = float32_ ## name(fdt0 >> 32); \
2383 return ((uint64_t)wth0 << 32) | wt0; \
2384 }
2385 FLOAT_UNOP(abs)
2386 FLOAT_UNOP(chs)
2387 #undef FLOAT_UNOP
2388
2389 /* MIPS specific unary operations */
2390 uint64_t helper_float_recip_d(uint64_t fdt0)
2391 {
2392 uint64_t fdt2;
2393
2394 set_float_exception_flags(0, &env->active_fpu.fp_status);
2395 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2396 update_fcr31();
2397 return fdt2;
2398 }
2399
2400 uint32_t helper_float_recip_s(uint32_t fst0)
2401 {
2402 uint32_t fst2;
2403
2404 set_float_exception_flags(0, &env->active_fpu.fp_status);
2405 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2406 update_fcr31();
2407 return fst2;
2408 }
2409
2410 uint64_t helper_float_rsqrt_d(uint64_t fdt0)
2411 {
2412 uint64_t fdt2;
2413
2414 set_float_exception_flags(0, &env->active_fpu.fp_status);
2415 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2416 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2417 update_fcr31();
2418 return fdt2;
2419 }
2420
2421 uint32_t helper_float_rsqrt_s(uint32_t fst0)
2422 {
2423 uint32_t fst2;
2424
2425 set_float_exception_flags(0, &env->active_fpu.fp_status);
2426 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2427 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2428 update_fcr31();
2429 return fst2;
2430 }
2431
2432 uint64_t helper_float_recip1_d(uint64_t fdt0)
2433 {
2434 uint64_t fdt2;
2435
2436 set_float_exception_flags(0, &env->active_fpu.fp_status);
2437 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2438 update_fcr31();
2439 return fdt2;
2440 }
2441
2442 uint32_t helper_float_recip1_s(uint32_t fst0)
2443 {
2444 uint32_t fst2;
2445
2446 set_float_exception_flags(0, &env->active_fpu.fp_status);
2447 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2448 update_fcr31();
2449 return fst2;
2450 }
2451
2452 uint64_t helper_float_recip1_ps(uint64_t fdt0)
2453 {
2454 uint32_t fst2;
2455 uint32_t fsth2;
2456
2457 set_float_exception_flags(0, &env->active_fpu.fp_status);
2458 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2459 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2460 update_fcr31();
2461 return ((uint64_t)fsth2 << 32) | fst2;
2462 }
2463
2464 uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
2465 {
2466 uint64_t fdt2;
2467
2468 set_float_exception_flags(0, &env->active_fpu.fp_status);
2469 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2470 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2471 update_fcr31();
2472 return fdt2;
2473 }
2474
2475 uint32_t helper_float_rsqrt1_s(uint32_t fst0)
2476 {
2477 uint32_t fst2;
2478
2479 set_float_exception_flags(0, &env->active_fpu.fp_status);
2480 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2481 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2482 update_fcr31();
2483 return fst2;
2484 }
2485
2486 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
2487 {
2488 uint32_t fst2;
2489 uint32_t fsth2;
2490
2491 set_float_exception_flags(0, &env->active_fpu.fp_status);
2492 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2493 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2494 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2495 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2496 update_fcr31();
2497 return ((uint64_t)fsth2 << 32) | fst2;
2498 }
2499
2500 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2501
2502 /* binary operations */
2503 #define FLOAT_BINOP(name) \
2504 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2505 { \
2506 uint64_t dt2; \
2507 \
2508 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2509 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2510 update_fcr31(); \
2511 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2512 dt2 = FLOAT_QNAN64; \
2513 return dt2; \
2514 } \
2515 \
2516 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2517 { \
2518 uint32_t wt2; \
2519 \
2520 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2521 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2522 update_fcr31(); \
2523 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2524 wt2 = FLOAT_QNAN32; \
2525 return wt2; \
2526 } \
2527 \
2528 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2529 { \
2530 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2531 uint32_t fsth0 = fdt0 >> 32; \
2532 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2533 uint32_t fsth1 = fdt1 >> 32; \
2534 uint32_t wt2; \
2535 uint32_t wth2; \
2536 \
2537 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2538 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2539 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2540 update_fcr31(); \
2541 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2542 wt2 = FLOAT_QNAN32; \
2543 wth2 = FLOAT_QNAN32; \
2544 } \
2545 return ((uint64_t)wth2 << 32) | wt2; \
2546 }
2547
2548 FLOAT_BINOP(add)
2549 FLOAT_BINOP(sub)
2550 FLOAT_BINOP(mul)
2551 FLOAT_BINOP(div)
2552 #undef FLOAT_BINOP
2553
2554 /* ternary operations */
2555 #define FLOAT_TERNOP(name1, name2) \
2556 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2557 uint64_t fdt2) \
2558 { \
2559 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2560 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2561 } \
2562 \
2563 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2564 uint32_t fst2) \
2565 { \
2566 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2567 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2568 } \
2569 \
2570 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2571 uint64_t fdt2) \
2572 { \
2573 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2574 uint32_t fsth0 = fdt0 >> 32; \
2575 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2576 uint32_t fsth1 = fdt1 >> 32; \
2577 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2578 uint32_t fsth2 = fdt2 >> 32; \
2579 \
2580 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2581 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2582 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2583 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2584 return ((uint64_t)fsth2 << 32) | fst2; \
2585 }
2586
2587 FLOAT_TERNOP(mul, add)
2588 FLOAT_TERNOP(mul, sub)
2589 #undef FLOAT_TERNOP
2590
2591 /* negated ternary operations */
2592 #define FLOAT_NTERNOP(name1, name2) \
2593 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2594 uint64_t fdt2) \
2595 { \
2596 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2597 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2598 return float64_chs(fdt2); \
2599 } \
2600 \
2601 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2602 uint32_t fst2) \
2603 { \
2604 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2605 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2606 return float32_chs(fst2); \
2607 } \
2608 \
2609 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2610 uint64_t fdt2) \
2611 { \
2612 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2613 uint32_t fsth0 = fdt0 >> 32; \
2614 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2615 uint32_t fsth1 = fdt1 >> 32; \
2616 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2617 uint32_t fsth2 = fdt2 >> 32; \
2618 \
2619 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2620 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2621 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2622 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2623 fst2 = float32_chs(fst2); \
2624 fsth2 = float32_chs(fsth2); \
2625 return ((uint64_t)fsth2 << 32) | fst2; \
2626 }
2627
2628 FLOAT_NTERNOP(mul, add)
2629 FLOAT_NTERNOP(mul, sub)
2630 #undef FLOAT_NTERNOP
2631
2632 /* MIPS specific binary operations */
2633 uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2634 {
2635 set_float_exception_flags(0, &env->active_fpu.fp_status);
2636 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2637 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2638 update_fcr31();
2639 return fdt2;
2640 }
2641
2642 uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
2643 {
2644 set_float_exception_flags(0, &env->active_fpu.fp_status);
2645 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2646 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2647 update_fcr31();
2648 return fst2;
2649 }
2650
2651 uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2652 {
2653 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2654 uint32_t fsth0 = fdt0 >> 32;
2655 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2656 uint32_t fsth2 = fdt2 >> 32;
2657
2658 set_float_exception_flags(0, &env->active_fpu.fp_status);
2659 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2660 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2661 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2662 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2663 update_fcr31();
2664 return ((uint64_t)fsth2 << 32) | fst2;
2665 }
2666
2667 uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2668 {
2669 set_float_exception_flags(0, &env->active_fpu.fp_status);
2670 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2671 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2672 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2673 update_fcr31();
2674 return fdt2;
2675 }
2676
2677 uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2678 {
2679 set_float_exception_flags(0, &env->active_fpu.fp_status);
2680 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2681 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2682 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2683 update_fcr31();
2684 return fst2;
2685 }
2686
2687 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2688 {
2689 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2690 uint32_t fsth0 = fdt0 >> 32;
2691 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2692 uint32_t fsth2 = fdt2 >> 32;
2693
2694 set_float_exception_flags(0, &env->active_fpu.fp_status);
2695 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2696 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2697 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2698 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2699 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2700 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2701 update_fcr31();
2702 return ((uint64_t)fsth2 << 32) | fst2;
2703 }
2704
2705 uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2706 {
2707 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2708 uint32_t fsth0 = fdt0 >> 32;
2709 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2710 uint32_t fsth1 = fdt1 >> 32;
2711 uint32_t fst2;
2712 uint32_t fsth2;
2713
2714 set_float_exception_flags(0, &env->active_fpu.fp_status);
2715 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2716 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2717 update_fcr31();
2718 return ((uint64_t)fsth2 << 32) | fst2;
2719 }
2720
2721 uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2722 {
2723 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2724 uint32_t fsth0 = fdt0 >> 32;
2725 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2726 uint32_t fsth1 = fdt1 >> 32;
2727 uint32_t fst2;
2728 uint32_t fsth2;
2729
2730 set_float_exception_flags(0, &env->active_fpu.fp_status);
2731 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2732 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2733 update_fcr31();
2734 return ((uint64_t)fsth2 << 32) | fst2;
2735 }
2736
2737 /* compare operations */
2738 #define FOP_COND_D(op, cond) \
2739 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2740 { \
2741 int c = cond; \
2742 update_fcr31(); \
2743 if (c) \
2744 SET_FP_COND(cc, env->active_fpu); \
2745 else \
2746 CLEAR_FP_COND(cc, env->active_fpu); \
2747 } \
2748 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2749 { \
2750 int c; \
2751 fdt0 = float64_abs(fdt0); \
2752 fdt1 = float64_abs(fdt1); \
2753 c = cond; \
2754 update_fcr31(); \
2755 if (c) \
2756 SET_FP_COND(cc, env->active_fpu); \
2757 else \
2758 CLEAR_FP_COND(cc, env->active_fpu); \
2759 }
2760
2761 static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2762 {
2763 if (float64_is_signaling_nan(a) ||
2764 float64_is_signaling_nan(b) ||
2765 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2766 float_raise(float_flag_invalid, status);
2767 return 1;
2768 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2769 return 1;
2770 } else {
2771 return 0;
2772 }
2773 }
2774
2775 /* NOTE: the comma operator will make "cond" to eval to false,
2776 * but float*_is_unordered() is still called. */
2777 FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2778 FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2779 FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2780 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2781 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2782 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2783 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2784 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2785 /* NOTE: the comma operator will make "cond" to eval to false,
2786 * but float*_is_unordered() is still called. */
2787 FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2788 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2789 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2790 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2791 FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2792 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2793 FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2794 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2795
2796 #define FOP_COND_S(op, cond) \
2797 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2798 { \
2799 int c = cond; \
2800 update_fcr31(); \
2801 if (c) \
2802 SET_FP_COND(cc, env->active_fpu); \
2803 else \
2804 CLEAR_FP_COND(cc, env->active_fpu); \
2805 } \
2806 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2807 { \
2808 int c; \
2809 fst0 = float32_abs(fst0); \
2810 fst1 = float32_abs(fst1); \
2811 c = cond; \
2812 update_fcr31(); \
2813 if (c) \
2814 SET_FP_COND(cc, env->active_fpu); \
2815 else \
2816 CLEAR_FP_COND(cc, env->active_fpu); \
2817 }
2818
2819 static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2820 {
2821 if (float32_is_signaling_nan(a) ||
2822 float32_is_signaling_nan(b) ||
2823 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2824 float_raise(float_flag_invalid, status);
2825 return 1;
2826 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2827 return 1;
2828 } else {
2829 return 0;
2830 }
2831 }
2832
2833 /* NOTE: the comma operator will make "cond" to eval to false,
2834 * but float*_is_unordered() is still called. */
2835 FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2836 FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2837 FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2838 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2839 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2840 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2841 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2842 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2843 /* NOTE: the comma operator will make "cond" to eval to false,
2844 * but float*_is_unordered() is still called. */
2845 FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2846 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2847 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2848 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2849 FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2850 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2851 FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2852 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2853
2854 #define FOP_COND_PS(op, condl, condh) \
2855 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2856 { \
2857 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2858 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2859 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2860 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2861 int cl = condl; \
2862 int ch = condh; \
2863 \
2864 update_fcr31(); \
2865 if (cl) \
2866 SET_FP_COND(cc, env->active_fpu); \
2867 else \
2868 CLEAR_FP_COND(cc, env->active_fpu); \
2869 if (ch) \
2870 SET_FP_COND(cc + 1, env->active_fpu); \
2871 else \
2872 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2873 } \
2874 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2875 { \
2876 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2877 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2878 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2879 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2880 int cl = condl; \
2881 int ch = condh; \
2882 \
2883 update_fcr31(); \
2884 if (cl) \
2885 SET_FP_COND(cc, env->active_fpu); \
2886 else \
2887 CLEAR_FP_COND(cc, env->active_fpu); \
2888 if (ch) \
2889 SET_FP_COND(cc + 1, env->active_fpu); \
2890 else \
2891 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2892 }
2893
2894 /* NOTE: the comma operator will make "cond" to eval to false,
2895 * but float*_is_unordered() is still called. */
2896 FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2897 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2898 FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2899 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2900 FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2901 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2902 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2903 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2904 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2905 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2906 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2907 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2908 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2909 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2910 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2911 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2912 /* NOTE: the comma operator will make "cond" to eval to false,
2913 * but float*_is_unordered() is still called. */
2914 FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2915 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2916 FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2917 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2918 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2919 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2920 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2921 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2922 FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2923 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2924 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2925 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2926 FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2927 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2928 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2929 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Anthony Liguori's QEMU queue