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Fix -device help and documentation
[qemu/aliguori-queue.git] / hw / sun4m.c
blob7ba0f763bca12224ec3ad3cd81dc4559cc3fc57f
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43
44 //#define DEBUG_IRQ
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #ifdef DEBUG_IRQ
75 #define DPRINTF(fmt, ...) \
76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
77 #else
78 #define DPRINTF(fmt, ...)
79 #endif
80
81 #define KERNEL_LOAD_ADDR 0x00004000
82 #define CMDLINE_ADDR 0x007ff000
83 #define INITRD_LOAD_ADDR 0x00800000
84 #define PROM_SIZE_MAX (1024 * 1024)
85 #define PROM_VADDR 0xffd00000
86 #define PROM_FILENAME "openbios-sparc32"
87 #define CFG_ADDR 0xd00000510ULL
88 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
89
90 #define MAX_CPUS 16
91 #define MAX_PILS 16
92
93 #define ESCC_CLOCK 4915200
94
95 struct sun4m_hwdef {
96 target_phys_addr_t iommu_base, slavio_base;
97 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
98 target_phys_addr_t serial_base, fd_base;
99 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
100 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
101 target_phys_addr_t ecc_base;
102 uint32_t ecc_version;
103 uint8_t nvram_machine_id;
104 uint16_t machine_id;
105 uint32_t iommu_version;
106 uint64_t max_mem;
107 const char * const default_cpu_model;
108 };
109
110 #define MAX_IOUNITS 5
111
112 struct sun4d_hwdef {
113 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
114 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
115 target_phys_addr_t serial_base;
116 target_phys_addr_t espdma_base, esp_base;
117 target_phys_addr_t ledma_base, le_base;
118 target_phys_addr_t tcx_base;
119 target_phys_addr_t sbi_base;
120 uint8_t nvram_machine_id;
121 uint16_t machine_id;
122 uint32_t iounit_version;
123 uint64_t max_mem;
124 const char * const default_cpu_model;
125 };
126
127 struct sun4c_hwdef {
128 target_phys_addr_t iommu_base, slavio_base;
129 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
130 target_phys_addr_t serial_base, fd_base;
131 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
132 target_phys_addr_t tcx_base, aux1_base;
133 uint8_t nvram_machine_id;
134 uint16_t machine_id;
135 uint32_t iommu_version;
136 uint64_t max_mem;
137 const char * const default_cpu_model;
138 };
139
140 int DMA_get_channel_mode (int nchan)
141 {
142 return 0;
143 }
144 int DMA_read_memory (int nchan, void *buf, int pos, int size)
145 {
146 return 0;
147 }
148 int DMA_write_memory (int nchan, void *buf, int pos, int size)
149 {
150 return 0;
151 }
152 void DMA_hold_DREQ (int nchan) {}
153 void DMA_release_DREQ (int nchan) {}
154 void DMA_schedule(int nchan) {}
155
156 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
157 {
158 }
159
160 void DMA_register_channel (int nchan,
161 DMA_transfer_handler transfer_handler,
162 void *opaque)
163 {
164 }
165
166 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
167 {
168 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
169 return 0;
170 }
171
172 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
173 const char *cmdline, const char *boot_devices,
174 ram_addr_t RAM_size, uint32_t kernel_size,
175 int width, int height, int depth,
176 int nvram_machine_id, const char *arch)
177 {
178 unsigned int i;
179 uint32_t start, end;
180 uint8_t image[0x1ff0];
181 struct OpenBIOS_nvpart_v1 *part_header;
182
183 memset(image, '\0', sizeof(image));
184
185 start = 0;
186
187 // OpenBIOS nvram variables
188 // Variable partition
189 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
190 part_header->signature = OPENBIOS_PART_SYSTEM;
191 pstrcpy(part_header->name, sizeof(part_header->name), "system");
192
193 end = start + sizeof(struct OpenBIOS_nvpart_v1);
194 for (i = 0; i < nb_prom_envs; i++)
195 end = OpenBIOS_set_var(image, end, prom_envs[i]);
196
197 // End marker
198 image[end++] = '\0';
199
200 end = start + ((end - start + 15) & ~15);
201 OpenBIOS_finish_partition(part_header, end - start);
202
203 // free partition
204 start = end;
205 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
206 part_header->signature = OPENBIOS_PART_FREE;
207 pstrcpy(part_header->name, sizeof(part_header->name), "free");
208
209 end = 0x1fd0;
210 OpenBIOS_finish_partition(part_header, end - start);
211
212 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
213 nvram_machine_id);
214
215 for (i = 0; i < sizeof(image); i++)
216 m48t59_write(nvram, i, image[i]);
217 }
218
219 static DeviceState *slavio_intctl;
220
221 void pic_info(Monitor *mon)
222 {
223 if (slavio_intctl)
224 slavio_pic_info(mon, slavio_intctl);
225 }
226
227 void irq_info(Monitor *mon)
228 {
229 if (slavio_intctl)
230 slavio_irq_info(mon, slavio_intctl);
231 }
232
233 void cpu_check_irqs(CPUState *env)
234 {
235 if (env->pil_in && (env->interrupt_index == 0 ||
236 (env->interrupt_index & ~15) == TT_EXTINT)) {
237 unsigned int i;
238
239 for (i = 15; i > 0; i--) {
240 if (env->pil_in & (1 << i)) {
241 int old_interrupt = env->interrupt_index;
242
243 env->interrupt_index = TT_EXTINT | i;
244 if (old_interrupt != env->interrupt_index) {
245 DPRINTF("Set CPU IRQ %d\n", i);
246 cpu_interrupt(env, CPU_INTERRUPT_HARD);
247 }
248 break;
249 }
250 }
251 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
252 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
253 env->interrupt_index = 0;
254 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 }
257
258 static void cpu_set_irq(void *opaque, int irq, int level)
259 {
260 CPUState *env = opaque;
261
262 if (level) {
263 DPRINTF("Raise CPU IRQ %d\n", irq);
264 env->halted = 0;
265 env->pil_in |= 1 << irq;
266 cpu_check_irqs(env);
267 } else {
268 DPRINTF("Lower CPU IRQ %d\n", irq);
269 env->pil_in &= ~(1 << irq);
270 cpu_check_irqs(env);
271 }
272 }
273
274 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
275 {
276 }
277
278 static void main_cpu_reset(void *opaque)
279 {
280 CPUState *env = opaque;
281
282 cpu_reset(env);
283 env->halted = 0;
284 }
285
286 static void secondary_cpu_reset(void *opaque)
287 {
288 CPUState *env = opaque;
289
290 cpu_reset(env);
291 env->halted = 1;
292 }
293
294 static void cpu_halt_signal(void *opaque, int irq, int level)
295 {
296 if (level && cpu_single_env)
297 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
298 }
299
300 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
301 {
302 return addr - 0xf0000000ULL;
303 }
304
305 static unsigned long sun4m_load_kernel(const char *kernel_filename,
306 const char *initrd_filename,
307 ram_addr_t RAM_size)
308 {
309 int linux_boot;
310 unsigned int i;
311 long initrd_size, kernel_size;
312 uint8_t *ptr;
313
314 linux_boot = (kernel_filename != NULL);
315
316 kernel_size = 0;
317 if (linux_boot) {
318 int bswap_needed;
319
320 #ifdef BSWAP_NEEDED
321 bswap_needed = 1;
322 #else
323 bswap_needed = 0;
324 #endif
325 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
326 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
327 if (kernel_size < 0)
328 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
329 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
330 TARGET_PAGE_SIZE);
331 if (kernel_size < 0)
332 kernel_size = load_image_targphys(kernel_filename,
333 KERNEL_LOAD_ADDR,
334 RAM_size - KERNEL_LOAD_ADDR);
335 if (kernel_size < 0) {
336 fprintf(stderr, "qemu: could not load kernel '%s'\n",
337 kernel_filename);
338 exit(1);
339 }
340
341 /* load initrd */
342 initrd_size = 0;
343 if (initrd_filename) {
344 initrd_size = load_image_targphys(initrd_filename,
345 INITRD_LOAD_ADDR,
346 RAM_size - INITRD_LOAD_ADDR);
347 if (initrd_size < 0) {
348 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
349 initrd_filename);
350 exit(1);
351 }
352 }
353 if (initrd_size > 0) {
354 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
355 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
356 if (ldl_p(ptr) == 0x48647253) { // HdrS
357 stl_p(ptr + 16, INITRD_LOAD_ADDR);
358 stl_p(ptr + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
368 {
369 DeviceState *dev;
370 SysBusDevice *s;
371
372 dev = qdev_create(NULL, "iommu");
373 qdev_prop_set_uint32(dev, "version", version);
374 qdev_init_nofail(dev);
375 s = sysbus_from_qdev(dev);
376 sysbus_connect_irq(s, 0, irq);
377 sysbus_mmio_map(s, 0, addr);
378
379 return s;
380 }
381
382 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
383 void *iommu, qemu_irq *dev_irq)
384 {
385 DeviceState *dev;
386 SysBusDevice *s;
387
388 dev = qdev_create(NULL, "sparc32_dma");
389 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
390 qdev_init_nofail(dev);
391 s = sysbus_from_qdev(dev);
392 sysbus_connect_irq(s, 0, parent_irq);
393 *dev_irq = qdev_get_gpio_in(dev, 0);
394 sysbus_mmio_map(s, 0, daddr);
395
396 return s;
397 }
398
399 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
400 void *dma_opaque, qemu_irq irq)
401 {
402 DeviceState *dev;
403 SysBusDevice *s;
404 qemu_irq reset;
405
406 qemu_check_nic_model(&nd_table[0], "lance");
407
408 dev = qdev_create(NULL, "lance");
409 qdev_set_nic_properties(dev, nd);
410 qdev_prop_set_ptr(dev, "dma", dma_opaque);
411 qdev_init_nofail(dev);
412 s = sysbus_from_qdev(dev);
413 sysbus_mmio_map(s, 0, leaddr);
414 sysbus_connect_irq(s, 0, irq);
415 reset = qdev_get_gpio_in(dev, 0);
416 qdev_connect_gpio_out(dma_opaque, 0, reset);
417 }
418
419 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
420 target_phys_addr_t addrg,
421 qemu_irq **parent_irq)
422 {
423 DeviceState *dev;
424 SysBusDevice *s;
425 unsigned int i, j;
426
427 dev = qdev_create(NULL, "slavio_intctl");
428 qdev_init_nofail(dev);
429
430 s = sysbus_from_qdev(dev);
431
432 for (i = 0; i < MAX_CPUS; i++) {
433 for (j = 0; j < MAX_PILS; j++) {
434 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
435 }
436 }
437 sysbus_mmio_map(s, 0, addrg);
438 for (i = 0; i < MAX_CPUS; i++) {
439 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
440 }
441
442 return dev;
443 }
444
445 #define SYS_TIMER_OFFSET 0x10000ULL
446 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
447
448 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
449 qemu_irq *cpu_irqs, unsigned int num_cpus)
450 {
451 DeviceState *dev;
452 SysBusDevice *s;
453 unsigned int i;
454
455 dev = qdev_create(NULL, "slavio_timer");
456 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
457 qdev_init_nofail(dev);
458 s = sysbus_from_qdev(dev);
459 sysbus_connect_irq(s, 0, master_irq);
460 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
461
462 for (i = 0; i < MAX_CPUS; i++) {
463 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
464 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
465 }
466 }
467
468 #define MISC_LEDS 0x01600000
469 #define MISC_CFG 0x01800000
470 #define MISC_DIAG 0x01a00000
471 #define MISC_MDM 0x01b00000
472 #define MISC_SYS 0x01f00000
473
474 static void slavio_misc_init(target_phys_addr_t base,
475 target_phys_addr_t aux1_base,
476 target_phys_addr_t aux2_base, qemu_irq irq,
477 qemu_irq fdc_tc)
478 {
479 DeviceState *dev;
480 SysBusDevice *s;
481
482 dev = qdev_create(NULL, "slavio_misc");
483 qdev_init_nofail(dev);
484 s = sysbus_from_qdev(dev);
485 if (base) {
486 /* 8 bit registers */
487 /* Slavio control */
488 sysbus_mmio_map(s, 0, base + MISC_CFG);
489 /* Diagnostics */
490 sysbus_mmio_map(s, 1, base + MISC_DIAG);
491 /* Modem control */
492 sysbus_mmio_map(s, 2, base + MISC_MDM);
493 /* 16 bit registers */
494 /* ss600mp diag LEDs */
495 sysbus_mmio_map(s, 3, base + MISC_LEDS);
496 /* 32 bit registers */
497 /* System control */
498 sysbus_mmio_map(s, 4, base + MISC_SYS);
499 }
500 if (aux1_base) {
501 /* AUX 1 (Misc System Functions) */
502 sysbus_mmio_map(s, 5, aux1_base);
503 }
504 if (aux2_base) {
505 /* AUX 2 (Software Powerdown Control) */
506 sysbus_mmio_map(s, 6, aux2_base);
507 }
508 sysbus_connect_irq(s, 0, irq);
509 sysbus_connect_irq(s, 1, fdc_tc);
510 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
511 }
512
513 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
514 {
515 DeviceState *dev;
516 SysBusDevice *s;
517
518 dev = qdev_create(NULL, "eccmemctl");
519 qdev_prop_set_uint32(dev, "version", version);
520 qdev_init_nofail(dev);
521 s = sysbus_from_qdev(dev);
522 sysbus_connect_irq(s, 0, irq);
523 sysbus_mmio_map(s, 0, base);
524 if (version == 0) { // SS-600MP only
525 sysbus_mmio_map(s, 1, base + 0x1000);
526 }
527 }
528
529 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
530 {
531 DeviceState *dev;
532 SysBusDevice *s;
533
534 dev = qdev_create(NULL, "apc");
535 qdev_init_nofail(dev);
536 s = sysbus_from_qdev(dev);
537 /* Power management (APC) XXX: not a Slavio device */
538 sysbus_mmio_map(s, 0, power_base);
539 sysbus_connect_irq(s, 0, cpu_halt);
540 }
541
542 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
543 int height, int depth)
544 {
545 DeviceState *dev;
546 SysBusDevice *s;
547
548 dev = qdev_create(NULL, "SUNW,tcx");
549 qdev_prop_set_taddr(dev, "addr", addr);
550 qdev_prop_set_uint32(dev, "vram_size", vram_size);
551 qdev_prop_set_uint16(dev, "width", width);
552 qdev_prop_set_uint16(dev, "height", height);
553 qdev_prop_set_uint16(dev, "depth", depth);
554 qdev_init_nofail(dev);
555 s = sysbus_from_qdev(dev);
556 /* 8-bit plane */
557 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
558 /* DAC */
559 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
560 /* TEC (dummy) */
561 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
562 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
563 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
564 if (depth == 24) {
565 /* 24-bit plane */
566 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
567 /* Control plane */
568 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
569 } else {
570 /* THC 8 bit (dummy) */
571 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
572 }
573 }
574
575 /* NCR89C100/MACIO Internal ID register */
576 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
577
578 static void idreg_init(target_phys_addr_t addr)
579 {
580 DeviceState *dev;
581 SysBusDevice *s;
582
583 dev = qdev_create(NULL, "macio_idreg");
584 qdev_init_nofail(dev);
585 s = sysbus_from_qdev(dev);
586
587 sysbus_mmio_map(s, 0, addr);
588 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
589 }
590
591 static int idreg_init1(SysBusDevice *dev)
592 {
593 ram_addr_t idreg_offset;
594
595 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
596 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
597 return 0;
598 }
599
600 static SysBusDeviceInfo idreg_info = {
601 .init = idreg_init1,
602 .qdev.name = "macio_idreg",
603 .qdev.size = sizeof(SysBusDevice),
604 };
605
606 static void idreg_register_devices(void)
607 {
608 sysbus_register_withprop(&idreg_info);
609 }
610
611 device_init(idreg_register_devices);
612
613 /* SS-5 TCX AFX register */
614 static void afx_init(target_phys_addr_t addr)
615 {
616 DeviceState *dev;
617 SysBusDevice *s;
618
619 dev = qdev_create(NULL, "tcx_afx");
620 qdev_init_nofail(dev);
621 s = sysbus_from_qdev(dev);
622
623 sysbus_mmio_map(s, 0, addr);
624 }
625
626 static int afx_init1(SysBusDevice *dev)
627 {
628 ram_addr_t afx_offset;
629
630 afx_offset = qemu_ram_alloc(4);
631 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
632 return 0;
633 }
634
635 static SysBusDeviceInfo afx_info = {
636 .init = afx_init1,
637 .qdev.name = "tcx_afx",
638 .qdev.size = sizeof(SysBusDevice),
639 };
640
641 static void afx_register_devices(void)
642 {
643 sysbus_register_withprop(&afx_info);
644 }
645
646 device_init(afx_register_devices);
647
648 /* Boot PROM (OpenBIOS) */
649 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
650 {
651 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
652 return addr + *base_addr - PROM_VADDR;
653 }
654
655 static void prom_init(target_phys_addr_t addr, const char *bios_name)
656 {
657 DeviceState *dev;
658 SysBusDevice *s;
659 char *filename;
660 int ret;
661
662 dev = qdev_create(NULL, "openprom");
663 qdev_init_nofail(dev);
664 s = sysbus_from_qdev(dev);
665
666 sysbus_mmio_map(s, 0, addr);
667
668 /* load boot prom */
669 if (bios_name == NULL) {
670 bios_name = PROM_FILENAME;
671 }
672 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
673 if (filename) {
674 ret = load_elf(filename, translate_prom_address, &addr, NULL,
675 NULL, NULL, 1, ELF_MACHINE, 0);
676 if (ret < 0 || ret > PROM_SIZE_MAX) {
677 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
678 }
679 qemu_free(filename);
680 } else {
681 ret = -1;
682 }
683 if (ret < 0 || ret > PROM_SIZE_MAX) {
684 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
685 exit(1);
686 }
687 }
688
689 static int prom_init1(SysBusDevice *dev)
690 {
691 ram_addr_t prom_offset;
692
693 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
694 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
695 return 0;
696 }
697
698 static SysBusDeviceInfo prom_info = {
699 .init = prom_init1,
700 .qdev.name = "openprom",
701 .qdev.size = sizeof(SysBusDevice),
702 .qdev.props = (Property[]) {
703 {/* end of property list */}
704 }
705 };
706
707 static void prom_register_devices(void)
708 {
709 sysbus_register_withprop(&prom_info);
710 }
711
712 device_init(prom_register_devices);
713
714 typedef struct RamDevice
715 {
716 SysBusDevice busdev;
717 uint64_t size;
718 } RamDevice;
719
720 /* System RAM */
721 static int ram_init1(SysBusDevice *dev)
722 {
723 ram_addr_t RAM_size, ram_offset;
724 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
725
726 RAM_size = d->size;
727
728 ram_offset = qemu_ram_alloc(RAM_size);
729 sysbus_init_mmio(dev, RAM_size, ram_offset);
730 return 0;
731 }
732
733 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
734 uint64_t max_mem)
735 {
736 DeviceState *dev;
737 SysBusDevice *s;
738 RamDevice *d;
739
740 /* allocate RAM */
741 if ((uint64_t)RAM_size > max_mem) {
742 fprintf(stderr,
743 "qemu: Too much memory for this machine: %d, maximum %d\n",
744 (unsigned int)(RAM_size / (1024 * 1024)),
745 (unsigned int)(max_mem / (1024 * 1024)));
746 exit(1);
747 }
748 dev = qdev_create(NULL, "memory");
749 s = sysbus_from_qdev(dev);
750
751 d = FROM_SYSBUS(RamDevice, s);
752 d->size = RAM_size;
753 qdev_init_nofail(dev);
754
755 sysbus_mmio_map(s, 0, addr);
756 }
757
758 static SysBusDeviceInfo ram_info = {
759 .init = ram_init1,
760 .qdev.name = "memory",
761 .qdev.size = sizeof(RamDevice),
762 .qdev.props = (Property[]) {
763 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
764 DEFINE_PROP_END_OF_LIST(),
765 }
766 };
767
768 static void ram_register_devices(void)
769 {
770 sysbus_register_withprop(&ram_info);
771 }
772
773 device_init(ram_register_devices);
774
775 static void cpu_devinit(const char *cpu_model, unsigned int id,
776 uint64_t prom_addr, qemu_irq **cpu_irqs)
777 {
778 CPUState *env;
779
780 env = cpu_init(cpu_model);
781 if (!env) {
782 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
783 exit(1);
784 }
785
786 cpu_sparc_set_id(env, id);
787 if (id == 0) {
788 qemu_register_reset(main_cpu_reset, env);
789 } else {
790 qemu_register_reset(secondary_cpu_reset, env);
791 env->halted = 1;
792 }
793 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
794 env->prom_addr = prom_addr;
795 }
796
797 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
798 const char *boot_device,
799 const char *kernel_filename,
800 const char *kernel_cmdline,
801 const char *initrd_filename, const char *cpu_model)
802 {
803 unsigned int i;
804 void *iommu, *espdma, *ledma, *nvram;
805 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
806 espdma_irq, ledma_irq;
807 qemu_irq esp_reset;
808 qemu_irq fdc_tc;
809 qemu_irq *cpu_halt;
810 unsigned long kernel_size;
811 DriveInfo *fd[MAX_FD];
812 void *fw_cfg;
813
814 /* init CPUs */
815 if (!cpu_model)
816 cpu_model = hwdef->default_cpu_model;
817
818 for(i = 0; i < smp_cpus; i++) {
819 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
820 }
821
822 for (i = smp_cpus; i < MAX_CPUS; i++)
823 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
824
825
826 /* set up devices */
827 ram_init(0, RAM_size, hwdef->max_mem);
828 /* models without ECC don't trap when missing ram is accessed */
829 if (!hwdef->ecc_base) {
830 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
831 }
832
833 prom_init(hwdef->slavio_base, bios_name);
834
835 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
836 hwdef->intctl_base + 0x10000ULL,
837 cpu_irqs);
838
839 for (i = 0; i < 32; i++) {
840 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
841 }
842 for (i = 0; i < MAX_CPUS; i++) {
843 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
844 }
845
846 if (hwdef->idreg_base) {
847 idreg_init(hwdef->idreg_base);
848 }
849
850 if (hwdef->afx_base) {
851 afx_init(hwdef->afx_base);
852 }
853
854 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
855 slavio_irq[30]);
856
857 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
858 iommu, &espdma_irq);
859
860 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
861 slavio_irq[16], iommu, &ledma_irq);
862
863 if (graphic_depth != 8 && graphic_depth != 24) {
864 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
865 exit (1);
866 }
867 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
868 graphic_depth);
869
870 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
871
872 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
873
874 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
875
876 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
877 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
878 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
879 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
880 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
881 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
882
883 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
884 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
885 slavio_irq[30], fdc_tc);
886
887 if (hwdef->apc_base) {
888 apc_init(hwdef->apc_base, cpu_halt[0]);
889 }
890
891 if (hwdef->fd_base) {
892 /* there is zero or one floppy drive */
893 memset(fd, 0, sizeof(fd));
894 fd[0] = drive_get(IF_FLOPPY, 0, 0);
895 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
896 &fdc_tc);
897 }
898
899 if (drive_get_max_bus(IF_SCSI) > 0) {
900 fprintf(stderr, "qemu: too many SCSI bus\n");
901 exit(1);
902 }
903
904 esp_reset = qdev_get_gpio_in(espdma, 0);
905 esp_init(hwdef->esp_base, 2,
906 espdma_memory_read, espdma_memory_write,
907 espdma, espdma_irq, &esp_reset);
908
909
910 if (hwdef->cs_base) {
911 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
912 slavio_irq[5]);
913 }
914
915 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
916 RAM_size);
917
918 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
919 boot_device, RAM_size, kernel_size, graphic_width,
920 graphic_height, graphic_depth, hwdef->nvram_machine_id,
921 "Sun4m");
922
923 if (hwdef->ecc_base)
924 ecc_init(hwdef->ecc_base, slavio_irq[28],
925 hwdef->ecc_version);
926
927 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
928 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
929 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
930 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
931 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
932 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
933 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
934 if (kernel_cmdline) {
935 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
936 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
937 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
938 (uint8_t*)strdup(kernel_cmdline),
939 strlen(kernel_cmdline) + 1);
940 } else {
941 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
942 }
943 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
944 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
945 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
946 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
947 }
948
949 enum {
950 ss2_id = 0,
951 ss5_id = 32,
952 vger_id,
953 lx_id,
954 ss4_id,
955 scls_id,
956 sbook_id,
957 ss10_id = 64,
958 ss20_id,
959 ss600mp_id,
960 ss1000_id = 96,
961 ss2000_id,
962 };
963
964 static const struct sun4m_hwdef sun4m_hwdefs[] = {
965 /* SS-5 */
966 {
967 .iommu_base = 0x10000000,
968 .tcx_base = 0x50000000,
969 .cs_base = 0x6c000000,
970 .slavio_base = 0x70000000,
971 .ms_kb_base = 0x71000000,
972 .serial_base = 0x71100000,
973 .nvram_base = 0x71200000,
974 .fd_base = 0x71400000,
975 .counter_base = 0x71d00000,
976 .intctl_base = 0x71e00000,
977 .idreg_base = 0x78000000,
978 .dma_base = 0x78400000,
979 .esp_base = 0x78800000,
980 .le_base = 0x78c00000,
981 .apc_base = 0x6a000000,
982 .afx_base = 0x6e000000,
983 .aux1_base = 0x71900000,
984 .aux2_base = 0x71910000,
985 .nvram_machine_id = 0x80,
986 .machine_id = ss5_id,
987 .iommu_version = 0x05000000,
988 .max_mem = 0x10000000,
989 .default_cpu_model = "Fujitsu MB86904",
990 },
991 /* SS-10 */
992 {
993 .iommu_base = 0xfe0000000ULL,
994 .tcx_base = 0xe20000000ULL,
995 .slavio_base = 0xff0000000ULL,
996 .ms_kb_base = 0xff1000000ULL,
997 .serial_base = 0xff1100000ULL,
998 .nvram_base = 0xff1200000ULL,
999 .fd_base = 0xff1700000ULL,
1000 .counter_base = 0xff1300000ULL,
1001 .intctl_base = 0xff1400000ULL,
1002 .idreg_base = 0xef0000000ULL,
1003 .dma_base = 0xef0400000ULL,
1004 .esp_base = 0xef0800000ULL,
1005 .le_base = 0xef0c00000ULL,
1006 .apc_base = 0xefa000000ULL, // XXX should not exist
1007 .aux1_base = 0xff1800000ULL,
1008 .aux2_base = 0xff1a01000ULL,
1009 .ecc_base = 0xf00000000ULL,
1010 .ecc_version = 0x10000000, // version 0, implementation 1
1011 .nvram_machine_id = 0x72,
1012 .machine_id = ss10_id,
1013 .iommu_version = 0x03000000,
1014 .max_mem = 0xf00000000ULL,
1015 .default_cpu_model = "TI SuperSparc II",
1016 },
1017 /* SS-600MP */
1018 {
1019 .iommu_base = 0xfe0000000ULL,
1020 .tcx_base = 0xe20000000ULL,
1021 .slavio_base = 0xff0000000ULL,
1022 .ms_kb_base = 0xff1000000ULL,
1023 .serial_base = 0xff1100000ULL,
1024 .nvram_base = 0xff1200000ULL,
1025 .counter_base = 0xff1300000ULL,
1026 .intctl_base = 0xff1400000ULL,
1027 .dma_base = 0xef0081000ULL,
1028 .esp_base = 0xef0080000ULL,
1029 .le_base = 0xef0060000ULL,
1030 .apc_base = 0xefa000000ULL, // XXX should not exist
1031 .aux1_base = 0xff1800000ULL,
1032 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1033 .ecc_base = 0xf00000000ULL,
1034 .ecc_version = 0x00000000, // version 0, implementation 0
1035 .nvram_machine_id = 0x71,
1036 .machine_id = ss600mp_id,
1037 .iommu_version = 0x01000000,
1038 .max_mem = 0xf00000000ULL,
1039 .default_cpu_model = "TI SuperSparc II",
1040 },
1041 /* SS-20 */
1042 {
1043 .iommu_base = 0xfe0000000ULL,
1044 .tcx_base = 0xe20000000ULL,
1045 .slavio_base = 0xff0000000ULL,
1046 .ms_kb_base = 0xff1000000ULL,
1047 .serial_base = 0xff1100000ULL,
1048 .nvram_base = 0xff1200000ULL,
1049 .fd_base = 0xff1700000ULL,
1050 .counter_base = 0xff1300000ULL,
1051 .intctl_base = 0xff1400000ULL,
1052 .idreg_base = 0xef0000000ULL,
1053 .dma_base = 0xef0400000ULL,
1054 .esp_base = 0xef0800000ULL,
1055 .le_base = 0xef0c00000ULL,
1056 .apc_base = 0xefa000000ULL, // XXX should not exist
1057 .aux1_base = 0xff1800000ULL,
1058 .aux2_base = 0xff1a01000ULL,
1059 .ecc_base = 0xf00000000ULL,
1060 .ecc_version = 0x20000000, // version 0, implementation 2
1061 .nvram_machine_id = 0x72,
1062 .machine_id = ss20_id,
1063 .iommu_version = 0x13000000,
1064 .max_mem = 0xf00000000ULL,
1065 .default_cpu_model = "TI SuperSparc II",
1066 },
1067 /* Voyager */
1068 {
1069 .iommu_base = 0x10000000,
1070 .tcx_base = 0x50000000,
1071 .slavio_base = 0x70000000,
1072 .ms_kb_base = 0x71000000,
1073 .serial_base = 0x71100000,
1074 .nvram_base = 0x71200000,
1075 .fd_base = 0x71400000,
1076 .counter_base = 0x71d00000,
1077 .intctl_base = 0x71e00000,
1078 .idreg_base = 0x78000000,
1079 .dma_base = 0x78400000,
1080 .esp_base = 0x78800000,
1081 .le_base = 0x78c00000,
1082 .apc_base = 0x71300000, // pmc
1083 .aux1_base = 0x71900000,
1084 .aux2_base = 0x71910000,
1085 .nvram_machine_id = 0x80,
1086 .machine_id = vger_id,
1087 .iommu_version = 0x05000000,
1088 .max_mem = 0x10000000,
1089 .default_cpu_model = "Fujitsu MB86904",
1090 },
1091 /* LX */
1092 {
1093 .iommu_base = 0x10000000,
1094 .tcx_base = 0x50000000,
1095 .slavio_base = 0x70000000,
1096 .ms_kb_base = 0x71000000,
1097 .serial_base = 0x71100000,
1098 .nvram_base = 0x71200000,
1099 .fd_base = 0x71400000,
1100 .counter_base = 0x71d00000,
1101 .intctl_base = 0x71e00000,
1102 .idreg_base = 0x78000000,
1103 .dma_base = 0x78400000,
1104 .esp_base = 0x78800000,
1105 .le_base = 0x78c00000,
1106 .aux1_base = 0x71900000,
1107 .aux2_base = 0x71910000,
1108 .nvram_machine_id = 0x80,
1109 .machine_id = lx_id,
1110 .iommu_version = 0x04000000,
1111 .max_mem = 0x10000000,
1112 .default_cpu_model = "TI MicroSparc I",
1113 },
1114 /* SS-4 */
1115 {
1116 .iommu_base = 0x10000000,
1117 .tcx_base = 0x50000000,
1118 .cs_base = 0x6c000000,
1119 .slavio_base = 0x70000000,
1120 .ms_kb_base = 0x71000000,
1121 .serial_base = 0x71100000,
1122 .nvram_base = 0x71200000,
1123 .fd_base = 0x71400000,
1124 .counter_base = 0x71d00000,
1125 .intctl_base = 0x71e00000,
1126 .idreg_base = 0x78000000,
1127 .dma_base = 0x78400000,
1128 .esp_base = 0x78800000,
1129 .le_base = 0x78c00000,
1130 .apc_base = 0x6a000000,
1131 .aux1_base = 0x71900000,
1132 .aux2_base = 0x71910000,
1133 .nvram_machine_id = 0x80,
1134 .machine_id = ss4_id,
1135 .iommu_version = 0x05000000,
1136 .max_mem = 0x10000000,
1137 .default_cpu_model = "Fujitsu MB86904",
1138 },
1139 /* SPARCClassic */
1140 {
1141 .iommu_base = 0x10000000,
1142 .tcx_base = 0x50000000,
1143 .slavio_base = 0x70000000,
1144 .ms_kb_base = 0x71000000,
1145 .serial_base = 0x71100000,
1146 .nvram_base = 0x71200000,
1147 .fd_base = 0x71400000,
1148 .counter_base = 0x71d00000,
1149 .intctl_base = 0x71e00000,
1150 .idreg_base = 0x78000000,
1151 .dma_base = 0x78400000,
1152 .esp_base = 0x78800000,
1153 .le_base = 0x78c00000,
1154 .apc_base = 0x6a000000,
1155 .aux1_base = 0x71900000,
1156 .aux2_base = 0x71910000,
1157 .nvram_machine_id = 0x80,
1158 .machine_id = scls_id,
1159 .iommu_version = 0x05000000,
1160 .max_mem = 0x10000000,
1161 .default_cpu_model = "TI MicroSparc I",
1162 },
1163 /* SPARCbook */
1164 {
1165 .iommu_base = 0x10000000,
1166 .tcx_base = 0x50000000, // XXX
1167 .slavio_base = 0x70000000,
1168 .ms_kb_base = 0x71000000,
1169 .serial_base = 0x71100000,
1170 .nvram_base = 0x71200000,
1171 .fd_base = 0x71400000,
1172 .counter_base = 0x71d00000,
1173 .intctl_base = 0x71e00000,
1174 .idreg_base = 0x78000000,
1175 .dma_base = 0x78400000,
1176 .esp_base = 0x78800000,
1177 .le_base = 0x78c00000,
1178 .apc_base = 0x6a000000,
1179 .aux1_base = 0x71900000,
1180 .aux2_base = 0x71910000,
1181 .nvram_machine_id = 0x80,
1182 .machine_id = sbook_id,
1183 .iommu_version = 0x05000000,
1184 .max_mem = 0x10000000,
1185 .default_cpu_model = "TI MicroSparc I",
1186 },
1187 };
1188
1189 /* SPARCstation 5 hardware initialisation */
1190 static void ss5_init(ram_addr_t RAM_size,
1191 const char *boot_device,
1192 const char *kernel_filename, const char *kernel_cmdline,
1193 const char *initrd_filename, const char *cpu_model)
1194 {
1195 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1196 kernel_cmdline, initrd_filename, cpu_model);
1197 }
1198
1199 /* SPARCstation 10 hardware initialisation */
1200 static void ss10_init(ram_addr_t RAM_size,
1201 const char *boot_device,
1202 const char *kernel_filename, const char *kernel_cmdline,
1203 const char *initrd_filename, const char *cpu_model)
1204 {
1205 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1206 kernel_cmdline, initrd_filename, cpu_model);
1207 }
1208
1209 /* SPARCserver 600MP hardware initialisation */
1210 static void ss600mp_init(ram_addr_t RAM_size,
1211 const char *boot_device,
1212 const char *kernel_filename,
1213 const char *kernel_cmdline,
1214 const char *initrd_filename, const char *cpu_model)
1215 {
1216 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1217 kernel_cmdline, initrd_filename, cpu_model);
1218 }
1219
1220 /* SPARCstation 20 hardware initialisation */
1221 static void ss20_init(ram_addr_t RAM_size,
1222 const char *boot_device,
1223 const char *kernel_filename, const char *kernel_cmdline,
1224 const char *initrd_filename, const char *cpu_model)
1225 {
1226 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1227 kernel_cmdline, initrd_filename, cpu_model);
1228 }
1229
1230 /* SPARCstation Voyager hardware initialisation */
1231 static void vger_init(ram_addr_t RAM_size,
1232 const char *boot_device,
1233 const char *kernel_filename, const char *kernel_cmdline,
1234 const char *initrd_filename, const char *cpu_model)
1235 {
1236 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1237 kernel_cmdline, initrd_filename, cpu_model);
1238 }
1239
1240 /* SPARCstation LX hardware initialisation */
1241 static void ss_lx_init(ram_addr_t RAM_size,
1242 const char *boot_device,
1243 const char *kernel_filename, const char *kernel_cmdline,
1244 const char *initrd_filename, const char *cpu_model)
1245 {
1246 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1247 kernel_cmdline, initrd_filename, cpu_model);
1248 }
1249
1250 /* SPARCstation 4 hardware initialisation */
1251 static void ss4_init(ram_addr_t RAM_size,
1252 const char *boot_device,
1253 const char *kernel_filename, const char *kernel_cmdline,
1254 const char *initrd_filename, const char *cpu_model)
1255 {
1256 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1257 kernel_cmdline, initrd_filename, cpu_model);
1258 }
1259
1260 /* SPARCClassic hardware initialisation */
1261 static void scls_init(ram_addr_t RAM_size,
1262 const char *boot_device,
1263 const char *kernel_filename, const char *kernel_cmdline,
1264 const char *initrd_filename, const char *cpu_model)
1265 {
1266 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1267 kernel_cmdline, initrd_filename, cpu_model);
1268 }
1269
1270 /* SPARCbook hardware initialisation */
1271 static void sbook_init(ram_addr_t RAM_size,
1272 const char *boot_device,
1273 const char *kernel_filename, const char *kernel_cmdline,
1274 const char *initrd_filename, const char *cpu_model)
1275 {
1276 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1277 kernel_cmdline, initrd_filename, cpu_model);
1278 }
1279
1280 static QEMUMachine ss5_machine = {
1281 .name = "SS-5",
1282 .desc = "Sun4m platform, SPARCstation 5",
1283 .init = ss5_init,
1284 .use_scsi = 1,
1285 .is_default = 1,
1286 };
1287
1288 static QEMUMachine ss10_machine = {
1289 .name = "SS-10",
1290 .desc = "Sun4m platform, SPARCstation 10",
1291 .init = ss10_init,
1292 .use_scsi = 1,
1293 .max_cpus = 4,
1294 };
1295
1296 static QEMUMachine ss600mp_machine = {
1297 .name = "SS-600MP",
1298 .desc = "Sun4m platform, SPARCserver 600MP",
1299 .init = ss600mp_init,
1300 .use_scsi = 1,
1301 .max_cpus = 4,
1302 };
1303
1304 static QEMUMachine ss20_machine = {
1305 .name = "SS-20",
1306 .desc = "Sun4m platform, SPARCstation 20",
1307 .init = ss20_init,
1308 .use_scsi = 1,
1309 .max_cpus = 4,
1310 };
1311
1312 static QEMUMachine voyager_machine = {
1313 .name = "Voyager",
1314 .desc = "Sun4m platform, SPARCstation Voyager",
1315 .init = vger_init,
1316 .use_scsi = 1,
1317 };
1318
1319 static QEMUMachine ss_lx_machine = {
1320 .name = "LX",
1321 .desc = "Sun4m platform, SPARCstation LX",
1322 .init = ss_lx_init,
1323 .use_scsi = 1,
1324 };
1325
1326 static QEMUMachine ss4_machine = {
1327 .name = "SS-4",
1328 .desc = "Sun4m platform, SPARCstation 4",
1329 .init = ss4_init,
1330 .use_scsi = 1,
1331 };
1332
1333 static QEMUMachine scls_machine = {
1334 .name = "SPARCClassic",
1335 .desc = "Sun4m platform, SPARCClassic",
1336 .init = scls_init,
1337 .use_scsi = 1,
1338 };
1339
1340 static QEMUMachine sbook_machine = {
1341 .name = "SPARCbook",
1342 .desc = "Sun4m platform, SPARCbook",
1343 .init = sbook_init,
1344 .use_scsi = 1,
1345 };
1346
1347 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1348 /* SS-1000 */
1349 {
1350 .iounit_bases = {
1351 0xfe0200000ULL,
1352 0xfe1200000ULL,
1353 0xfe2200000ULL,
1354 0xfe3200000ULL,
1355 -1,
1356 },
1357 .tcx_base = 0x820000000ULL,
1358 .slavio_base = 0xf00000000ULL,
1359 .ms_kb_base = 0xf00240000ULL,
1360 .serial_base = 0xf00200000ULL,
1361 .nvram_base = 0xf00280000ULL,
1362 .counter_base = 0xf00300000ULL,
1363 .espdma_base = 0x800081000ULL,
1364 .esp_base = 0x800080000ULL,
1365 .ledma_base = 0x800040000ULL,
1366 .le_base = 0x800060000ULL,
1367 .sbi_base = 0xf02800000ULL,
1368 .nvram_machine_id = 0x80,
1369 .machine_id = ss1000_id,
1370 .iounit_version = 0x03000000,
1371 .max_mem = 0xf00000000ULL,
1372 .default_cpu_model = "TI SuperSparc II",
1373 },
1374 /* SS-2000 */
1375 {
1376 .iounit_bases = {
1377 0xfe0200000ULL,
1378 0xfe1200000ULL,
1379 0xfe2200000ULL,
1380 0xfe3200000ULL,
1381 0xfe4200000ULL,
1382 },
1383 .tcx_base = 0x820000000ULL,
1384 .slavio_base = 0xf00000000ULL,
1385 .ms_kb_base = 0xf00240000ULL,
1386 .serial_base = 0xf00200000ULL,
1387 .nvram_base = 0xf00280000ULL,
1388 .counter_base = 0xf00300000ULL,
1389 .espdma_base = 0x800081000ULL,
1390 .esp_base = 0x800080000ULL,
1391 .ledma_base = 0x800040000ULL,
1392 .le_base = 0x800060000ULL,
1393 .sbi_base = 0xf02800000ULL,
1394 .nvram_machine_id = 0x80,
1395 .machine_id = ss2000_id,
1396 .iounit_version = 0x03000000,
1397 .max_mem = 0xf00000000ULL,
1398 .default_cpu_model = "TI SuperSparc II",
1399 },
1400 };
1401
1402 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1403 {
1404 DeviceState *dev;
1405 SysBusDevice *s;
1406 unsigned int i;
1407
1408 dev = qdev_create(NULL, "sbi");
1409 qdev_init_nofail(dev);
1410
1411 s = sysbus_from_qdev(dev);
1412
1413 for (i = 0; i < MAX_CPUS; i++) {
1414 sysbus_connect_irq(s, i, *parent_irq[i]);
1415 }
1416
1417 sysbus_mmio_map(s, 0, addr);
1418
1419 return dev;
1420 }
1421
1422 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1423 const char *boot_device,
1424 const char *kernel_filename,
1425 const char *kernel_cmdline,
1426 const char *initrd_filename, const char *cpu_model)
1427 {
1428 unsigned int i;
1429 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1430 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1431 espdma_irq, ledma_irq;
1432 qemu_irq esp_reset;
1433 unsigned long kernel_size;
1434 void *fw_cfg;
1435 DeviceState *dev;
1436
1437 /* init CPUs */
1438 if (!cpu_model)
1439 cpu_model = hwdef->default_cpu_model;
1440
1441 for(i = 0; i < smp_cpus; i++) {
1442 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1443 }
1444
1445 for (i = smp_cpus; i < MAX_CPUS; i++)
1446 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1447
1448 /* set up devices */
1449 ram_init(0, RAM_size, hwdef->max_mem);
1450
1451 prom_init(hwdef->slavio_base, bios_name);
1452
1453 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1454
1455 for (i = 0; i < 32; i++) {
1456 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1457 }
1458 for (i = 0; i < MAX_CPUS; i++) {
1459 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1460 }
1461
1462 for (i = 0; i < MAX_IOUNITS; i++)
1463 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1464 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1465 hwdef->iounit_version,
1466 sbi_irq[0]);
1467
1468 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1469 iounits[0], &espdma_irq);
1470
1471 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1472 iounits[0], &ledma_irq);
1473
1474 if (graphic_depth != 8 && graphic_depth != 24) {
1475 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1476 exit (1);
1477 }
1478 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1479 graphic_depth);
1480
1481 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1482
1483 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1484
1485 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1486
1487 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1488 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1489 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1490 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1491 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1492 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1493
1494 if (drive_get_max_bus(IF_SCSI) > 0) {
1495 fprintf(stderr, "qemu: too many SCSI bus\n");
1496 exit(1);
1497 }
1498
1499 esp_reset = qdev_get_gpio_in(espdma, 0);
1500 esp_init(hwdef->esp_base, 2,
1501 espdma_memory_read, espdma_memory_write,
1502 espdma, espdma_irq, &esp_reset);
1503
1504 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1505 RAM_size);
1506
1507 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1508 boot_device, RAM_size, kernel_size, graphic_width,
1509 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1510 "Sun4d");
1511
1512 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1513 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1514 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1515 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1516 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1517 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1518 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1519 if (kernel_cmdline) {
1520 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1521 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1522 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1523 (uint8_t*)strdup(kernel_cmdline),
1524 strlen(kernel_cmdline) + 1);
1525 } else {
1526 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1527 }
1528 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1529 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1530 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1531 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1532 }
1533
1534 /* SPARCserver 1000 hardware initialisation */
1535 static void ss1000_init(ram_addr_t RAM_size,
1536 const char *boot_device,
1537 const char *kernel_filename, const char *kernel_cmdline,
1538 const char *initrd_filename, const char *cpu_model)
1539 {
1540 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1541 kernel_cmdline, initrd_filename, cpu_model);
1542 }
1543
1544 /* SPARCcenter 2000 hardware initialisation */
1545 static void ss2000_init(ram_addr_t RAM_size,
1546 const char *boot_device,
1547 const char *kernel_filename, const char *kernel_cmdline,
1548 const char *initrd_filename, const char *cpu_model)
1549 {
1550 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1551 kernel_cmdline, initrd_filename, cpu_model);
1552 }
1553
1554 static QEMUMachine ss1000_machine = {
1555 .name = "SS-1000",
1556 .desc = "Sun4d platform, SPARCserver 1000",
1557 .init = ss1000_init,
1558 .use_scsi = 1,
1559 .max_cpus = 8,
1560 };
1561
1562 static QEMUMachine ss2000_machine = {
1563 .name = "SS-2000",
1564 .desc = "Sun4d platform, SPARCcenter 2000",
1565 .init = ss2000_init,
1566 .use_scsi = 1,
1567 .max_cpus = 20,
1568 };
1569
1570 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1571 /* SS-2 */
1572 {
1573 .iommu_base = 0xf8000000,
1574 .tcx_base = 0xfe000000,
1575 .slavio_base = 0xf6000000,
1576 .intctl_base = 0xf5000000,
1577 .counter_base = 0xf3000000,
1578 .ms_kb_base = 0xf0000000,
1579 .serial_base = 0xf1000000,
1580 .nvram_base = 0xf2000000,
1581 .fd_base = 0xf7200000,
1582 .dma_base = 0xf8400000,
1583 .esp_base = 0xf8800000,
1584 .le_base = 0xf8c00000,
1585 .aux1_base = 0xf7400003,
1586 .nvram_machine_id = 0x55,
1587 .machine_id = ss2_id,
1588 .max_mem = 0x10000000,
1589 .default_cpu_model = "Cypress CY7C601",
1590 },
1591 };
1592
1593 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1594 qemu_irq *parent_irq)
1595 {
1596 DeviceState *dev;
1597 SysBusDevice *s;
1598 unsigned int i;
1599
1600 dev = qdev_create(NULL, "sun4c_intctl");
1601 qdev_init_nofail(dev);
1602
1603 s = sysbus_from_qdev(dev);
1604
1605 for (i = 0; i < MAX_PILS; i++) {
1606 sysbus_connect_irq(s, i, parent_irq[i]);
1607 }
1608 sysbus_mmio_map(s, 0, addr);
1609
1610 return dev;
1611 }
1612
1613 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1614 const char *boot_device,
1615 const char *kernel_filename,
1616 const char *kernel_cmdline,
1617 const char *initrd_filename, const char *cpu_model)
1618 {
1619 void *iommu, *espdma, *ledma, *nvram;
1620 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1621 qemu_irq esp_reset;
1622 qemu_irq fdc_tc;
1623 unsigned long kernel_size;
1624 DriveInfo *fd[MAX_FD];
1625 void *fw_cfg;
1626 DeviceState *dev;
1627 unsigned int i;
1628
1629 /* init CPU */
1630 if (!cpu_model)
1631 cpu_model = hwdef->default_cpu_model;
1632
1633 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1634
1635 /* set up devices */
1636 ram_init(0, RAM_size, hwdef->max_mem);
1637
1638 prom_init(hwdef->slavio_base, bios_name);
1639
1640 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1641
1642 for (i = 0; i < 8; i++) {
1643 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1644 }
1645
1646 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1647 slavio_irq[1]);
1648
1649 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1650 iommu, &espdma_irq);
1651
1652 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1653 slavio_irq[3], iommu, &ledma_irq);
1654
1655 if (graphic_depth != 8 && graphic_depth != 24) {
1656 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1657 exit (1);
1658 }
1659 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1660 graphic_depth);
1661
1662 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1663
1664 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1665
1666 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1667 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1668 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1669 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1670 escc_init(hwdef->serial_base, slavio_irq[1],
1671 slavio_irq[1], serial_hds[0], serial_hds[1],
1672 ESCC_CLOCK, 1);
1673
1674 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1675
1676 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1677 /* there is zero or one floppy drive */
1678 memset(fd, 0, sizeof(fd));
1679 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1680 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1681 &fdc_tc);
1682 }
1683
1684 if (drive_get_max_bus(IF_SCSI) > 0) {
1685 fprintf(stderr, "qemu: too many SCSI bus\n");
1686 exit(1);
1687 }
1688
1689 esp_reset = qdev_get_gpio_in(espdma, 0);
1690 esp_init(hwdef->esp_base, 2,
1691 espdma_memory_read, espdma_memory_write,
1692 espdma, espdma_irq, &esp_reset);
1693
1694 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1695 RAM_size);
1696
1697 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1698 boot_device, RAM_size, kernel_size, graphic_width,
1699 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1700 "Sun4c");
1701
1702 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1703 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1704 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1705 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1706 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1707 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1708 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1709 if (kernel_cmdline) {
1710 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1711 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1712 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1713 (uint8_t*)strdup(kernel_cmdline),
1714 strlen(kernel_cmdline) + 1);
1715 } else {
1716 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1717 }
1718 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1719 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1720 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1721 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1722 }
1723
1724 /* SPARCstation 2 hardware initialisation */
1725 static void ss2_init(ram_addr_t RAM_size,
1726 const char *boot_device,
1727 const char *kernel_filename, const char *kernel_cmdline,
1728 const char *initrd_filename, const char *cpu_model)
1729 {
1730 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1731 kernel_cmdline, initrd_filename, cpu_model);
1732 }
1733
1734 static QEMUMachine ss2_machine = {
1735 .name = "SS-2",
1736 .desc = "Sun4c platform, SPARCstation 2",
1737 .init = ss2_init,
1738 .use_scsi = 1,
1739 };
1740
1741 static void ss2_machine_init(void)
1742 {
1743 qemu_register_machine(&ss5_machine);
1744 qemu_register_machine(&ss10_machine);
1745 qemu_register_machine(&ss600mp_machine);
1746 qemu_register_machine(&ss20_machine);
1747 qemu_register_machine(&voyager_machine);
1748 qemu_register_machine(&ss_lx_machine);
1749 qemu_register_machine(&ss4_machine);
1750 qemu_register_machine(&scls_machine);
1751 qemu_register_machine(&sbook_machine);
1752 qemu_register_machine(&ss1000_machine);
1753 qemu_register_machine(&ss2000_machine);
1754 qemu_register_machine(&ss2_machine);
1755 }
1756
1757 machine_init(ss2_machine_init);
Anthony Liguori's QEMU queue