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Fix -device help and documentation
[qemu/aliguori-queue.git] / hw / pci.c
blob8d84651f19f0df1ddf68a358e431bc0a79b474ea
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29 #include "loader.h"
30 #include "qemu-objects.h"
31
32 //#define DEBUG_PCI
33 #ifdef DEBUG_PCI
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
35 #else
36 # define PCI_DPRINTF(format, ...) do { } while (0)
37 #endif
38
39 struct PCIBus {
40 BusState qbus;
41 int devfn_min;
42 pci_set_irq_fn set_irq;
43 pci_map_irq_fn map_irq;
44 pci_hotplug_fn hotplug;
45 DeviceState *hotplug_qdev;
46 void *irq_opaque;
47 PCIDevice *devices[256];
48 PCIDevice *parent_dev;
49 target_phys_addr_t mem_base;
50
51 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
52 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
53
54 /* The bus IRQ state is the logical OR of the connected devices.
55 Keep a count of the number of devices with raised IRQs. */
56 int nirq;
57 int *irq_count;
58 };
59
60 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
61
62 static struct BusInfo pci_bus_info = {
63 .name = "PCI",
64 .size = sizeof(PCIBus),
65 .print_dev = pcibus_dev_print,
66 .props = (Property[]) {
67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
68 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
69 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
70 DEFINE_PROP_END_OF_LIST()
71 }
72 };
73
74 static void pci_update_mappings(PCIDevice *d);
75 static void pci_set_irq(void *opaque, int irq_num, int level);
76 static int pci_add_option_rom(PCIDevice *pdev);
77
78 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
79 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
80
81 struct PCIHostBus {
82 int domain;
83 struct PCIBus *bus;
84 QLIST_ENTRY(PCIHostBus) next;
85 };
86 static QLIST_HEAD(, PCIHostBus) host_buses;
87
88 static const VMStateDescription vmstate_pcibus = {
89 .name = "PCIBUS",
90 .version_id = 1,
91 .minimum_version_id = 1,
92 .minimum_version_id_old = 1,
93 .fields = (VMStateField []) {
94 VMSTATE_INT32_EQUAL(nirq, PCIBus),
95 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
96 VMSTATE_END_OF_LIST()
97 }
98 };
99
100 static int pci_bar(PCIDevice *d, int reg)
101 {
102 uint8_t type;
103
104 if (reg != PCI_ROM_SLOT)
105 return PCI_BASE_ADDRESS_0 + reg * 4;
106
107 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
108 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
109 }
110
111 static inline int pci_irq_state(PCIDevice *d, int irq_num)
112 {
113 return (d->irq_state >> irq_num) & 0x1;
114 }
115
116 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
117 {
118 d->irq_state &= ~(0x1 << irq_num);
119 d->irq_state |= level << irq_num;
120 }
121
122 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
123 {
124 PCIBus *bus;
125 for (;;) {
126 bus = pci_dev->bus;
127 irq_num = bus->map_irq(pci_dev, irq_num);
128 if (bus->set_irq)
129 break;
130 pci_dev = bus->parent_dev;
131 }
132 bus->irq_count[irq_num] += change;
133 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 static void pci_device_reset(PCIDevice *dev)
148 {
149 int r;
150
151 dev->irq_state = 0;
152 pci_update_irq_status(dev);
153 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
154 PCI_COMMAND_MASTER);
155 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
156 dev->config[PCI_INTERRUPT_LINE] = 0x0;
157 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
158 if (!dev->io_regions[r].size) {
159 continue;
160 }
161 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
162 }
163 pci_update_mappings(dev);
164 }
165
166 static void pci_bus_reset(void *opaque)
167 {
168 PCIBus *bus = opaque;
169 int i;
170
171 for (i = 0; i < bus->nirq; i++) {
172 bus->irq_count[i] = 0;
173 }
174 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
175 if (bus->devices[i]) {
176 pci_device_reset(bus->devices[i]);
177 }
178 }
179 }
180
181 static void pci_host_bus_register(int domain, PCIBus *bus)
182 {
183 struct PCIHostBus *host;
184 host = qemu_mallocz(sizeof(*host));
185 host->domain = domain;
186 host->bus = bus;
187 QLIST_INSERT_HEAD(&host_buses, host, next);
188 }
189
190 PCIBus *pci_find_root_bus(int domain)
191 {
192 struct PCIHostBus *host;
193
194 QLIST_FOREACH(host, &host_buses, next) {
195 if (host->domain == domain) {
196 return host->bus;
197 }
198 }
199
200 return NULL;
201 }
202
203 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
204 const char *name, int devfn_min)
205 {
206 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
207 bus->devfn_min = devfn_min;
208
209 /* host bridge */
210 QLIST_INIT(&bus->child);
211 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
212
213 vmstate_register(-1, &vmstate_pcibus, bus);
214 qemu_register_reset(pci_bus_reset, bus);
215 }
216
217 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
218 {
219 PCIBus *bus;
220
221 bus = qemu_mallocz(sizeof(*bus));
222 bus->qbus.qdev_allocated = 1;
223 pci_bus_new_inplace(bus, parent, name, devfn_min);
224 return bus;
225 }
226
227 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
228 void *irq_opaque, int nirq)
229 {
230 bus->set_irq = set_irq;
231 bus->map_irq = map_irq;
232 bus->irq_opaque = irq_opaque;
233 bus->nirq = nirq;
234 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
235 }
236
237 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
238 {
239 bus->qbus.allow_hotplug = 1;
240 bus->hotplug = hotplug;
241 bus->hotplug_qdev = qdev;
242 }
243
244 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
245 {
246 bus->mem_base = base;
247 }
248
249 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
250 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
251 void *irq_opaque, int devfn_min, int nirq)
252 {
253 PCIBus *bus;
254
255 bus = pci_bus_new(parent, name, devfn_min);
256 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
257 return bus;
258 }
259
260 static void pci_register_secondary_bus(PCIBus *parent,
261 PCIBus *bus,
262 PCIDevice *dev,
263 pci_map_irq_fn map_irq,
264 const char *name)
265 {
266 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
267 bus->map_irq = map_irq;
268 bus->parent_dev = dev;
269
270 QLIST_INIT(&bus->child);
271 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
272 }
273
274 static void pci_unregister_secondary_bus(PCIBus *bus)
275 {
276 assert(QLIST_EMPTY(&bus->child));
277 QLIST_REMOVE(bus, sibling);
278 }
279
280 int pci_bus_num(PCIBus *s)
281 {
282 if (!s->parent_dev)
283 return 0; /* pci host bridge */
284 return s->parent_dev->config[PCI_SECONDARY_BUS];
285 }
286
287 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
288 {
289 PCIDevice *s = container_of(pv, PCIDevice, config);
290 uint8_t *config;
291 int i;
292
293 assert(size == pci_config_size(s));
294 config = qemu_malloc(size);
295
296 qemu_get_buffer(f, config, size);
297 for (i = 0; i < size; ++i) {
298 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
299 qemu_free(config);
300 return -EINVAL;
301 }
302 }
303 memcpy(s->config, config, size);
304
305 pci_update_mappings(s);
306
307 qemu_free(config);
308 return 0;
309 }
310
311 /* just put buffer */
312 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
313 {
314 const uint8_t **v = pv;
315 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
316 qemu_put_buffer(f, *v, size);
317 }
318
319 static VMStateInfo vmstate_info_pci_config = {
320 .name = "pci config",
321 .get = get_pci_config_device,
322 .put = put_pci_config_device,
323 };
324
325 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
326 {
327 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
328 uint32_t irq_state[PCI_NUM_PINS];
329 int i;
330 for (i = 0; i < PCI_NUM_PINS; ++i) {
331 irq_state[i] = qemu_get_be32(f);
332 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
333 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
334 irq_state[i]);
335 return -EINVAL;
336 }
337 }
338
339 for (i = 0; i < PCI_NUM_PINS; ++i) {
340 pci_set_irq_state(s, i, irq_state[i]);
341 }
342
343 return 0;
344 }
345
346 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
347 {
348 int i;
349 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
350
351 for (i = 0; i < PCI_NUM_PINS; ++i) {
352 qemu_put_be32(f, pci_irq_state(s, i));
353 }
354 }
355
356 static VMStateInfo vmstate_info_pci_irq_state = {
357 .name = "pci irq state",
358 .get = get_pci_irq_state,
359 .put = put_pci_irq_state,
360 };
361
362 const VMStateDescription vmstate_pci_device = {
363 .name = "PCIDevice",
364 .version_id = 2,
365 .minimum_version_id = 1,
366 .minimum_version_id_old = 1,
367 .fields = (VMStateField []) {
368 VMSTATE_INT32_LE(version_id, PCIDevice),
369 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
370 vmstate_info_pci_config,
371 PCI_CONFIG_SPACE_SIZE),
372 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
373 vmstate_info_pci_irq_state,
374 PCI_NUM_PINS * sizeof(int32_t)),
375 VMSTATE_END_OF_LIST()
376 }
377 };
378
379 const VMStateDescription vmstate_pcie_device = {
380 .name = "PCIDevice",
381 .version_id = 2,
382 .minimum_version_id = 1,
383 .minimum_version_id_old = 1,
384 .fields = (VMStateField []) {
385 VMSTATE_INT32_LE(version_id, PCIDevice),
386 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
387 vmstate_info_pci_config,
388 PCIE_CONFIG_SPACE_SIZE),
389 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
390 vmstate_info_pci_irq_state,
391 PCI_NUM_PINS * sizeof(int32_t)),
392 VMSTATE_END_OF_LIST()
393 }
394 };
395
396 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
397 {
398 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
399 }
400
401 void pci_device_save(PCIDevice *s, QEMUFile *f)
402 {
403 /* Clear interrupt status bit: it is implicit
404 * in irq_state which we are saving.
405 * This makes us compatible with old devices
406 * which never set or clear this bit. */
407 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
408 vmstate_save_state(f, pci_get_vmstate(s), s);
409 /* Restore the interrupt status bit. */
410 pci_update_irq_status(s);
411 }
412
413 int pci_device_load(PCIDevice *s, QEMUFile *f)
414 {
415 int ret;
416 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
417 /* Restore the interrupt status bit. */
418 pci_update_irq_status(s);
419 return ret;
420 }
421
422 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
423 {
424 uint16_t *id;
425
426 id = (void*)(&pci_dev->config[PCI_SUBSYSTEM_VENDOR_ID]);
427 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
428 id[1] = cpu_to_le16(pci_default_sub_device_id);
429 return 0;
430 }
431
432 /*
433 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
434 */
435 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
436 {
437 const char *p;
438 char *e;
439 unsigned long val;
440 unsigned long dom = 0, bus = 0;
441 unsigned slot = 0;
442
443 p = addr;
444 val = strtoul(p, &e, 16);
445 if (e == p)
446 return -1;
447 if (*e == ':') {
448 bus = val;
449 p = e + 1;
450 val = strtoul(p, &e, 16);
451 if (e == p)
452 return -1;
453 if (*e == ':') {
454 dom = bus;
455 bus = val;
456 p = e + 1;
457 val = strtoul(p, &e, 16);
458 if (e == p)
459 return -1;
460 }
461 }
462
463 if (dom > 0xffff || bus > 0xff || val > 0x1f)
464 return -1;
465
466 slot = val;
467
468 if (*e)
469 return -1;
470
471 /* Note: QEMU doesn't implement domains other than 0 */
472 if (!pci_find_bus(pci_find_root_bus(dom), bus))
473 return -1;
474
475 *domp = dom;
476 *busp = bus;
477 *slotp = slot;
478 return 0;
479 }
480
481 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
482 unsigned *slotp)
483 {
484 /* strip legacy tag */
485 if (!strncmp(addr, "pci_addr=", 9)) {
486 addr += 9;
487 }
488 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
489 monitor_printf(mon, "Invalid pci address\n");
490 return -1;
491 }
492 return 0;
493 }
494
495 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
496 {
497 int dom, bus;
498 unsigned slot;
499
500 if (!devaddr) {
501 *devfnp = -1;
502 return pci_find_bus(pci_find_root_bus(0), 0);
503 }
504
505 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
506 return NULL;
507 }
508
509 *devfnp = slot << 3;
510 return pci_find_bus(pci_find_root_bus(0), bus);
511 }
512
513 static void pci_init_cmask(PCIDevice *dev)
514 {
515 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
516 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
517 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
518 dev->cmask[PCI_REVISION_ID] = 0xff;
519 dev->cmask[PCI_CLASS_PROG] = 0xff;
520 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
521 dev->cmask[PCI_HEADER_TYPE] = 0xff;
522 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
523 }
524
525 static void pci_init_wmask(PCIDevice *dev)
526 {
527 int config_size = pci_config_size(dev);
528
529 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
530 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
531 pci_set_word(dev->wmask + PCI_COMMAND,
532 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
533 PCI_COMMAND_INTX_DISABLE);
534
535 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
536 config_size - PCI_CONFIG_HEADER_SIZE);
537 }
538
539 static void pci_init_wmask_bridge(PCIDevice *d)
540 {
541 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
542 PCI_SEC_LETENCY_TIMER */
543 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
544
545 /* base and limit */
546 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
547 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
548 pci_set_word(d->wmask + PCI_MEMORY_BASE,
549 PCI_MEMORY_RANGE_MASK & 0xffff);
550 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
551 PCI_MEMORY_RANGE_MASK & 0xffff);
552 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
553 PCI_PREF_RANGE_MASK & 0xffff);
554 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
555 PCI_PREF_RANGE_MASK & 0xffff);
556
557 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
558 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
559
560 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
561 }
562
563 static void pci_config_alloc(PCIDevice *pci_dev)
564 {
565 int config_size = pci_config_size(pci_dev);
566
567 pci_dev->config = qemu_mallocz(config_size);
568 pci_dev->cmask = qemu_mallocz(config_size);
569 pci_dev->wmask = qemu_mallocz(config_size);
570 pci_dev->used = qemu_mallocz(config_size);
571 }
572
573 static void pci_config_free(PCIDevice *pci_dev)
574 {
575 qemu_free(pci_dev->config);
576 qemu_free(pci_dev->cmask);
577 qemu_free(pci_dev->wmask);
578 qemu_free(pci_dev->used);
579 }
580
581 /* -1 for devfn means auto assign */
582 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
583 const char *name, int devfn,
584 PCIConfigReadFunc *config_read,
585 PCIConfigWriteFunc *config_write,
586 uint8_t header_type)
587 {
588 if (devfn < 0) {
589 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
590 devfn += 8) {
591 if (!bus->devices[devfn])
592 goto found;
593 }
594 error_report("PCI: no devfn available for %s, all in use", name);
595 return NULL;
596 found: ;
597 } else if (bus->devices[devfn]) {
598 error_report("PCI: devfn %d not available for %s, in use by %s",
599 devfn, name, bus->devices[devfn]->name);
600 return NULL;
601 }
602 pci_dev->bus = bus;
603 pci_dev->devfn = devfn;
604 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
605 pci_dev->irq_state = 0;
606 pci_config_alloc(pci_dev);
607
608 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
609 if (header_type == PCI_HEADER_TYPE_NORMAL) {
610 pci_set_default_subsystem_id(pci_dev);
611 }
612 pci_init_cmask(pci_dev);
613 pci_init_wmask(pci_dev);
614 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
615 pci_init_wmask_bridge(pci_dev);
616 }
617
618 if (!config_read)
619 config_read = pci_default_read_config;
620 if (!config_write)
621 config_write = pci_default_write_config;
622 pci_dev->config_read = config_read;
623 pci_dev->config_write = config_write;
624 bus->devices[devfn] = pci_dev;
625 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
626 pci_dev->version_id = 2; /* Current pci device vmstate version */
627 return pci_dev;
628 }
629
630 static void do_pci_unregister_device(PCIDevice *pci_dev)
631 {
632 qemu_free_irqs(pci_dev->irq);
633 pci_dev->bus->devices[pci_dev->devfn] = NULL;
634 pci_config_free(pci_dev);
635 }
636
637 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
638 int instance_size, int devfn,
639 PCIConfigReadFunc *config_read,
640 PCIConfigWriteFunc *config_write)
641 {
642 PCIDevice *pci_dev;
643
644 pci_dev = qemu_mallocz(instance_size);
645 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
646 config_read, config_write,
647 PCI_HEADER_TYPE_NORMAL);
648 if (pci_dev == NULL) {
649 hw_error("PCI: can't register device\n");
650 }
651 return pci_dev;
652 }
653
654 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
655 target_phys_addr_t addr)
656 {
657 return addr + bus->mem_base;
658 }
659
660 static void pci_unregister_io_regions(PCIDevice *pci_dev)
661 {
662 PCIIORegion *r;
663 int i;
664
665 for(i = 0; i < PCI_NUM_REGIONS; i++) {
666 r = &pci_dev->io_regions[i];
667 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
668 continue;
669 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
670 isa_unassign_ioport(r->addr, r->filtered_size);
671 } else {
672 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
673 r->addr),
674 r->filtered_size,
675 IO_MEM_UNASSIGNED);
676 }
677 }
678 }
679
680 static int pci_unregister_device(DeviceState *dev)
681 {
682 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
683 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
684 int ret = 0;
685
686 if (info->exit)
687 ret = info->exit(pci_dev);
688 if (ret)
689 return ret;
690
691 pci_unregister_io_regions(pci_dev);
692 do_pci_unregister_device(pci_dev);
693 return 0;
694 }
695
696 void pci_register_bar(PCIDevice *pci_dev, int region_num,
697 pcibus_t size, int type,
698 PCIMapIORegionFunc *map_func)
699 {
700 PCIIORegion *r;
701 uint32_t addr;
702 pcibus_t wmask;
703
704 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
705 return;
706
707 if (size & (size-1)) {
708 fprintf(stderr, "ERROR: PCI region size must be pow2 "
709 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
710 exit(1);
711 }
712
713 r = &pci_dev->io_regions[region_num];
714 r->addr = PCI_BAR_UNMAPPED;
715 r->size = size;
716 r->filtered_size = size;
717 r->type = type;
718 r->map_func = map_func;
719
720 wmask = ~(size - 1);
721 addr = pci_bar(pci_dev, region_num);
722 if (region_num == PCI_ROM_SLOT) {
723 /* ROM enable bit is writeable */
724 wmask |= PCI_ROM_ADDRESS_ENABLE;
725 }
726 pci_set_long(pci_dev->config + addr, type);
727 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
728 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
729 pci_set_quad(pci_dev->wmask + addr, wmask);
730 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
731 } else {
732 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
733 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
734 }
735 }
736
737 static uint32_t pci_config_get_io_base(PCIDevice *d,
738 uint32_t base, uint32_t base_upper16)
739 {
740 uint32_t val;
741
742 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
743 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
744 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
745 }
746 return val;
747 }
748
749 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
750 {
751 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
752 << 16;
753 }
754
755 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
756 uint32_t base, uint32_t upper)
757 {
758 pcibus_t tmp;
759 pcibus_t val;
760
761 tmp = (pcibus_t)pci_get_word(d->config + base);
762 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
763 if (tmp & PCI_PREF_RANGE_TYPE_64) {
764 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
765 }
766 return val;
767 }
768
769 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
770 {
771 pcibus_t base;
772 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
773 base = pci_config_get_io_base(bridge,
774 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
775 } else {
776 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
777 base = pci_config_get_pref_base(
778 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
779 } else {
780 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
781 }
782 }
783
784 return base;
785 }
786
787 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
788 {
789 pcibus_t limit;
790 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
791 limit = pci_config_get_io_base(bridge,
792 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
793 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
794 } else {
795 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
796 limit = pci_config_get_pref_base(
797 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
798 } else {
799 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
800 }
801 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
802 }
803 return limit;
804 }
805
806 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
807 uint8_t type)
808 {
809 pcibus_t base = *addr;
810 pcibus_t limit = *addr + *size - 1;
811 PCIDevice *br;
812
813 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
814 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
815
816 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
817 if (!(cmd & PCI_COMMAND_IO)) {
818 goto no_map;
819 }
820 } else {
821 if (!(cmd & PCI_COMMAND_MEMORY)) {
822 goto no_map;
823 }
824 }
825
826 base = MAX(base, pci_bridge_get_base(br, type));
827 limit = MIN(limit, pci_bridge_get_limit(br, type));
828 }
829
830 if (base > limit) {
831 goto no_map;
832 }
833 *addr = base;
834 *size = limit - base + 1;
835 return;
836 no_map:
837 *addr = PCI_BAR_UNMAPPED;
838 *size = 0;
839 }
840
841 static pcibus_t pci_bar_address(PCIDevice *d,
842 int reg, uint8_t type, pcibus_t size)
843 {
844 pcibus_t new_addr, last_addr;
845 int bar = pci_bar(d, reg);
846 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
847
848 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
849 if (!(cmd & PCI_COMMAND_IO)) {
850 return PCI_BAR_UNMAPPED;
851 }
852 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
853 last_addr = new_addr + size - 1;
854 /* NOTE: we have only 64K ioports on PC */
855 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
856 return PCI_BAR_UNMAPPED;
857 }
858 return new_addr;
859 }
860
861 if (!(cmd & PCI_COMMAND_MEMORY)) {
862 return PCI_BAR_UNMAPPED;
863 }
864 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
865 new_addr = pci_get_quad(d->config + bar);
866 } else {
867 new_addr = pci_get_long(d->config + bar);
868 }
869 /* the ROM slot has a specific enable bit */
870 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
871 return PCI_BAR_UNMAPPED;
872 }
873 new_addr &= ~(size - 1);
874 last_addr = new_addr + size - 1;
875 /* NOTE: we do not support wrapping */
876 /* XXX: as we cannot support really dynamic
877 mappings, we handle specific values as invalid
878 mappings. */
879 if (last_addr <= new_addr || new_addr == 0 ||
880 last_addr == PCI_BAR_UNMAPPED) {
881 return PCI_BAR_UNMAPPED;
882 }
883
884 /* Now pcibus_t is 64bit.
885 * Check if 32 bit BAR wraps around explicitly.
886 * Without this, PC ide doesn't work well.
887 * TODO: remove this work around.
888 */
889 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
890 return PCI_BAR_UNMAPPED;
891 }
892
893 /*
894 * OS is allowed to set BAR beyond its addressable
895 * bits. For example, 32 bit OS can set 64bit bar
896 * to >4G. Check it. TODO: we might need to support
897 * it in the future for e.g. PAE.
898 */
899 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
900 return PCI_BAR_UNMAPPED;
901 }
902
903 return new_addr;
904 }
905
906 static void pci_update_mappings(PCIDevice *d)
907 {
908 PCIIORegion *r;
909 int i;
910 pcibus_t new_addr, filtered_size;
911
912 for(i = 0; i < PCI_NUM_REGIONS; i++) {
913 r = &d->io_regions[i];
914
915 /* this region isn't registered */
916 if (!r->size)
917 continue;
918
919 new_addr = pci_bar_address(d, i, r->type, r->size);
920
921 /* bridge filtering */
922 filtered_size = r->size;
923 if (new_addr != PCI_BAR_UNMAPPED) {
924 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
925 }
926
927 /* This bar isn't changed */
928 if (new_addr == r->addr && filtered_size == r->filtered_size)
929 continue;
930
931 /* now do the real mapping */
932 if (r->addr != PCI_BAR_UNMAPPED) {
933 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
934 int class;
935 /* NOTE: specific hack for IDE in PC case:
936 only one byte must be mapped. */
937 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
938 if (class == 0x0101 && r->size == 4) {
939 isa_unassign_ioport(r->addr + 2, 1);
940 } else {
941 isa_unassign_ioport(r->addr, r->filtered_size);
942 }
943 } else {
944 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
945 r->filtered_size,
946 IO_MEM_UNASSIGNED);
947 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
948 }
949 }
950 r->addr = new_addr;
951 r->filtered_size = filtered_size;
952 if (r->addr != PCI_BAR_UNMAPPED) {
953 /*
954 * TODO: currently almost all the map funcions assumes
955 * filtered_size == size and addr & ~(size - 1) == addr.
956 * However with bridge filtering, they aren't always true.
957 * Teach them such cases, such that filtered_size < size and
958 * addr & (size - 1) != 0.
959 */
960 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
961 r->map_func(d, i, r->addr, r->filtered_size, r->type);
962 } else {
963 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
964 r->filtered_size, r->type);
965 }
966 }
967 }
968 }
969
970 static inline int pci_irq_disabled(PCIDevice *d)
971 {
972 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
973 }
974
975 /* Called after interrupt disabled field update in config space,
976 * assert/deassert interrupts if necessary.
977 * Gets original interrupt disable bit value (before update). */
978 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
979 {
980 int i, disabled = pci_irq_disabled(d);
981 if (disabled == was_irq_disabled)
982 return;
983 for (i = 0; i < PCI_NUM_PINS; ++i) {
984 int state = pci_irq_state(d, i);
985 pci_change_irq_level(d, i, disabled ? -state : state);
986 }
987 }
988
989 uint32_t pci_default_read_config(PCIDevice *d,
990 uint32_t address, int len)
991 {
992 uint32_t val = 0;
993 assert(len == 1 || len == 2 || len == 4);
994 len = MIN(len, pci_config_size(d) - address);
995 memcpy(&val, d->config + address, len);
996 return le32_to_cpu(val);
997 }
998
999 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1000 {
1001 int i, was_irq_disabled = pci_irq_disabled(d);
1002 uint32_t config_size = pci_config_size(d);
1003
1004 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1005 uint8_t wmask = d->wmask[addr + i];
1006 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1007 }
1008 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1009 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1010 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1011 range_covers_byte(addr, l, PCI_COMMAND))
1012 pci_update_mappings(d);
1013
1014 if (range_covers_byte(addr, l, PCI_COMMAND))
1015 pci_update_irq_disabled(d, was_irq_disabled);
1016 }
1017
1018 /***********************************************************/
1019 /* generic PCI irq support */
1020
1021 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1022 static void pci_set_irq(void *opaque, int irq_num, int level)
1023 {
1024 PCIDevice *pci_dev = opaque;
1025 int change;
1026
1027 change = level - pci_irq_state(pci_dev, irq_num);
1028 if (!change)
1029 return;
1030
1031 pci_set_irq_state(pci_dev, irq_num, level);
1032 pci_update_irq_status(pci_dev);
1033 if (pci_irq_disabled(pci_dev))
1034 return;
1035 pci_change_irq_level(pci_dev, irq_num, change);
1036 }
1037
1038 /***********************************************************/
1039 /* monitor info on PCI */
1040
1041 typedef struct {
1042 uint16_t class;
1043 const char *desc;
1044 } pci_class_desc;
1045
1046 static const pci_class_desc pci_class_descriptions[] =
1047 {
1048 { 0x0100, "SCSI controller"},
1049 { 0x0101, "IDE controller"},
1050 { 0x0102, "Floppy controller"},
1051 { 0x0103, "IPI controller"},
1052 { 0x0104, "RAID controller"},
1053 { 0x0106, "SATA controller"},
1054 { 0x0107, "SAS controller"},
1055 { 0x0180, "Storage controller"},
1056 { 0x0200, "Ethernet controller"},
1057 { 0x0201, "Token Ring controller"},
1058 { 0x0202, "FDDI controller"},
1059 { 0x0203, "ATM controller"},
1060 { 0x0280, "Network controller"},
1061 { 0x0300, "VGA controller"},
1062 { 0x0301, "XGA controller"},
1063 { 0x0302, "3D controller"},
1064 { 0x0380, "Display controller"},
1065 { 0x0400, "Video controller"},
1066 { 0x0401, "Audio controller"},
1067 { 0x0402, "Phone"},
1068 { 0x0480, "Multimedia controller"},
1069 { 0x0500, "RAM controller"},
1070 { 0x0501, "Flash controller"},
1071 { 0x0580, "Memory controller"},
1072 { 0x0600, "Host bridge"},
1073 { 0x0601, "ISA bridge"},
1074 { 0x0602, "EISA bridge"},
1075 { 0x0603, "MC bridge"},
1076 { 0x0604, "PCI bridge"},
1077 { 0x0605, "PCMCIA bridge"},
1078 { 0x0606, "NUBUS bridge"},
1079 { 0x0607, "CARDBUS bridge"},
1080 { 0x0608, "RACEWAY bridge"},
1081 { 0x0680, "Bridge"},
1082 { 0x0c03, "USB controller"},
1083 { 0, NULL}
1084 };
1085
1086 static void pci_for_each_device_under_bus(PCIBus *bus,
1087 void (*fn)(PCIBus *b, PCIDevice *d))
1088 {
1089 PCIDevice *d;
1090 int devfn;
1091
1092 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1093 d = bus->devices[devfn];
1094 if (d) {
1095 fn(bus, d);
1096 }
1097 }
1098 }
1099
1100 void pci_for_each_device(PCIBus *bus, int bus_num,
1101 void (*fn)(PCIBus *b, PCIDevice *d))
1102 {
1103 bus = pci_find_bus(bus, bus_num);
1104
1105 if (bus) {
1106 pci_for_each_device_under_bus(bus, fn);
1107 }
1108 }
1109
1110 static void pci_device_print(Monitor *mon, QDict *device)
1111 {
1112 QDict *qdict;
1113 QListEntry *entry;
1114 uint64_t addr, size;
1115
1116 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1117 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1118 qdict_get_int(device, "slot"),
1119 qdict_get_int(device, "function"));
1120 monitor_printf(mon, " ");
1121
1122 qdict = qdict_get_qdict(device, "class_info");
1123 if (qdict_haskey(qdict, "desc")) {
1124 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1125 } else {
1126 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1127 }
1128
1129 qdict = qdict_get_qdict(device, "id");
1130 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1131 qdict_get_int(qdict, "device"),
1132 qdict_get_int(qdict, "vendor"));
1133
1134 if (qdict_haskey(device, "irq")) {
1135 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1136 qdict_get_int(device, "irq"));
1137 }
1138
1139 if (qdict_haskey(device, "pci_bridge")) {
1140 QDict *info;
1141
1142 qdict = qdict_get_qdict(device, "pci_bridge");
1143
1144 info = qdict_get_qdict(qdict, "bus");
1145 monitor_printf(mon, " BUS %" PRId64 ".\n",
1146 qdict_get_int(info, "number"));
1147 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1148 qdict_get_int(info, "secondary"));
1149 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1150 qdict_get_int(info, "subordinate"));
1151
1152 info = qdict_get_qdict(qdict, "io_range");
1153 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1154 qdict_get_int(info, "base"),
1155 qdict_get_int(info, "limit"));
1156
1157 info = qdict_get_qdict(qdict, "memory_range");
1158 monitor_printf(mon,
1159 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1160 qdict_get_int(info, "base"),
1161 qdict_get_int(info, "limit"));
1162
1163 info = qdict_get_qdict(qdict, "prefetchable_range");
1164 monitor_printf(mon, " prefetchable memory range "
1165 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1166 qdict_get_int(info, "base"),
1167 qdict_get_int(info, "limit"));
1168 }
1169
1170 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1171 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1172 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1173
1174 addr = qdict_get_int(qdict, "address");
1175 size = qdict_get_int(qdict, "size");
1176
1177 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1178 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1179 " [0x%04"FMT_PCIBUS"].\n",
1180 addr, addr + size - 1);
1181 } else {
1182 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1183 " [0x%08"FMT_PCIBUS"].\n",
1184 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1185 qdict_get_bool(qdict, "prefetch") ?
1186 " prefetchable" : "", addr, addr + size - 1);
1187 }
1188 }
1189
1190 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1191
1192 if (qdict_haskey(device, "pci_bridge")) {
1193 qdict = qdict_get_qdict(device, "pci_bridge");
1194 if (qdict_haskey(qdict, "devices")) {
1195 QListEntry *dev;
1196 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1197 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1198 }
1199 }
1200 }
1201 }
1202
1203 void do_pci_info_print(Monitor *mon, const QObject *data)
1204 {
1205 QListEntry *bus, *dev;
1206
1207 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1208 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1209 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1210 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1211 }
1212 }
1213 }
1214
1215 static QObject *pci_get_dev_class(const PCIDevice *dev)
1216 {
1217 int class;
1218 const pci_class_desc *desc;
1219
1220 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1221 desc = pci_class_descriptions;
1222 while (desc->desc && class != desc->class)
1223 desc++;
1224
1225 if (desc->desc) {
1226 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1227 desc->desc, class);
1228 } else {
1229 return qobject_from_jsonf("{ 'class': %d }", class);
1230 }
1231 }
1232
1233 static QObject *pci_get_dev_id(const PCIDevice *dev)
1234 {
1235 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1236 pci_get_word(dev->config + PCI_VENDOR_ID),
1237 pci_get_word(dev->config + PCI_DEVICE_ID));
1238 }
1239
1240 static QObject *pci_get_regions_list(const PCIDevice *dev)
1241 {
1242 int i;
1243 QList *regions_list;
1244
1245 regions_list = qlist_new();
1246
1247 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1248 QObject *obj;
1249 const PCIIORegion *r = &dev->io_regions[i];
1250
1251 if (!r->size) {
1252 continue;
1253 }
1254
1255 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1256 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1257 "'address': %" PRId64 ", "
1258 "'size': %" PRId64 " }",
1259 i, r->addr, r->size);
1260 } else {
1261 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1262
1263 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1264 "'mem_type_64': %i, 'prefetch': %i, "
1265 "'address': %" PRId64 ", "
1266 "'size': %" PRId64 " }",
1267 i, mem_type_64,
1268 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1269 r->addr, r->size);
1270 }
1271
1272 qlist_append_obj(regions_list, obj);
1273 }
1274
1275 return QOBJECT(regions_list);
1276 }
1277
1278 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1279
1280 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1281 {
1282 uint8_t type;
1283 QObject *obj;
1284
1285 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1286 " 'qdev_id': %s }",
1287 bus_num,
1288 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1289 pci_get_dev_class(dev), pci_get_dev_id(dev),
1290 pci_get_regions_list(dev),
1291 dev->qdev.id ? dev->qdev.id : "");
1292
1293 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1294 QDict *qdict = qobject_to_qdict(obj);
1295 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1296 }
1297
1298 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1299 if (type == PCI_HEADER_TYPE_BRIDGE) {
1300 QDict *qdict;
1301 QObject *pci_bridge;
1302
1303 pci_bridge = qobject_from_jsonf("{ 'bus': "
1304 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1305 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1306 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1307 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1308 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1309 dev->config[PCI_SUBORDINATE_BUS],
1310 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1311 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1312 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1313 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1314 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1315 PCI_BASE_ADDRESS_MEM_PREFETCH),
1316 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1317 PCI_BASE_ADDRESS_MEM_PREFETCH));
1318
1319 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1320 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1321
1322 if (child_bus) {
1323 qdict = qobject_to_qdict(pci_bridge);
1324 qdict_put_obj(qdict, "devices",
1325 pci_get_devices_list(child_bus,
1326 dev->config[PCI_SECONDARY_BUS]));
1327 }
1328 }
1329 qdict = qobject_to_qdict(obj);
1330 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1331 }
1332
1333 return obj;
1334 }
1335
1336 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1337 {
1338 int devfn;
1339 PCIDevice *dev;
1340 QList *dev_list;
1341
1342 dev_list = qlist_new();
1343
1344 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1345 dev = bus->devices[devfn];
1346 if (dev) {
1347 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1348 }
1349 }
1350
1351 return QOBJECT(dev_list);
1352 }
1353
1354 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1355 {
1356 bus = pci_find_bus(bus, bus_num);
1357 if (bus) {
1358 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1359 bus_num, pci_get_devices_list(bus, bus_num));
1360 }
1361
1362 return NULL;
1363 }
1364
1365 /**
1366 * do_pci_info(): PCI buses and devices information
1367 *
1368 * The returned QObject is a QList of all buses. Each bus is
1369 * represented by a QDict, which has a key with a QList of all
1370 * PCI devices attached to it. Each device is represented by
1371 * a QDict.
1372 *
1373 * The bus QDict contains the following:
1374 *
1375 * - "bus": bus number
1376 * - "devices": a QList of QDicts, each QDict represents a PCI
1377 * device
1378 *
1379 * The PCI device QDict contains the following:
1380 *
1381 * - "bus": identical to the parent's bus number
1382 * - "slot": slot number
1383 * - "function": function number
1384 * - "class_info": a QDict containing:
1385 * - "desc": device class description (optional)
1386 * - "class": device class number
1387 * - "id": a QDict containing:
1388 * - "device": device ID
1389 * - "vendor": vendor ID
1390 * - "irq": device's IRQ if assigned (optional)
1391 * - "qdev_id": qdev id string
1392 * - "pci_bridge": It's a QDict, only present if this device is a
1393 * PCI bridge, contains:
1394 * - "bus": bus number
1395 * - "secondary": secondary bus number
1396 * - "subordinate": subordinate bus number
1397 * - "io_range": a QDict with memory range information
1398 * - "memory_range": a QDict with memory range information
1399 * - "prefetchable_range": a QDict with memory range information
1400 * - "devices": a QList of PCI devices if there's any attached (optional)
1401 * - "regions": a QList of QDicts, each QDict represents a
1402 * memory region of this device
1403 *
1404 * The memory range QDict contains the following:
1405 *
1406 * - "base": base memory address
1407 * - "limit": limit value
1408 *
1409 * The region QDict can be an I/O region or a memory region,
1410 * an I/O region QDict contains the following:
1411 *
1412 * - "type": "io"
1413 * - "bar": BAR number
1414 * - "address": memory address
1415 * - "size": memory size
1416 *
1417 * A memory region QDict contains the following:
1418 *
1419 * - "type": "memory"
1420 * - "bar": BAR number
1421 * - "address": memory address
1422 * - "size": memory size
1423 * - "mem_type_64": true or false
1424 * - "prefetch": true or false
1425 */
1426 void do_pci_info(Monitor *mon, QObject **ret_data)
1427 {
1428 QList *bus_list;
1429 struct PCIHostBus *host;
1430
1431 bus_list = qlist_new();
1432
1433 QLIST_FOREACH(host, &host_buses, next) {
1434 QObject *obj = pci_get_bus_dict(host->bus, 0);
1435 if (obj) {
1436 qlist_append_obj(bus_list, obj);
1437 }
1438 }
1439
1440 *ret_data = QOBJECT(bus_list);
1441 }
1442
1443 static const char * const pci_nic_models[] = {
1444 "ne2k_pci",
1445 "i82551",
1446 "i82557b",
1447 "i82559er",
1448 "rtl8139",
1449 "e1000",
1450 "pcnet",
1451 "virtio",
1452 NULL
1453 };
1454
1455 static const char * const pci_nic_names[] = {
1456 "ne2k_pci",
1457 "i82551",
1458 "i82557b",
1459 "i82559er",
1460 "rtl8139",
1461 "e1000",
1462 "pcnet",
1463 "virtio-net-pci",
1464 NULL
1465 };
1466
1467 /* Initialize a PCI NIC. */
1468 /* FIXME callers should check for failure, but don't */
1469 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1470 const char *default_devaddr)
1471 {
1472 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1473 PCIBus *bus;
1474 int devfn;
1475 PCIDevice *pci_dev;
1476 DeviceState *dev;
1477 int i;
1478
1479 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1480 if (i < 0)
1481 return NULL;
1482
1483 bus = pci_get_bus_devfn(&devfn, devaddr);
1484 if (!bus) {
1485 error_report("Invalid PCI device address %s for device %s",
1486 devaddr, pci_nic_names[i]);
1487 return NULL;
1488 }
1489
1490 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1491 dev = &pci_dev->qdev;
1492 if (nd->name)
1493 dev->id = qemu_strdup(nd->name);
1494 qdev_set_nic_properties(dev, nd);
1495 if (qdev_init(dev) < 0)
1496 return NULL;
1497 return pci_dev;
1498 }
1499
1500 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1501 const char *default_devaddr)
1502 {
1503 PCIDevice *res;
1504
1505 if (qemu_show_nic_models(nd->model, pci_nic_models))
1506 exit(0);
1507
1508 res = pci_nic_init(nd, default_model, default_devaddr);
1509 if (!res)
1510 exit(1);
1511 return res;
1512 }
1513
1514 typedef struct {
1515 PCIDevice dev;
1516 PCIBus bus;
1517 uint32_t vid;
1518 uint32_t did;
1519 } PCIBridge;
1520
1521
1522 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1523 {
1524 pci_update_mappings(d);
1525 }
1526
1527 static void pci_bridge_update_mappings(PCIBus *b)
1528 {
1529 PCIBus *child;
1530
1531 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1532
1533 QLIST_FOREACH(child, &b->child, sibling) {
1534 pci_bridge_update_mappings(child);
1535 }
1536 }
1537
1538 static void pci_bridge_write_config(PCIDevice *d,
1539 uint32_t address, uint32_t val, int len)
1540 {
1541 pci_default_write_config(d, address, val, len);
1542
1543 if (/* io base/limit */
1544 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1545
1546 /* memory base/limit, prefetchable base/limit and
1547 io base/limit upper 16 */
1548 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1549 pci_bridge_update_mappings(d->bus);
1550 }
1551 }
1552
1553 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1554 {
1555 PCIBus *sec;
1556
1557 if (!bus) {
1558 return NULL;
1559 }
1560
1561 if (pci_bus_num(bus) == bus_num) {
1562 return bus;
1563 }
1564
1565 /* try child bus */
1566 if (!bus->parent_dev /* host pci bridge */ ||
1567 (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1568 bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1569 for (; bus; bus = sec) {
1570 QLIST_FOREACH(sec, &bus->child, sibling) {
1571 assert(sec->parent_dev);
1572 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1573 return sec;
1574 }
1575 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1576 bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1577 break;
1578 }
1579 }
1580 }
1581 }
1582
1583 return NULL;
1584 }
1585
1586 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1587 {
1588 bus = pci_find_bus(bus, bus_num);
1589
1590 if (!bus)
1591 return NULL;
1592
1593 return bus->devices[PCI_DEVFN(slot, function)];
1594 }
1595
1596 static int pci_bridge_initfn(PCIDevice *dev)
1597 {
1598 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1599
1600 pci_config_set_vendor_id(s->dev.config, s->vid);
1601 pci_config_set_device_id(s->dev.config, s->did);
1602
1603 pci_set_word(dev->config + PCI_STATUS,
1604 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1605 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1606 dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1607 pci_set_word(dev->config + PCI_SEC_STATUS,
1608 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1609 return 0;
1610 }
1611
1612 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1613 {
1614 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1615 PCIBus *bus = &s->bus;
1616 pci_unregister_secondary_bus(bus);
1617 return 0;
1618 }
1619
1620 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1621 pci_map_irq_fn map_irq, const char *name)
1622 {
1623 PCIDevice *dev;
1624 PCIBridge *s;
1625
1626 dev = pci_create(bus, devfn, "pci-bridge");
1627 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1628 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1629 qdev_init_nofail(&dev->qdev);
1630
1631 s = DO_UPCAST(PCIBridge, dev, dev);
1632 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1633 return &s->bus;
1634 }
1635
1636 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1637 {
1638 return bus->parent_dev;
1639 }
1640
1641 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1642 {
1643 PCIDevice *pci_dev = (PCIDevice *)qdev;
1644 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1645 PCIBus *bus;
1646 int devfn, rc;
1647
1648 /* initialize cap_present for pci_is_express() and pci_config_size() */
1649 if (info->is_express) {
1650 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1651 }
1652
1653 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1654 devfn = pci_dev->devfn;
1655 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1656 info->config_read, info->config_write,
1657 info->header_type);
1658 if (pci_dev == NULL)
1659 return -1;
1660 rc = info->init(pci_dev);
1661 if (rc != 0) {
1662 do_pci_unregister_device(pci_dev);
1663 return rc;
1664 }
1665
1666 /* rom loading */
1667 if (pci_dev->romfile == NULL && info->romfile != NULL)
1668 pci_dev->romfile = qemu_strdup(info->romfile);
1669 pci_add_option_rom(pci_dev);
1670
1671 if (qdev->hotplugged)
1672 bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1673 return 0;
1674 }
1675
1676 static int pci_unplug_device(DeviceState *qdev)
1677 {
1678 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1679
1680 dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1681 return 0;
1682 }
1683
1684 void pci_qdev_register(PCIDeviceInfo *info)
1685 {
1686 info->qdev.init = pci_qdev_init;
1687 info->qdev.unplug = pci_unplug_device;
1688 info->qdev.exit = pci_unregister_device;
1689 info->qdev.bus_info = &pci_bus_info;
1690 qdev_register(&info->qdev);
1691 }
1692
1693 void pci_qdev_register_many(PCIDeviceInfo *info)
1694 {
1695 while (info->qdev.name) {
1696 pci_qdev_register(info);
1697 info++;
1698 }
1699 }
1700
1701 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1702 {
1703 DeviceState *dev;
1704
1705 dev = qdev_create(&bus->qbus, name);
1706 qdev_prop_set_uint32(dev, "addr", devfn);
1707 return DO_UPCAST(PCIDevice, qdev, dev);
1708 }
1709
1710 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1711 {
1712 PCIDevice *dev = pci_create(bus, devfn, name);
1713 qdev_init_nofail(&dev->qdev);
1714 return dev;
1715 }
1716
1717 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1718 {
1719 int config_size = pci_config_size(pdev);
1720 int offset = PCI_CONFIG_HEADER_SIZE;
1721 int i;
1722 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1723 if (pdev->used[i])
1724 offset = i + 1;
1725 else if (i - offset + 1 == size)
1726 return offset;
1727 return 0;
1728 }
1729
1730 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1731 uint8_t *prev_p)
1732 {
1733 uint8_t next, prev;
1734
1735 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1736 return 0;
1737
1738 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1739 prev = next + PCI_CAP_LIST_NEXT)
1740 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1741 break;
1742
1743 if (prev_p)
1744 *prev_p = prev;
1745 return next;
1746 }
1747
1748 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1749 {
1750 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1751 }
1752
1753 /* Add an option rom for the device */
1754 static int pci_add_option_rom(PCIDevice *pdev)
1755 {
1756 int size;
1757 char *path;
1758 void *ptr;
1759
1760 if (!pdev->romfile)
1761 return 0;
1762 if (strlen(pdev->romfile) == 0)
1763 return 0;
1764
1765 if (!pdev->rom_bar) {
1766 /*
1767 * Load rom via fw_cfg instead of creating a rom bar,
1768 * for 0.11 compatibility.
1769 */
1770 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1771 if (class == 0x0300) {
1772 rom_add_vga(pdev->romfile);
1773 } else {
1774 rom_add_option(pdev->romfile);
1775 }
1776 return 0;
1777 }
1778
1779 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1780 if (path == NULL) {
1781 path = qemu_strdup(pdev->romfile);
1782 }
1783
1784 size = get_image_size(path);
1785 if (size < 0) {
1786 error_report("%s: failed to find romfile \"%s\"",
1787 __FUNCTION__, pdev->romfile);
1788 return -1;
1789 }
1790 if (size & (size - 1)) {
1791 size = 1 << qemu_fls(size);
1792 }
1793
1794 pdev->rom_offset = qemu_ram_alloc(size);
1795
1796 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1797 load_image(path, ptr);
1798 qemu_free(path);
1799
1800 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1801 0, pci_map_option_rom);
1802
1803 return 0;
1804 }
1805
1806 /* Reserve space and add capability to the linked list in pci config space */
1807 int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
1808 uint8_t offset, uint8_t size)
1809 {
1810 uint8_t *config = pdev->config + offset;
1811 config[PCI_CAP_LIST_ID] = cap_id;
1812 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1813 pdev->config[PCI_CAPABILITY_LIST] = offset;
1814 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1815 memset(pdev->used + offset, 0xFF, size);
1816 /* Make capability read-only by default */
1817 memset(pdev->wmask + offset, 0, size);
1818 /* Check capability by default */
1819 memset(pdev->cmask + offset, 0xFF, size);
1820 return offset;
1821 }
1822
1823 /* Find and reserve space and add capability to the linked list
1824 * in pci config space */
1825 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1826 {
1827 uint8_t offset = pci_find_space(pdev, size);
1828 if (!offset) {
1829 return -ENOSPC;
1830 }
1831 return pci_add_capability_at_offset(pdev, cap_id, offset, size);
1832 }
1833
1834 /* Unlink capability from the pci config space. */
1835 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1836 {
1837 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1838 if (!offset)
1839 return;
1840 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1841 /* Make capability writeable again */
1842 memset(pdev->wmask + offset, 0xff, size);
1843 /* Clear cmask as device-specific registers can't be checked */
1844 memset(pdev->cmask + offset, 0, size);
1845 memset(pdev->used + offset, 0, size);
1846
1847 if (!pdev->config[PCI_CAPABILITY_LIST])
1848 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1849 }
1850
1851 /* Reserve space for capability at a known offset (to call after load). */
1852 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1853 {
1854 memset(pdev->used + offset, 0xff, size);
1855 }
1856
1857 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1858 {
1859 return pci_find_capability_list(pdev, cap_id, NULL);
1860 }
1861
1862 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1863 {
1864 PCIDevice *d = (PCIDevice *)dev;
1865 const pci_class_desc *desc;
1866 char ctxt[64];
1867 PCIIORegion *r;
1868 int i, class;
1869
1870 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1871 desc = pci_class_descriptions;
1872 while (desc->desc && class != desc->class)
1873 desc++;
1874 if (desc->desc) {
1875 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1876 } else {
1877 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1878 }
1879
1880 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1881 "pci id %04x:%04x (sub %04x:%04x)\n",
1882 indent, "", ctxt,
1883 d->config[PCI_SECONDARY_BUS],
1884 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1885 pci_get_word(d->config + PCI_VENDOR_ID),
1886 pci_get_word(d->config + PCI_DEVICE_ID),
1887 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1888 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1889 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1890 r = &d->io_regions[i];
1891 if (!r->size)
1892 continue;
1893 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1894 " [0x%"FMT_PCIBUS"]\n",
1895 indent, "",
1896 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1897 r->addr, r->addr + r->size - 1);
1898 }
1899 }
1900
1901 static PCIDeviceInfo bridge_info = {
1902 .qdev.name = "pci-bridge",
1903 .qdev.size = sizeof(PCIBridge),
1904 .init = pci_bridge_initfn,
1905 .exit = pci_bridge_exitfn,
1906 .config_write = pci_bridge_write_config,
1907 .header_type = PCI_HEADER_TYPE_BRIDGE,
1908 .qdev.props = (Property[]) {
1909 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1910 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1911 DEFINE_PROP_END_OF_LIST(),
1912 }
1913 };
1914
1915 static void pci_register_devices(void)
1916 {
1917 pci_qdev_register(&bridge_info);
1918 }
1919
1920 device_init(pci_register_devices)
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