hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "pci.h"
  21 #include "qemu-timer.h"
  22 #include "sysemu.h"
  23 #include "i2c.h"
  24 #include "smbus.h"
  25
  26 //#define DEBUG
  27
  28 /* i82731AB (PIIX4) compatible power management function */
  29 #define PM_FREQ 3579545
  30
  31 #define ACPI_DBG_IO_ADDR  0xb044
  32
  33 typedef struct PIIX4PMState {
  34     PCIDevice dev;
  35     uint16_t pmsts;
  36     uint16_t pmen;
  37     uint16_t pmcntrl;
  38     uint8_t apmc;
  39     uint8_t apms;
  40     QEMUTimer *tmr_timer;
  41     int64_t tmr_overflow_time;
  42     i2c_bus *smbus;
  43     uint8_t smb_stat;
  44     uint8_t smb_ctl;
  45     uint8_t smb_cmd;
  46     uint8_t smb_addr;
  47     uint8_t smb_data0;
  48     uint8_t smb_data1;
  49     uint8_t smb_data[32];
  50     uint8_t smb_index;
  51     qemu_irq irq;
  52     qemu_irq cmos_s3;
  53     qemu_irq smi_irq;
  54     int kvm_enabled;
  55 } PIIX4PMState;
  56
  57 #define RSM_STS (1 << 15)
  58 #define PWRBTN_STS (1 << 8)
  59 #define RTC_EN (1 << 10)
  60 #define PWRBTN_EN (1 << 8)
  61 #define GBL_EN (1 << 5)
  62 #define TMROF_EN (1 << 0)
  63
  64 #define SCI_EN (1 << 0)
  65
  66 #define SUS_EN (1 << 13)
  67
  68 #define ACPI_ENABLE 0xf1
  69 #define ACPI_DISABLE 0xf0
  70
  71 #define SMBHSTSTS 0x00
  72 #define SMBHSTCNT 0x02
  73 #define SMBHSTCMD 0x03
  74 #define SMBHSTADD 0x04
  75 #define SMBHSTDAT0 0x05
  76 #define SMBHSTDAT1 0x06
  77 #define SMBBLKDAT 0x07
  78
  79 static PIIX4PMState *pm_state;
  80
  81 static uint32_t get_pmtmr(PIIX4PMState *s)
  82 {
  83     uint32_t d;
  84     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  85     return d & 0xffffff;
  86 }
  87
  88 static int get_pmsts(PIIX4PMState *s)
  89 {
  90     int64_t d;
  91     int pmsts;
  92     pmsts = s->pmsts;
  93     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  94     if (d >= s->tmr_overflow_time)
  95         s->pmsts |= TMROF_EN;
  96     return s->pmsts;
  97 }
  98
  99 static void pm_update_sci(PIIX4PMState *s)
 100 {
 101     int sci_level, pmsts;
 102     int64_t expire_time;
 103
 104     pmsts = get_pmsts(s);
 105     sci_level = (((pmsts & s->pmen) &
 106                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 107     qemu_set_irq(s->irq, sci_level);
 108     /* schedule a timer interruption if needed */
 109     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 110         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ);
 111         qemu_mod_timer(s->tmr_timer, expire_time);
 112     } else {
 113         qemu_del_timer(s->tmr_timer);
 114     }
 115 }
 116
 117 static void pm_tmr_timer(void *opaque)
 118 {
 119     PIIX4PMState *s = opaque;
 120     pm_update_sci(s);
 121 }
 122
 123 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 124 {
 125     PIIX4PMState *s = opaque;
 126     addr &= 0x3f;
 127     switch(addr) {
 128     case 0x00:
 129         {
 130             int64_t d;
 131             int pmsts;
 132             pmsts = get_pmsts(s);
 133             if (pmsts & val & TMROF_EN) {
 134                 /* if TMRSTS is reset, then compute the new overflow time */
 135                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ,
 136                              get_ticks_per_sec());
 137                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 138             }
 139             s->pmsts &= ~val;
 140             pm_update_sci(s);
 141         }
 142         break;
 143     case 0x02:
 144         s->pmen = val;
 145         pm_update_sci(s);
 146         break;
 147     case 0x04:
 148         {
 149             int sus_typ;
 150             s->pmcntrl = val & ~(SUS_EN);
 151             if (val & SUS_EN) {
 152                 /* change suspend type */
 153                 sus_typ = (val >> 10) & 7;
 154                 switch(sus_typ) {
 155                 case 0: /* soft power off */
 156                     qemu_system_shutdown_request();
 157                     break;
 158                 case 1:
 159                     /* RSM_STS should be set on resume. Pretend that resume
 160                        was caused by power button */
 161                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 162                     qemu_system_reset_request();
 163                     if (s->cmos_s3) {
 164                         qemu_irq_raise(s->cmos_s3);
 165                     }
 166                 default:
 167                     break;
 168                 }
 169             }
 170         }
 171         break;
 172     default:
 173         break;
 174     }
 175 #ifdef DEBUG
 176     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 177 #endif
 178 }
 179
 180 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 181 {
 182     PIIX4PMState *s = opaque;
 183     uint32_t val;
 184
 185     addr &= 0x3f;
 186     switch(addr) {
 187     case 0x00:
 188         val = get_pmsts(s);
 189         break;
 190     case 0x02:
 191         val = s->pmen;
 192         break;
 193     case 0x04:
 194         val = s->pmcntrl;
 195         break;
 196     default:
 197         val = 0;
 198         break;
 199     }
 200 #ifdef DEBUG
 201     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 202 #endif
 203     return val;
 204 }
 205
 206 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 207 {
 208     //    PIIX4PMState *s = opaque;
 209     addr &= 0x3f;
 210 #ifdef DEBUG
 211     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 212 #endif
 213 }
 214
 215 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 216 {
 217     PIIX4PMState *s = opaque;
 218     uint32_t val;
 219
 220     addr &= 0x3f;
 221     switch(addr) {
 222     case 0x08:
 223         val = get_pmtmr(s);
 224         break;
 225     default:
 226         val = 0;
 227         break;
 228     }
 229 #ifdef DEBUG
 230     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 231 #endif
 232     return val;
 233 }
 234
 235 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 236 {
 237     PIIX4PMState *s = opaque;
 238     addr &= 1;
 239 #ifdef DEBUG
 240     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 241 #endif
 242     if (addr == 0) {
 243         s->apmc = val;
 244
 245         /* ACPI specs 3.0, 4.7.2.5 */
 246         if (val == ACPI_ENABLE) {
 247             s->pmcntrl |= SCI_EN;
 248         } else if (val == ACPI_DISABLE) {
 249             s->pmcntrl &= ~SCI_EN;
 250         }
 251
 252         if (s->dev.config[0x5b] & (1 << 1)) {
 253             if (s->smi_irq) {
 254                 qemu_irq_raise(s->smi_irq);
 255             }
 256         }
 257     } else {
 258         s->apms = val;
 259     }
 260 }
 261
 262 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 263 {
 264     PIIX4PMState *s = opaque;
 265     uint32_t val;
 266
 267     addr &= 1;
 268     if (addr == 0) {
 269         val = s->apmc;
 270     } else {
 271         val = s->apms;
 272     }
 273 #ifdef DEBUG
 274     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 275 #endif
 276     return val;
 277 }
 278
 279 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 280 {
 281 #if defined(DEBUG)
 282     printf("ACPI: DBG: 0x%08x\n", val);
 283 #endif
 284 }
 285
 286 static void smb_transaction(PIIX4PMState *s)
 287 {
 288     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 289     uint8_t read = s->smb_addr & 0x01;
 290     uint8_t cmd = s->smb_cmd;
 291     uint8_t addr = s->smb_addr >> 1;
 292     i2c_bus *bus = s->smbus;
 293
 294 #ifdef DEBUG
 295     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 296 #endif
 297     switch(prot) {
 298     case 0x0:
 299         smbus_quick_command(bus, addr, read);
 300         break;
 301     case 0x1:
 302         if (read) {
 303             s->smb_data0 = smbus_receive_byte(bus, addr);
 304         } else {
 305             smbus_send_byte(bus, addr, cmd);
 306         }
 307         break;
 308     case 0x2:
 309         if (read) {
 310             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 311         } else {
 312             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 313         }
 314         break;
 315     case 0x3:
 316         if (read) {
 317             uint16_t val;
 318             val = smbus_read_word(bus, addr, cmd);
 319             s->smb_data0 = val;
 320             s->smb_data1 = val >> 8;
 321         } else {
 322             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 323         }
 324         break;
 325     case 0x5:
 326         if (read) {
 327             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 328         } else {
 329             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 330         }
 331         break;
 332     default:
 333         goto error;
 334     }
 335     return;
 336
 337   error:
 338     s->smb_stat |= 0x04;
 339 }
 340
 341 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 342 {
 343     PIIX4PMState *s = opaque;
 344     addr &= 0x3f;
 345 #ifdef DEBUG
 346     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 347 #endif
 348     switch(addr) {
 349     case SMBHSTSTS:
 350         s->smb_stat = 0;
 351         s->smb_index = 0;
 352         break;
 353     case SMBHSTCNT:
 354         s->smb_ctl = val;
 355         if (val & 0x40)
 356             smb_transaction(s);
 357         break;
 358     case SMBHSTCMD:
 359         s->smb_cmd = val;
 360         break;
 361     case SMBHSTADD:
 362         s->smb_addr = val;
 363         break;
 364     case SMBHSTDAT0:
 365         s->smb_data0 = val;
 366         break;
 367     case SMBHSTDAT1:
 368         s->smb_data1 = val;
 369         break;
 370     case SMBBLKDAT:
 371         s->smb_data[s->smb_index++] = val;
 372         if (s->smb_index > 31)
 373             s->smb_index = 0;
 374         break;
 375     default:
 376         break;
 377     }
 378 }
 379
 380 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 381 {
 382     PIIX4PMState *s = opaque;
 383     uint32_t val;
 384
 385     addr &= 0x3f;
 386     switch(addr) {
 387     case SMBHSTSTS:
 388         val = s->smb_stat;
 389         break;
 390     case SMBHSTCNT:
 391         s->smb_index = 0;
 392         val = s->smb_ctl & 0x1f;
 393         break;
 394     case SMBHSTCMD:
 395         val = s->smb_cmd;
 396         break;
 397     case SMBHSTADD:
 398         val = s->smb_addr;
 399         break;
 400     case SMBHSTDAT0:
 401         val = s->smb_data0;
 402         break;
 403     case SMBHSTDAT1:
 404         val = s->smb_data1;
 405         break;
 406     case SMBBLKDAT:
 407         val = s->smb_data[s->smb_index++];
 408         if (s->smb_index > 31)
 409             s->smb_index = 0;
 410         break;
 411     default:
 412         val = 0;
 413         break;
 414     }
 415 #ifdef DEBUG
 416     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 417 #endif
 418     return val;
 419 }
 420
 421 static void pm_io_space_update(PIIX4PMState *s)
 422 {
 423     uint32_t pm_io_base;
 424
 425     if (s->dev.config[0x80] & 1) {
 426         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 427         pm_io_base &= 0xffc0;
 428
 429         /* XXX: need to improve memory and ioport allocation */
 430 #if defined(DEBUG)
 431         printf("PM: mapping to 0x%x\n", pm_io_base);
 432 #endif
 433         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 434         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 435         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 436         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 437     }
 438 }
 439
 440 static void pm_write_config(PCIDevice *d,
 441                             uint32_t address, uint32_t val, int len)
 442 {
 443     pci_default_write_config(d, address, val, len);
 444     if (range_covers_byte(address, len, 0x80))
 445         pm_io_space_update((PIIX4PMState *)d);
 446 }
 447
 448 static int vmstate_acpi_post_load(void *opaque, int version_id)
 449 {
 450     PIIX4PMState *s = opaque;
 451
 452     pm_io_space_update(s);
 453     return 0;
 454 }
 455
 456 static const VMStateDescription vmstate_acpi = {
 457     .name = "piix4_pm",
 458     .version_id = 1,
 459     .minimum_version_id = 1,
 460     .minimum_version_id_old = 1,
 461     .post_load = vmstate_acpi_post_load,
 462     .fields      = (VMStateField []) {
 463         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 464         VMSTATE_UINT16(pmsts, PIIX4PMState),
 465         VMSTATE_UINT16(pmen, PIIX4PMState),
 466         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 467         VMSTATE_UINT8(apmc, PIIX4PMState),
 468         VMSTATE_UINT8(apms, PIIX4PMState),
 469         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 470         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 471         VMSTATE_END_OF_LIST()
 472     }
 473 };
 474
 475 static void piix4_reset(void *opaque)
 476 {
 477     PIIX4PMState *s = opaque;
 478     uint8_t *pci_conf = s->dev.config;
 479
 480     pci_conf[0x58] = 0;
 481     pci_conf[0x59] = 0;
 482     pci_conf[0x5a] = 0;
 483     pci_conf[0x5b] = 0;
 484
 485     if (s->kvm_enabled) {
 486         /* Mark SMM as already inited (until KVM supports SMM). */
 487         pci_conf[0x5B] = 0x02;
 488     }
 489 }
 490
 491 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 492 {
 493     PIIX4PMState *s = opaque;
 494
 495     if (!s) {
 496         qemu_system_shutdown_request();
 497     } else if (s->pmen & PWRBTN_EN) {
 498         s->pmsts |= PWRBTN_EN;
 499         pm_update_sci(s);
 500     }
 501 }
 502
 503 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 504                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 505                        int kvm_enabled)
 506 {
 507     PIIX4PMState *s;
 508     uint8_t *pci_conf;
 509
 510     s = (PIIX4PMState *)pci_register_device(bus,
 511                                          "PM", sizeof(PIIX4PMState),
 512                                          devfn, NULL, pm_write_config);
 513     pm_state = s;
 514     pci_conf = s->dev.config;
 515     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 516     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 517     pci_conf[0x06] = 0x80;
 518     pci_conf[0x07] = 0x02;
 519     pci_conf[0x08] = 0x03; // revision number
 520     pci_conf[0x09] = 0x00;
 521     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 522     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 523     pci_conf[0x3d] = 0x01; // interrupt pin 1
 524
 525     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 526
 527     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 528     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 529
 530     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 531
 532     s->kvm_enabled = kvm_enabled;
 533     if (s->kvm_enabled) {
 534         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 535          * support SMM mode. */
 536         pci_conf[0x5B] = 0x02;
 537     }
 538
 539     /* XXX: which specification is used ? The i82731AB has different
 540        mappings */
 541     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 542     pci_conf[0x63] = 0x60;
 543     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 544         (serial_hds[1] != NULL ? 0x90 : 0);
 545
 546     pci_conf[0x90] = smb_io_base | 1;
 547     pci_conf[0x91] = smb_io_base >> 8;
 548     pci_conf[0xd2] = 0x09;
 549     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 550     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 551
 552     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 553
 554     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 555
 556     vmstate_register(0, &vmstate_acpi, s);
 557
 558     s->smbus = i2c_init_bus(NULL, "i2c");
 559     s->irq = sci_irq;
 560     s->cmos_s3 = cmos_s3;
 561     s->smi_irq = smi_irq;
 562     qemu_register_reset(piix4_reset, s);
 563
 564     return s->smbus;
 565 }
 566
 567 #define GPE_BASE 0xafe0
 568 #define PCI_BASE 0xae00
 569 #define PCI_EJ_BASE 0xae08
 570
 571 struct gpe_regs {
 572     uint16_t sts; /* status */
 573     uint16_t en;  /* enabled */
 574 };
 575
 576 struct pci_status {
 577     uint32_t up;
 578     uint32_t down;
 579 };
 580
 581 static struct gpe_regs gpe;
 582 static struct pci_status pci0_status;
 583
 584 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 585 {
 586     if (addr & 1)
 587         return (val >> 8) & 0xff;
 588     return val & 0xff;
 589 }
 590
 591 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 592 {
 593     uint32_t val = 0;
 594     struct gpe_regs *g = opaque;
 595     switch (addr) {
 596         case GPE_BASE:
 597         case GPE_BASE + 1:
 598             val = gpe_read_val(g->sts, addr);
 599             break;
 600         case GPE_BASE + 2:
 601         case GPE_BASE + 3:
 602             val = gpe_read_val(g->en, addr);
 603             break;
 604         default:
 605             break;
 606     }
 607
 608 #if defined(DEBUG)
 609     printf("gpe read %x == %x\n", addr, val);
 610 #endif
 611     return val;
 612 }
 613
 614 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 615 {
 616     if (addr & 1)
 617         *cur = (*cur & 0xff) | (val << 8);
 618     else
 619         *cur = (*cur & 0xff00) | (val & 0xff);
 620 }
 621
 622 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 623 {
 624     uint16_t x1, x0 = val & 0xff;
 625     int shift = (addr & 1) ? 8 : 0;
 626
 627     x1 = (*cur >> shift) & 0xff;
 628
 629     x1 = x1 & ~x0;
 630
 631     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 632 }
 633
 634 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 635 {
 636     struct gpe_regs *g = opaque;
 637     switch (addr) {
 638         case GPE_BASE:
 639         case GPE_BASE + 1:
 640             gpe_reset_val(&g->sts, addr, val);
 641             break;
 642         case GPE_BASE + 2:
 643         case GPE_BASE + 3:
 644             gpe_write_val(&g->en, addr, val);
 645             break;
 646         default:
 647             break;
 648    }
 649
 650 #if defined(DEBUG)
 651     printf("gpe write %x <== %d\n", addr, val);
 652 #endif
 653 }
 654
 655 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 656 {
 657     uint32_t val = 0;
 658     struct pci_status *g = opaque;
 659     switch (addr) {
 660         case PCI_BASE:
 661             val = g->up;
 662             break;
 663         case PCI_BASE + 4:
 664             val = g->down;
 665             break;
 666         default:
 667             break;
 668     }
 669
 670 #if defined(DEBUG)
 671     printf("pcihotplug read %x == %x\n", addr, val);
 672 #endif
 673     return val;
 674 }
 675
 676 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 677 {
 678     struct pci_status *g = opaque;
 679     switch (addr) {
 680         case PCI_BASE:
 681             g->up = val;
 682             break;
 683         case PCI_BASE + 4:
 684             g->down = val;
 685             break;
 686    }
 687
 688 #if defined(DEBUG)
 689     printf("pcihotplug write %x <== %d\n", addr, val);
 690 #endif
 691 }
 692
 693 static uint32_t pciej_read(void *opaque, uint32_t addr)
 694 {
 695 #if defined(DEBUG)
 696     printf("pciej read %x\n", addr);
 697 #endif
 698     return 0;
 699 }
 700
 701 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 702 {
 703     BusState *bus = opaque;
 704     DeviceState *qdev, *next;
 705     PCIDevice *dev;
 706     int slot = ffs(val) - 1;
 707
 708     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 709         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 710         if (PCI_SLOT(dev->devfn) == slot) {
 711             qdev_free(qdev);
 712         }
 713     }
 714
 715
 716 #if defined(DEBUG)
 717     printf("pciej write %x <== %d\n", addr, val);
 718 #endif
 719 }
 720
 721 static int piix4_device_hotplug(PCIDevice *dev, int state);
 722
 723 void piix4_acpi_system_hot_add_init(PCIBus *bus)
 724 {
 725     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 726     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 727
 728     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 729     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 730
 731     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 732     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 733
 734     pci_bus_hotplug(bus, piix4_device_hotplug);
 735 }
 736
 737 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 738 {
 739     g->sts |= 2;
 740     p->up |= (1 << slot);
 741 }
 742
 743 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 744 {
 745     g->sts |= 2;
 746     p->down |= (1 << slot);
 747 }
 748
 749 static int piix4_device_hotplug(PCIDevice *dev, int state)
 750 {
 751     int slot = PCI_SLOT(dev->devfn);
 752
 753     pci0_status.up = 0;
 754     pci0_status.down = 0;
 755     if (state)
 756         enable_device(&pci0_status, &gpe, slot);
 757     else
 758         disable_device(&pci0_status, &gpe, slot);
 759     if (gpe.en & 2) {
 760         qemu_set_irq(pm_state->irq, 1);
 761         qemu_set_irq(pm_state->irq, 0);
 762     }
 763     return 0;
 764 }
 765
 766 struct acpi_table_header
 767 {
 768     char signature [4];    /* ACPI signature (4 ASCII characters) */
 769     uint32_t length;          /* Length of table, in bytes, including header */
 770     uint8_t revision;         /* ACPI Specification minor version # */
 771     uint8_t checksum;         /* To make sum of entire table == 0 */
 772     char oem_id [6];       /* OEM identification */
 773     char oem_table_id [8]; /* OEM table identification */
 774     uint32_t oem_revision;    /* OEM revision number */
 775     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 776     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 777 } __attribute__((packed));
 778
 779 char *acpi_tables;
 780 size_t acpi_tables_len;
 781
 782 static int acpi_checksum(const uint8_t *data, int len)
 783 {
 784     int sum, i;
 785     sum = 0;
 786     for(i = 0; i < len; i++)
 787         sum += data[i];
 788     return (-sum) & 0xff;
 789 }
 790
 791 int acpi_table_add(const char *t)
 792 {
 793     static const char *dfl_id = "QEMUQEMU";
 794     char buf[1024], *p, *f;
 795     struct acpi_table_header acpi_hdr;
 796     unsigned long val;
 797     size_t off;
 798
 799     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 800
 801     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 802         strncpy(acpi_hdr.signature, buf, 4);
 803     } else {
 804         strncpy(acpi_hdr.signature, dfl_id, 4);
 805     }
 806     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 807         val = strtoul(buf, &p, 10);
 808         if (val > 255 || *p != '\0')
 809             goto out;
 810     } else {
 811         val = 1;
 812     }
 813     acpi_hdr.revision = (int8_t)val;
 814
 815     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 816         strncpy(acpi_hdr.oem_id, buf, 6);
 817     } else {
 818         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 819     }
 820
 821     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 822         strncpy(acpi_hdr.oem_table_id, buf, 8);
 823     } else {
 824         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 825     }
 826
 827     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 828         val = strtol(buf, &p, 10);
 829         if(*p != '\0')
 830             goto out;
 831     } else {
 832         val = 1;
 833     }
 834     acpi_hdr.oem_revision = cpu_to_le32(val);
 835
 836     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 837         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 838     } else {
 839         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 840     }
 841
 842     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 843         val = strtol(buf, &p, 10);
 844         if(*p != '\0')
 845             goto out;
 846     } else {
 847         val = 1;
 848     }
 849     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 850
 851     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 852          buf[0] = '\0';
 853     }
 854
 855     acpi_hdr.length = sizeof(acpi_hdr);
 856
 857     f = buf;
 858     while (buf[0]) {
 859         struct stat s;
 860         char *n = strchr(f, ':');
 861         if (n)
 862             *n = '\0';
 863         if(stat(f, &s) < 0) {
 864             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 865             goto out;
 866         }
 867         acpi_hdr.length += s.st_size;
 868         if (!n)
 869             break;
 870         *n = ':';
 871         f = n + 1;
 872     }
 873
 874     if (!acpi_tables) {
 875         acpi_tables_len = sizeof(uint16_t);
 876         acpi_tables = qemu_mallocz(acpi_tables_len);
 877     }
 878     p = acpi_tables + acpi_tables_len;
 879     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 880     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 881
 882     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 883     *(uint16_t*)p = acpi_hdr.length;
 884     p += sizeof(uint16_t);
 885     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 886     off = sizeof(acpi_hdr);
 887
 888     f = buf;
 889     while (buf[0]) {
 890         struct stat s;
 891         int fd;
 892         char *n = strchr(f, ':');
 893         if (n)
 894             *n = '\0';
 895         fd = open(f, O_RDONLY);
 896
 897         if(fd < 0)
 898             goto out;
 899         if(fstat(fd, &s) < 0) {
 900             close(fd);
 901             goto out;
 902         }
 903
 904         do {
 905             int r;
 906             r = read(fd, p + off, s.st_size);
 907             if (r > 0) {
 908                 off += r;
 909                 s.st_size -= r;
 910             } else if ((r < 0 && errno != EINTR) || r == 0) {
 911                 close(fd);
 912                 goto out;
 913             }
 914         } while(s.st_size);
 915
 916         close(fd);
 917         if (!n)
 918             break;
 919         f = n + 1;
 920     }
 921
 922     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
 923     /* increase number of tables */
 924     (*(uint16_t*)acpi_tables) =
 925             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
 926     return 0;
 927 out:
 928     if (acpi_tables) {
 929         qemu_free(acpi_tables);
 930         acpi_tables = NULL;
 931     }
 932     return -1;
 933 }