hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "fdc.h"
  27 #include "pci.h"
  28 #include "vmware_vga.h"
  29 #include "usb-uhci.h"
  30 #include "usb-ohci.h"
  31 #include "prep_pci.h"
  32 #include "apb_pci.h"
  33 #include "block.h"
  34 #include "sysemu.h"
  35 #include "audio/audio.h"
  36 #include "net.h"
  37 #include "smbus.h"
  38 #include "boards.h"
  39 #include "monitor.h"
  40 #include "fw_cfg.h"
  41 #include "hpet_emul.h"
  42 #include "watchdog.h"
  43 #include "smbios.h"
  44 #include "ide.h"
  45 #include "loader.h"
  46 #include "elf.h"
  47
  48 /* output Bochs bios info messages */
  49 //#define DEBUG_BIOS
  50
  51 /* Show multiboot debug output */
  52 //#define DEBUG_MULTIBOOT
  53
  54 #define BIOS_FILENAME "bios.bin"
  55
  56 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  57
  58 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  59 #define ACPI_DATA_SIZE       0x10000
  60 #define BIOS_CFG_IOPORT 0x510
  61 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  62 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  63 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  64
  65 #define MAX_IDE_BUS 2
  66
  67 static fdctrl_t *floppy_controller;
  68 static RTCState *rtc_state;
  69 static PITState *pit;
  70 static PCII440FXState *i440fx_state;
  71
  72 typedef struct isa_irq_state {
  73     qemu_irq *i8259;
  74     qemu_irq *ioapic;
  75 } IsaIrqState;
  76
  77 static void isa_irq_handler(void *opaque, int n, int level)
  78 {
  79     IsaIrqState *isa = (IsaIrqState *)opaque;
  80
  81     if (n < 16) {
  82         qemu_set_irq(isa->i8259[n], level);
  83     }
  84     if (isa->ioapic)
  85         qemu_set_irq(isa->ioapic[n], level);
  86 };
  87
  88 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  89 {
  90 }
  91
  92 /* MSDOS compatibility mode FPU exception support */
  93 static qemu_irq ferr_irq;
  94 /* XXX: add IGNNE support */
  95 void cpu_set_ferr(CPUX86State *s)
  96 {
  97     qemu_irq_raise(ferr_irq);
  98 }
  99
 100 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 101 {
 102     qemu_irq_lower(ferr_irq);
 103 }
 104
 105 /* TSC handling */
 106 uint64_t cpu_get_tsc(CPUX86State *env)
 107 {
 108     return cpu_get_ticks();
 109 }
 110
 111 /* SMM support */
 112 void cpu_smm_update(CPUState *env)
 113 {
 114     if (i440fx_state && env == first_cpu)
 115         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 116 }
 117
 118
 119 /* IRQ handling */
 120 int cpu_get_pic_interrupt(CPUState *env)
 121 {
 122     int intno;
 123
 124     intno = apic_get_interrupt(env);
 125     if (intno >= 0) {
 126         /* set irq request if a PIC irq is still pending */
 127         /* XXX: improve that */
 128         pic_update_irq(isa_pic);
 129         return intno;
 130     }
 131     /* read the irq from the PIC */
 132     if (!apic_accept_pic_intr(env))
 133         return -1;
 134
 135     intno = pic_read_irq(isa_pic);
 136     return intno;
 137 }
 138
 139 static void pic_irq_request(void *opaque, int irq, int level)
 140 {
 141     CPUState *env = first_cpu;
 142
 143     if (env->apic_state) {
 144         while (env) {
 145             if (apic_accept_pic_intr(env))
 146                 apic_deliver_pic_intr(env, level);
 147             env = env->next_cpu;
 148         }
 149     } else {
 150         if (level)
 151             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 152         else
 153             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 154     }
 155 }
 156
 157 /* PC cmos mappings */
 158
 159 #define REG_EQUIPMENT_BYTE          0x14
 160
 161 static int cmos_get_fd_drive_type(int fd0)
 162 {
 163     int val;
 164
 165     switch (fd0) {
 166     case 0:
 167         /* 1.44 Mb 3"5 drive */
 168         val = 4;
 169         break;
 170     case 1:
 171         /* 2.88 Mb 3"5 drive */
 172         val = 5;
 173         break;
 174     case 2:
 175         /* 1.2 Mb 5"5 drive */
 176         val = 2;
 177         break;
 178     default:
 179         val = 0;
 180         break;
 181     }
 182     return val;
 183 }
 184
 185 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 186 {
 187     RTCState *s = rtc_state;
 188     int cylinders, heads, sectors;
 189     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 190     rtc_set_memory(s, type_ofs, 47);
 191     rtc_set_memory(s, info_ofs, cylinders);
 192     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 193     rtc_set_memory(s, info_ofs + 2, heads);
 194     rtc_set_memory(s, info_ofs + 3, 0xff);
 195     rtc_set_memory(s, info_ofs + 4, 0xff);
 196     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 197     rtc_set_memory(s, info_ofs + 6, cylinders);
 198     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 199     rtc_set_memory(s, info_ofs + 8, sectors);
 200 }
 201
 202 /* convert boot_device letter to something recognizable by the bios */
 203 static int boot_device2nibble(char boot_device)
 204 {
 205     switch(boot_device) {
 206     case 'a':
 207     case 'b':
 208         return 0x01; /* floppy boot */
 209     case 'c':
 210         return 0x02; /* hard drive boot */
 211     case 'd':
 212         return 0x03; /* CD-ROM boot */
 213     case 'n':
 214         return 0x04; /* Network boot */
 215     }
 216     return 0;
 217 }
 218
 219 /* copy/pasted from cmos_init, should be made a general function
 220  and used there as well */
 221 static int pc_boot_set(void *opaque, const char *boot_device)
 222 {
 223     Monitor *mon = cur_mon;
 224 #define PC_MAX_BOOT_DEVICES 3
 225     RTCState *s = (RTCState *)opaque;
 226     int nbds, bds[3] = { 0, };
 227     int i;
 228
 229     nbds = strlen(boot_device);
 230     if (nbds > PC_MAX_BOOT_DEVICES) {
 231         monitor_printf(mon, "Too many boot devices for PC\n");
 232         return(1);
 233     }
 234     for (i = 0; i < nbds; i++) {
 235         bds[i] = boot_device2nibble(boot_device[i]);
 236         if (bds[i] == 0) {
 237             monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
 238                            boot_device[i]);
 239             return(1);
 240         }
 241     }
 242     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 243     rtc_set_memory(s, 0x38, (bds[2] << 4));
 244     return(0);
 245 }
 246
 247 /* hd_table must contain 4 block drivers */
 248 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 249                       const char *boot_device, DriveInfo **hd_table)
 250 {
 251     RTCState *s = rtc_state;
 252     int nbds, bds[3] = { 0, };
 253     int val;
 254     int fd0, fd1, nb;
 255     int i;
 256
 257     /* various important CMOS locations needed by PC/Bochs bios */
 258
 259     /* memory size */
 260     val = 640; /* base memory in K */
 261     rtc_set_memory(s, 0x15, val);
 262     rtc_set_memory(s, 0x16, val >> 8);
 263
 264     val = (ram_size / 1024) - 1024;
 265     if (val > 65535)
 266         val = 65535;
 267     rtc_set_memory(s, 0x17, val);
 268     rtc_set_memory(s, 0x18, val >> 8);
 269     rtc_set_memory(s, 0x30, val);
 270     rtc_set_memory(s, 0x31, val >> 8);
 271
 272     if (above_4g_mem_size) {
 273         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 274         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 275         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 276     }
 277
 278     if (ram_size > (16 * 1024 * 1024))
 279         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 280     else
 281         val = 0;
 282     if (val > 65535)
 283         val = 65535;
 284     rtc_set_memory(s, 0x34, val);
 285     rtc_set_memory(s, 0x35, val >> 8);
 286
 287     /* set the number of CPU */
 288     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 289
 290     /* set boot devices, and disable floppy signature check if requested */
 291 #define PC_MAX_BOOT_DEVICES 3
 292     nbds = strlen(boot_device);
 293     if (nbds > PC_MAX_BOOT_DEVICES) {
 294         fprintf(stderr, "Too many boot devices for PC\n");
 295         exit(1);
 296     }
 297     for (i = 0; i < nbds; i++) {
 298         bds[i] = boot_device2nibble(boot_device[i]);
 299         if (bds[i] == 0) {
 300             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 301                     boot_device[i]);
 302             exit(1);
 303         }
 304     }
 305     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 306     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 307
 308     /* floppy type */
 309
 310     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 311     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 312
 313     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 314     rtc_set_memory(s, 0x10, val);
 315
 316     val = 0;
 317     nb = 0;
 318     if (fd0 < 3)
 319         nb++;
 320     if (fd1 < 3)
 321         nb++;
 322     switch (nb) {
 323     case 0:
 324         break;
 325     case 1:
 326         val |= 0x01; /* 1 drive, ready for boot */
 327         break;
 328     case 2:
 329         val |= 0x41; /* 2 drives, ready for boot */
 330         break;
 331     }
 332     val |= 0x02; /* FPU is there */
 333     val |= 0x04; /* PS/2 mouse installed */
 334     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 335
 336     /* hard drives */
 337
 338     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 339     if (hd_table[0])
 340         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
 341     if (hd_table[1])
 342         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
 343
 344     val = 0;
 345     for (i = 0; i < 4; i++) {
 346         if (hd_table[i]) {
 347             int cylinders, heads, sectors, translation;
 348             /* NOTE: bdrv_get_geometry_hint() returns the physical
 349                 geometry.  It is always such that: 1 <= sects <= 63, 1
 350                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 351                 geometry can be different if a translation is done. */
 352             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 353             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 354                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 355                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 356                     /* No translation. */
 357                     translation = 0;
 358                 } else {
 359                     /* LBA translation. */
 360                     translation = 1;
 361                 }
 362             } else {
 363                 translation--;
 364             }
 365             val |= translation << (i * 2);
 366         }
 367     }
 368     rtc_set_memory(s, 0x39, val);
 369 }
 370
 371 void ioport_set_a20(int enable)
 372 {
 373     /* XXX: send to all CPUs ? */
 374     cpu_x86_set_a20(first_cpu, enable);
 375 }
 376
 377 int ioport_get_a20(void)
 378 {
 379     return ((first_cpu->a20_mask >> 20) & 1);
 380 }
 381
 382 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 383 {
 384     ioport_set_a20((val >> 1) & 1);
 385     /* XXX: bit 0 is fast reset */
 386 }
 387
 388 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 389 {
 390     return ioport_get_a20() << 1;
 391 }
 392
 393 /***********************************************************/
 394 /* Bochs BIOS debug ports */
 395
 396 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 397 {
 398     static const char shutdown_str[8] = "Shutdown";
 399     static int shutdown_index = 0;
 400
 401     switch(addr) {
 402         /* Bochs BIOS messages */
 403     case 0x400:
 404     case 0x401:
 405         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 406         exit(1);
 407     case 0x402:
 408     case 0x403:
 409 #ifdef DEBUG_BIOS
 410         fprintf(stderr, "%c", val);
 411 #endif
 412         break;
 413     case 0x8900:
 414         /* same as Bochs power off */
 415         if (val == shutdown_str[shutdown_index]) {
 416             shutdown_index++;
 417             if (shutdown_index == 8) {
 418                 shutdown_index = 0;
 419                 qemu_system_shutdown_request();
 420             }
 421         } else {
 422             shutdown_index = 0;
 423         }
 424         break;
 425
 426         /* LGPL'ed VGA BIOS messages */
 427     case 0x501:
 428     case 0x502:
 429         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 430         exit(1);
 431     case 0x500:
 432     case 0x503:
 433 #ifdef DEBUG_BIOS
 434         fprintf(stderr, "%c", val);
 435 #endif
 436         break;
 437     }
 438 }
 439
 440 static void *bochs_bios_init(void)
 441 {
 442     void *fw_cfg;
 443     uint8_t *smbios_table;
 444     size_t smbios_len;
 445     uint64_t *numa_fw_cfg;
 446     int i, j;
 447
 448     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 449     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 450     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 451     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 452     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 453
 454     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 455     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 456     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 457     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 458
 459     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 460
 461     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 462     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 463     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 464                      acpi_tables_len);
 465     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 466
 467     smbios_table = smbios_get_table(&smbios_len);
 468     if (smbios_table)
 469         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 470                          smbios_table, smbios_len);
 471
 472     /* allocate memory for the NUMA channel: one (64bit) word for the number
 473      * of nodes, one word for each VCPU->node and one word for each node to
 474      * hold the amount of memory.
 475      */
 476     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 477     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 478     for (i = 0; i < smp_cpus; i++) {
 479         for (j = 0; j < nb_numa_nodes; j++) {
 480             if (node_cpumask[j] & (1 << i)) {
 481                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 482                 break;
 483             }
 484         }
 485     }
 486     for (i = 0; i < nb_numa_nodes; i++) {
 487         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 488     }
 489     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 490                      (1 + smp_cpus + nb_numa_nodes) * 8);
 491
 492     return fw_cfg;
 493 }
 494
 495 static long get_file_size(FILE *f)
 496 {
 497     long where, size;
 498
 499     /* XXX: on Unix systems, using fstat() probably makes more sense */
 500
 501     where = ftell(f);
 502     fseek(f, 0, SEEK_END);
 503     size = ftell(f);
 504     fseek(f, where, SEEK_SET);
 505
 506     return size;
 507 }
 508
 509 #define MULTIBOOT_STRUCT_ADDR 0x9000
 510
 511 #if MULTIBOOT_STRUCT_ADDR > 0xf0000
 512 #error multiboot struct needs to fit in 16 bit real mode
 513 #endif
 514
 515 static int load_multiboot(void *fw_cfg,
 516                           FILE *f,
 517                           const char *kernel_filename,
 518                           const char *initrd_filename,
 519                           const char *kernel_cmdline,
 520                           uint8_t *header)
 521 {
 522     int i, is_multiboot = 0;
 523     uint32_t flags = 0;
 524     uint32_t mh_entry_addr;
 525     uint32_t mh_load_addr;
 526     uint32_t mb_kernel_size;
 527     uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
 528     uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
 529     uint32_t mb_mod_end;
 530     uint8_t bootinfo[0x500];
 531     uint32_t cmdline = 0x200;
 532     uint8_t *mb_kernel_data;
 533     uint8_t *mb_bootinfo_data;
 534
 535     /* Ok, let's see if it is a multiboot image.
 536        The header is 12x32bit long, so the latest entry may be 8192 - 48. */
 537     for (i = 0; i < (8192 - 48); i += 4) {
 538         if (ldl_p(header+i) == 0x1BADB002) {
 539             uint32_t checksum = ldl_p(header+i+8);
 540             flags = ldl_p(header+i+4);
 541             checksum += flags;
 542             checksum += (uint32_t)0x1BADB002;
 543             if (!checksum) {
 544                 is_multiboot = 1;
 545                 break;
 546             }
 547         }
 548     }
 549
 550     if (!is_multiboot)
 551         return 0; /* no multiboot */
 552
 553 #ifdef DEBUG_MULTIBOOT
 554     fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
 555 #endif
 556     memset(bootinfo, 0, sizeof(bootinfo));
 557
 558     if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
 559         fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
 560     }
 561     if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
 562         uint64_t elf_entry;
 563         int kernel_size;
 564         fclose(f);
 565         kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL,
 566                                0, ELF_MACHINE, 0);
 567         if (kernel_size < 0) {
 568             fprintf(stderr, "Error while loading elf kernel\n");
 569             exit(1);
 570         }
 571         mh_load_addr = mh_entry_addr = elf_entry;
 572         mb_kernel_size = kernel_size;
 573
 574         mb_kernel_data = qemu_malloc(mb_kernel_size);
 575         if (rom_copy(mb_kernel_data, elf_entry, kernel_size) != kernel_size) {
 576             fprintf(stderr, "Error while fetching elf kernel from rom\n");
 577             exit(1);
 578         }
 579
 580 #ifdef DEBUG_MULTIBOOT
 581         fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
 582                 mb_kernel_size, (size_t)mh_entry_addr);
 583 #endif
 584     } else {
 585         /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
 586         uint32_t mh_header_addr = ldl_p(header+i+12);
 587         mh_load_addr = ldl_p(header+i+16);
 588 #ifdef DEBUG_MULTIBOOT
 589         uint32_t mh_load_end_addr = ldl_p(header+i+20);
 590         uint32_t mh_bss_end_addr = ldl_p(header+i+24);
 591 #endif
 592         uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
 593
 594         mh_entry_addr = ldl_p(header+i+28);
 595         mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
 596
 597         /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
 598         uint32_t mh_mode_type = ldl_p(header+i+32);
 599         uint32_t mh_width = ldl_p(header+i+36);
 600         uint32_t mh_height = ldl_p(header+i+40);
 601         uint32_t mh_depth = ldl_p(header+i+44); */
 602
 603 #ifdef DEBUG_MULTIBOOT
 604         fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
 605         fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
 606         fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
 607         fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
 608         fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
 609                 mb_kernel_size, mh_load_addr);
 610 #endif
 611
 612         mb_kernel_data = qemu_malloc(mb_kernel_size);
 613         fseek(f, mb_kernel_text_offset, SEEK_SET);
 614         fread(mb_kernel_data, 1, mb_kernel_size, f);
 615         fclose(f);
 616     }
 617
 618     /* blob size is only the kernel for now */
 619     mb_mod_end = mh_load_addr + mb_kernel_size;
 620
 621     /* load modules */
 622     stl_p(bootinfo + 20, 0x0); /* mods_count */
 623     if (initrd_filename) {
 624         uint32_t mb_mod_info = 0x100;
 625         uint32_t mb_mod_cmdline = 0x300;
 626         uint32_t mb_mod_start = mh_load_addr;
 627         uint32_t mb_mod_length = mb_kernel_size;
 628         char *next_initrd;
 629         char *next_space;
 630         int mb_mod_count = 0;
 631
 632         do {
 633             if (mb_mod_info + 16 > mb_mod_cmdline) {
 634                 printf("WARNING: Too many modules loaded, aborting.\n");
 635                 break;
 636             }
 637             next_initrd = strchr(initrd_filename, ',');
 638             if (next_initrd)
 639                 *next_initrd = '\0';
 640             /* if a space comes after the module filename, treat everything
 641                after that as parameters */
 642             pstrcpy((char*)bootinfo + mb_mod_cmdline,
 643                     sizeof(bootinfo) - mb_mod_cmdline,
 644                     initrd_filename);
 645             stl_p(bootinfo + mb_mod_info + 8, mb_bootinfo + mb_mod_cmdline); /* string */
 646             mb_mod_cmdline += strlen(initrd_filename) + 1;
 647             if (mb_mod_cmdline > sizeof(bootinfo)) {
 648                 mb_mod_cmdline = sizeof(bootinfo);
 649                 printf("WARNING: Too many module cmdlines loaded, aborting.\n");
 650                 break;
 651             }
 652             if ((next_space = strchr(initrd_filename, ' ')))
 653                 *next_space = '\0';
 654 #ifdef DEBUG_MULTIBOOT
 655             printf("multiboot loading module: %s\n", initrd_filename);
 656 #endif
 657             mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
 658                          & (TARGET_PAGE_MASK);
 659             mb_mod_length = get_image_size(initrd_filename);
 660             if (mb_mod_length < 0) {
 661                 fprintf(stderr, "failed to get %s image size\n", initrd_filename);
 662                 exit(1);
 663             }
 664             mb_mod_end = mb_mod_start + mb_mod_length;
 665             mb_mod_count++;
 666
 667             /* append module data at the end of last module */
 668             mb_kernel_data = qemu_realloc(mb_kernel_data,
 669                                           mh_load_addr - mb_mod_end);
 670             load_image(initrd_filename,
 671                        mb_kernel_data + mb_mod_start - mh_load_addr);
 672
 673             stl_p(bootinfo + mb_mod_info + 0, mb_mod_start);
 674             stl_p(bootinfo + mb_mod_info + 4, mb_mod_start + mb_mod_length);
 675             stl_p(bootinfo + mb_mod_info + 12, 0x0); /* reserved */
 676 #ifdef DEBUG_MULTIBOOT
 677             printf("mod_start: %#x\nmod_end:   %#x\n", mb_mod_start,
 678                    mb_mod_start + mb_mod_length);
 679 #endif
 680             initrd_filename = next_initrd+1;
 681             mb_mod_info += 16;
 682         } while (next_initrd);
 683         stl_p(bootinfo + 20, mb_mod_count); /* mods_count */
 684         stl_p(bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
 685     }
 686
 687     /* Commandline support */
 688     stl_p(bootinfo + 16, mb_bootinfo + cmdline);
 689     snprintf((char*)bootinfo + cmdline, 0x100, "%s %s",
 690              kernel_filename, kernel_cmdline);
 691
 692     /* the kernel is where we want it to be now */
 693 #define MULTIBOOT_FLAGS_MEMORY (1 << 0)
 694 #define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
 695 #define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
 696 #define MULTIBOOT_FLAGS_MODULES (1 << 3)
 697 #define MULTIBOOT_FLAGS_MMAP (1 << 6)
 698     stl_p(bootinfo, MULTIBOOT_FLAGS_MEMORY
 699                   | MULTIBOOT_FLAGS_BOOT_DEVICE
 700                   | MULTIBOOT_FLAGS_CMDLINE
 701                   | MULTIBOOT_FLAGS_MODULES
 702                   | MULTIBOOT_FLAGS_MMAP);
 703     stl_p(bootinfo + 4, 640); /* mem_lower */
 704     stl_p(bootinfo + 8, ram_size / 1024); /* mem_upper */
 705     stl_p(bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
 706     stl_p(bootinfo + 48, mmap_addr); /* mmap_addr */
 707
 708 #ifdef DEBUG_MULTIBOOT
 709     fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
 710 #endif
 711
 712     /* save bootinfo off the stack */
 713     mb_bootinfo_data = qemu_malloc(sizeof(bootinfo));
 714     memcpy(mb_bootinfo_data, bootinfo, sizeof(bootinfo));
 715
 716     /* Pass variables to option rom */
 717     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, mh_entry_addr);
 718     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
 719     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, mb_mod_end - mh_load_addr);
 720     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, mb_kernel_data,
 721                      mb_mod_end - mh_load_addr);
 722
 723     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
 724     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, sizeof(bootinfo));
 725     fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, mb_bootinfo_data,
 726                      sizeof(bootinfo));
 727
 728     option_rom[nb_option_roms] = "multiboot.bin";
 729     nb_option_roms++;
 730
 731     return 1; /* yes, we are multiboot */
 732 }
 733
 734 static void load_linux(void *fw_cfg,
 735                        const char *kernel_filename,
 736                        const char *initrd_filename,
 737                        const char *kernel_cmdline,
 738                        target_phys_addr_t max_ram_size)
 739 {
 740     uint16_t protocol;
 741     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 742     uint32_t initrd_max;
 743     uint8_t header[8192], *setup, *kernel, *initrd_data;
 744     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 745     FILE *f;
 746     char *vmode;
 747
 748     /* Align to 16 bytes as a paranoia measure */
 749     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 750
 751     /* load the kernel header */
 752     f = fopen(kernel_filename, "rb");
 753     if (!f || !(kernel_size = get_file_size(f)) ||
 754         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 755         MIN(ARRAY_SIZE(header), kernel_size)) {
 756         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 757                 kernel_filename, strerror(errno));
 758         exit(1);
 759     }
 760
 761     /* kernel protocol version */
 762 #if 0
 763     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 764 #endif
 765     if (ldl_p(header+0x202) == 0x53726448)
 766         protocol = lduw_p(header+0x206);
 767     else {
 768         /* This looks like a multiboot kernel. If it is, let's stop
 769            treating it like a Linux kernel. */
 770         if (load_multiboot(fw_cfg, f, kernel_filename,
 771                            initrd_filename, kernel_cmdline, header))
 772             return;
 773         protocol = 0;
 774     }
 775
 776     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 777         /* Low kernel */
 778         real_addr    = 0x90000;
 779         cmdline_addr = 0x9a000 - cmdline_size;
 780         prot_addr    = 0x10000;
 781     } else if (protocol < 0x202) {
 782         /* High but ancient kernel */
 783         real_addr    = 0x90000;
 784         cmdline_addr = 0x9a000 - cmdline_size;
 785         prot_addr    = 0x100000;
 786     } else {
 787         /* High and recent kernel */
 788         real_addr    = 0x10000;
 789         cmdline_addr = 0x20000;
 790         prot_addr    = 0x100000;
 791     }
 792
 793 #if 0
 794     fprintf(stderr,
 795             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 796             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 797             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 798             real_addr,
 799             cmdline_addr,
 800             prot_addr);
 801 #endif
 802
 803     /* highest address for loading the initrd */
 804     if (protocol >= 0x203)
 805         initrd_max = ldl_p(header+0x22c);
 806     else
 807         initrd_max = 0x37ffffff;
 808
 809     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 810         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 811
 812     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 813     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 814     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 815                      (uint8_t*)strdup(kernel_cmdline),
 816                      strlen(kernel_cmdline)+1);
 817
 818     if (protocol >= 0x202) {
 819         stl_p(header+0x228, cmdline_addr);
 820     } else {
 821         stw_p(header+0x20, 0xA33F);
 822         stw_p(header+0x22, cmdline_addr-real_addr);
 823     }
 824
 825     /* handle vga= parameter */
 826     vmode = strstr(kernel_cmdline, "vga=");
 827     if (vmode) {
 828         unsigned int video_mode;
 829         /* skip "vga=" */
 830         vmode += 4;
 831         if (!strncmp(vmode, "normal", 6)) {
 832             video_mode = 0xffff;
 833         } else if (!strncmp(vmode, "ext", 3)) {
 834             video_mode = 0xfffe;
 835         } else if (!strncmp(vmode, "ask", 3)) {
 836             video_mode = 0xfffd;
 837         } else {
 838             video_mode = strtol(vmode, NULL, 0);
 839         }
 840         stw_p(header+0x1fa, video_mode);
 841     }
 842
 843     /* loader type */
 844     /* High nybble = B reserved for Qemu; low nybble is revision number.
 845        If this code is substantially changed, you may want to consider
 846        incrementing the revision. */
 847     if (protocol >= 0x200)
 848         header[0x210] = 0xB0;
 849
 850     /* heap */
 851     if (protocol >= 0x201) {
 852         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 853         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 854     }
 855
 856     /* load initrd */
 857     if (initrd_filename) {
 858         if (protocol < 0x200) {
 859             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 860             exit(1);
 861         }
 862
 863         initrd_size = get_image_size(initrd_filename);
 864         initrd_addr = (initrd_max-initrd_size) & ~4095;
 865
 866         initrd_data = qemu_malloc(initrd_size);
 867         load_image(initrd_filename, initrd_data);
 868
 869         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 870         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 871         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 872
 873         stl_p(header+0x218, initrd_addr);
 874         stl_p(header+0x21c, initrd_size);
 875     }
 876
 877     /* load kernel and setup */
 878     setup_size = header[0x1f1];
 879     if (setup_size == 0)
 880         setup_size = 4;
 881     setup_size = (setup_size+1)*512;
 882     kernel_size -= setup_size;
 883
 884     setup  = qemu_malloc(setup_size);
 885     kernel = qemu_malloc(kernel_size);
 886     fseek(f, 0, SEEK_SET);
 887     fread(setup, 1, setup_size, f);
 888     fread(kernel, 1, kernel_size, f);
 889     fclose(f);
 890     memcpy(setup, header, MIN(sizeof(header), setup_size));
 891
 892     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 893     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 894     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 895
 896     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 897     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 898     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 899
 900     option_rom[nb_option_roms] = "linuxboot.bin";
 901     nb_option_roms++;
 902 }
 903
 904 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 905 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 906 static const int ide_irq[2] = { 14, 15 };
 907
 908 #define NE2000_NB_MAX 6
 909
 910 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 911                                               0x280, 0x380 };
 912 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 913
 914 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 915 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 916
 917 #ifdef HAS_AUDIO
 918 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 919 {
 920     struct soundhw *c;
 921
 922     for (c = soundhw; c->name; ++c) {
 923         if (c->enabled) {
 924             if (c->isa) {
 925                 c->init.init_isa(pic);
 926             } else {
 927                 if (pci_bus) {
 928                     c->init.init_pci(pci_bus);
 929                 }
 930             }
 931         }
 932     }
 933 }
 934 #endif
 935
 936 static void pc_init_ne2k_isa(NICInfo *nd)
 937 {
 938     static int nb_ne2k = 0;
 939
 940     if (nb_ne2k == NE2000_NB_MAX)
 941         return;
 942     isa_ne2000_init(ne2000_io[nb_ne2k],
 943                     ne2000_irq[nb_ne2k], nd);
 944     nb_ne2k++;
 945 }
 946
 947 int cpu_is_bsp(CPUState *env)
 948 {
 949     return env->cpuid_apic_id == 0;
 950 }
 951
 952 static CPUState *pc_new_cpu(const char *cpu_model)
 953 {
 954     CPUState *env;
 955
 956     env = cpu_init(cpu_model);
 957     if (!env) {
 958         fprintf(stderr, "Unable to find x86 CPU definition\n");
 959         exit(1);
 960     }
 961     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 962         env->cpuid_apic_id = env->cpu_index;
 963         /* APIC reset callback resets cpu */
 964         apic_init(env);
 965     } else {
 966         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 967     }
 968     return env;
 969 }
 970
 971 /* PC hardware initialisation */
 972 static void pc_init1(ram_addr_t ram_size,
 973                      const char *boot_device,
 974                      const char *kernel_filename,
 975                      const char *kernel_cmdline,
 976                      const char *initrd_filename,
 977                      const char *cpu_model,
 978                      int pci_enabled)
 979 {
 980     char *filename;
 981     int ret, linux_boot, i;
 982     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 983     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 984     int bios_size, isa_bios_size;
 985     PCIBus *pci_bus;
 986     ISADevice *isa_dev;
 987     int piix3_devfn = -1;
 988     CPUState *env;
 989     qemu_irq *cpu_irq;
 990     qemu_irq *isa_irq;
 991     qemu_irq *i8259;
 992     IsaIrqState *isa_irq_state;
 993     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 994     DriveInfo *fd[MAX_FD];
 995     void *fw_cfg;
 996
 997     if (ram_size >= 0xe0000000 ) {
 998         above_4g_mem_size = ram_size - 0xe0000000;
 999         below_4g_mem_size = 0xe0000000;
1000     } else {
1001         below_4g_mem_size = ram_size;
1002     }
1003
1004     linux_boot = (kernel_filename != NULL);
1005
1006     /* init CPUs */
1007     if (cpu_model == NULL) {
1008 #ifdef TARGET_X86_64
1009         cpu_model = "qemu64";
1010 #else
1011         cpu_model = "qemu32";
1012 #endif
1013     }
1014
1015     for (i = 0; i < smp_cpus; i++) {
1016         env = pc_new_cpu(cpu_model);
1017     }
1018
1019     vmport_init();
1020
1021     /* allocate RAM */
1022     ram_addr = qemu_ram_alloc(0xa0000);
1023     cpu_register_physical_memory(0, 0xa0000, ram_addr);
1024
1025     /* Allocate, even though we won't register, so we don't break the
1026      * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1027      * and some bios areas, which will be registered later
1028      */
1029     ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1030     ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1031     cpu_register_physical_memory(0x100000,
1032                  below_4g_mem_size - 0x100000,
1033                  ram_addr);
1034
1035     /* above 4giga memory allocation */
1036     if (above_4g_mem_size > 0) {
1037 #if TARGET_PHYS_ADDR_BITS == 32
1038         hw_error("To much RAM for 32-bit physical address");
1039 #else
1040         ram_addr = qemu_ram_alloc(above_4g_mem_size);
1041         cpu_register_physical_memory(0x100000000ULL,
1042                                      above_4g_mem_size,
1043                                      ram_addr);
1044 #endif
1045     }
1046
1047
1048     /* BIOS load */
1049     if (bios_name == NULL)
1050         bios_name = BIOS_FILENAME;
1051     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1052     if (filename) {
1053         bios_size = get_image_size(filename);
1054     } else {
1055         bios_size = -1;
1056     }
1057     if (bios_size <= 0 ||
1058         (bios_size % 65536) != 0) {
1059         goto bios_error;
1060     }
1061     bios_offset = qemu_ram_alloc(bios_size);
1062     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
1063     if (ret != 0) {
1064     bios_error:
1065         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1066         exit(1);
1067     }
1068     if (filename) {
1069         qemu_free(filename);
1070     }
1071     /* map the last 128KB of the BIOS in ISA space */
1072     isa_bios_size = bios_size;
1073     if (isa_bios_size > (128 * 1024))
1074         isa_bios_size = 128 * 1024;
1075     cpu_register_physical_memory(0x100000 - isa_bios_size,
1076                                  isa_bios_size,
1077                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1078
1079
1080
1081     rom_enable_driver_roms = 1;
1082     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
1083     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
1084
1085     /* map all the bios at the top of memory */
1086     cpu_register_physical_memory((uint32_t)(-bios_size),
1087                                  bios_size, bios_offset | IO_MEM_ROM);
1088
1089     fw_cfg = bochs_bios_init();
1090
1091     if (linux_boot) {
1092         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1093     }
1094
1095     for (i = 0; i < nb_option_roms; i++) {
1096         rom_add_option(option_rom[i]);
1097     }
1098
1099     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1100     i8259 = i8259_init(cpu_irq[0]);
1101     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1102     isa_irq_state->i8259 = i8259;
1103     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
1104
1105     if (pci_enabled) {
1106         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
1107     } else {
1108         pci_bus = NULL;
1109         isa_bus_new(NULL);
1110     }
1111     isa_bus_irqs(isa_irq);
1112
1113     ferr_irq = isa_reserve_irq(13);
1114
1115     /* init basic PC hardware */
1116     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1117
1118     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1119
1120     if (cirrus_vga_enabled) {
1121         if (pci_enabled) {
1122             pci_cirrus_vga_init(pci_bus);
1123         } else {
1124             isa_cirrus_vga_init();
1125         }
1126     } else if (vmsvga_enabled) {
1127         if (pci_enabled)
1128             pci_vmsvga_init(pci_bus);
1129         else
1130             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1131     } else if (std_vga_enabled) {
1132         if (pci_enabled) {
1133             pci_vga_init(pci_bus, 0, 0);
1134         } else {
1135             isa_vga_init();
1136         }
1137     }
1138
1139     rtc_state = rtc_init(2000);
1140
1141     qemu_register_boot_set(pc_boot_set, rtc_state);
1142
1143     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1144     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1145
1146     if (pci_enabled) {
1147         isa_irq_state->ioapic = ioapic_init();
1148     }
1149     pit = pit_init(0x40, isa_reserve_irq(0));
1150     pcspk_init(pit);
1151     if (!no_hpet) {
1152         hpet_init(isa_irq);
1153     }
1154
1155     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1156         if (serial_hds[i]) {
1157             serial_isa_init(i, serial_hds[i]);
1158         }
1159     }
1160
1161     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1162         if (parallel_hds[i]) {
1163             parallel_init(i, parallel_hds[i]);
1164         }
1165     }
1166
1167     for(i = 0; i < nb_nics; i++) {
1168         NICInfo *nd = &nd_table[i];
1169
1170         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1171             pc_init_ne2k_isa(nd);
1172         else
1173             pci_nic_init_nofail(nd, "e1000", NULL);
1174     }
1175
1176     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1177         fprintf(stderr, "qemu: too many IDE bus\n");
1178         exit(1);
1179     }
1180
1181     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1182         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1183     }
1184
1185     if (pci_enabled) {
1186         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
1187     } else {
1188         for(i = 0; i < MAX_IDE_BUS; i++) {
1189             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
1190                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1191         }
1192     }
1193
1194     isa_dev = isa_create_simple("i8042");
1195     DMA_init(0);
1196 #ifdef HAS_AUDIO
1197     audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1198 #endif
1199
1200     for(i = 0; i < MAX_FD; i++) {
1201         fd[i] = drive_get(IF_FLOPPY, 0, i);
1202     }
1203     floppy_controller = fdctrl_init_isa(fd);
1204
1205     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1206
1207     if (pci_enabled && usb_enabled) {
1208         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1209     }
1210
1211     if (pci_enabled && acpi_enabled) {
1212         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1213         i2c_bus *smbus;
1214
1215         /* TODO: Populate SPD eeprom data.  */
1216         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1217                               isa_reserve_irq(9));
1218         for (i = 0; i < 8; i++) {
1219             DeviceState *eeprom;
1220             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1221             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1222             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1223             qdev_init_nofail(eeprom);
1224         }
1225         piix4_acpi_system_hot_add_init(pci_bus);
1226     }
1227
1228     if (i440fx_state) {
1229         i440fx_init_memory_mappings(i440fx_state);
1230     }
1231
1232     if (pci_enabled) {
1233         int max_bus;
1234         int bus;
1235
1236         max_bus = drive_get_max_bus(IF_SCSI);
1237         for (bus = 0; bus <= max_bus; bus++) {
1238             pci_create_simple(pci_bus, -1, "lsi53c895a");
1239         }
1240     }
1241
1242     /* Add virtio console devices */
1243     if (pci_enabled) {
1244         for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1245             if (virtcon_hds[i]) {
1246                 pci_create_simple(pci_bus, -1, "virtio-console-pci");
1247             }
1248         }
1249     }
1250 }
1251
1252 static void pc_init_pci(ram_addr_t ram_size,
1253                         const char *boot_device,
1254                         const char *kernel_filename,
1255                         const char *kernel_cmdline,
1256                         const char *initrd_filename,
1257                         const char *cpu_model)
1258 {
1259     pc_init1(ram_size, boot_device,
1260              kernel_filename, kernel_cmdline,
1261              initrd_filename, cpu_model, 1);
1262 }
1263
1264 static void pc_init_isa(ram_addr_t ram_size,
1265                         const char *boot_device,
1266                         const char *kernel_filename,
1267                         const char *kernel_cmdline,
1268                         const char *initrd_filename,
1269                         const char *cpu_model)
1270 {
1271     if (cpu_model == NULL)
1272         cpu_model = "486";
1273     pc_init1(ram_size, boot_device,
1274              kernel_filename, kernel_cmdline,
1275              initrd_filename, cpu_model, 0);
1276 }
1277
1278 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1279    BIOS will read it and start S3 resume at POST Entry */
1280 void cmos_set_s3_resume(void)
1281 {
1282     if (rtc_state)
1283         rtc_set_memory(rtc_state, 0xF, 0xFE);
1284 }
1285
1286 static QEMUMachine pc_machine = {
1287     .name = "pc-0.11",
1288     .alias = "pc",
1289     .desc = "Standard PC",
1290     .init = pc_init_pci,
1291     .max_cpus = 255,
1292     .is_default = 1,
1293 };
1294
1295 static QEMUMachine pc_machine_v0_10 = {
1296     .name = "pc-0.10",
1297     .desc = "Standard PC, qemu 0.10",
1298     .init = pc_init_pci,
1299     .max_cpus = 255,
1300     .compat_props = (CompatProperty[]) {
1301         {
1302             .driver   = "virtio-blk-pci",
1303             .property = "class",
1304             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1305         },{
1306             .driver   = "virtio-console-pci",
1307             .property = "class",
1308             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1309         },{
1310             .driver   = "virtio-net-pci",
1311             .property = "vectors",
1312             .value    = stringify(0),
1313         },{
1314             .driver   = "virtio-blk-pci",
1315             .property = "vectors",
1316             .value    = stringify(0),
1317         },
1318         { /* end of list */ }
1319     },
1320 };
1321
1322 static QEMUMachine isapc_machine = {
1323     .name = "isapc",
1324     .desc = "ISA-only PC",
1325     .init = pc_init_isa,
1326     .max_cpus = 1,
1327 };
1328
1329 static void pc_machine_init(void)
1330 {
1331     qemu_register_machine(&pc_machine);
1332     qemu_register_machine(&pc_machine_v0_10);
1333     qemu_register_machine(&isapc_machine);
1334 }
1335
1336 machine_init(pc_machine_init);