pc: make pc_init1() not refer ferr_irq directly.
[qemu/aliguori-queue.git] / hw / msix.c
blob2ca0900c3c65f3cfeb130c7fa682ed4fa0e359c7
1 /*
2 * MSI-X device support
4 * This module includes support for MSI-X in pci devices.
6 * Author: Michael S. Tsirkin <mst@redhat.com>
8 * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
10 * This work is licensed under the terms of the GNU GPL, version 2. See
11 * the COPYING file in the top-level directory.
14 #include "hw.h"
15 #include "msix.h"
16 #include "pci.h"
18 /* Declaration from linux/pci_regs.h */
19 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
20 #define PCI_MSIX_FLAGS 2 /* Table at lower 11 bits */
21 #define PCI_MSIX_FLAGS_QSIZE 0x7FF
22 #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
23 #define PCI_MSIX_FLAGS_MASKALL (1 << 14)
24 #define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
26 /* MSI-X capability structure */
27 #define MSIX_TABLE_OFFSET 4
28 #define MSIX_PBA_OFFSET 8
29 #define MSIX_CAP_LENGTH 12
31 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
32 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
33 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
34 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
36 /* MSI-X table format */
37 #define MSIX_MSG_ADDR 0
38 #define MSIX_MSG_UPPER_ADDR 4
39 #define MSIX_MSG_DATA 8
40 #define MSIX_VECTOR_CTRL 12
41 #define MSIX_ENTRY_SIZE 16
42 #define MSIX_VECTOR_MASK 0x1
44 /* How much space does an MSIX table need. */
45 /* The spec requires giving the table structure
46 * a 4K aligned region all by itself. */
47 #define MSIX_PAGE_SIZE 0x1000
48 /* Reserve second half of the page for pending bits */
49 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
50 #define MSIX_MAX_ENTRIES 32
53 #ifdef MSIX_DEBUG
54 #define DEBUG(fmt, ...) \
55 do { \
56 fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
57 } while (0)
58 #else
59 #define DEBUG(fmt, ...) do { } while(0)
60 #endif
62 /* Flag for interrupt controller to declare MSI-X support */
63 int msix_supported;
65 /* Add MSI-X capability to the config space for the device. */
66 /* Given a bar and its size, add MSI-X table on top of it
67 * and fill MSI-X capability in the config space.
68 * Original bar size must be a power of 2 or 0.
69 * New bar size is returned. */
70 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
71 unsigned bar_nr, unsigned bar_size)
73 int config_offset;
74 uint8_t *config;
75 uint32_t new_size;
77 if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
78 return -EINVAL;
79 if (bar_size > 0x80000000)
80 return -ENOSPC;
82 /* Add space for MSI-X structures */
83 if (!bar_size) {
84 new_size = MSIX_PAGE_SIZE;
85 } else if (bar_size < MSIX_PAGE_SIZE) {
86 bar_size = MSIX_PAGE_SIZE;
87 new_size = MSIX_PAGE_SIZE * 2;
88 } else {
89 new_size = bar_size * 2;
92 pdev->msix_bar_size = new_size;
93 config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
94 if (config_offset < 0)
95 return config_offset;
96 config = pdev->config + config_offset;
98 pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
99 /* Table on top of BAR */
100 pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
101 /* Pending bits on top of that */
102 pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
103 bar_nr);
104 pdev->msix_cap = config_offset;
105 /* Make flags bit writeable. */
106 pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
107 MSIX_MASKALL_MASK;
108 return 0;
111 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
113 PCIDevice *dev = opaque;
114 unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
115 void *page = dev->msix_table_page;
117 return pci_get_long(page + offset);
120 static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
122 fprintf(stderr, "MSI-X: only dword read is allowed!\n");
123 return 0;
126 static uint8_t msix_pending_mask(int vector)
128 return 1 << (vector % 8);
131 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
133 return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
136 static int msix_is_pending(PCIDevice *dev, int vector)
138 return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
141 static void msix_set_pending(PCIDevice *dev, int vector)
143 *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
146 static void msix_clr_pending(PCIDevice *dev, int vector)
148 *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
151 static int msix_function_masked(PCIDevice *dev)
153 return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
156 static int msix_is_masked(PCIDevice *dev, int vector)
158 unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
159 return msix_function_masked(dev) ||
160 dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
163 static void msix_handle_mask_update(PCIDevice *dev, int vector)
165 if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
166 msix_clr_pending(dev, vector);
167 msix_notify(dev, vector);
171 /* Handle MSI-X capability config write. */
172 void msix_write_config(PCIDevice *dev, uint32_t addr,
173 uint32_t val, int len)
175 unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
176 int vector;
178 if (!range_covers_byte(addr, len, enable_pos)) {
179 return;
182 if (!msix_enabled(dev)) {
183 return;
186 qemu_set_irq(dev->irq[0], 0);
188 if (msix_function_masked(dev)) {
189 return;
192 for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
193 msix_handle_mask_update(dev, vector);
197 static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
198 uint32_t val)
200 PCIDevice *dev = opaque;
201 unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
202 int vector = offset / MSIX_ENTRY_SIZE;
203 pci_set_long(dev->msix_table_page + offset, val);
204 msix_handle_mask_update(dev, vector);
207 static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
208 uint32_t val)
210 fprintf(stderr, "MSI-X: only dword write is allowed!\n");
213 static CPUWriteMemoryFunc * const msix_mmio_write[] = {
214 msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
217 static CPUReadMemoryFunc * const msix_mmio_read[] = {
218 msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
221 /* Should be called from device's map method. */
222 void msix_mmio_map(PCIDevice *d, int region_num,
223 pcibus_t addr, pcibus_t size, int type)
225 uint8_t *config = d->config + d->msix_cap;
226 uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
227 uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
228 /* TODO: for assigned devices, we'll want to make it possible to map
229 * pending bits separately in case they are in a separate bar. */
230 int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
232 if (table_bir != region_num)
233 return;
234 if (size <= offset)
235 return;
236 cpu_register_physical_memory(addr + offset, size - offset,
237 d->msix_mmio_index);
240 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
242 int vector;
243 for (vector = 0; vector < nentries; ++vector) {
244 unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
245 dev->msix_table_page[offset] |= MSIX_VECTOR_MASK;
249 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
250 * modified, it should be retrieved with msix_bar_size. */
251 int msix_init(struct PCIDevice *dev, unsigned short nentries,
252 unsigned bar_nr, unsigned bar_size)
254 int ret;
255 /* Nothing to do if MSI is not supported by interrupt controller */
256 if (!msix_supported)
257 return -ENOTSUP;
259 if (nentries > MSIX_MAX_ENTRIES)
260 return -EINVAL;
262 dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
263 sizeof *dev->msix_entry_used);
265 dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
266 msix_mask_all(dev, nentries);
268 dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
269 msix_mmio_write, dev);
270 if (dev->msix_mmio_index == -1) {
271 ret = -EBUSY;
272 goto err_index;
275 dev->msix_entries_nr = nentries;
276 ret = msix_add_config(dev, nentries, bar_nr, bar_size);
277 if (ret)
278 goto err_config;
280 dev->cap_present |= QEMU_PCI_CAP_MSIX;
281 return 0;
283 err_config:
284 dev->msix_entries_nr = 0;
285 cpu_unregister_io_memory(dev->msix_mmio_index);
286 err_index:
287 qemu_free(dev->msix_table_page);
288 dev->msix_table_page = NULL;
289 qemu_free(dev->msix_entry_used);
290 dev->msix_entry_used = NULL;
291 return ret;
294 static void msix_free_irq_entries(PCIDevice *dev)
296 int vector;
298 for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
299 dev->msix_entry_used[vector] = 0;
300 msix_clr_pending(dev, vector);
304 /* Clean up resources for the device. */
305 int msix_uninit(PCIDevice *dev)
307 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
308 return 0;
309 pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
310 dev->msix_cap = 0;
311 msix_free_irq_entries(dev);
312 dev->msix_entries_nr = 0;
313 cpu_unregister_io_memory(dev->msix_mmio_index);
314 qemu_free(dev->msix_table_page);
315 dev->msix_table_page = NULL;
316 qemu_free(dev->msix_entry_used);
317 dev->msix_entry_used = NULL;
318 dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
319 return 0;
322 void msix_save(PCIDevice *dev, QEMUFile *f)
324 unsigned n = dev->msix_entries_nr;
326 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
327 return;
330 qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
331 qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
334 /* Should be called after restoring the config space. */
335 void msix_load(PCIDevice *dev, QEMUFile *f)
337 unsigned n = dev->msix_entries_nr;
339 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
340 return;
343 msix_free_irq_entries(dev);
344 qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
345 qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
348 /* Does device support MSI-X? */
349 int msix_present(PCIDevice *dev)
351 return dev->cap_present & QEMU_PCI_CAP_MSIX;
354 /* Is MSI-X enabled? */
355 int msix_enabled(PCIDevice *dev)
357 return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
358 (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
359 MSIX_ENABLE_MASK);
362 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
363 uint32_t msix_bar_size(PCIDevice *dev)
365 return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
366 dev->msix_bar_size : 0;
369 /* Send an MSI-X message */
370 void msix_notify(PCIDevice *dev, unsigned vector)
372 uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
373 uint64_t address;
374 uint32_t data;
376 if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
377 return;
378 if (msix_is_masked(dev, vector)) {
379 msix_set_pending(dev, vector);
380 return;
383 address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
384 address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
385 data = pci_get_long(table_entry + MSIX_MSG_DATA);
386 stl_phys(address, data);
389 void msix_reset(PCIDevice *dev)
391 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
392 return;
393 msix_free_irq_entries(dev);
394 dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
395 ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
396 memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
397 msix_mask_all(dev, dev->msix_entries_nr);
400 /* PCI spec suggests that devices make it possible for software to configure
401 * less vectors than supported by the device, but does not specify a standard
402 * mechanism for devices to do so.
404 * We support this by asking devices to declare vectors software is going to
405 * actually use, and checking this on the notification path. Devices that
406 * don't want to follow the spec suggestion can declare all vectors as used. */
408 /* Mark vector as used. */
409 int msix_vector_use(PCIDevice *dev, unsigned vector)
411 if (vector >= dev->msix_entries_nr)
412 return -EINVAL;
413 dev->msix_entry_used[vector]++;
414 return 0;
417 /* Mark vector as unused. */
418 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
420 if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
421 return;
423 if (--dev->msix_entry_used[vector]) {
424 return;
426 msix_clr_pending(dev, vector);
429 void msix_unuse_all_vectors(PCIDevice *dev)
431 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
432 return;
433 msix_free_irq_entries(dev);