hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "acpi.h"
  27
  28 //#define DEBUG
  29
  30 #define ACPI_DBG_IO_ADDR  0xb044
  31
  32 typedef struct PIIX4PMState {
  33     PCIDevice dev;
  34     uint16_t pmsts;
  35     uint16_t pmen;
  36     uint16_t pmcntrl;
  37
  38     APMState apm;
  39
  40     QEMUTimer *tmr_timer;
  41     int64_t tmr_overflow_time;
  42
  43     PMSMBus smb;
  44
  45     qemu_irq irq;
  46     qemu_irq cmos_s3;
  47     qemu_irq smi_irq;
  48     int kvm_enabled;
  49 } PIIX4PMState;
  50
  51 #define ACPI_ENABLE 0xf1
  52 #define ACPI_DISABLE 0xf0
  53
  54 static PIIX4PMState *pm_state;
  55
  56 static uint32_t get_pmtmr(PIIX4PMState *s)
  57 {
  58     uint32_t d;
  59     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  60     return d & 0xffffff;
  61 }
  62
  63 static int get_pmsts(PIIX4PMState *s)
  64 {
  65     int64_t d;
  66
  67     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  68                  get_ticks_per_sec());
  69     if (d >= s->tmr_overflow_time)
  70         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
  71     return s->pmsts;
  72 }
  73
  74 static void pm_update_sci(PIIX4PMState *s)
  75 {
  76     int sci_level, pmsts;
  77     int64_t expire_time;
  78
  79     pmsts = get_pmsts(s);
  80     sci_level = (((pmsts & s->pmen) &
  81                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  82                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  83                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  84                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
  85     qemu_set_irq(s->irq, sci_level);
  86     /* schedule a timer interruption if needed */
  87     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
  88         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
  89         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
  90                                PM_TIMER_FREQUENCY);
  91         qemu_mod_timer(s->tmr_timer, expire_time);
  92     } else {
  93         qemu_del_timer(s->tmr_timer);
  94     }
  95 }
  96
  97 static void pm_tmr_timer(void *opaque)
  98 {
  99     PIIX4PMState *s = opaque;
 100     pm_update_sci(s);
 101 }
 102
 103 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 104 {
 105     PIIX4PMState *s = opaque;
 106     addr &= 0x3f;
 107     switch(addr) {
 108     case 0x00:
 109         {
 110             int64_t d;
 111             int pmsts;
 112             pmsts = get_pmsts(s);
 113             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 114                 /* if TMRSTS is reset, then compute the new overflow time */
 115                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 116                              get_ticks_per_sec());
 117                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 118             }
 119             s->pmsts &= ~val;
 120             pm_update_sci(s);
 121         }
 122         break;
 123     case 0x02:
 124         s->pmen = val;
 125         pm_update_sci(s);
 126         break;
 127     case 0x04:
 128         {
 129             int sus_typ;
 130             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 131             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 132                 /* change suspend type */
 133                 sus_typ = (val >> 10) & 7;
 134                 switch(sus_typ) {
 135                 case 0: /* soft power off */
 136                     qemu_system_shutdown_request();
 137                     break;
 138                 case 1:
 139                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 140                        Pretend that resume was caused by power button */
 141                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 142                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 143                     qemu_system_reset_request();
 144                     if (s->cmos_s3) {
 145                         qemu_irq_raise(s->cmos_s3);
 146                     }
 147                 default:
 148                     break;
 149                 }
 150             }
 151         }
 152         break;
 153     default:
 154         break;
 155     }
 156 #ifdef DEBUG
 157     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 158 #endif
 159 }
 160
 161 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 162 {
 163     PIIX4PMState *s = opaque;
 164     uint32_t val;
 165
 166     addr &= 0x3f;
 167     switch(addr) {
 168     case 0x00:
 169         val = get_pmsts(s);
 170         break;
 171     case 0x02:
 172         val = s->pmen;
 173         break;
 174     case 0x04:
 175         val = s->pmcntrl;
 176         break;
 177     default:
 178         val = 0;
 179         break;
 180     }
 181 #ifdef DEBUG
 182     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 183 #endif
 184     return val;
 185 }
 186
 187 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 188 {
 189     //    PIIX4PMState *s = opaque;
 190 #ifdef DEBUG
 191     addr &= 0x3f;
 192     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 193 #endif
 194 }
 195
 196 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 197 {
 198     PIIX4PMState *s = opaque;
 199     uint32_t val;
 200
 201     addr &= 0x3f;
 202     switch(addr) {
 203     case 0x08:
 204         val = get_pmtmr(s);
 205         break;
 206     default:
 207         val = 0;
 208         break;
 209     }
 210 #ifdef DEBUG
 211     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 212 #endif
 213     return val;
 214 }
 215
 216 static void apm_ctrl_changed(uint32_t val, void *arg)
 217 {
 218     PIIX4PMState *s = arg;
 219
 220     /* ACPI specs 3.0, 4.7.2.5 */
 221     if (val == ACPI_ENABLE) {
 222         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 223     } else if (val == ACPI_DISABLE) {
 224         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 225     }
 226
 227     if (s->dev.config[0x5b] & (1 << 1)) {
 228         if (s->smi_irq) {
 229             qemu_irq_raise(s->smi_irq);
 230         }
 231     }
 232 }
 233
 234 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 235 {
 236 #if defined(DEBUG)
 237     printf("ACPI: DBG: 0x%08x\n", val);
 238 #endif
 239 }
 240
 241 static void pm_io_space_update(PIIX4PMState *s)
 242 {
 243     uint32_t pm_io_base;
 244
 245     if (s->dev.config[0x80] & 1) {
 246         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 247         pm_io_base &= 0xffc0;
 248
 249         /* XXX: need to improve memory and ioport allocation */
 250 #if defined(DEBUG)
 251         printf("PM: mapping to 0x%x\n", pm_io_base);
 252 #endif
 253         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 254         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 255         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 256         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 257     }
 258 }
 259
 260 static void pm_write_config(PCIDevice *d,
 261                             uint32_t address, uint32_t val, int len)
 262 {
 263     pci_default_write_config(d, address, val, len);
 264     if (range_covers_byte(address, len, 0x80))
 265         pm_io_space_update((PIIX4PMState *)d);
 266 }
 267
 268 static int vmstate_acpi_post_load(void *opaque, int version_id)
 269 {
 270     PIIX4PMState *s = opaque;
 271
 272     pm_io_space_update(s);
 273     return 0;
 274 }
 275
 276 static const VMStateDescription vmstate_acpi = {
 277     .name = "piix4_pm",
 278     .version_id = 1,
 279     .minimum_version_id = 1,
 280     .minimum_version_id_old = 1,
 281     .post_load = vmstate_acpi_post_load,
 282     .fields      = (VMStateField []) {
 283         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 284         VMSTATE_UINT16(pmsts, PIIX4PMState),
 285         VMSTATE_UINT16(pmen, PIIX4PMState),
 286         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 287         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 288         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 289         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 290         VMSTATE_END_OF_LIST()
 291     }
 292 };
 293
 294 static void piix4_reset(void *opaque)
 295 {
 296     PIIX4PMState *s = opaque;
 297     uint8_t *pci_conf = s->dev.config;
 298
 299     pci_conf[0x58] = 0;
 300     pci_conf[0x59] = 0;
 301     pci_conf[0x5a] = 0;
 302     pci_conf[0x5b] = 0;
 303
 304     if (s->kvm_enabled) {
 305         /* Mark SMM as already inited (until KVM supports SMM). */
 306         pci_conf[0x5B] = 0x02;
 307     }
 308 }
 309
 310 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 311 {
 312     PIIX4PMState *s = opaque;
 313
 314     if (!s) {
 315         qemu_system_shutdown_request();
 316     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 317         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 318         pm_update_sci(s);
 319     }
 320 }
 321
 322 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 323                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 324                        int kvm_enabled)
 325 {
 326     PIIX4PMState *s;
 327     uint8_t *pci_conf;
 328
 329     s = (PIIX4PMState *)pci_register_device(bus,
 330                                          "PM", sizeof(PIIX4PMState),
 331                                          devfn, NULL, pm_write_config);
 332     pm_state = s;
 333     pci_conf = s->dev.config;
 334     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 335     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 336     pci_conf[0x06] = 0x80;
 337     pci_conf[0x07] = 0x02;
 338     pci_conf[0x08] = 0x03; // revision number
 339     pci_conf[0x09] = 0x00;
 340     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 341     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 342     pci_conf[0x3d] = 0x01; // interrupt pin 1
 343
 344     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 345
 346     /* APM */
 347     apm_init(&s->apm, apm_ctrl_changed, s);
 348
 349     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 350
 351     s->kvm_enabled = kvm_enabled;
 352     if (s->kvm_enabled) {
 353         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 354          * support SMM mode. */
 355         pci_conf[0x5B] = 0x02;
 356     }
 357
 358     /* XXX: which specification is used ? The i82731AB has different
 359        mappings */
 360     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 361     pci_conf[0x63] = 0x60;
 362     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 363         (serial_hds[1] != NULL ? 0x90 : 0);
 364
 365     pci_conf[0x90] = smb_io_base | 1;
 366     pci_conf[0x91] = smb_io_base >> 8;
 367     pci_conf[0xd2] = 0x09;
 368     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 369     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 370
 371     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 372
 373     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 374
 375     vmstate_register(0, &vmstate_acpi, s);
 376
 377     pm_smbus_init(NULL, &s->smb);
 378     s->irq = sci_irq;
 379     s->cmos_s3 = cmos_s3;
 380     s->smi_irq = smi_irq;
 381     qemu_register_reset(piix4_reset, s);
 382
 383     return s->smb.smbus;
 384 }
 385
 386 #define GPE_BASE 0xafe0
 387 #define PCI_BASE 0xae00
 388 #define PCI_EJ_BASE 0xae08
 389
 390 struct gpe_regs {
 391     uint16_t sts; /* status */
 392     uint16_t en;  /* enabled */
 393 };
 394
 395 struct pci_status {
 396     uint32_t up;
 397     uint32_t down;
 398 };
 399
 400 static struct gpe_regs gpe;
 401 static struct pci_status pci0_status;
 402
 403 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 404 {
 405     if (addr & 1)
 406         return (val >> 8) & 0xff;
 407     return val & 0xff;
 408 }
 409
 410 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 411 {
 412     uint32_t val = 0;
 413     struct gpe_regs *g = opaque;
 414     switch (addr) {
 415         case GPE_BASE:
 416         case GPE_BASE + 1:
 417             val = gpe_read_val(g->sts, addr);
 418             break;
 419         case GPE_BASE + 2:
 420         case GPE_BASE + 3:
 421             val = gpe_read_val(g->en, addr);
 422             break;
 423         default:
 424             break;
 425     }
 426
 427 #if defined(DEBUG)
 428     printf("gpe read %x == %x\n", addr, val);
 429 #endif
 430     return val;
 431 }
 432
 433 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 434 {
 435     if (addr & 1)
 436         *cur = (*cur & 0xff) | (val << 8);
 437     else
 438         *cur = (*cur & 0xff00) | (val & 0xff);
 439 }
 440
 441 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 442 {
 443     uint16_t x1, x0 = val & 0xff;
 444     int shift = (addr & 1) ? 8 : 0;
 445
 446     x1 = (*cur >> shift) & 0xff;
 447
 448     x1 = x1 & ~x0;
 449
 450     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 451 }
 452
 453 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 454 {
 455     struct gpe_regs *g = opaque;
 456     switch (addr) {
 457         case GPE_BASE:
 458         case GPE_BASE + 1:
 459             gpe_reset_val(&g->sts, addr, val);
 460             break;
 461         case GPE_BASE + 2:
 462         case GPE_BASE + 3:
 463             gpe_write_val(&g->en, addr, val);
 464             break;
 465         default:
 466             break;
 467    }
 468
 469 #if defined(DEBUG)
 470     printf("gpe write %x <== %d\n", addr, val);
 471 #endif
 472 }
 473
 474 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 475 {
 476     uint32_t val = 0;
 477     struct pci_status *g = opaque;
 478     switch (addr) {
 479         case PCI_BASE:
 480             val = g->up;
 481             break;
 482         case PCI_BASE + 4:
 483             val = g->down;
 484             break;
 485         default:
 486             break;
 487     }
 488
 489 #if defined(DEBUG)
 490     printf("pcihotplug read %x == %x\n", addr, val);
 491 #endif
 492     return val;
 493 }
 494
 495 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 496 {
 497     struct pci_status *g = opaque;
 498     switch (addr) {
 499         case PCI_BASE:
 500             g->up = val;
 501             break;
 502         case PCI_BASE + 4:
 503             g->down = val;
 504             break;
 505    }
 506
 507 #if defined(DEBUG)
 508     printf("pcihotplug write %x <== %d\n", addr, val);
 509 #endif
 510 }
 511
 512 static uint32_t pciej_read(void *opaque, uint32_t addr)
 513 {
 514 #if defined(DEBUG)
 515     printf("pciej read %x\n", addr);
 516 #endif
 517     return 0;
 518 }
 519
 520 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 521 {
 522     BusState *bus = opaque;
 523     DeviceState *qdev, *next;
 524     PCIDevice *dev;
 525     int slot = ffs(val) - 1;
 526
 527     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 528         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 529         if (PCI_SLOT(dev->devfn) == slot) {
 530             qdev_free(qdev);
 531         }
 532     }
 533
 534
 535 #if defined(DEBUG)
 536     printf("pciej write %x <== %d\n", addr, val);
 537 #endif
 538 }
 539
 540 static int piix4_device_hotplug(PCIDevice *dev, int state);
 541
 542 void piix4_acpi_system_hot_add_init(PCIBus *bus)
 543 {
 544     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 545     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 546
 547     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 548     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 549
 550     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 551     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 552
 553     pci_bus_hotplug(bus, piix4_device_hotplug);
 554 }
 555
 556 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 557 {
 558     g->sts |= 2;
 559     p->up |= (1 << slot);
 560 }
 561
 562 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 563 {
 564     g->sts |= 2;
 565     p->down |= (1 << slot);
 566 }
 567
 568 static int piix4_device_hotplug(PCIDevice *dev, int state)
 569 {
 570     int slot = PCI_SLOT(dev->devfn);
 571
 572     pci0_status.up = 0;
 573     pci0_status.down = 0;
 574     if (state)
 575         enable_device(&pci0_status, &gpe, slot);
 576     else
 577         disable_device(&pci0_status, &gpe, slot);
 578     if (gpe.en & 2) {
 579         qemu_set_irq(pm_state->irq, 1);
 580         qemu_set_irq(pm_state->irq, 0);
 581     }
 582     return 0;
 583 }