hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "usb-uhci.h"
  31 #include "usb-ohci.h"
  32 #include "prep_pci.h"
  33 #include "apb_pci.h"
  34 #include "block.h"
  35 #include "sysemu.h"
  36 #include "audio/audio.h"
  37 #include "net.h"
  38 #include "smbus.h"
  39 #include "boards.h"
  40 #include "monitor.h"
  41 #include "fw_cfg.h"
  42 #include "hpet_emul.h"
  43 #include "watchdog.h"
  44 #include "smbios.h"
  45 #include "ide.h"
  46 #include "loader.h"
  47 #include "elf.h"
  48 #include "multiboot.h"
  49
  50 /* output Bochs bios info messages */
  51 //#define DEBUG_BIOS
  52
  53 #define BIOS_FILENAME "bios.bin"
  54
  55 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  56
  57 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  58 #define ACPI_DATA_SIZE       0x10000
  59 #define BIOS_CFG_IOPORT 0x510
  60 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  61 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  62 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  63 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  64
  65 #define MAX_IDE_BUS 2
  66
  67 static FDCtrl *floppy_controller;
  68 static RTCState *rtc_state;
  69 static PITState *pit;
  70 static PCII440FXState *i440fx_state;
  71
  72 #define E820_NR_ENTRIES         16
  73
  74 struct e820_entry {
  75     uint64_t address;
  76     uint64_t length;
  77     uint32_t type;
  78 };
  79
  80 struct e820_table {
  81     uint32_t count;
  82     struct e820_entry entry[E820_NR_ENTRIES];
  83 };
  84
  85 static struct e820_table e820_table;
  86
  87 typedef struct isa_irq_state {
  88     qemu_irq *i8259;
  89     qemu_irq *ioapic;
  90 } IsaIrqState;
  91
  92 static void isa_irq_handler(void *opaque, int n, int level)
  93 {
  94     IsaIrqState *isa = (IsaIrqState *)opaque;
  95
  96     if (n < 16) {
  97         qemu_set_irq(isa->i8259[n], level);
  98     }
  99     if (isa->ioapic)
 100         qemu_set_irq(isa->ioapic[n], level);
 101 };
 102
 103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105 }
 106
 107 /* MSDOS compatibility mode FPU exception support */
 108 static qemu_irq ferr_irq;
 109 /* XXX: add IGNNE support */
 110 void cpu_set_ferr(CPUX86State *s)
 111 {
 112     qemu_irq_raise(ferr_irq);
 113 }
 114
 115 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 116 {
 117     qemu_irq_lower(ferr_irq);
 118 }
 119
 120 /* TSC handling */
 121 uint64_t cpu_get_tsc(CPUX86State *env)
 122 {
 123     return cpu_get_ticks();
 124 }
 125
 126 /* SMM support */
 127 void cpu_smm_update(CPUState *env)
 128 {
 129     if (i440fx_state && env == first_cpu)
 130         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 131 }
 132
 133
 134 /* IRQ handling */
 135 int cpu_get_pic_interrupt(CPUState *env)
 136 {
 137     int intno;
 138
 139     intno = apic_get_interrupt(env);
 140     if (intno >= 0) {
 141         /* set irq request if a PIC irq is still pending */
 142         /* XXX: improve that */
 143         pic_update_irq(isa_pic);
 144         return intno;
 145     }
 146     /* read the irq from the PIC */
 147     if (!apic_accept_pic_intr(env))
 148         return -1;
 149
 150     intno = pic_read_irq(isa_pic);
 151     return intno;
 152 }
 153
 154 static void pic_irq_request(void *opaque, int irq, int level)
 155 {
 156     CPUState *env = first_cpu;
 157
 158     if (env->apic_state) {
 159         while (env) {
 160             if (apic_accept_pic_intr(env))
 161                 apic_deliver_pic_intr(env, level);
 162             env = env->next_cpu;
 163         }
 164     } else {
 165         if (level)
 166             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 167         else
 168             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 169     }
 170 }
 171
 172 /* PC cmos mappings */
 173
 174 #define REG_EQUIPMENT_BYTE          0x14
 175
 176 static int cmos_get_fd_drive_type(int fd0)
 177 {
 178     int val;
 179
 180     switch (fd0) {
 181     case 0:
 182         /* 1.44 Mb 3"5 drive */
 183         val = 4;
 184         break;
 185     case 1:
 186         /* 2.88 Mb 3"5 drive */
 187         val = 5;
 188         break;
 189     case 2:
 190         /* 1.2 Mb 5"5 drive */
 191         val = 2;
 192         break;
 193     default:
 194         val = 0;
 195         break;
 196     }
 197     return val;
 198 }
 199
 200 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 201 {
 202     RTCState *s = rtc_state;
 203     int cylinders, heads, sectors;
 204     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 205     rtc_set_memory(s, type_ofs, 47);
 206     rtc_set_memory(s, info_ofs, cylinders);
 207     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 208     rtc_set_memory(s, info_ofs + 2, heads);
 209     rtc_set_memory(s, info_ofs + 3, 0xff);
 210     rtc_set_memory(s, info_ofs + 4, 0xff);
 211     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 212     rtc_set_memory(s, info_ofs + 6, cylinders);
 213     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 214     rtc_set_memory(s, info_ofs + 8, sectors);
 215 }
 216
 217 /* convert boot_device letter to something recognizable by the bios */
 218 static int boot_device2nibble(char boot_device)
 219 {
 220     switch(boot_device) {
 221     case 'a':
 222     case 'b':
 223         return 0x01; /* floppy boot */
 224     case 'c':
 225         return 0x02; /* hard drive boot */
 226     case 'd':
 227         return 0x03; /* CD-ROM boot */
 228     case 'n':
 229         return 0x04; /* Network boot */
 230     }
 231     return 0;
 232 }
 233
 234 static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk)
 235 {
 236 #define PC_MAX_BOOT_DEVICES 3
 237     int nbds, bds[3] = { 0, };
 238     int i;
 239
 240     nbds = strlen(boot_device);
 241     if (nbds > PC_MAX_BOOT_DEVICES) {
 242         error_report("Too many boot devices for PC");
 243         return(1);
 244     }
 245     for (i = 0; i < nbds; i++) {
 246         bds[i] = boot_device2nibble(boot_device[i]);
 247         if (bds[i] == 0) {
 248             error_report("Invalid boot device for PC: '%c'",
 249                          boot_device[i]);
 250             return(1);
 251         }
 252     }
 253     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 254     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 255     return(0);
 256 }
 257
 258 static int pc_boot_set(void *opaque, const char *boot_device)
 259 {
 260     return set_boot_dev(opaque, boot_device, 0);
 261 }
 262
 263 /* hd_table must contain 4 block drivers */
 264 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 265                       const char *boot_device, DriveInfo **hd_table)
 266 {
 267     RTCState *s = rtc_state;
 268     int val;
 269     int fd0, fd1, nb;
 270     int i;
 271
 272     /* various important CMOS locations needed by PC/Bochs bios */
 273
 274     /* memory size */
 275     val = 640; /* base memory in K */
 276     rtc_set_memory(s, 0x15, val);
 277     rtc_set_memory(s, 0x16, val >> 8);
 278
 279     val = (ram_size / 1024) - 1024;
 280     if (val > 65535)
 281         val = 65535;
 282     rtc_set_memory(s, 0x17, val);
 283     rtc_set_memory(s, 0x18, val >> 8);
 284     rtc_set_memory(s, 0x30, val);
 285     rtc_set_memory(s, 0x31, val >> 8);
 286
 287     if (above_4g_mem_size) {
 288         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 289         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 290         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 291     }
 292
 293     if (ram_size > (16 * 1024 * 1024))
 294         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 295     else
 296         val = 0;
 297     if (val > 65535)
 298         val = 65535;
 299     rtc_set_memory(s, 0x34, val);
 300     rtc_set_memory(s, 0x35, val >> 8);
 301
 302     /* set the number of CPU */
 303     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 304
 305     /* set boot devices, and disable floppy signature check if requested */
 306     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 307         exit(1);
 308     }
 309
 310     /* floppy type */
 311
 312     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 313     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 314
 315     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 316     rtc_set_memory(s, 0x10, val);
 317
 318     val = 0;
 319     nb = 0;
 320     if (fd0 < 3)
 321         nb++;
 322     if (fd1 < 3)
 323         nb++;
 324     switch (nb) {
 325     case 0:
 326         break;
 327     case 1:
 328         val |= 0x01; /* 1 drive, ready for boot */
 329         break;
 330     case 2:
 331         val |= 0x41; /* 2 drives, ready for boot */
 332         break;
 333     }
 334     val |= 0x02; /* FPU is there */
 335     val |= 0x04; /* PS/2 mouse installed */
 336     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 337
 338     /* hard drives */
 339
 340     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 341     if (hd_table[0])
 342         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
 343     if (hd_table[1])
 344         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
 345
 346     val = 0;
 347     for (i = 0; i < 4; i++) {
 348         if (hd_table[i]) {
 349             int cylinders, heads, sectors, translation;
 350             /* NOTE: bdrv_get_geometry_hint() returns the physical
 351                 geometry.  It is always such that: 1 <= sects <= 63, 1
 352                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 353                 geometry can be different if a translation is done. */
 354             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 355             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 356                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 357                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 358                     /* No translation. */
 359                     translation = 0;
 360                 } else {
 361                     /* LBA translation. */
 362                     translation = 1;
 363                 }
 364             } else {
 365                 translation--;
 366             }
 367             val |= translation << (i * 2);
 368         }
 369     }
 370     rtc_set_memory(s, 0x39, val);
 371 }
 372
 373 void ioport_set_a20(int enable)
 374 {
 375     /* XXX: send to all CPUs ? */
 376     cpu_x86_set_a20(first_cpu, enable);
 377 }
 378
 379 int ioport_get_a20(void)
 380 {
 381     return ((first_cpu->a20_mask >> 20) & 1);
 382 }
 383
 384 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 385 {
 386     ioport_set_a20((val >> 1) & 1);
 387     /* XXX: bit 0 is fast reset */
 388 }
 389
 390 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 391 {
 392     return ioport_get_a20() << 1;
 393 }
 394
 395 /***********************************************************/
 396 /* Bochs BIOS debug ports */
 397
 398 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 399 {
 400     static const char shutdown_str[8] = "Shutdown";
 401     static int shutdown_index = 0;
 402
 403     switch(addr) {
 404         /* Bochs BIOS messages */
 405     case 0x400:
 406     case 0x401:
 407         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 408         exit(1);
 409     case 0x402:
 410     case 0x403:
 411 #ifdef DEBUG_BIOS
 412         fprintf(stderr, "%c", val);
 413 #endif
 414         break;
 415     case 0x8900:
 416         /* same as Bochs power off */
 417         if (val == shutdown_str[shutdown_index]) {
 418             shutdown_index++;
 419             if (shutdown_index == 8) {
 420                 shutdown_index = 0;
 421                 qemu_system_shutdown_request();
 422             }
 423         } else {
 424             shutdown_index = 0;
 425         }
 426         break;
 427
 428         /* LGPL'ed VGA BIOS messages */
 429     case 0x501:
 430     case 0x502:
 431         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 432         exit(1);
 433     case 0x500:
 434     case 0x503:
 435 #ifdef DEBUG_BIOS
 436         fprintf(stderr, "%c", val);
 437 #endif
 438         break;
 439     }
 440 }
 441
 442 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 443 {
 444     int index = e820_table.count;
 445     struct e820_entry *entry;
 446
 447     if (index >= E820_NR_ENTRIES)
 448         return -EBUSY;
 449     entry = &e820_table.entry[index];
 450
 451     entry->address = address;
 452     entry->length = length;
 453     entry->type = type;
 454
 455     e820_table.count++;
 456     return e820_table.count;
 457 }
 458
 459 static void *bochs_bios_init(void)
 460 {
 461     void *fw_cfg;
 462     uint8_t *smbios_table;
 463     size_t smbios_len;
 464     uint64_t *numa_fw_cfg;
 465     int i, j;
 466
 467     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 468     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 469     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 470     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 471     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 472
 473     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 474     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 475     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 476     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 477
 478     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 479
 480     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 481     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 482     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 483                      acpi_tables_len);
 484     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 485
 486     smbios_table = smbios_get_table(&smbios_len);
 487     if (smbios_table)
 488         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 489                          smbios_table, smbios_len);
 490     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 491                      sizeof(struct e820_table));
 492
 493     /* allocate memory for the NUMA channel: one (64bit) word for the number
 494      * of nodes, one word for each VCPU->node and one word for each node to
 495      * hold the amount of memory.
 496      */
 497     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 498     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 499     for (i = 0; i < smp_cpus; i++) {
 500         for (j = 0; j < nb_numa_nodes; j++) {
 501             if (node_cpumask[j] & (1 << i)) {
 502                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 503                 break;
 504             }
 505         }
 506     }
 507     for (i = 0; i < nb_numa_nodes; i++) {
 508         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 509     }
 510     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 511                      (1 + smp_cpus + nb_numa_nodes) * 8);
 512
 513     return fw_cfg;
 514 }
 515
 516 static long get_file_size(FILE *f)
 517 {
 518     long where, size;
 519
 520     /* XXX: on Unix systems, using fstat() probably makes more sense */
 521
 522     where = ftell(f);
 523     fseek(f, 0, SEEK_END);
 524     size = ftell(f);
 525     fseek(f, where, SEEK_SET);
 526
 527     return size;
 528 }
 529
 530 static void load_linux(void *fw_cfg,
 531                        const char *kernel_filename,
 532                        const char *initrd_filename,
 533                        const char *kernel_cmdline,
 534                        target_phys_addr_t max_ram_size)
 535 {
 536     uint16_t protocol;
 537     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 538     uint32_t initrd_max;
 539     uint8_t header[8192], *setup, *kernel, *initrd_data;
 540     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 541     FILE *f;
 542     char *vmode;
 543
 544     /* Align to 16 bytes as a paranoia measure */
 545     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 546
 547     /* load the kernel header */
 548     f = fopen(kernel_filename, "rb");
 549     if (!f || !(kernel_size = get_file_size(f)) ||
 550         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 551         MIN(ARRAY_SIZE(header), kernel_size)) {
 552         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 553                 kernel_filename, strerror(errno));
 554         exit(1);
 555     }
 556
 557     /* kernel protocol version */
 558 #if 0
 559     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 560 #endif
 561     if (ldl_p(header+0x202) == 0x53726448)
 562         protocol = lduw_p(header+0x206);
 563     else {
 564         /* This looks like a multiboot kernel. If it is, let's stop
 565            treating it like a Linux kernel. */
 566         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 567                            kernel_cmdline, kernel_size, header))
 568             return;
 569         protocol = 0;
 570     }
 571
 572     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 573         /* Low kernel */
 574         real_addr    = 0x90000;
 575         cmdline_addr = 0x9a000 - cmdline_size;
 576         prot_addr    = 0x10000;
 577     } else if (protocol < 0x202) {
 578         /* High but ancient kernel */
 579         real_addr    = 0x90000;
 580         cmdline_addr = 0x9a000 - cmdline_size;
 581         prot_addr    = 0x100000;
 582     } else {
 583         /* High and recent kernel */
 584         real_addr    = 0x10000;
 585         cmdline_addr = 0x20000;
 586         prot_addr    = 0x100000;
 587     }
 588
 589 #if 0
 590     fprintf(stderr,
 591             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 592             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 593             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 594             real_addr,
 595             cmdline_addr,
 596             prot_addr);
 597 #endif
 598
 599     /* highest address for loading the initrd */
 600     if (protocol >= 0x203)
 601         initrd_max = ldl_p(header+0x22c);
 602     else
 603         initrd_max = 0x37ffffff;
 604
 605     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 606         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 607
 608     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 609     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 610     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 611                      (uint8_t*)strdup(kernel_cmdline),
 612                      strlen(kernel_cmdline)+1);
 613
 614     if (protocol >= 0x202) {
 615         stl_p(header+0x228, cmdline_addr);
 616     } else {
 617         stw_p(header+0x20, 0xA33F);
 618         stw_p(header+0x22, cmdline_addr-real_addr);
 619     }
 620
 621     /* handle vga= parameter */
 622     vmode = strstr(kernel_cmdline, "vga=");
 623     if (vmode) {
 624         unsigned int video_mode;
 625         /* skip "vga=" */
 626         vmode += 4;
 627         if (!strncmp(vmode, "normal", 6)) {
 628             video_mode = 0xffff;
 629         } else if (!strncmp(vmode, "ext", 3)) {
 630             video_mode = 0xfffe;
 631         } else if (!strncmp(vmode, "ask", 3)) {
 632             video_mode = 0xfffd;
 633         } else {
 634             video_mode = strtol(vmode, NULL, 0);
 635         }
 636         stw_p(header+0x1fa, video_mode);
 637     }
 638
 639     /* loader type */
 640     /* High nybble = B reserved for Qemu; low nybble is revision number.
 641        If this code is substantially changed, you may want to consider
 642        incrementing the revision. */
 643     if (protocol >= 0x200)
 644         header[0x210] = 0xB0;
 645
 646     /* heap */
 647     if (protocol >= 0x201) {
 648         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 649         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 650     }
 651
 652     /* load initrd */
 653     if (initrd_filename) {
 654         if (protocol < 0x200) {
 655             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 656             exit(1);
 657         }
 658
 659         initrd_size = get_image_size(initrd_filename);
 660         initrd_addr = (initrd_max-initrd_size) & ~4095;
 661
 662         initrd_data = qemu_malloc(initrd_size);
 663         load_image(initrd_filename, initrd_data);
 664
 665         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 666         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 667         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 668
 669         stl_p(header+0x218, initrd_addr);
 670         stl_p(header+0x21c, initrd_size);
 671     }
 672
 673     /* load kernel and setup */
 674     setup_size = header[0x1f1];
 675     if (setup_size == 0)
 676         setup_size = 4;
 677     setup_size = (setup_size+1)*512;
 678     kernel_size -= setup_size;
 679
 680     setup  = qemu_malloc(setup_size);
 681     kernel = qemu_malloc(kernel_size);
 682     fseek(f, 0, SEEK_SET);
 683     if (fread(setup, 1, setup_size, f) != setup_size) {
 684         fprintf(stderr, "fread() failed\n");
 685         exit(1);
 686     }
 687     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 688         fprintf(stderr, "fread() failed\n");
 689         exit(1);
 690     }
 691     fclose(f);
 692     memcpy(setup, header, MIN(sizeof(header), setup_size));
 693
 694     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 695     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 696     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 697
 698     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 699     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 700     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 701
 702     option_rom[nb_option_roms] = "linuxboot.bin";
 703     nb_option_roms++;
 704 }
 705
 706 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 707 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 708 static const int ide_irq[2] = { 14, 15 };
 709
 710 #define NE2000_NB_MAX 6
 711
 712 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 713                                               0x280, 0x380 };
 714 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 715
 716 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 717 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 718
 719 #ifdef HAS_AUDIO
 720 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 721 {
 722     struct soundhw *c;
 723
 724     for (c = soundhw; c->name; ++c) {
 725         if (c->enabled) {
 726             if (c->isa) {
 727                 c->init.init_isa(pic);
 728             } else {
 729                 if (pci_bus) {
 730                     c->init.init_pci(pci_bus);
 731                 }
 732             }
 733         }
 734     }
 735 }
 736 #endif
 737
 738 static void pc_init_ne2k_isa(NICInfo *nd)
 739 {
 740     static int nb_ne2k = 0;
 741
 742     if (nb_ne2k == NE2000_NB_MAX)
 743         return;
 744     isa_ne2000_init(ne2000_io[nb_ne2k],
 745                     ne2000_irq[nb_ne2k], nd);
 746     nb_ne2k++;
 747 }
 748
 749 int cpu_is_bsp(CPUState *env)
 750 {
 751     /* We hard-wire the BSP to the first CPU. */
 752     return env->cpu_index == 0;
 753 }
 754
 755 static CPUState *pc_new_cpu(const char *cpu_model)
 756 {
 757     CPUState *env;
 758
 759     env = cpu_init(cpu_model);
 760     if (!env) {
 761         fprintf(stderr, "Unable to find x86 CPU definition\n");
 762         exit(1);
 763     }
 764     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 765         env->cpuid_apic_id = env->cpu_index;
 766         /* APIC reset callback resets cpu */
 767         apic_init(env);
 768     } else {
 769         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 770     }
 771     return env;
 772 }
 773
 774 /* PC hardware initialisation */
 775 static void pc_init1(ram_addr_t ram_size,
 776                      const char *boot_device,
 777                      const char *kernel_filename,
 778                      const char *kernel_cmdline,
 779                      const char *initrd_filename,
 780                      const char *cpu_model,
 781                      int pci_enabled)
 782 {
 783     char *filename;
 784     int ret, linux_boot, i;
 785     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 786     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 787     int bios_size, isa_bios_size;
 788     PCIBus *pci_bus;
 789     ISADevice *isa_dev;
 790     int piix3_devfn = -1;
 791     CPUState *env;
 792     qemu_irq *cpu_irq;
 793     qemu_irq *isa_irq;
 794     qemu_irq *i8259;
 795     IsaIrqState *isa_irq_state;
 796     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 797     DriveInfo *fd[MAX_FD];
 798     void *fw_cfg;
 799
 800     if (ram_size >= 0xe0000000 ) {
 801         above_4g_mem_size = ram_size - 0xe0000000;
 802         below_4g_mem_size = 0xe0000000;
 803     } else {
 804         below_4g_mem_size = ram_size;
 805     }
 806
 807     linux_boot = (kernel_filename != NULL);
 808
 809     /* init CPUs */
 810     if (cpu_model == NULL) {
 811 #ifdef TARGET_X86_64
 812         cpu_model = "qemu64";
 813 #else
 814         cpu_model = "qemu32";
 815 #endif
 816     }
 817
 818     for (i = 0; i < smp_cpus; i++) {
 819         env = pc_new_cpu(cpu_model);
 820     }
 821
 822     vmport_init();
 823
 824     /* allocate RAM */
 825     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 826     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 827     cpu_register_physical_memory(0x100000,
 828                  below_4g_mem_size - 0x100000,
 829                  ram_addr + 0x100000);
 830
 831     /* above 4giga memory allocation */
 832     if (above_4g_mem_size > 0) {
 833 #if TARGET_PHYS_ADDR_BITS == 32
 834         hw_error("To much RAM for 32-bit physical address");
 835 #else
 836         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 837         cpu_register_physical_memory(0x100000000ULL,
 838                                      above_4g_mem_size,
 839                                      ram_addr);
 840 #endif
 841     }
 842
 843
 844     /* BIOS load */
 845     if (bios_name == NULL)
 846         bios_name = BIOS_FILENAME;
 847     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 848     if (filename) {
 849         bios_size = get_image_size(filename);
 850     } else {
 851         bios_size = -1;
 852     }
 853     if (bios_size <= 0 ||
 854         (bios_size % 65536) != 0) {
 855         goto bios_error;
 856     }
 857     bios_offset = qemu_ram_alloc(bios_size);
 858     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 859     if (ret != 0) {
 860     bios_error:
 861         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 862         exit(1);
 863     }
 864     if (filename) {
 865         qemu_free(filename);
 866     }
 867     /* map the last 128KB of the BIOS in ISA space */
 868     isa_bios_size = bios_size;
 869     if (isa_bios_size > (128 * 1024))
 870         isa_bios_size = 128 * 1024;
 871     cpu_register_physical_memory(0x100000 - isa_bios_size,
 872                                  isa_bios_size,
 873                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 874
 875     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 876     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 877
 878     /* map all the bios at the top of memory */
 879     cpu_register_physical_memory((uint32_t)(-bios_size),
 880                                  bios_size, bios_offset | IO_MEM_ROM);
 881
 882     fw_cfg = bochs_bios_init();
 883     rom_set_fw(fw_cfg);
 884
 885     if (linux_boot) {
 886         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 887     }
 888
 889     for (i = 0; i < nb_option_roms; i++) {
 890         rom_add_option(option_rom[i]);
 891     }
 892
 893     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 894     i8259 = i8259_init(cpu_irq[0]);
 895     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
 896     isa_irq_state->i8259 = i8259;
 897     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 898
 899     if (pci_enabled) {
 900         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
 901     } else {
 902         pci_bus = NULL;
 903         isa_bus_new(NULL);
 904     }
 905     isa_bus_irqs(isa_irq);
 906
 907     ferr_irq = isa_reserve_irq(13);
 908
 909     /* init basic PC hardware */
 910     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 911
 912     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 913
 914     if (cirrus_vga_enabled) {
 915         if (pci_enabled) {
 916             pci_cirrus_vga_init(pci_bus);
 917         } else {
 918             isa_cirrus_vga_init();
 919         }
 920     } else if (vmsvga_enabled) {
 921         if (pci_enabled)
 922             pci_vmsvga_init(pci_bus);
 923         else
 924             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 925     } else if (std_vga_enabled) {
 926         if (pci_enabled) {
 927             pci_vga_init(pci_bus, 0, 0);
 928         } else {
 929             isa_vga_init();
 930         }
 931     }
 932
 933     rtc_state = rtc_init(2000);
 934
 935     qemu_register_boot_set(pc_boot_set, rtc_state);
 936
 937     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
 938     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
 939
 940     if (pci_enabled) {
 941         isa_irq_state->ioapic = ioapic_init();
 942     }
 943     pit = pit_init(0x40, isa_reserve_irq(0));
 944     pcspk_init(pit);
 945     if (!no_hpet) {
 946         hpet_init(isa_irq);
 947     }
 948
 949     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 950         if (serial_hds[i]) {
 951             serial_isa_init(i, serial_hds[i]);
 952         }
 953     }
 954
 955     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 956         if (parallel_hds[i]) {
 957             parallel_init(i, parallel_hds[i]);
 958         }
 959     }
 960
 961     for(i = 0; i < nb_nics; i++) {
 962         NICInfo *nd = &nd_table[i];
 963
 964         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 965             pc_init_ne2k_isa(nd);
 966         else
 967             pci_nic_init_nofail(nd, "e1000", NULL);
 968     }
 969
 970     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 971         fprintf(stderr, "qemu: too many IDE bus\n");
 972         exit(1);
 973     }
 974
 975     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 976         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 977     }
 978
 979     if (pci_enabled) {
 980         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
 981     } else {
 982         for(i = 0; i < MAX_IDE_BUS; i++) {
 983             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 984                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 985         }
 986     }
 987
 988     isa_dev = isa_create_simple("i8042");
 989     DMA_init(0);
 990 #ifdef HAS_AUDIO
 991     audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
 992 #endif
 993
 994     for(i = 0; i < MAX_FD; i++) {
 995         fd[i] = drive_get(IF_FLOPPY, 0, i);
 996     }
 997     floppy_controller = fdctrl_init_isa(fd);
 998
 999     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1000
1001     if (pci_enabled && usb_enabled) {
1002         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1003     }
1004
1005     if (pci_enabled && acpi_enabled) {
1006         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1007         i2c_bus *smbus;
1008
1009         /* TODO: Populate SPD eeprom data.  */
1010         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1011                               isa_reserve_irq(9));
1012         for (i = 0; i < 8; i++) {
1013             DeviceState *eeprom;
1014             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1015             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1016             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1017             qdev_init_nofail(eeprom);
1018         }
1019         piix4_acpi_system_hot_add_init(pci_bus);
1020     }
1021
1022     if (i440fx_state) {
1023         i440fx_init_memory_mappings(i440fx_state);
1024     }
1025
1026     if (pci_enabled) {
1027         int max_bus;
1028         int bus;
1029
1030         max_bus = drive_get_max_bus(IF_SCSI);
1031         for (bus = 0; bus <= max_bus; bus++) {
1032             pci_create_simple(pci_bus, -1, "lsi53c895a");
1033         }
1034     }
1035 }
1036
1037 static void pc_init_pci(ram_addr_t ram_size,
1038                         const char *boot_device,
1039                         const char *kernel_filename,
1040                         const char *kernel_cmdline,
1041                         const char *initrd_filename,
1042                         const char *cpu_model)
1043 {
1044     pc_init1(ram_size, boot_device,
1045              kernel_filename, kernel_cmdline,
1046              initrd_filename, cpu_model, 1);
1047 }
1048
1049 static void pc_init_isa(ram_addr_t ram_size,
1050                         const char *boot_device,
1051                         const char *kernel_filename,
1052                         const char *kernel_cmdline,
1053                         const char *initrd_filename,
1054                         const char *cpu_model)
1055 {
1056     if (cpu_model == NULL)
1057         cpu_model = "486";
1058     pc_init1(ram_size, boot_device,
1059              kernel_filename, kernel_cmdline,
1060              initrd_filename, cpu_model, 0);
1061 }
1062
1063 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1064    BIOS will read it and start S3 resume at POST Entry */
1065 void cmos_set_s3_resume(void)
1066 {
1067     if (rtc_state)
1068         rtc_set_memory(rtc_state, 0xF, 0xFE);
1069 }
1070
1071 static QEMUMachine pc_machine = {
1072     .name = "pc-0.13",
1073     .alias = "pc",
1074     .desc = "Standard PC",
1075     .init = pc_init_pci,
1076     .max_cpus = 255,
1077     .is_default = 1,
1078 };
1079
1080 static QEMUMachine pc_machine_v0_12 = {
1081     .name = "pc-0.12",
1082     .desc = "Standard PC",
1083     .init = pc_init_pci,
1084     .max_cpus = 255,
1085     .compat_props = (GlobalProperty[]) {
1086         {
1087             .driver   = "virtio-serial-pci",
1088             .property = "max_nr_ports",
1089             .value    = stringify(1),
1090         },{
1091             .driver   = "virtio-serial-pci",
1092             .property = "vectors",
1093             .value    = stringify(0),
1094         },
1095         { /* end of list */ }
1096     }
1097 };
1098
1099 static QEMUMachine pc_machine_v0_11 = {
1100     .name = "pc-0.11",
1101     .desc = "Standard PC, qemu 0.11",
1102     .init = pc_init_pci,
1103     .max_cpus = 255,
1104     .compat_props = (GlobalProperty[]) {
1105         {
1106             .driver   = "virtio-blk-pci",
1107             .property = "vectors",
1108             .value    = stringify(0),
1109         },{
1110             .driver   = "virtio-serial-pci",
1111             .property = "max_nr_ports",
1112             .value    = stringify(1),
1113         },{
1114             .driver   = "virtio-serial-pci",
1115             .property = "vectors",
1116             .value    = stringify(0),
1117         },{
1118             .driver   = "ide-drive",
1119             .property = "ver",
1120             .value    = "0.11",
1121         },{
1122             .driver   = "scsi-disk",
1123             .property = "ver",
1124             .value    = "0.11",
1125         },{
1126             .driver   = "PCI",
1127             .property = "rombar",
1128             .value    = stringify(0),
1129         },
1130         { /* end of list */ }
1131     }
1132 };
1133
1134 static QEMUMachine pc_machine_v0_10 = {
1135     .name = "pc-0.10",
1136     .desc = "Standard PC, qemu 0.10",
1137     .init = pc_init_pci,
1138     .max_cpus = 255,
1139     .compat_props = (GlobalProperty[]) {
1140         {
1141             .driver   = "virtio-blk-pci",
1142             .property = "class",
1143             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1144         },{
1145             .driver   = "virtio-serial-pci",
1146             .property = "class",
1147             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1148         },{
1149             .driver   = "virtio-serial-pci",
1150             .property = "max_nr_ports",
1151             .value    = stringify(1),
1152         },{
1153             .driver   = "virtio-serial-pci",
1154             .property = "vectors",
1155             .value    = stringify(0),
1156         },{
1157             .driver   = "virtio-net-pci",
1158             .property = "vectors",
1159             .value    = stringify(0),
1160         },{
1161             .driver   = "virtio-blk-pci",
1162             .property = "vectors",
1163             .value    = stringify(0),
1164         },{
1165             .driver   = "ide-drive",
1166             .property = "ver",
1167             .value    = "0.10",
1168         },{
1169             .driver   = "scsi-disk",
1170             .property = "ver",
1171             .value    = "0.10",
1172         },{
1173             .driver   = "PCI",
1174             .property = "rombar",
1175             .value    = stringify(0),
1176         },
1177         { /* end of list */ }
1178     },
1179 };
1180
1181 static QEMUMachine isapc_machine = {
1182     .name = "isapc",
1183     .desc = "ISA-only PC",
1184     .init = pc_init_isa,
1185     .max_cpus = 1,
1186 };
1187
1188 static void pc_machine_init(void)
1189 {
1190     qemu_register_machine(&pc_machine);
1191     qemu_register_machine(&pc_machine_v0_12);
1192     qemu_register_machine(&pc_machine_v0_11);
1193     qemu_register_machine(&pc_machine_v0_10);
1194     qemu_register_machine(&isapc_machine);
1195 }
1196
1197 machine_init(pc_machine_init);