hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "boards.h"
  36 #include "fw_cfg.h"
  37 #include "escc.h"
  38
  39 #define MAX_IDE_BUS 2
  40 #define VGA_BIOS_SIZE 65536
  41 #define CFG_ADDR 0xf0000510
  42
  43 /* temporary frame buffer OSI calls for the video.x driver. The right
  44    solution is to modify the driver to use VGA PCI I/Os */
  45 /* XXX: to be removed. This is no way related to emulation */
  46 static int vga_osi_call (CPUState *env)
  47 {
  48     static int vga_vbl_enabled;
  49     int linesize;
  50
  51     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  52
  53     /* same handler as PearPC, coming from the original MOL video
  54        driver. */
  55     switch(env->gpr[5]) {
  56     case 4:
  57         break;
  58     case 28: /* set_vmode */
  59         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  60             env->gpr[3] = 1;
  61         else
  62             env->gpr[3] = 0;
  63         break;
  64     case 29: /* get_vmode_info */
  65         if (env->gpr[6] != 0) {
  66             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  67                 env->gpr[3] = 1;
  68                 break;
  69             }
  70         }
  71         env->gpr[3] = 0;
  72         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  73         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  74         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  75         env->gpr[7] = 85 << 16; /* refresh rate */
  76         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  77         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  78         linesize = (linesize + 3) & ~3;
  79         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  80         break;
  81     case 31: /* set_video power */
  82         env->gpr[3] = 0;
  83         break;
  84     case 39: /* video_ctrl */
  85         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  86             vga_vbl_enabled = env->gpr[6];
  87         env->gpr[3] = 0;
  88         break;
  89     case 47:
  90         break;
  91     case 59: /* set_color */
  92         /* R6 = index, R7 = RGB */
  93         env->gpr[3] = 0;
  94         break;
  95     case 64: /* get color */
  96         /* R6 = index */
  97         env->gpr[3] = 0;
  98         break;
  99     case 116: /* set hwcursor */
 100         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 101         break;
 102     default:
 103         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 104                 ppc_dump_gpr(env, 5));
 105         break;
 106     }
 107
 108     return 1; /* osi_call handled */
 109 }
 110
 111 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 112 {
 113     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 114     return 0;
 115 }
 116
 117 static void ppc_heathrow_init (ram_addr_t ram_size,
 118                                const char *boot_device,
 119                                const char *kernel_filename,
 120                                const char *kernel_cmdline,
 121                                const char *initrd_filename,
 122                                const char *cpu_model)
 123 {
 124     CPUState *env = NULL, *envs[MAX_CPUS];
 125     char *filename;
 126     qemu_irq *pic, **heathrow_irqs;
 127     int linux_boot, i;
 128     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 129     uint32_t kernel_base, initrd_base;
 130     int32_t kernel_size, initrd_size;
 131     PCIBus *pci_bus;
 132     MacIONVRAMState *nvr;
 133     int vga_bios_size, bios_size;
 134     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 135     int escc_mem_index, ide_mem_index[2];
 136     uint16_t ppc_boot_device;
 137     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 138     int index;
 139     void *fw_cfg;
 140     void *dbdma;
 141     uint8_t *vga_bios_ptr;
 142
 143     linux_boot = (kernel_filename != NULL);
 144
 145     /* init CPUs */
 146     if (cpu_model == NULL)
 147         cpu_model = "G3";
 148     for (i = 0; i < smp_cpus; i++) {
 149         env = cpu_init(cpu_model);
 150         if (!env) {
 151             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 152             exit(1);
 153         }
 154         /* Set time-base frequency to 16.6 Mhz */
 155         cpu_ppc_tb_init(env,  16600000UL);
 156         env->osi_call = vga_osi_call;
 157         qemu_register_reset(&cpu_ppc_reset, env);
 158         envs[i] = env;
 159     }
 160
 161     /* allocate RAM */
 162     if (ram_size > (2047 << 20)) {
 163         fprintf(stderr,
 164                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 165                 ((unsigned int)ram_size / (1 << 20)));
 166         exit(1);
 167     }
 168
 169     ram_offset = qemu_ram_alloc(ram_size);
 170     cpu_register_physical_memory(0, ram_size, ram_offset);
 171
 172     /* allocate and load BIOS */
 173     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 174     if (bios_name == NULL)
 175         bios_name = PROM_FILENAME;
 176     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 177     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 178
 179     /* Load OpenBIOS (ELF) */
 180     if (filename) {
 181         bios_size = load_elf(filename, 0, NULL, NULL, NULL);
 182         qemu_free(filename);
 183     } else {
 184         bios_size = -1;
 185     }
 186     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 187         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 188         exit(1);
 189     }
 190
 191     /* allocate and load VGA BIOS */
 192     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 193     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 194     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 195     if (filename) {
 196         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 197         qemu_free(filename);
 198     } else {
 199         vga_bios_size = -1;
 200     }
 201     if (vga_bios_size < 0) {
 202         /* if no bios is present, we can still work */
 203         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 204                 VGABIOS_FILENAME);
 205         vga_bios_size = 0;
 206     } else {
 207         /* set a specific header (XXX: find real Apple format for NDRV
 208            drivers) */
 209         vga_bios_ptr[0] = 'N';
 210         vga_bios_ptr[1] = 'D';
 211         vga_bios_ptr[2] = 'R';
 212         vga_bios_ptr[3] = 'V';
 213         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 214         vga_bios_size += 8;
 215     }
 216
 217     if (linux_boot) {
 218         uint64_t lowaddr = 0;
 219         kernel_base = KERNEL_LOAD_ADDR;
 220         /* Now we can load the kernel. The first step tries to load the kernel
 221            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 222            loaded again, the new PhysAddr being computed from lowaddr. */
 223         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
 224         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 225             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 226                                    NULL, 0, NULL);
 227         }
 228         if (kernel_size < 0)
 229             kernel_size = load_aout(kernel_filename, kernel_base,
 230                                     ram_size - kernel_base);
 231         if (kernel_size < 0)
 232             kernel_size = load_image_targphys(kernel_filename,
 233                                               kernel_base,
 234                                               ram_size - kernel_base);
 235         if (kernel_size < 0) {
 236             hw_error("qemu: could not load kernel '%s'\n",
 237                       kernel_filename);
 238             exit(1);
 239         }
 240         /* load initrd */
 241         if (initrd_filename) {
 242             initrd_base = INITRD_LOAD_ADDR;
 243             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 244                                               ram_size - initrd_base);
 245             if (initrd_size < 0) {
 246                 hw_error("qemu: could not load initial ram disk '%s'\n",
 247                          initrd_filename);
 248                 exit(1);
 249             }
 250         } else {
 251             initrd_base = 0;
 252             initrd_size = 0;
 253         }
 254         ppc_boot_device = 'm';
 255     } else {
 256         kernel_base = 0;
 257         kernel_size = 0;
 258         initrd_base = 0;
 259         initrd_size = 0;
 260         ppc_boot_device = '\0';
 261         for (i = 0; boot_device[i] != '\0'; i++) {
 262             /* TOFIX: for now, the second IDE channel is not properly
 263              *        used by OHW. The Mac floppy disk are not emulated.
 264              *        For now, OHW cannot boot from the network.
 265              */
 266 #if 0
 267             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 268                 ppc_boot_device = boot_device[i];
 269                 break;
 270             }
 271 #else
 272             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 273                 ppc_boot_device = boot_device[i];
 274                 break;
 275             }
 276 #endif
 277         }
 278         if (ppc_boot_device == '\0') {
 279             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 280             exit(1);
 281         }
 282     }
 283
 284     isa_mem_base = 0x80000000;
 285
 286     /* Register 2 MB of ISA IO space */
 287     isa_mmio_init(0xfe000000, 0x00200000);
 288
 289     /* XXX: we register only 1 output pin for heathrow PIC */
 290     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 291     heathrow_irqs[0] =
 292         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 293     /* Connect the heathrow PIC outputs to the 6xx bus */
 294     for (i = 0; i < smp_cpus; i++) {
 295         switch (PPC_INPUT(env)) {
 296         case PPC_FLAGS_INPUT_6xx:
 297             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 298             heathrow_irqs[i][0] =
 299                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 300             break;
 301         default:
 302             hw_error("Bus model not supported on OldWorld Mac machine\n");
 303         }
 304     }
 305
 306     /* init basic PC hardware */
 307     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 308         hw_error("Only 6xx bus is supported on heathrow machine\n");
 309     }
 310     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 311     pci_bus = pci_grackle_init(0xfec00000, pic);
 312     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 313
 314     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 315                                serial_hds[1], ESCC_CLOCK, 4);
 316
 317     for(i = 0; i < nb_nics; i++)
 318         pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
 319
 320
 321     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 322         fprintf(stderr, "qemu: too many IDE bus\n");
 323         exit(1);
 324     }
 325
 326     /* First IDE channel is a MAC IDE on the MacIO bus */
 327     index = drive_get_index(IF_IDE, 0, 0);
 328     if (index == -1)
 329         hd[0] = NULL;
 330     else
 331         hd[0] =  drives_table[index].bdrv;
 332     index = drive_get_index(IF_IDE, 0, 1);
 333     if (index == -1)
 334         hd[1] = NULL;
 335     else
 336         hd[1] =  drives_table[index].bdrv;
 337     dbdma = DBDMA_init(&dbdma_mem_index);
 338     ide_mem_index[0] = -1;
 339     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 340
 341     /* Second IDE channel is a CMD646 on the PCI bus */
 342     index = drive_get_index(IF_IDE, 1, 0);
 343     if (index == -1)
 344         hd[0] = NULL;
 345     else
 346         hd[0] =  drives_table[index].bdrv;
 347     index = drive_get_index(IF_IDE, 1, 1);
 348     if (index == -1)
 349         hd[1] = NULL;
 350     else
 351         hd[1] =  drives_table[index].bdrv;
 352     hd[3] = hd[2] = NULL;
 353     pci_cmd646_ide_init(pci_bus, hd, 0);
 354
 355     /* cuda also initialize ADB */
 356     cuda_init(&cuda_mem_index, pic[0x12]);
 357
 358     adb_kbd_init(&adb_bus);
 359     adb_mouse_init(&adb_bus);
 360
 361     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 362     pmac_format_nvram_partition(nvr, 0x2000);
 363
 364     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 365                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 366                escc_mem_index);
 367
 368     if (usb_enabled) {
 369         usb_ohci_init_pci(pci_bus, 3, -1);
 370     }
 371
 372     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 373         graphic_depth = 15;
 374
 375     /* No PCI init: the BIOS will do it */
 376
 377     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 378     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 379     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 380     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 381     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 382     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 383     if (kernel_cmdline) {
 384         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 385         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 386     } else {
 387         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 388     }
 389     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 390     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 391     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 392     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 393 }
 394
 395 static QEMUMachine heathrow_machine = {
 396     .name = "g3beige",
 397     .desc = "Heathrow based PowerMAC",
 398     .init = ppc_heathrow_init,
 399     .max_cpus = MAX_CPUS,
 400     .is_default = 1,
 401 };
 402
 403 static void heathrow_machine_init(void)
 404 {
 405     qemu_register_machine(&heathrow_machine);
 406 }
 407
 408 machine_init(heathrow_machine_init);