hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40
  41 //#define DEBUG_IRQ
  42 //#define DEBUG_EBUS
  43
  44 #ifdef DEBUG_IRQ
  45 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  46     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  47 #else
  48 #define CPUIRQ_DPRINTF(fmt, ...)
  49 #endif
  50
  51 #ifdef DEBUG_EBUS
  52 #define EBUS_DPRINTF(fmt, ...)                                  \
  53     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  54 #else
  55 #define EBUS_DPRINTF(fmt, ...)
  56 #endif
  57
  58 #define KERNEL_LOAD_ADDR     0x00404000
  59 #define CMDLINE_ADDR         0x003ff000
  60 #define INITRD_LOAD_ADDR     0x00300000
  61 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  62 #define PROM_VADDR           0x000ffd00000ULL
  63 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  64 #define APB_MEM_BASE         0x1ff00000000ULL
  65 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  66 #define PROM_FILENAME        "openbios-sparc64"
  67 #define NVRAM_SIZE           0x2000
  68 #define MAX_IDE_BUS          2
  69 #define BIOS_CFG_IOPORT      0x510
  70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  73
  74 #define MAX_PILS 16
  75
  76 #define TICK_MAX             0x7fffffffffffffffULL
  77
  78 struct hwdef {
  79     const char * const default_cpu_model;
  80     uint16_t machine_id;
  81     uint64_t prom_addr;
  82     uint64_t console_serial_base;
  83 };
  84
  85 int DMA_get_channel_mode (int nchan)
  86 {
  87     return 0;
  88 }
  89 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  90 {
  91     return 0;
  92 }
  93 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  94 {
  95     return 0;
  96 }
  97 void DMA_hold_DREQ (int nchan) {}
  98 void DMA_release_DREQ (int nchan) {}
  99 void DMA_schedule(int nchan) {}
 100 void DMA_init (int high_page_enable) {}
 101 void DMA_register_channel (int nchan,
 102                            DMA_transfer_handler transfer_handler,
 103                            void *opaque)
 104 {
 105 }
 106
 107 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 108 {
 109     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 110     return 0;
 111 }
 112
 113 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 114                                    const char *arch,
 115                                    ram_addr_t RAM_size,
 116                                    const char *boot_devices,
 117                                    uint32_t kernel_image, uint32_t kernel_size,
 118                                    const char *cmdline,
 119                                    uint32_t initrd_image, uint32_t initrd_size,
 120                                    uint32_t NVRAM_image,
 121                                    int width, int height, int depth,
 122                                    const uint8_t *macaddr)
 123 {
 124     unsigned int i;
 125     uint32_t start, end;
 126     uint8_t image[0x1ff0];
 127     struct OpenBIOS_nvpart_v1 *part_header;
 128
 129     memset(image, '\0', sizeof(image));
 130
 131     start = 0;
 132
 133     // OpenBIOS nvram variables
 134     // Variable partition
 135     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 136     part_header->signature = OPENBIOS_PART_SYSTEM;
 137     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 138
 139     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 140     for (i = 0; i < nb_prom_envs; i++)
 141         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 142
 143     // End marker
 144     image[end++] = '\0';
 145
 146     end = start + ((end - start + 15) & ~15);
 147     OpenBIOS_finish_partition(part_header, end - start);
 148
 149     // free partition
 150     start = end;
 151     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 152     part_header->signature = OPENBIOS_PART_FREE;
 153     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 154
 155     end = 0x1fd0;
 156     OpenBIOS_finish_partition(part_header, end - start);
 157
 158     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 159
 160     for (i = 0; i < sizeof(image); i++)
 161         m48t59_write(nvram, i, image[i]);
 162
 163     return 0;
 164 }
 165 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 166                                        const char *initrd_filename,
 167                                        ram_addr_t RAM_size, long *initrd_size)
 168 {
 169     int linux_boot;
 170     unsigned int i;
 171     long kernel_size;
 172
 173     linux_boot = (kernel_filename != NULL);
 174
 175     kernel_size = 0;
 176     if (linux_boot) {
 177         int bswap_needed;
 178
 179 #ifdef BSWAP_NEEDED
 180         bswap_needed = 1;
 181 #else
 182         bswap_needed = 0;
 183 #endif
 184         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL,
 185                                1, ELF_MACHINE, 0);
 186         if (kernel_size < 0)
 187             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 188                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 189                                     TARGET_PAGE_SIZE);
 190         if (kernel_size < 0)
 191             kernel_size = load_image_targphys(kernel_filename,
 192                                               KERNEL_LOAD_ADDR,
 193                                               RAM_size - KERNEL_LOAD_ADDR);
 194         if (kernel_size < 0) {
 195             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 196                     kernel_filename);
 197             exit(1);
 198         }
 199
 200         /* load initrd */
 201         *initrd_size = 0;
 202         if (initrd_filename) {
 203             *initrd_size = load_image_targphys(initrd_filename,
 204                                                INITRD_LOAD_ADDR,
 205                                                RAM_size - INITRD_LOAD_ADDR);
 206             if (*initrd_size < 0) {
 207                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 208                         initrd_filename);
 209                 exit(1);
 210             }
 211         }
 212         if (*initrd_size > 0) {
 213             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 214                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 215                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 216                     stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
 217                     break;
 218                 }
 219             }
 220         }
 221     }
 222     return kernel_size;
 223 }
 224
 225 void pic_info(Monitor *mon)
 226 {
 227 }
 228
 229 void irq_info(Monitor *mon)
 230 {
 231 }
 232
 233 void cpu_check_irqs(CPUState *env)
 234 {
 235     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 236         ((env->softint & SOFTINT_TIMER) << 14);
 237
 238     if (pil && (env->interrupt_index == 0 ||
 239                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 240         unsigned int i;
 241
 242         for (i = 15; i > 0; i--) {
 243             if (pil & (1 << i)) {
 244                 int old_interrupt = env->interrupt_index;
 245
 246                 env->interrupt_index = TT_EXTINT | i;
 247                 if (old_interrupt != env->interrupt_index) {
 248                     CPUIRQ_DPRINTF("Set CPU IRQ %d\n", i);
 249                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 250                 }
 251                 break;
 252             }
 253         }
 254     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 255         CPUIRQ_DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 256         env->interrupt_index = 0;
 257         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 258     }
 259 }
 260
 261 static void cpu_set_irq(void *opaque, int irq, int level)
 262 {
 263     CPUState *env = opaque;
 264
 265     if (level) {
 266         CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
 267         env->halted = 0;
 268         env->pil_in |= 1 << irq;
 269         cpu_check_irqs(env);
 270     } else {
 271         CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
 272         env->pil_in &= ~(1 << irq);
 273         cpu_check_irqs(env);
 274     }
 275 }
 276
 277 typedef struct ResetData {
 278     CPUState *env;
 279     uint64_t prom_addr;
 280 } ResetData;
 281
 282 static void main_cpu_reset(void *opaque)
 283 {
 284     ResetData *s = (ResetData *)opaque;
 285     CPUState *env = s->env;
 286     static unsigned int nr_resets;
 287
 288     cpu_reset(env);
 289     env->tick_cmpr = TICK_INT_DIS | 0;
 290     ptimer_set_limit(env->tick, TICK_MAX, 1);
 291     ptimer_run(env->tick, 1);
 292     env->stick_cmpr = TICK_INT_DIS | 0;
 293     ptimer_set_limit(env->stick, TICK_MAX, 1);
 294     ptimer_run(env->stick, 1);
 295     env->hstick_cmpr = TICK_INT_DIS | 0;
 296     ptimer_set_limit(env->hstick, TICK_MAX, 1);
 297     ptimer_run(env->hstick, 1);
 298     env->gregs[1] = 0; // Memory start
 299     env->gregs[2] = ram_size; // Memory size
 300     env->gregs[3] = 0; // Machine description XXX
 301     if (nr_resets++ == 0) {
 302         /* Power on reset */
 303         env->pc = s->prom_addr + 0x20ULL;
 304     } else {
 305         env->pc = s->prom_addr + 0x40ULL;
 306     }
 307     env->npc = env->pc + 4;
 308 }
 309
 310 static void tick_irq(void *opaque)
 311 {
 312     CPUState *env = opaque;
 313
 314     if (!(env->tick_cmpr & TICK_INT_DIS)) {
 315         env->softint |= SOFTINT_TIMER;
 316         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 317     }
 318 }
 319
 320 static void stick_irq(void *opaque)
 321 {
 322     CPUState *env = opaque;
 323
 324     if (!(env->stick_cmpr & TICK_INT_DIS)) {
 325         env->softint |= SOFTINT_STIMER;
 326         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 327     }
 328 }
 329
 330 static void hstick_irq(void *opaque)
 331 {
 332     CPUState *env = opaque;
 333
 334     if (!(env->hstick_cmpr & TICK_INT_DIS)) {
 335         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 336     }
 337 }
 338
 339 void cpu_tick_set_count(void *opaque, uint64_t count)
 340 {
 341     ptimer_set_count(opaque, -count);
 342 }
 343
 344 uint64_t cpu_tick_get_count(void *opaque)
 345 {
 346     return -ptimer_get_count(opaque);
 347 }
 348
 349 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 350 {
 351     ptimer_set_limit(opaque, -limit, 0);
 352 }
 353
 354 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 355                               pcibus_t addr, pcibus_t size, int type)
 356 {
 357     EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
 358                  region_num, addr);
 359     switch (region_num) {
 360     case 0:
 361         isa_mmio_init(addr, 0x1000000);
 362         break;
 363     case 1:
 364         isa_mmio_init(addr, 0x800000);
 365         break;
 366     }
 367 }
 368
 369 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 370 {
 371 }
 372
 373 /* EBUS (Eight bit bus) bridge */
 374 static void
 375 pci_ebus_init(PCIBus *bus, int devfn)
 376 {
 377     qemu_irq *isa_irq;
 378
 379     pci_create_simple(bus, devfn, "ebus");
 380     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 381     isa_bus_irqs(isa_irq);
 382 }
 383
 384 static int
 385 pci_ebus_init1(PCIDevice *s)
 386 {
 387     isa_bus_new(&s->qdev);
 388
 389     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 390     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 391     s->config[0x04] = 0x06; // command = bus master, pci mem
 392     s->config[0x05] = 0x00;
 393     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 394     s->config[0x07] = 0x03; // status = medium devsel
 395     s->config[0x08] = 0x01; // revision
 396     s->config[0x09] = 0x00; // programming i/f
 397     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 398     s->config[0x0D] = 0x0a; // latency_timer
 399     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 400
 401     pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
 402                            ebus_mmio_mapfunc);
 403     pci_register_bar(s, 1, 0x800000,  PCI_BASE_ADDRESS_SPACE_MEMORY,
 404                            ebus_mmio_mapfunc);
 405     return 0;
 406 }
 407
 408 static PCIDeviceInfo ebus_info = {
 409     .qdev.name = "ebus",
 410     .qdev.size = sizeof(PCIDevice),
 411     .init = pci_ebus_init1,
 412 };
 413
 414 static void pci_ebus_register(void)
 415 {
 416     pci_qdev_register(&ebus_info);
 417 }
 418
 419 device_init(pci_ebus_register);
 420
 421 /* Boot PROM (OpenBIOS) */
 422 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 423 {
 424     DeviceState *dev;
 425     SysBusDevice *s;
 426     char *filename;
 427     int ret;
 428
 429     dev = qdev_create(NULL, "openprom");
 430     qdev_init_nofail(dev);
 431     s = sysbus_from_qdev(dev);
 432
 433     sysbus_mmio_map(s, 0, addr);
 434
 435     /* load boot prom */
 436     if (bios_name == NULL) {
 437         bios_name = PROM_FILENAME;
 438     }
 439     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 440     if (filename) {
 441         ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
 442                        1, ELF_MACHINE, 0);
 443         if (ret < 0 || ret > PROM_SIZE_MAX) {
 444             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 445         }
 446         qemu_free(filename);
 447     } else {
 448         ret = -1;
 449     }
 450     if (ret < 0 || ret > PROM_SIZE_MAX) {
 451         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 452         exit(1);
 453     }
 454 }
 455
 456 static int prom_init1(SysBusDevice *dev)
 457 {
 458     ram_addr_t prom_offset;
 459
 460     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 461     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 462     return 0;
 463 }
 464
 465 static SysBusDeviceInfo prom_info = {
 466     .init = prom_init1,
 467     .qdev.name  = "openprom",
 468     .qdev.size  = sizeof(SysBusDevice),
 469     .qdev.props = (Property[]) {
 470         {/* end of property list */}
 471     }
 472 };
 473
 474 static void prom_register_devices(void)
 475 {
 476     sysbus_register_withprop(&prom_info);
 477 }
 478
 479 device_init(prom_register_devices);
 480
 481
 482 typedef struct RamDevice
 483 {
 484     SysBusDevice busdev;
 485     uint64_t size;
 486 } RamDevice;
 487
 488 /* System RAM */
 489 static int ram_init1(SysBusDevice *dev)
 490 {
 491     ram_addr_t RAM_size, ram_offset;
 492     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 493
 494     RAM_size = d->size;
 495
 496     ram_offset = qemu_ram_alloc(RAM_size);
 497     sysbus_init_mmio(dev, RAM_size, ram_offset);
 498     return 0;
 499 }
 500
 501 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 502 {
 503     DeviceState *dev;
 504     SysBusDevice *s;
 505     RamDevice *d;
 506
 507     /* allocate RAM */
 508     dev = qdev_create(NULL, "memory");
 509     s = sysbus_from_qdev(dev);
 510
 511     d = FROM_SYSBUS(RamDevice, s);
 512     d->size = RAM_size;
 513     qdev_init_nofail(dev);
 514
 515     sysbus_mmio_map(s, 0, addr);
 516 }
 517
 518 static SysBusDeviceInfo ram_info = {
 519     .init = ram_init1,
 520     .qdev.name  = "memory",
 521     .qdev.size  = sizeof(RamDevice),
 522     .qdev.props = (Property[]) {
 523         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 524         DEFINE_PROP_END_OF_LIST(),
 525     }
 526 };
 527
 528 static void ram_register_devices(void)
 529 {
 530     sysbus_register_withprop(&ram_info);
 531 }
 532
 533 device_init(ram_register_devices);
 534
 535 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 536 {
 537     CPUState *env;
 538     QEMUBH *bh;
 539     ResetData *reset_info;
 540
 541     if (!cpu_model)
 542         cpu_model = hwdef->default_cpu_model;
 543     env = cpu_init(cpu_model);
 544     if (!env) {
 545         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 546         exit(1);
 547     }
 548     bh = qemu_bh_new(tick_irq, env);
 549     env->tick = ptimer_init(bh);
 550     ptimer_set_period(env->tick, 1ULL);
 551
 552     bh = qemu_bh_new(stick_irq, env);
 553     env->stick = ptimer_init(bh);
 554     ptimer_set_period(env->stick, 1ULL);
 555
 556     bh = qemu_bh_new(hstick_irq, env);
 557     env->hstick = ptimer_init(bh);
 558     ptimer_set_period(env->hstick, 1ULL);
 559
 560     reset_info = qemu_mallocz(sizeof(ResetData));
 561     reset_info->env = env;
 562     reset_info->prom_addr = hwdef->prom_addr;
 563     qemu_register_reset(main_cpu_reset, reset_info);
 564
 565     return env;
 566 }
 567
 568 static void sun4uv_init(ram_addr_t RAM_size,
 569                         const char *boot_devices,
 570                         const char *kernel_filename, const char *kernel_cmdline,
 571                         const char *initrd_filename, const char *cpu_model,
 572                         const struct hwdef *hwdef)
 573 {
 574     CPUState *env;
 575     m48t59_t *nvram;
 576     unsigned int i;
 577     long initrd_size, kernel_size;
 578     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 579     qemu_irq *irq;
 580     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 581     DriveInfo *fd[MAX_FD];
 582     void *fw_cfg;
 583
 584     /* init CPUs */
 585     env = cpu_devinit(cpu_model, hwdef);
 586
 587     /* set up devices */
 588     ram_init(0, RAM_size);
 589
 590     prom_init(hwdef->prom_addr, bios_name);
 591
 592
 593     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 594     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 595                            &pci_bus3);
 596     isa_mem_base = VGA_BASE;
 597     pci_vga_init(pci_bus, 0, 0);
 598
 599     // XXX Should be pci_bus3
 600     pci_ebus_init(pci_bus, -1);
 601
 602     i = 0;
 603     if (hwdef->console_serial_base) {
 604         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 605                        serial_hds[i], 1);
 606         i++;
 607     }
 608     for(; i < MAX_SERIAL_PORTS; i++) {
 609         if (serial_hds[i]) {
 610             serial_isa_init(i, serial_hds[i]);
 611         }
 612     }
 613
 614     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 615         if (parallel_hds[i]) {
 616             parallel_init(i, parallel_hds[i]);
 617         }
 618     }
 619
 620     for(i = 0; i < nb_nics; i++)
 621         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 622
 623     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 624         fprintf(stderr, "qemu: too many IDE bus\n");
 625         exit(1);
 626     }
 627     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 628         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 629                           i % MAX_IDE_DEVS);
 630     }
 631
 632     pci_cmd646_ide_init(pci_bus, hd, 1);
 633
 634     isa_create_simple("i8042");
 635     for(i = 0; i < MAX_FD; i++) {
 636         fd[i] = drive_get(IF_FLOPPY, 0, i);
 637     }
 638     fdctrl_init_isa(fd);
 639     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 640
 641     initrd_size = 0;
 642     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 643                                     ram_size, &initrd_size);
 644
 645     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 646                            KERNEL_LOAD_ADDR, kernel_size,
 647                            kernel_cmdline,
 648                            INITRD_LOAD_ADDR, initrd_size,
 649                            /* XXX: need an option to load a NVRAM image */
 650                            0,
 651                            graphic_width, graphic_height, graphic_depth,
 652                            (uint8_t *)&nd_table[0].macaddr);
 653
 654     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 655     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 656     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 657     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 658     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 659     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 660     if (kernel_cmdline) {
 661         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 662         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 663         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 664                          (uint8_t*)strdup(kernel_cmdline),
 665                          strlen(kernel_cmdline) + 1);
 666     } else {
 667         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 668     }
 669     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 670     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 671     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 672
 673     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 674     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 675     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 676
 677     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 678 }
 679
 680 enum {
 681     sun4u_id = 0,
 682     sun4v_id = 64,
 683     niagara_id,
 684 };
 685
 686 static const struct hwdef hwdefs[] = {
 687     /* Sun4u generic PC-like machine */
 688     {
 689         .default_cpu_model = "TI UltraSparc II",
 690         .machine_id = sun4u_id,
 691         .prom_addr = 0x1fff0000000ULL,
 692         .console_serial_base = 0,
 693     },
 694     /* Sun4v generic PC-like machine */
 695     {
 696         .default_cpu_model = "Sun UltraSparc T1",
 697         .machine_id = sun4v_id,
 698         .prom_addr = 0x1fff0000000ULL,
 699         .console_serial_base = 0,
 700     },
 701     /* Sun4v generic Niagara machine */
 702     {
 703         .default_cpu_model = "Sun UltraSparc T1",
 704         .machine_id = niagara_id,
 705         .prom_addr = 0xfff0000000ULL,
 706         .console_serial_base = 0xfff0c2c000ULL,
 707     },
 708 };
 709
 710 /* Sun4u hardware initialisation */
 711 static void sun4u_init(ram_addr_t RAM_size,
 712                        const char *boot_devices,
 713                        const char *kernel_filename, const char *kernel_cmdline,
 714                        const char *initrd_filename, const char *cpu_model)
 715 {
 716     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 717                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 718 }
 719
 720 /* Sun4v hardware initialisation */
 721 static void sun4v_init(ram_addr_t RAM_size,
 722                        const char *boot_devices,
 723                        const char *kernel_filename, const char *kernel_cmdline,
 724                        const char *initrd_filename, const char *cpu_model)
 725 {
 726     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 727                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 728 }
 729
 730 /* Niagara hardware initialisation */
 731 static void niagara_init(ram_addr_t RAM_size,
 732                          const char *boot_devices,
 733                          const char *kernel_filename, const char *kernel_cmdline,
 734                          const char *initrd_filename, const char *cpu_model)
 735 {
 736     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 737                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 738 }
 739
 740 static QEMUMachine sun4u_machine = {
 741     .name = "sun4u",
 742     .desc = "Sun4u platform",
 743     .init = sun4u_init,
 744     .max_cpus = 1, // XXX for now
 745     .is_default = 1,
 746 };
 747
 748 static QEMUMachine sun4v_machine = {
 749     .name = "sun4v",
 750     .desc = "Sun4v platform",
 751     .init = sun4v_init,
 752     .max_cpus = 1, // XXX for now
 753 };
 754
 755 static QEMUMachine niagara_machine = {
 756     .name = "Niagara",
 757     .desc = "Sun4v platform, Niagara",
 758     .init = niagara_init,
 759     .max_cpus = 1, // XXX for now
 760 };
 761
 762 static void sun4u_machine_init(void)
 763 {
 764     qemu_register_machine(&sun4u_machine);
 765     qemu_register_machine(&sun4v_machine);
 766     qemu_register_machine(&niagara_machine);
 767 }
 768
 769 machine_init(sun4u_machine_init);