4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu-common.h"
21 #ifdef CONFIG_USER_ONLY
33 #include "qemu-char.h"
38 #define MAX_PACKET_LENGTH 4096
40 #include "qemu_socket.h"
48 GDB_SIGNAL_UNKNOWN
= 143
51 #ifdef CONFIG_USER_ONLY
53 /* Map target signal numbers to GDB protocol signal numbers and vice
54 * versa. For user emulation's currently supported systems, we can
55 * assume most signals are defined.
58 static int gdb_signal_table
[] = {
218 /* In system mode we only need SIGINT and SIGTRAP; other signals
219 are not yet supported. */
226 static int gdb_signal_table
[] = {
236 #ifdef CONFIG_USER_ONLY
237 static int target_signal_to_gdb (int sig
)
240 for (i
= 0; i
< ARRAY_SIZE (gdb_signal_table
); i
++)
241 if (gdb_signal_table
[i
] == sig
)
243 return GDB_SIGNAL_UNKNOWN
;
247 static int gdb_signal_to_target (int sig
)
249 if (sig
< ARRAY_SIZE (gdb_signal_table
))
250 return gdb_signal_table
[sig
];
257 typedef struct GDBRegisterState
{
263 struct GDBRegisterState
*next
;
274 typedef struct GDBState
{
275 CPUState
*c_cpu
; /* current CPU for step/continue ops */
276 CPUState
*g_cpu
; /* current CPU for other ops */
277 CPUState
*query_cpu
; /* for q{f|s}ThreadInfo */
278 enum RSState state
; /* parsing state */
279 char line_buf
[MAX_PACKET_LENGTH
];
282 uint8_t last_packet
[MAX_PACKET_LENGTH
+ 4];
285 #ifdef CONFIG_USER_ONLY
289 CharDriverState
*chr
;
290 CharDriverState
*mon_chr
;
294 /* By default use no IRQs and no timers while single stepping so as to
295 * make single stepping like an ICE HW step.
297 static int sstep_flags
= SSTEP_ENABLE
|SSTEP_NOIRQ
|SSTEP_NOTIMER
;
299 static GDBState
*gdbserver_state
;
301 /* This is an ugly hack to cope with both new and old gdb.
302 If gdb sends qXfer:features:read then assume we're talking to a newish
303 gdb that understands target descriptions. */
304 static int gdb_has_xml
;
306 #ifdef CONFIG_USER_ONLY
307 /* XXX: This is not thread safe. Do we care? */
308 static int gdbserver_fd
= -1;
310 static int get_char(GDBState
*s
)
316 ret
= recv(s
->fd
, &ch
, 1, 0);
318 if (errno
== ECONNRESET
)
320 if (errno
!= EINTR
&& errno
!= EAGAIN
)
322 } else if (ret
== 0) {
334 static gdb_syscall_complete_cb gdb_current_syscall_cb
;
342 /* If gdb is connected when the first semihosting syscall occurs then use
343 remote gdb syscalls. Otherwise use native file IO. */
344 int use_gdb_syscalls(void)
346 if (gdb_syscall_mode
== GDB_SYS_UNKNOWN
) {
347 gdb_syscall_mode
= (gdbserver_state
? GDB_SYS_ENABLED
350 return gdb_syscall_mode
== GDB_SYS_ENABLED
;
353 /* Resume execution. */
354 static inline void gdb_continue(GDBState
*s
)
356 #ifdef CONFIG_USER_ONLY
357 s
->running_state
= 1;
363 static void put_buffer(GDBState
*s
, const uint8_t *buf
, int len
)
365 #ifdef CONFIG_USER_ONLY
369 ret
= send(s
->fd
, buf
, len
, 0);
371 if (errno
!= EINTR
&& errno
!= EAGAIN
)
379 qemu_chr_write(s
->chr
, buf
, len
);
383 static inline int fromhex(int v
)
385 if (v
>= '0' && v
<= '9')
387 else if (v
>= 'A' && v
<= 'F')
389 else if (v
>= 'a' && v
<= 'f')
395 static inline int tohex(int v
)
403 static void memtohex(char *buf
, const uint8_t *mem
, int len
)
408 for(i
= 0; i
< len
; i
++) {
410 *q
++ = tohex(c
>> 4);
411 *q
++ = tohex(c
& 0xf);
416 static void hextomem(uint8_t *mem
, const char *buf
, int len
)
420 for(i
= 0; i
< len
; i
++) {
421 mem
[i
] = (fromhex(buf
[0]) << 4) | fromhex(buf
[1]);
426 /* return -1 if error, 0 if OK */
427 static int put_packet_binary(GDBState
*s
, const char *buf
, int len
)
438 for(i
= 0; i
< len
; i
++) {
442 *(p
++) = tohex((csum
>> 4) & 0xf);
443 *(p
++) = tohex((csum
) & 0xf);
445 s
->last_packet_len
= p
- s
->last_packet
;
446 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
448 #ifdef CONFIG_USER_ONLY
461 /* return -1 if error, 0 if OK */
462 static int put_packet(GDBState
*s
, const char *buf
)
465 printf("reply='%s'\n", buf
);
468 return put_packet_binary(s
, buf
, strlen(buf
));
471 /* The GDB remote protocol transfers values in target byte order. This means
472 we can use the raw memory access routines to access the value buffer.
473 Conveniently, these also handle the case where the buffer is mis-aligned.
475 #define GET_REG8(val) do { \
476 stb_p(mem_buf, val); \
479 #define GET_REG16(val) do { \
480 stw_p(mem_buf, val); \
483 #define GET_REG32(val) do { \
484 stl_p(mem_buf, val); \
487 #define GET_REG64(val) do { \
488 stq_p(mem_buf, val); \
492 #if TARGET_LONG_BITS == 64
493 #define GET_REGL(val) GET_REG64(val)
494 #define ldtul_p(addr) ldq_p(addr)
496 #define GET_REGL(val) GET_REG32(val)
497 #define ldtul_p(addr) ldl_p(addr)
500 #if defined(TARGET_I386)
503 static const int gpr_map
[16] = {
504 R_EAX
, R_EBX
, R_ECX
, R_EDX
, R_ESI
, R_EDI
, R_EBP
, R_ESP
,
505 8, 9, 10, 11, 12, 13, 14, 15
508 #define gpr_map gpr_map32
510 static const int gpr_map32
[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
512 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
514 #define IDX_IP_REG CPU_NB_REGS
515 #define IDX_FLAGS_REG (IDX_IP_REG + 1)
516 #define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
517 #define IDX_FP_REGS (IDX_SEG_REGS + 6)
518 #define IDX_XMM_REGS (IDX_FP_REGS + 16)
519 #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
521 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
523 if (n
< CPU_NB_REGS
) {
524 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
525 GET_REG64(env
->regs
[gpr_map
[n
]]);
526 } else if (n
< CPU_NB_REGS32
) {
527 GET_REG32(env
->regs
[gpr_map32
[n
]]);
529 } else if (n
>= IDX_FP_REGS
&& n
< IDX_FP_REGS
+ 8) {
530 #ifdef USE_X86LDOUBLE
531 /* FIXME: byteswap float values - after fixing fpregs layout. */
532 memcpy(mem_buf
, &env
->fpregs
[n
- IDX_FP_REGS
], 10);
534 memset(mem_buf
, 0, 10);
537 } else if (n
>= IDX_XMM_REGS
&& n
< IDX_XMM_REGS
+ CPU_NB_REGS
) {
539 if (n
< CPU_NB_REGS32
||
540 (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
)) {
541 stq_p(mem_buf
, env
->xmm_regs
[n
].XMM_Q(0));
542 stq_p(mem_buf
+ 8, env
->xmm_regs
[n
].XMM_Q(1));
548 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
553 case IDX_FLAGS_REG
: GET_REG32(env
->eflags
);
555 case IDX_SEG_REGS
: GET_REG32(env
->segs
[R_CS
].selector
);
556 case IDX_SEG_REGS
+ 1: GET_REG32(env
->segs
[R_SS
].selector
);
557 case IDX_SEG_REGS
+ 2: GET_REG32(env
->segs
[R_DS
].selector
);
558 case IDX_SEG_REGS
+ 3: GET_REG32(env
->segs
[R_ES
].selector
);
559 case IDX_SEG_REGS
+ 4: GET_REG32(env
->segs
[R_FS
].selector
);
560 case IDX_SEG_REGS
+ 5: GET_REG32(env
->segs
[R_GS
].selector
);
562 case IDX_FP_REGS
+ 8: GET_REG32(env
->fpuc
);
563 case IDX_FP_REGS
+ 9: GET_REG32((env
->fpus
& ~0x3800) |
564 (env
->fpstt
& 0x7) << 11);
565 case IDX_FP_REGS
+ 10: GET_REG32(0); /* ftag */
566 case IDX_FP_REGS
+ 11: GET_REG32(0); /* fiseg */
567 case IDX_FP_REGS
+ 12: GET_REG32(0); /* fioff */
568 case IDX_FP_REGS
+ 13: GET_REG32(0); /* foseg */
569 case IDX_FP_REGS
+ 14: GET_REG32(0); /* fooff */
570 case IDX_FP_REGS
+ 15: GET_REG32(0); /* fop */
572 case IDX_MXCSR_REG
: GET_REG32(env
->mxcsr
);
578 static int cpu_x86_gdb_load_seg(CPUState
*env
, int sreg
, uint8_t *mem_buf
)
580 uint16_t selector
= ldl_p(mem_buf
);
582 if (selector
!= env
->segs
[sreg
].selector
) {
583 #if defined(CONFIG_USER_ONLY)
584 cpu_x86_load_seg(env
, sreg
, selector
);
586 unsigned int limit
, flags
;
589 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
590 base
= selector
<< 4;
594 if (!cpu_x86_get_descr_debug(env
, selector
, &base
, &limit
, &flags
))
597 cpu_x86_load_seg_cache(env
, sreg
, selector
, base
, limit
, flags
);
603 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
607 if (n
< CPU_NB_REGS
) {
608 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
609 env
->regs
[gpr_map
[n
]] = ldtul_p(mem_buf
);
610 return sizeof(target_ulong
);
611 } else if (n
< CPU_NB_REGS32
) {
613 env
->regs
[n
] &= ~0xffffffffUL
;
614 env
->regs
[n
] |= (uint32_t)ldl_p(mem_buf
);
617 } else if (n
>= IDX_FP_REGS
&& n
< IDX_FP_REGS
+ 8) {
618 #ifdef USE_X86LDOUBLE
619 /* FIXME: byteswap float values - after fixing fpregs layout. */
620 memcpy(&env
->fpregs
[n
- IDX_FP_REGS
], mem_buf
, 10);
623 } else if (n
>= IDX_XMM_REGS
&& n
< IDX_XMM_REGS
+ CPU_NB_REGS
) {
625 if (n
< CPU_NB_REGS32
||
626 (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
)) {
627 env
->xmm_regs
[n
].XMM_Q(0) = ldq_p(mem_buf
);
628 env
->xmm_regs
[n
].XMM_Q(1) = ldq_p(mem_buf
+ 8);
634 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
635 env
->eip
= ldq_p(mem_buf
);
638 env
->eip
&= ~0xffffffffUL
;
639 env
->eip
|= (uint32_t)ldl_p(mem_buf
);
643 env
->eflags
= ldl_p(mem_buf
);
646 case IDX_SEG_REGS
: return cpu_x86_gdb_load_seg(env
, R_CS
, mem_buf
);
647 case IDX_SEG_REGS
+ 1: return cpu_x86_gdb_load_seg(env
, R_SS
, mem_buf
);
648 case IDX_SEG_REGS
+ 2: return cpu_x86_gdb_load_seg(env
, R_DS
, mem_buf
);
649 case IDX_SEG_REGS
+ 3: return cpu_x86_gdb_load_seg(env
, R_ES
, mem_buf
);
650 case IDX_SEG_REGS
+ 4: return cpu_x86_gdb_load_seg(env
, R_FS
, mem_buf
);
651 case IDX_SEG_REGS
+ 5: return cpu_x86_gdb_load_seg(env
, R_GS
, mem_buf
);
653 case IDX_FP_REGS
+ 8:
654 env
->fpuc
= ldl_p(mem_buf
);
656 case IDX_FP_REGS
+ 9:
657 tmp
= ldl_p(mem_buf
);
658 env
->fpstt
= (tmp
>> 11) & 7;
659 env
->fpus
= tmp
& ~0x3800;
661 case IDX_FP_REGS
+ 10: /* ftag */ return 4;
662 case IDX_FP_REGS
+ 11: /* fiseg */ return 4;
663 case IDX_FP_REGS
+ 12: /* fioff */ return 4;
664 case IDX_FP_REGS
+ 13: /* foseg */ return 4;
665 case IDX_FP_REGS
+ 14: /* fooff */ return 4;
666 case IDX_FP_REGS
+ 15: /* fop */ return 4;
669 env
->mxcsr
= ldl_p(mem_buf
);
673 /* Unrecognised register. */
677 #elif defined (TARGET_PPC)
679 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
680 expects whatever the target description contains. Due to a
681 historical mishap the FP registers appear in between core integer
682 regs and PC, MSR, CR, and so forth. We hack round this by giving the
683 FP regs zero size when talking to a newer gdb. */
684 #define NUM_CORE_REGS 71
685 #if defined (TARGET_PPC64)
686 #define GDB_CORE_XML "power64-core.xml"
688 #define GDB_CORE_XML "power-core.xml"
691 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
695 GET_REGL(env
->gpr
[n
]);
700 stfq_p(mem_buf
, env
->fpr
[n
-32]);
704 case 64: GET_REGL(env
->nip
);
705 case 65: GET_REGL(env
->msr
);
710 for (i
= 0; i
< 8; i
++)
711 cr
|= env
->crf
[i
] << (32 - ((i
+ 1) * 4));
714 case 67: GET_REGL(env
->lr
);
715 case 68: GET_REGL(env
->ctr
);
716 case 69: GET_REGL(env
->xer
);
721 GET_REG32(0); /* fpscr */
728 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
732 env
->gpr
[n
] = ldtul_p(mem_buf
);
733 return sizeof(target_ulong
);
738 env
->fpr
[n
-32] = ldfq_p(mem_buf
);
743 env
->nip
= ldtul_p(mem_buf
);
744 return sizeof(target_ulong
);
746 ppc_store_msr(env
, ldtul_p(mem_buf
));
747 return sizeof(target_ulong
);
750 uint32_t cr
= ldl_p(mem_buf
);
752 for (i
= 0; i
< 8; i
++)
753 env
->crf
[i
] = (cr
>> (32 - ((i
+ 1) * 4))) & 0xF;
757 env
->lr
= ldtul_p(mem_buf
);
758 return sizeof(target_ulong
);
760 env
->ctr
= ldtul_p(mem_buf
);
761 return sizeof(target_ulong
);
763 env
->xer
= ldtul_p(mem_buf
);
764 return sizeof(target_ulong
);
775 #elif defined (TARGET_SPARC)
777 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
778 #define NUM_CORE_REGS 86
780 #define NUM_CORE_REGS 72
784 #define GET_REGA(val) GET_REG32(val)
786 #define GET_REGA(val) GET_REGL(val)
789 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
793 GET_REGA(env
->gregs
[n
]);
796 /* register window */
797 GET_REGA(env
->regwptr
[n
- 8]);
799 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
802 GET_REG32(*((uint32_t *)&env
->fpr
[n
- 32]));
804 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
806 case 64: GET_REGA(env
->y
);
807 case 65: GET_REGA(GET_PSR(env
));
808 case 66: GET_REGA(env
->wim
);
809 case 67: GET_REGA(env
->tbr
);
810 case 68: GET_REGA(env
->pc
);
811 case 69: GET_REGA(env
->npc
);
812 case 70: GET_REGA(env
->fsr
);
813 case 71: GET_REGA(0); /* csr */
814 default: GET_REGA(0);
819 GET_REG32(*((uint32_t *)&env
->fpr
[n
- 32]));
822 /* f32-f62 (double width, even numbers only) */
825 val
= (uint64_t)*((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 32]) << 32;
826 val
|= *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 33]);
830 case 80: GET_REGL(env
->pc
);
831 case 81: GET_REGL(env
->npc
);
832 case 82: GET_REGL(((uint64_t)GET_CCR(env
) << 32) |
833 ((env
->asi
& 0xff) << 24) |
834 ((env
->pstate
& 0xfff) << 8) |
836 case 83: GET_REGL(env
->fsr
);
837 case 84: GET_REGL(env
->fprs
);
838 case 85: GET_REGL(env
->y
);
844 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
846 #if defined(TARGET_ABI32)
849 tmp
= ldl_p(mem_buf
);
853 tmp
= ldtul_p(mem_buf
);
860 /* register window */
861 env
->regwptr
[n
- 8] = tmp
;
863 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
866 *((uint32_t *)&env
->fpr
[n
- 32]) = tmp
;
868 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
870 case 64: env
->y
= tmp
; break;
871 case 65: PUT_PSR(env
, tmp
); break;
872 case 66: env
->wim
= tmp
; break;
873 case 67: env
->tbr
= tmp
; break;
874 case 68: env
->pc
= tmp
; break;
875 case 69: env
->npc
= tmp
; break;
876 case 70: env
->fsr
= tmp
; break;
884 env
->fpr
[n
] = ldfl_p(mem_buf
);
887 /* f32-f62 (double width, even numbers only) */
888 *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 32]) = tmp
>> 32;
889 *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 33]) = tmp
;
892 case 80: env
->pc
= tmp
; break;
893 case 81: env
->npc
= tmp
; break;
895 PUT_CCR(env
, tmp
>> 32);
896 env
->asi
= (tmp
>> 24) & 0xff;
897 env
->pstate
= (tmp
>> 8) & 0xfff;
898 PUT_CWP64(env
, tmp
& 0xff);
900 case 83: env
->fsr
= tmp
; break;
901 case 84: env
->fprs
= tmp
; break;
902 case 85: env
->y
= tmp
; break;
909 #elif defined (TARGET_ARM)
911 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
912 whatever the target description contains. Due to a historical mishap
913 the FPA registers appear in between core integer regs and the CPSR.
914 We hack round this by giving the FPA regs zero size when talking to a
916 #define NUM_CORE_REGS 26
917 #define GDB_CORE_XML "arm-core.xml"
919 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
922 /* Core integer register. */
923 GET_REG32(env
->regs
[n
]);
929 memset(mem_buf
, 0, 12);
934 /* FPA status register. */
940 GET_REG32(cpsr_read(env
));
942 /* Unknown register. */
946 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
950 tmp
= ldl_p(mem_buf
);
952 /* Mask out low bit of PC to workaround gdb bugs. This will probably
953 cause problems if we ever implement the Jazelle DBX extensions. */
958 /* Core integer register. */
962 if (n
< 24) { /* 16-23 */
963 /* FPA registers (ignored). */
970 /* FPA status register (ignored). */
976 cpsr_write (env
, tmp
, 0xffffffff);
979 /* Unknown register. */
983 #elif defined (TARGET_M68K)
985 #define NUM_CORE_REGS 18
987 #define GDB_CORE_XML "cf-core.xml"
989 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
993 GET_REG32(env
->dregs
[n
]);
996 GET_REG32(env
->aregs
[n
- 8]);
999 case 16: GET_REG32(env
->sr
);
1000 case 17: GET_REG32(env
->pc
);
1003 /* FP registers not included here because they vary between
1004 ColdFire and m68k. Use XML bits for these. */
1008 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1012 tmp
= ldl_p(mem_buf
);
1016 env
->dregs
[n
] = tmp
;
1017 } else if (n
< 16) {
1019 env
->aregs
[n
- 8] = tmp
;
1022 case 16: env
->sr
= tmp
; break;
1023 case 17: env
->pc
= tmp
; break;
1029 #elif defined (TARGET_MIPS)
1031 #define NUM_CORE_REGS 73
1033 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1036 GET_REGL(env
->active_tc
.gpr
[n
]);
1038 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
1039 if (n
>= 38 && n
< 70) {
1040 if (env
->CP0_Status
& (1 << CP0St_FR
))
1041 GET_REGL(env
->active_fpu
.fpr
[n
- 38].d
);
1043 GET_REGL(env
->active_fpu
.fpr
[n
- 38].w
[FP_ENDIAN_IDX
]);
1046 case 70: GET_REGL((int32_t)env
->active_fpu
.fcr31
);
1047 case 71: GET_REGL((int32_t)env
->active_fpu
.fcr0
);
1051 case 32: GET_REGL((int32_t)env
->CP0_Status
);
1052 case 33: GET_REGL(env
->active_tc
.LO
[0]);
1053 case 34: GET_REGL(env
->active_tc
.HI
[0]);
1054 case 35: GET_REGL(env
->CP0_BadVAddr
);
1055 case 36: GET_REGL((int32_t)env
->CP0_Cause
);
1056 case 37: GET_REGL(env
->active_tc
.PC
| !!(env
->hflags
& MIPS_HFLAG_M16
));
1057 case 72: GET_REGL(0); /* fp */
1058 case 89: GET_REGL((int32_t)env
->CP0_PRid
);
1060 if (n
>= 73 && n
<= 88) {
1061 /* 16 embedded regs. */
1068 /* convert MIPS rounding mode in FCR31 to IEEE library */
1069 static unsigned int ieee_rm
[] =
1071 float_round_nearest_even
,
1072 float_round_to_zero
,
1076 #define RESTORE_ROUNDING_MODE \
1077 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1079 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1083 tmp
= ldtul_p(mem_buf
);
1086 env
->active_tc
.gpr
[n
] = tmp
;
1087 return sizeof(target_ulong
);
1089 if (env
->CP0_Config1
& (1 << CP0C1_FP
)
1090 && n
>= 38 && n
< 73) {
1092 if (env
->CP0_Status
& (1 << CP0St_FR
))
1093 env
->active_fpu
.fpr
[n
- 38].d
= tmp
;
1095 env
->active_fpu
.fpr
[n
- 38].w
[FP_ENDIAN_IDX
] = tmp
;
1099 env
->active_fpu
.fcr31
= tmp
& 0xFF83FFFF;
1100 /* set rounding mode */
1101 RESTORE_ROUNDING_MODE
;
1102 #ifndef CONFIG_SOFTFLOAT
1103 /* no floating point exception for native float */
1104 SET_FP_ENABLE(env
->active_fpu
.fcr31
, 0);
1107 case 71: env
->active_fpu
.fcr0
= tmp
; break;
1109 return sizeof(target_ulong
);
1112 case 32: env
->CP0_Status
= tmp
; break;
1113 case 33: env
->active_tc
.LO
[0] = tmp
; break;
1114 case 34: env
->active_tc
.HI
[0] = tmp
; break;
1115 case 35: env
->CP0_BadVAddr
= tmp
; break;
1116 case 36: env
->CP0_Cause
= tmp
; break;
1118 env
->active_tc
.PC
= tmp
& ~(target_ulong
)1;
1120 env
->hflags
|= MIPS_HFLAG_M16
;
1122 env
->hflags
&= ~(MIPS_HFLAG_M16
);
1125 case 72: /* fp, ignored */ break;
1129 /* Other registers are readonly. Ignore writes. */
1133 return sizeof(target_ulong
);
1135 #elif defined (TARGET_SH4)
1137 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1138 /* FIXME: We should use XML for this. */
1140 #define NUM_CORE_REGS 59
1142 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1145 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
1146 GET_REGL(env
->gregs
[n
+ 16]);
1148 GET_REGL(env
->gregs
[n
]);
1150 } else if (n
< 16) {
1151 GET_REGL(env
->gregs
[n
- 8]);
1152 } else if (n
>= 25 && n
< 41) {
1153 GET_REGL(env
->fregs
[(n
- 25) + ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
1154 } else if (n
>= 43 && n
< 51) {
1155 GET_REGL(env
->gregs
[n
- 43]);
1156 } else if (n
>= 51 && n
< 59) {
1157 GET_REGL(env
->gregs
[n
- (51 - 16)]);
1160 case 16: GET_REGL(env
->pc
);
1161 case 17: GET_REGL(env
->pr
);
1162 case 18: GET_REGL(env
->gbr
);
1163 case 19: GET_REGL(env
->vbr
);
1164 case 20: GET_REGL(env
->mach
);
1165 case 21: GET_REGL(env
->macl
);
1166 case 22: GET_REGL(env
->sr
);
1167 case 23: GET_REGL(env
->fpul
);
1168 case 24: GET_REGL(env
->fpscr
);
1169 case 41: GET_REGL(env
->ssr
);
1170 case 42: GET_REGL(env
->spc
);
1176 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1180 tmp
= ldl_p(mem_buf
);
1183 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
1184 env
->gregs
[n
+ 16] = tmp
;
1186 env
->gregs
[n
] = tmp
;
1189 } else if (n
< 16) {
1190 env
->gregs
[n
- 8] = tmp
;
1192 } else if (n
>= 25 && n
< 41) {
1193 env
->fregs
[(n
- 25) + ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)] = tmp
;
1194 } else if (n
>= 43 && n
< 51) {
1195 env
->gregs
[n
- 43] = tmp
;
1197 } else if (n
>= 51 && n
< 59) {
1198 env
->gregs
[n
- (51 - 16)] = tmp
;
1202 case 16: env
->pc
= tmp
;
1203 case 17: env
->pr
= tmp
;
1204 case 18: env
->gbr
= tmp
;
1205 case 19: env
->vbr
= tmp
;
1206 case 20: env
->mach
= tmp
;
1207 case 21: env
->macl
= tmp
;
1208 case 22: env
->sr
= tmp
;
1209 case 23: env
->fpul
= tmp
;
1210 case 24: env
->fpscr
= tmp
;
1211 case 41: env
->ssr
= tmp
;
1212 case 42: env
->spc
= tmp
;
1218 #elif defined (TARGET_MICROBLAZE)
1220 #define NUM_CORE_REGS (32 + 5)
1222 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1225 GET_REG32(env
->regs
[n
]);
1227 GET_REG32(env
->sregs
[n
- 32]);
1232 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1236 if (n
> NUM_CORE_REGS
)
1239 tmp
= ldl_p(mem_buf
);
1244 env
->sregs
[n
- 32] = tmp
;
1248 #elif defined (TARGET_CRIS)
1250 #define NUM_CORE_REGS 49
1253 read_register_crisv10(CPUState
*env
, uint8_t *mem_buf
, int n
)
1256 GET_REG32(env
->regs
[n
]);
1266 GET_REG8(env
->pregs
[n
- 16]);
1269 GET_REG8(env
->pregs
[n
- 16]);
1273 GET_REG16(env
->pregs
[n
- 16]);
1277 GET_REG32(env
->pregs
[n
- 16]);
1285 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1289 if (env
->pregs
[PR_VR
] < 32)
1290 return read_register_crisv10(env
, mem_buf
, n
);
1292 srs
= env
->pregs
[PR_SRS
];
1294 GET_REG32(env
->regs
[n
]);
1297 if (n
>= 21 && n
< 32) {
1298 GET_REG32(env
->pregs
[n
- 16]);
1300 if (n
>= 33 && n
< 49) {
1301 GET_REG32(env
->sregs
[srs
][n
- 33]);
1304 case 16: GET_REG8(env
->pregs
[0]);
1305 case 17: GET_REG8(env
->pregs
[1]);
1306 case 18: GET_REG32(env
->pregs
[2]);
1307 case 19: GET_REG8(srs
);
1308 case 20: GET_REG16(env
->pregs
[4]);
1309 case 32: GET_REG32(env
->pc
);
1315 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1322 tmp
= ldl_p(mem_buf
);
1328 if (n
>= 21 && n
< 32) {
1329 env
->pregs
[n
- 16] = tmp
;
1332 /* FIXME: Should support function regs be writable? */
1336 case 18: env
->pregs
[PR_PID
] = tmp
; break;
1339 case 32: env
->pc
= tmp
; break;
1344 #elif defined (TARGET_ALPHA)
1346 #define NUM_CORE_REGS 65
1348 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1351 GET_REGL(env
->ir
[n
]);
1359 val
= *((uint64_t *)&env
->fir
[n
-32]);
1363 GET_REGL(env
->fpcr
);
1375 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1378 tmp
= ldtul_p(mem_buf
);
1384 if (n
> 31 && n
< 63) {
1385 env
->fir
[n
- 32] = ldfl_p(mem_buf
);
1394 #elif defined (TARGET_S390X)
1396 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1398 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1401 case S390_PSWM_REGNUM
: GET_REGL(env
->psw
.mask
); break;
1402 case S390_PSWA_REGNUM
: GET_REGL(env
->psw
.addr
); break;
1403 case S390_R0_REGNUM
... S390_R15_REGNUM
:
1404 GET_REGL(env
->regs
[n
-S390_R0_REGNUM
]); break;
1405 case S390_A0_REGNUM
... S390_A15_REGNUM
:
1406 GET_REG32(env
->aregs
[n
-S390_A0_REGNUM
]); break;
1407 case S390_FPC_REGNUM
: GET_REG32(env
->fpc
); break;
1408 case S390_F0_REGNUM
... S390_F15_REGNUM
:
1411 case S390_PC_REGNUM
: GET_REGL(env
->psw
.addr
); break;
1412 case S390_CC_REGNUM
: GET_REG32(env
->cc
); break;
1418 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1423 tmpl
= ldtul_p(mem_buf
);
1424 tmp32
= ldl_p(mem_buf
);
1427 case S390_PSWM_REGNUM
: env
->psw
.mask
= tmpl
; break;
1428 case S390_PSWA_REGNUM
: env
->psw
.addr
= tmpl
; break;
1429 case S390_R0_REGNUM
... S390_R15_REGNUM
:
1430 env
->regs
[n
-S390_R0_REGNUM
] = tmpl
; break;
1431 case S390_A0_REGNUM
... S390_A15_REGNUM
:
1432 env
->aregs
[n
-S390_A0_REGNUM
] = tmp32
; r
=4; break;
1433 case S390_FPC_REGNUM
: env
->fpc
= tmp32
; r
=4; break;
1434 case S390_F0_REGNUM
... S390_F15_REGNUM
:
1437 case S390_PC_REGNUM
: env
->psw
.addr
= tmpl
; break;
1438 case S390_CC_REGNUM
: env
->cc
= tmp32
; r
=4; break;
1445 #define NUM_CORE_REGS 0
1447 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1452 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1459 static int num_g_regs
= NUM_CORE_REGS
;
1462 /* Encode data using the encoding for 'x' packets. */
1463 static int memtox(char *buf
, const char *mem
, int len
)
1471 case '#': case '$': case '*': case '}':
1483 static const char *get_feature_xml(const char *p
, const char **newp
)
1485 extern const char *const xml_builtin
[][2];
1489 static char target_xml
[1024];
1492 while (p
[len
] && p
[len
] != ':')
1497 if (strncmp(p
, "target.xml", len
) == 0) {
1498 /* Generate the XML description for this CPU. */
1499 if (!target_xml
[0]) {
1500 GDBRegisterState
*r
;
1502 snprintf(target_xml
, sizeof(target_xml
),
1503 "<?xml version=\"1.0\"?>"
1504 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1506 "<xi:include href=\"%s\"/>",
1509 for (r
= first_cpu
->gdb_regs
; r
; r
= r
->next
) {
1510 pstrcat(target_xml
, sizeof(target_xml
), "<xi:include href=\"");
1511 pstrcat(target_xml
, sizeof(target_xml
), r
->xml
);
1512 pstrcat(target_xml
, sizeof(target_xml
), "\"/>");
1514 pstrcat(target_xml
, sizeof(target_xml
), "</target>");
1518 for (i
= 0; ; i
++) {
1519 name
= xml_builtin
[i
][0];
1520 if (!name
|| (strncmp(name
, p
, len
) == 0 && strlen(name
) == len
))
1523 return name
? xml_builtin
[i
][1] : NULL
;
1527 static int gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int reg
)
1529 GDBRegisterState
*r
;
1531 if (reg
< NUM_CORE_REGS
)
1532 return cpu_gdb_read_register(env
, mem_buf
, reg
);
1534 for (r
= env
->gdb_regs
; r
; r
= r
->next
) {
1535 if (r
->base_reg
<= reg
&& reg
< r
->base_reg
+ r
->num_regs
) {
1536 return r
->get_reg(env
, mem_buf
, reg
- r
->base_reg
);
1542 static int gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int reg
)
1544 GDBRegisterState
*r
;
1546 if (reg
< NUM_CORE_REGS
)
1547 return cpu_gdb_write_register(env
, mem_buf
, reg
);
1549 for (r
= env
->gdb_regs
; r
; r
= r
->next
) {
1550 if (r
->base_reg
<= reg
&& reg
< r
->base_reg
+ r
->num_regs
) {
1551 return r
->set_reg(env
, mem_buf
, reg
- r
->base_reg
);
1557 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1558 specifies the first register number and these registers are included in
1559 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1560 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1563 void gdb_register_coprocessor(CPUState
* env
,
1564 gdb_reg_cb get_reg
, gdb_reg_cb set_reg
,
1565 int num_regs
, const char *xml
, int g_pos
)
1567 GDBRegisterState
*s
;
1568 GDBRegisterState
**p
;
1569 static int last_reg
= NUM_CORE_REGS
;
1571 s
= (GDBRegisterState
*)qemu_mallocz(sizeof(GDBRegisterState
));
1572 s
->base_reg
= last_reg
;
1573 s
->num_regs
= num_regs
;
1574 s
->get_reg
= get_reg
;
1575 s
->set_reg
= set_reg
;
1579 /* Check for duplicates. */
1580 if (strcmp((*p
)->xml
, xml
) == 0)
1584 /* Add to end of list. */
1585 last_reg
+= num_regs
;
1588 if (g_pos
!= s
->base_reg
) {
1589 fprintf(stderr
, "Error: Bad gdb register numbering for '%s'\n"
1590 "Expected %d got %d\n", xml
, g_pos
, s
->base_reg
);
1592 num_g_regs
= last_reg
;
1597 #ifndef CONFIG_USER_ONLY
1598 static const int xlat_gdb_type
[] = {
1599 [GDB_WATCHPOINT_WRITE
] = BP_GDB
| BP_MEM_WRITE
,
1600 [GDB_WATCHPOINT_READ
] = BP_GDB
| BP_MEM_READ
,
1601 [GDB_WATCHPOINT_ACCESS
] = BP_GDB
| BP_MEM_ACCESS
,
1605 static int gdb_breakpoint_insert(target_ulong addr
, target_ulong len
, int type
)
1611 return kvm_insert_breakpoint(gdbserver_state
->c_cpu
, addr
, len
, type
);
1614 case GDB_BREAKPOINT_SW
:
1615 case GDB_BREAKPOINT_HW
:
1616 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1617 err
= cpu_breakpoint_insert(env
, addr
, BP_GDB
, NULL
);
1622 #ifndef CONFIG_USER_ONLY
1623 case GDB_WATCHPOINT_WRITE
:
1624 case GDB_WATCHPOINT_READ
:
1625 case GDB_WATCHPOINT_ACCESS
:
1626 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1627 err
= cpu_watchpoint_insert(env
, addr
, len
, xlat_gdb_type
[type
],
1639 static int gdb_breakpoint_remove(target_ulong addr
, target_ulong len
, int type
)
1645 return kvm_remove_breakpoint(gdbserver_state
->c_cpu
, addr
, len
, type
);
1648 case GDB_BREAKPOINT_SW
:
1649 case GDB_BREAKPOINT_HW
:
1650 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1651 err
= cpu_breakpoint_remove(env
, addr
, BP_GDB
);
1656 #ifndef CONFIG_USER_ONLY
1657 case GDB_WATCHPOINT_WRITE
:
1658 case GDB_WATCHPOINT_READ
:
1659 case GDB_WATCHPOINT_ACCESS
:
1660 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1661 err
= cpu_watchpoint_remove(env
, addr
, len
, xlat_gdb_type
[type
]);
1672 static void gdb_breakpoint_remove_all(void)
1676 if (kvm_enabled()) {
1677 kvm_remove_all_breakpoints(gdbserver_state
->c_cpu
);
1681 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1682 cpu_breakpoint_remove_all(env
, BP_GDB
);
1683 #ifndef CONFIG_USER_ONLY
1684 cpu_watchpoint_remove_all(env
, BP_GDB
);
1689 static void gdb_set_cpu_pc(GDBState
*s
, target_ulong pc
)
1691 #if defined(TARGET_I386)
1692 cpu_synchronize_state(s
->c_cpu
);
1694 #elif defined (TARGET_PPC)
1696 #elif defined (TARGET_SPARC)
1698 s
->c_cpu
->npc
= pc
+ 4;
1699 #elif defined (TARGET_ARM)
1700 s
->c_cpu
->regs
[15] = pc
;
1701 #elif defined (TARGET_SH4)
1703 #elif defined (TARGET_MIPS)
1704 s
->c_cpu
->active_tc
.PC
= pc
& ~(target_ulong
)1;
1706 s
->c_cpu
->hflags
|= MIPS_HFLAG_M16
;
1708 s
->c_cpu
->hflags
&= ~(MIPS_HFLAG_M16
);
1710 #elif defined (TARGET_MICROBLAZE)
1711 s
->c_cpu
->sregs
[SR_PC
] = pc
;
1712 #elif defined (TARGET_CRIS)
1714 #elif defined (TARGET_ALPHA)
1716 #elif defined (TARGET_S390X)
1717 cpu_synchronize_state(s
->c_cpu
);
1718 s
->c_cpu
->psw
.addr
= pc
;
1722 static inline int gdb_id(CPUState
*env
)
1724 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1725 return env
->host_tid
;
1727 return env
->cpu_index
+ 1;
1731 static CPUState
*find_cpu(uint32_t thread_id
)
1735 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1736 if (gdb_id(env
) == thread_id
) {
1744 static int gdb_handle_packet(GDBState
*s
, const char *line_buf
)
1749 int ch
, reg_size
, type
, res
;
1750 char buf
[MAX_PACKET_LENGTH
];
1751 uint8_t mem_buf
[MAX_PACKET_LENGTH
];
1753 target_ulong addr
, len
;
1756 printf("command='%s'\n", line_buf
);
1762 /* TODO: Make this return the correct value for user-mode. */
1763 snprintf(buf
, sizeof(buf
), "T%02xthread:%02x;", GDB_SIGNAL_TRAP
,
1766 /* Remove all the breakpoints when this query is issued,
1767 * because gdb is doing and initial connect and the state
1768 * should be cleaned up.
1770 gdb_breakpoint_remove_all();
1774 addr
= strtoull(p
, (char **)&p
, 16);
1775 gdb_set_cpu_pc(s
, addr
);
1781 s
->signal
= gdb_signal_to_target (strtoul(p
, (char **)&p
, 16));
1782 if (s
->signal
== -1)
1787 if (strncmp(p
, "Cont", 4) == 0) {
1788 int res_signal
, res_thread
;
1792 put_packet(s
, "vCont;c;C;s;S");
1807 if (action
== 'C' || action
== 'S') {
1808 signal
= strtoul(p
, (char **)&p
, 16);
1809 } else if (action
!= 'c' && action
!= 's') {
1815 thread
= strtoull(p
+1, (char **)&p
, 16);
1817 action
= tolower(action
);
1818 if (res
== 0 || (res
== 'c' && action
== 's')) {
1820 res_signal
= signal
;
1821 res_thread
= thread
;
1825 if (res_thread
!= -1 && res_thread
!= 0) {
1826 env
= find_cpu(res_thread
);
1828 put_packet(s
, "E22");
1834 cpu_single_step(s
->c_cpu
, sstep_flags
);
1836 s
->signal
= res_signal
;
1842 goto unknown_command
;
1845 /* Kill the target */
1846 fprintf(stderr
, "\nQEMU: Terminated via GDBstub\n");
1850 gdb_breakpoint_remove_all();
1852 put_packet(s
, "OK");
1856 addr
= strtoull(p
, (char **)&p
, 16);
1857 gdb_set_cpu_pc(s
, addr
);
1859 cpu_single_step(s
->c_cpu
, sstep_flags
);
1867 ret
= strtoull(p
, (char **)&p
, 16);
1870 err
= strtoull(p
, (char **)&p
, 16);
1877 if (gdb_current_syscall_cb
)
1878 gdb_current_syscall_cb(s
->c_cpu
, ret
, err
);
1880 put_packet(s
, "T02");
1887 cpu_synchronize_state(s
->g_cpu
);
1889 for (addr
= 0; addr
< num_g_regs
; addr
++) {
1890 reg_size
= gdb_read_register(s
->g_cpu
, mem_buf
+ len
, addr
);
1893 memtohex(buf
, mem_buf
, len
);
1897 cpu_synchronize_state(s
->g_cpu
);
1898 registers
= mem_buf
;
1899 len
= strlen(p
) / 2;
1900 hextomem((uint8_t *)registers
, p
, len
);
1901 for (addr
= 0; addr
< num_g_regs
&& len
> 0; addr
++) {
1902 reg_size
= gdb_write_register(s
->g_cpu
, registers
, addr
);
1904 registers
+= reg_size
;
1906 put_packet(s
, "OK");
1909 addr
= strtoull(p
, (char **)&p
, 16);
1912 len
= strtoull(p
, NULL
, 16);
1913 if (cpu_memory_rw_debug(s
->g_cpu
, addr
, mem_buf
, len
, 0) != 0) {
1914 put_packet (s
, "E14");
1916 memtohex(buf
, mem_buf
, len
);
1921 addr
= strtoull(p
, (char **)&p
, 16);
1924 len
= strtoull(p
, (char **)&p
, 16);
1927 hextomem(mem_buf
, p
, len
);
1928 if (cpu_memory_rw_debug(s
->g_cpu
, addr
, mem_buf
, len
, 1) != 0)
1929 put_packet(s
, "E14");
1931 put_packet(s
, "OK");
1934 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1935 This works, but can be very slow. Anything new enough to
1936 understand XML also knows how to use this properly. */
1938 goto unknown_command
;
1939 addr
= strtoull(p
, (char **)&p
, 16);
1940 reg_size
= gdb_read_register(s
->g_cpu
, mem_buf
, addr
);
1942 memtohex(buf
, mem_buf
, reg_size
);
1945 put_packet(s
, "E14");
1950 goto unknown_command
;
1951 addr
= strtoull(p
, (char **)&p
, 16);
1954 reg_size
= strlen(p
) / 2;
1955 hextomem(mem_buf
, p
, reg_size
);
1956 gdb_write_register(s
->g_cpu
, mem_buf
, addr
);
1957 put_packet(s
, "OK");
1961 type
= strtoul(p
, (char **)&p
, 16);
1964 addr
= strtoull(p
, (char **)&p
, 16);
1967 len
= strtoull(p
, (char **)&p
, 16);
1969 res
= gdb_breakpoint_insert(addr
, len
, type
);
1971 res
= gdb_breakpoint_remove(addr
, len
, type
);
1973 put_packet(s
, "OK");
1974 else if (res
== -ENOSYS
)
1977 put_packet(s
, "E22");
1981 thread
= strtoull(p
, (char **)&p
, 16);
1982 if (thread
== -1 || thread
== 0) {
1983 put_packet(s
, "OK");
1986 env
= find_cpu(thread
);
1988 put_packet(s
, "E22");
1994 put_packet(s
, "OK");
1998 put_packet(s
, "OK");
2001 put_packet(s
, "E22");
2006 thread
= strtoull(p
, (char **)&p
, 16);
2007 env
= find_cpu(thread
);
2010 put_packet(s
, "OK");
2012 put_packet(s
, "E22");
2017 /* parse any 'q' packets here */
2018 if (!strcmp(p
,"qemu.sstepbits")) {
2019 /* Query Breakpoint bit definitions */
2020 snprintf(buf
, sizeof(buf
), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2026 } else if (strncmp(p
,"qemu.sstep",10) == 0) {
2027 /* Display or change the sstep_flags */
2030 /* Display current setting */
2031 snprintf(buf
, sizeof(buf
), "0x%x", sstep_flags
);
2036 type
= strtoul(p
, (char **)&p
, 16);
2038 put_packet(s
, "OK");
2040 } else if (strcmp(p
,"C") == 0) {
2041 /* "Current thread" remains vague in the spec, so always return
2042 * the first CPU (gdb returns the first thread). */
2043 put_packet(s
, "QC1");
2045 } else if (strcmp(p
,"fThreadInfo") == 0) {
2046 s
->query_cpu
= first_cpu
;
2047 goto report_cpuinfo
;
2048 } else if (strcmp(p
,"sThreadInfo") == 0) {
2051 snprintf(buf
, sizeof(buf
), "m%x", gdb_id(s
->query_cpu
));
2053 s
->query_cpu
= s
->query_cpu
->next_cpu
;
2057 } else if (strncmp(p
,"ThreadExtraInfo,", 16) == 0) {
2058 thread
= strtoull(p
+16, (char **)&p
, 16);
2059 env
= find_cpu(thread
);
2061 cpu_synchronize_state(env
);
2062 len
= snprintf((char *)mem_buf
, sizeof(mem_buf
),
2063 "CPU#%d [%s]", env
->cpu_index
,
2064 env
->halted
? "halted " : "running");
2065 memtohex(buf
, mem_buf
, len
);
2070 #ifdef CONFIG_USER_ONLY
2071 else if (strncmp(p
, "Offsets", 7) == 0) {
2072 TaskState
*ts
= s
->c_cpu
->opaque
;
2074 snprintf(buf
, sizeof(buf
),
2075 "Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
2076 ";Bss=" TARGET_ABI_FMT_lx
,
2077 ts
->info
->code_offset
,
2078 ts
->info
->data_offset
,
2079 ts
->info
->data_offset
);
2083 #else /* !CONFIG_USER_ONLY */
2084 else if (strncmp(p
, "Rcmd,", 5) == 0) {
2085 int len
= strlen(p
+ 5);
2087 if ((len
% 2) != 0) {
2088 put_packet(s
, "E01");
2091 hextomem(mem_buf
, p
+ 5, len
);
2094 qemu_chr_read(s
->mon_chr
, mem_buf
, len
);
2095 put_packet(s
, "OK");
2098 #endif /* !CONFIG_USER_ONLY */
2099 if (strncmp(p
, "Supported", 9) == 0) {
2100 snprintf(buf
, sizeof(buf
), "PacketSize=%x", MAX_PACKET_LENGTH
);
2102 pstrcat(buf
, sizeof(buf
), ";qXfer:features:read+");
2108 if (strncmp(p
, "Xfer:features:read:", 19) == 0) {
2110 target_ulong total_len
;
2114 xml
= get_feature_xml(p
, &p
);
2116 snprintf(buf
, sizeof(buf
), "E00");
2123 addr
= strtoul(p
, (char **)&p
, 16);
2126 len
= strtoul(p
, (char **)&p
, 16);
2128 total_len
= strlen(xml
);
2129 if (addr
> total_len
) {
2130 snprintf(buf
, sizeof(buf
), "E00");
2134 if (len
> (MAX_PACKET_LENGTH
- 5) / 2)
2135 len
= (MAX_PACKET_LENGTH
- 5) / 2;
2136 if (len
< total_len
- addr
) {
2138 len
= memtox(buf
+ 1, xml
+ addr
, len
);
2141 len
= memtox(buf
+ 1, xml
+ addr
, total_len
- addr
);
2143 put_packet_binary(s
, buf
, len
+ 1);
2147 /* Unrecognised 'q' command. */
2148 goto unknown_command
;
2152 /* put empty packet */
2160 void gdb_set_stop_cpu(CPUState
*env
)
2162 gdbserver_state
->c_cpu
= env
;
2163 gdbserver_state
->g_cpu
= env
;
2166 #ifndef CONFIG_USER_ONLY
2167 static void gdb_vm_state_change(void *opaque
, int running
, int reason
)
2169 GDBState
*s
= gdbserver_state
;
2170 CPUState
*env
= s
->c_cpu
;
2175 if (running
|| (reason
!= EXCP_DEBUG
&& reason
!= EXCP_INTERRUPT
) ||
2176 s
->state
== RS_INACTIVE
|| s
->state
== RS_SYSCALL
)
2179 /* disable single step if it was enable */
2180 cpu_single_step(env
, 0);
2182 if (reason
== EXCP_DEBUG
) {
2183 if (env
->watchpoint_hit
) {
2184 switch (env
->watchpoint_hit
->flags
& BP_MEM_ACCESS
) {
2195 snprintf(buf
, sizeof(buf
),
2196 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx
";",
2197 GDB_SIGNAL_TRAP
, gdb_id(env
), type
,
2198 env
->watchpoint_hit
->vaddr
);
2200 env
->watchpoint_hit
= NULL
;
2204 ret
= GDB_SIGNAL_TRAP
;
2206 ret
= GDB_SIGNAL_INT
;
2208 snprintf(buf
, sizeof(buf
), "T%02xthread:%02x;", ret
, gdb_id(env
));
2213 /* Send a gdb syscall request.
2214 This accepts limited printf-style format specifiers, specifically:
2215 %x - target_ulong argument printed in hex.
2216 %lx - 64-bit argument printed in hex.
2217 %s - string pointer (target_ulong) and length (int) pair. */
2218 void gdb_do_syscall(gdb_syscall_complete_cb cb
, const char *fmt
, ...)
2227 s
= gdbserver_state
;
2230 gdb_current_syscall_cb
= cb
;
2231 s
->state
= RS_SYSCALL
;
2232 #ifndef CONFIG_USER_ONLY
2233 vm_stop(EXCP_DEBUG
);
2244 addr
= va_arg(va
, target_ulong
);
2245 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, TARGET_FMT_lx
, addr
);
2248 if (*(fmt
++) != 'x')
2250 i64
= va_arg(va
, uint64_t);
2251 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, "%" PRIx64
, i64
);
2254 addr
= va_arg(va
, target_ulong
);
2255 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, TARGET_FMT_lx
"/%x",
2256 addr
, va_arg(va
, int));
2260 fprintf(stderr
, "gdbstub: Bad syscall format string '%s'\n",
2271 #ifdef CONFIG_USER_ONLY
2272 gdb_handlesig(s
->c_cpu
, 0);
2278 static void gdb_read_byte(GDBState
*s
, int ch
)
2283 #ifndef CONFIG_USER_ONLY
2284 if (s
->last_packet_len
) {
2285 /* Waiting for a response to the last packet. If we see the start
2286 of a new command then abandon the previous response. */
2289 printf("Got NACK, retransmitting\n");
2291 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
2295 printf("Got ACK\n");
2297 printf("Got '%c' when expecting ACK/NACK\n", ch
);
2299 if (ch
== '+' || ch
== '$')
2300 s
->last_packet_len
= 0;
2305 /* when the CPU is running, we cannot do anything except stop
2306 it when receiving a char */
2307 vm_stop(EXCP_INTERRUPT
);
2314 s
->line_buf_index
= 0;
2315 s
->state
= RS_GETLINE
;
2320 s
->state
= RS_CHKSUM1
;
2321 } else if (s
->line_buf_index
>= sizeof(s
->line_buf
) - 1) {
2324 s
->line_buf
[s
->line_buf_index
++] = ch
;
2328 s
->line_buf
[s
->line_buf_index
] = '\0';
2329 s
->line_csum
= fromhex(ch
) << 4;
2330 s
->state
= RS_CHKSUM2
;
2333 s
->line_csum
|= fromhex(ch
);
2335 for(i
= 0; i
< s
->line_buf_index
; i
++) {
2336 csum
+= s
->line_buf
[i
];
2338 if (s
->line_csum
!= (csum
& 0xff)) {
2340 put_buffer(s
, &reply
, 1);
2344 put_buffer(s
, &reply
, 1);
2345 s
->state
= gdb_handle_packet(s
, s
->line_buf
);
2354 #ifdef CONFIG_USER_ONLY
2360 s
= gdbserver_state
;
2362 if (gdbserver_fd
< 0 || s
->fd
< 0)
2369 gdb_handlesig (CPUState
*env
, int sig
)
2375 s
= gdbserver_state
;
2376 if (gdbserver_fd
< 0 || s
->fd
< 0)
2379 /* disable single step if it was enabled */
2380 cpu_single_step(env
, 0);
2385 snprintf(buf
, sizeof(buf
), "S%02x", target_signal_to_gdb (sig
));
2388 /* put_packet() might have detected that the peer terminated the
2395 s
->running_state
= 0;
2396 while (s
->running_state
== 0) {
2397 n
= read (s
->fd
, buf
, 256);
2402 for (i
= 0; i
< n
; i
++)
2403 gdb_read_byte (s
, buf
[i
]);
2405 else if (n
== 0 || errno
!= EAGAIN
)
2407 /* XXX: Connection closed. Should probably wait for annother
2408 connection before continuing. */
2417 /* Tell the remote gdb that the process has exited. */
2418 void gdb_exit(CPUState
*env
, int code
)
2423 s
= gdbserver_state
;
2424 if (gdbserver_fd
< 0 || s
->fd
< 0)
2427 snprintf(buf
, sizeof(buf
), "W%02x", code
);
2431 /* Tell the remote gdb that the process has exited due to SIG. */
2432 void gdb_signalled(CPUState
*env
, int sig
)
2437 s
= gdbserver_state
;
2438 if (gdbserver_fd
< 0 || s
->fd
< 0)
2441 snprintf(buf
, sizeof(buf
), "X%02x", target_signal_to_gdb (sig
));
2445 static void gdb_accept(void)
2448 struct sockaddr_in sockaddr
;
2453 len
= sizeof(sockaddr
);
2454 fd
= accept(gdbserver_fd
, (struct sockaddr
*)&sockaddr
, &len
);
2455 if (fd
< 0 && errno
!= EINTR
) {
2458 } else if (fd
>= 0) {
2460 fcntl(fd
, F_SETFD
, FD_CLOEXEC
);
2466 /* set short latency */
2468 setsockopt(fd
, IPPROTO_TCP
, TCP_NODELAY
, (char *)&val
, sizeof(val
));
2470 s
= qemu_mallocz(sizeof(GDBState
));
2471 s
->c_cpu
= first_cpu
;
2472 s
->g_cpu
= first_cpu
;
2476 gdbserver_state
= s
;
2478 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
2481 static int gdbserver_open(int port
)
2483 struct sockaddr_in sockaddr
;
2486 fd
= socket(PF_INET
, SOCK_STREAM
, 0);
2492 fcntl(fd
, F_SETFD
, FD_CLOEXEC
);
2495 /* allow fast reuse */
2497 setsockopt(fd
, SOL_SOCKET
, SO_REUSEADDR
, (char *)&val
, sizeof(val
));
2499 sockaddr
.sin_family
= AF_INET
;
2500 sockaddr
.sin_port
= htons(port
);
2501 sockaddr
.sin_addr
.s_addr
= 0;
2502 ret
= bind(fd
, (struct sockaddr
*)&sockaddr
, sizeof(sockaddr
));
2507 ret
= listen(fd
, 0);
2515 int gdbserver_start(int port
)
2517 gdbserver_fd
= gdbserver_open(port
);
2518 if (gdbserver_fd
< 0)
2520 /* accept connections */
2525 /* Disable gdb stub for child processes. */
2526 void gdbserver_fork(CPUState
*env
)
2528 GDBState
*s
= gdbserver_state
;
2529 if (gdbserver_fd
< 0 || s
->fd
< 0)
2533 cpu_breakpoint_remove_all(env
, BP_GDB
);
2534 cpu_watchpoint_remove_all(env
, BP_GDB
);
2537 static int gdb_chr_can_receive(void *opaque
)
2539 /* We can handle an arbitrarily large amount of data.
2540 Pick the maximum packet size, which is as good as anything. */
2541 return MAX_PACKET_LENGTH
;
2544 static void gdb_chr_receive(void *opaque
, const uint8_t *buf
, int size
)
2548 for (i
= 0; i
< size
; i
++) {
2549 gdb_read_byte(gdbserver_state
, buf
[i
]);
2553 static void gdb_chr_event(void *opaque
, int event
)
2556 case CHR_EVENT_OPENED
:
2557 vm_stop(EXCP_INTERRUPT
);
2565 static void gdb_monitor_output(GDBState
*s
, const char *msg
, int len
)
2567 char buf
[MAX_PACKET_LENGTH
];
2570 if (len
> (MAX_PACKET_LENGTH
/2) - 1)
2571 len
= (MAX_PACKET_LENGTH
/2) - 1;
2572 memtohex(buf
+ 1, (uint8_t *)msg
, len
);
2576 static int gdb_monitor_write(CharDriverState
*chr
, const uint8_t *buf
, int len
)
2578 const char *p
= (const char *)buf
;
2581 max_sz
= (sizeof(gdbserver_state
->last_packet
) - 2) / 2;
2583 if (len
<= max_sz
) {
2584 gdb_monitor_output(gdbserver_state
, p
, len
);
2587 gdb_monitor_output(gdbserver_state
, p
, max_sz
);
2595 static void gdb_sigterm_handler(int signal
)
2598 vm_stop(EXCP_INTERRUPT
);
2602 int gdbserver_start(const char *device
)
2605 char gdbstub_device_name
[128];
2606 CharDriverState
*chr
= NULL
;
2607 CharDriverState
*mon_chr
;
2611 if (strcmp(device
, "none") != 0) {
2612 if (strstart(device
, "tcp:", NULL
)) {
2613 /* enforce required TCP attributes */
2614 snprintf(gdbstub_device_name
, sizeof(gdbstub_device_name
),
2615 "%s,nowait,nodelay,server", device
);
2616 device
= gdbstub_device_name
;
2619 else if (strcmp(device
, "stdio") == 0) {
2620 struct sigaction act
;
2622 memset(&act
, 0, sizeof(act
));
2623 act
.sa_handler
= gdb_sigterm_handler
;
2624 sigaction(SIGINT
, &act
, NULL
);
2627 chr
= qemu_chr_open("gdb", device
, NULL
);
2631 qemu_chr_add_handlers(chr
, gdb_chr_can_receive
, gdb_chr_receive
,
2632 gdb_chr_event
, NULL
);
2635 s
= gdbserver_state
;
2637 s
= qemu_mallocz(sizeof(GDBState
));
2638 gdbserver_state
= s
;
2640 qemu_add_vm_change_state_handler(gdb_vm_state_change
, NULL
);
2642 /* Initialize a monitor terminal for gdb */
2643 mon_chr
= qemu_mallocz(sizeof(*mon_chr
));
2644 mon_chr
->chr_write
= gdb_monitor_write
;
2645 monitor_init(mon_chr
, 0);
2648 qemu_chr_close(s
->chr
);
2649 mon_chr
= s
->mon_chr
;
2650 memset(s
, 0, sizeof(GDBState
));
2652 s
->c_cpu
= first_cpu
;
2653 s
->g_cpu
= first_cpu
;
2655 s
->state
= chr
? RS_IDLE
: RS_INACTIVE
;
2656 s
->mon_chr
= mon_chr
;