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Remove l1_phys_map from userspace emulation
[qemu/aliguori-queue.git] / target-mips / translate.c
blobba660ab8ac8e496c5dbbbd03f1f6544cbdc95c41
1 /*
2 * MIPS32 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 support)
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <stdarg.h>
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <string.h>
27 #include <inttypes.h>
28
29 #include "cpu.h"
30 #include "exec-all.h"
31 #include "disas.h"
32 #include "tcg-op.h"
33 #include "qemu-common.h"
34
35 #include "helper.h"
36 #define GEN_HELPER 1
37 #include "helper.h"
38
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
41
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
44
45 enum {
46 /* indirect opcode tables */
47 OPC_SPECIAL = (0x00 << 26),
48 OPC_REGIMM = (0x01 << 26),
49 OPC_CP0 = (0x10 << 26),
50 OPC_CP1 = (0x11 << 26),
51 OPC_CP2 = (0x12 << 26),
52 OPC_CP3 = (0x13 << 26),
53 OPC_SPECIAL2 = (0x1C << 26),
54 OPC_SPECIAL3 = (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI = (0x08 << 26),
57 OPC_ADDIU = (0x09 << 26),
58 OPC_SLTI = (0x0A << 26),
59 OPC_SLTIU = (0x0B << 26),
60 /* logic with immediate */
61 OPC_ANDI = (0x0C << 26),
62 OPC_ORI = (0x0D << 26),
63 OPC_XORI = (0x0E << 26),
64 OPC_LUI = (0x0F << 26),
65 /* arithmetic with immediate */
66 OPC_DADDI = (0x18 << 26),
67 OPC_DADDIU = (0x19 << 26),
68 /* Jump and branches */
69 OPC_J = (0x02 << 26),
70 OPC_JAL = (0x03 << 26),
71 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
72 OPC_BEQL = (0x14 << 26),
73 OPC_BNE = (0x05 << 26),
74 OPC_BNEL = (0x15 << 26),
75 OPC_BLEZ = (0x06 << 26),
76 OPC_BLEZL = (0x16 << 26),
77 OPC_BGTZ = (0x07 << 26),
78 OPC_BGTZL = (0x17 << 26),
79 OPC_JALX = (0x1D << 26), /* MIPS 16 only */
80 /* Load and stores */
81 OPC_LDL = (0x1A << 26),
82 OPC_LDR = (0x1B << 26),
83 OPC_LB = (0x20 << 26),
84 OPC_LH = (0x21 << 26),
85 OPC_LWL = (0x22 << 26),
86 OPC_LW = (0x23 << 26),
87 OPC_LWPC = OPC_LW | 0x5,
88 OPC_LBU = (0x24 << 26),
89 OPC_LHU = (0x25 << 26),
90 OPC_LWR = (0x26 << 26),
91 OPC_LWU = (0x27 << 26),
92 OPC_SB = (0x28 << 26),
93 OPC_SH = (0x29 << 26),
94 OPC_SWL = (0x2A << 26),
95 OPC_SW = (0x2B << 26),
96 OPC_SDL = (0x2C << 26),
97 OPC_SDR = (0x2D << 26),
98 OPC_SWR = (0x2E << 26),
99 OPC_LL = (0x30 << 26),
100 OPC_LLD = (0x34 << 26),
101 OPC_LD = (0x37 << 26),
102 OPC_LDPC = OPC_LD | 0x5,
103 OPC_SC = (0x38 << 26),
104 OPC_SCD = (0x3C << 26),
105 OPC_SD = (0x3F << 26),
106 /* Floating point load/store */
107 OPC_LWC1 = (0x31 << 26),
108 OPC_LWC2 = (0x32 << 26),
109 OPC_LDC1 = (0x35 << 26),
110 OPC_LDC2 = (0x36 << 26),
111 OPC_SWC1 = (0x39 << 26),
112 OPC_SWC2 = (0x3A << 26),
113 OPC_SDC1 = (0x3D << 26),
114 OPC_SDC2 = (0x3E << 26),
115 /* MDMX ASE specific */
116 OPC_MDMX = (0x1E << 26),
117 /* Cache and prefetch */
118 OPC_CACHE = (0x2F << 26),
119 OPC_PREF = (0x33 << 26),
120 /* Reserved major opcode */
121 OPC_MAJOR3B_RESERVED = (0x3B << 26),
122 };
123
124 /* MIPS special opcodes */
125 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
126
127 enum {
128 /* Shifts */
129 OPC_SLL = 0x00 | OPC_SPECIAL,
130 /* NOP is SLL r0, r0, 0 */
131 /* SSNOP is SLL r0, r0, 1 */
132 /* EHB is SLL r0, r0, 3 */
133 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
134 OPC_ROTR = OPC_SRL | (1 << 21),
135 OPC_SRA = 0x03 | OPC_SPECIAL,
136 OPC_SLLV = 0x04 | OPC_SPECIAL,
137 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
138 OPC_ROTRV = OPC_SRLV | (1 << 6),
139 OPC_SRAV = 0x07 | OPC_SPECIAL,
140 OPC_DSLLV = 0x14 | OPC_SPECIAL,
141 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
142 OPC_DROTRV = OPC_DSRLV | (1 << 6),
143 OPC_DSRAV = 0x17 | OPC_SPECIAL,
144 OPC_DSLL = 0x38 | OPC_SPECIAL,
145 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
146 OPC_DROTR = OPC_DSRL | (1 << 21),
147 OPC_DSRA = 0x3B | OPC_SPECIAL,
148 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
149 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
150 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
151 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
152 /* Multiplication / division */
153 OPC_MULT = 0x18 | OPC_SPECIAL,
154 OPC_MULTU = 0x19 | OPC_SPECIAL,
155 OPC_DIV = 0x1A | OPC_SPECIAL,
156 OPC_DIVU = 0x1B | OPC_SPECIAL,
157 OPC_DMULT = 0x1C | OPC_SPECIAL,
158 OPC_DMULTU = 0x1D | OPC_SPECIAL,
159 OPC_DDIV = 0x1E | OPC_SPECIAL,
160 OPC_DDIVU = 0x1F | OPC_SPECIAL,
161 /* 2 registers arithmetic / logic */
162 OPC_ADD = 0x20 | OPC_SPECIAL,
163 OPC_ADDU = 0x21 | OPC_SPECIAL,
164 OPC_SUB = 0x22 | OPC_SPECIAL,
165 OPC_SUBU = 0x23 | OPC_SPECIAL,
166 OPC_AND = 0x24 | OPC_SPECIAL,
167 OPC_OR = 0x25 | OPC_SPECIAL,
168 OPC_XOR = 0x26 | OPC_SPECIAL,
169 OPC_NOR = 0x27 | OPC_SPECIAL,
170 OPC_SLT = 0x2A | OPC_SPECIAL,
171 OPC_SLTU = 0x2B | OPC_SPECIAL,
172 OPC_DADD = 0x2C | OPC_SPECIAL,
173 OPC_DADDU = 0x2D | OPC_SPECIAL,
174 OPC_DSUB = 0x2E | OPC_SPECIAL,
175 OPC_DSUBU = 0x2F | OPC_SPECIAL,
176 /* Jumps */
177 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
178 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
179 OPC_JALRC = OPC_JALR | (0x5 << 6),
180 /* Traps */
181 OPC_TGE = 0x30 | OPC_SPECIAL,
182 OPC_TGEU = 0x31 | OPC_SPECIAL,
183 OPC_TLT = 0x32 | OPC_SPECIAL,
184 OPC_TLTU = 0x33 | OPC_SPECIAL,
185 OPC_TEQ = 0x34 | OPC_SPECIAL,
186 OPC_TNE = 0x36 | OPC_SPECIAL,
187 /* HI / LO registers load & stores */
188 OPC_MFHI = 0x10 | OPC_SPECIAL,
189 OPC_MTHI = 0x11 | OPC_SPECIAL,
190 OPC_MFLO = 0x12 | OPC_SPECIAL,
191 OPC_MTLO = 0x13 | OPC_SPECIAL,
192 /* Conditional moves */
193 OPC_MOVZ = 0x0A | OPC_SPECIAL,
194 OPC_MOVN = 0x0B | OPC_SPECIAL,
195
196 OPC_MOVCI = 0x01 | OPC_SPECIAL,
197
198 /* Special */
199 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
200 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
201 OPC_BREAK = 0x0D | OPC_SPECIAL,
202 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
203 OPC_SYNC = 0x0F | OPC_SPECIAL,
204
205 OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
206 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
207 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
208 OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
209 OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
210 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
211 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
212 };
213
214 /* Multiplication variants of the vr54xx. */
215 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
216
217 enum {
218 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
219 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
220 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
221 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
222 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
223 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
224 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
225 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
226 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
227 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
228 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
229 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
230 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
231 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
232 };
233
234 /* REGIMM (rt field) opcodes */
235 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
236
237 enum {
238 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
239 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
240 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
241 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
242 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
243 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
244 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
245 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
246 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
247 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
248 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
249 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
250 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
251 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
252 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
253 };
254
255 /* Special2 opcodes */
256 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
257
258 enum {
259 /* Multiply & xxx operations */
260 OPC_MADD = 0x00 | OPC_SPECIAL2,
261 OPC_MADDU = 0x01 | OPC_SPECIAL2,
262 OPC_MUL = 0x02 | OPC_SPECIAL2,
263 OPC_MSUB = 0x04 | OPC_SPECIAL2,
264 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
265 /* Misc */
266 OPC_CLZ = 0x20 | OPC_SPECIAL2,
267 OPC_CLO = 0x21 | OPC_SPECIAL2,
268 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
269 OPC_DCLO = 0x25 | OPC_SPECIAL2,
270 /* Special */
271 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
272 };
273
274 /* Special3 opcodes */
275 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
276
277 enum {
278 OPC_EXT = 0x00 | OPC_SPECIAL3,
279 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
280 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
281 OPC_DEXT = 0x03 | OPC_SPECIAL3,
282 OPC_INS = 0x04 | OPC_SPECIAL3,
283 OPC_DINSM = 0x05 | OPC_SPECIAL3,
284 OPC_DINSU = 0x06 | OPC_SPECIAL3,
285 OPC_DINS = 0x07 | OPC_SPECIAL3,
286 OPC_FORK = 0x08 | OPC_SPECIAL3,
287 OPC_YIELD = 0x09 | OPC_SPECIAL3,
288 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
289 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
290 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
291 };
292
293 /* BSHFL opcodes */
294 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
295
296 enum {
297 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
298 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
299 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
300 };
301
302 /* DBSHFL opcodes */
303 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
304
305 enum {
306 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
307 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
308 };
309
310 /* Coprocessor 0 (rs field) */
311 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
312
313 enum {
314 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
315 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
316 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
317 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
318 OPC_MFTR = (0x08 << 21) | OPC_CP0,
319 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
320 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
321 OPC_MTTR = (0x0C << 21) | OPC_CP0,
322 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
323 OPC_C0 = (0x10 << 21) | OPC_CP0,
324 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
325 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
326 };
327
328 /* MFMC0 opcodes */
329 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
330
331 enum {
332 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
333 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
334 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
335 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
336 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
337 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
338 };
339
340 /* Coprocessor 0 (with rs == C0) */
341 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
342
343 enum {
344 OPC_TLBR = 0x01 | OPC_C0,
345 OPC_TLBWI = 0x02 | OPC_C0,
346 OPC_TLBWR = 0x06 | OPC_C0,
347 OPC_TLBP = 0x08 | OPC_C0,
348 OPC_RFE = 0x10 | OPC_C0,
349 OPC_ERET = 0x18 | OPC_C0,
350 OPC_DERET = 0x1F | OPC_C0,
351 OPC_WAIT = 0x20 | OPC_C0,
352 };
353
354 /* Coprocessor 1 (rs field) */
355 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
356
357 enum {
358 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
359 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
360 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
361 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
362 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
363 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
364 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
365 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
366 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
367 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
368 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
369 OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
370 OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
371 OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
372 OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
373 OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
374 OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
375 OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */
376 };
377
378 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
379 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
380
381 enum {
382 OPC_BC1F = (0x00 << 16) | OPC_BC1,
383 OPC_BC1T = (0x01 << 16) | OPC_BC1,
384 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
385 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
386 };
387
388 enum {
389 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
390 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
391 };
392
393 enum {
394 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
395 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
396 };
397
398 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
399
400 enum {
401 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
402 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
403 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
404 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
405 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
406 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
407 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
408 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
409 OPC_BC2 = (0x08 << 21) | OPC_CP2,
410 };
411
412 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
413
414 enum {
415 OPC_LWXC1 = 0x00 | OPC_CP3,
416 OPC_LDXC1 = 0x01 | OPC_CP3,
417 OPC_LUXC1 = 0x05 | OPC_CP3,
418 OPC_SWXC1 = 0x08 | OPC_CP3,
419 OPC_SDXC1 = 0x09 | OPC_CP3,
420 OPC_SUXC1 = 0x0D | OPC_CP3,
421 OPC_PREFX = 0x0F | OPC_CP3,
422 OPC_ALNV_PS = 0x1E | OPC_CP3,
423 OPC_MADD_S = 0x20 | OPC_CP3,
424 OPC_MADD_D = 0x21 | OPC_CP3,
425 OPC_MADD_PS = 0x26 | OPC_CP3,
426 OPC_MSUB_S = 0x28 | OPC_CP3,
427 OPC_MSUB_D = 0x29 | OPC_CP3,
428 OPC_MSUB_PS = 0x2E | OPC_CP3,
429 OPC_NMADD_S = 0x30 | OPC_CP3,
430 OPC_NMADD_D = 0x31 | OPC_CP3,
431 OPC_NMADD_PS= 0x36 | OPC_CP3,
432 OPC_NMSUB_S = 0x38 | OPC_CP3,
433 OPC_NMSUB_D = 0x39 | OPC_CP3,
434 OPC_NMSUB_PS= 0x3E | OPC_CP3,
435 };
436
437 /* global register indices */
438 static TCGv_ptr cpu_env;
439 static TCGv cpu_gpr[32], cpu_PC;
440 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
441 static TCGv cpu_dspctrl, btarget, bcond;
442 static TCGv_i32 hflags;
443 static TCGv_i32 fpu_fcr0, fpu_fcr31;
444
445 #include "gen-icount.h"
446
447 #define gen_helper_0i(name, arg) do { \
448 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
449 gen_helper_##name(helper_tmp); \
450 tcg_temp_free_i32(helper_tmp); \
451 } while(0)
452
453 #define gen_helper_1i(name, arg1, arg2) do { \
454 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
455 gen_helper_##name(arg1, helper_tmp); \
456 tcg_temp_free_i32(helper_tmp); \
457 } while(0)
458
459 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
460 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
461 gen_helper_##name(arg1, arg2, helper_tmp); \
462 tcg_temp_free_i32(helper_tmp); \
463 } while(0)
464
465 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
466 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
467 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
468 tcg_temp_free_i32(helper_tmp); \
469 } while(0)
470
471 typedef struct DisasContext {
472 struct TranslationBlock *tb;
473 target_ulong pc, saved_pc;
474 uint32_t opcode;
475 int singlestep_enabled;
476 /* Routine used to access memory */
477 int mem_idx;
478 uint32_t hflags, saved_hflags;
479 int bstate;
480 target_ulong btarget;
481 } DisasContext;
482
483 enum {
484 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
485 * exception condition */
486 BS_STOP = 1, /* We want to stop translation for any reason */
487 BS_BRANCH = 2, /* We reached a branch condition */
488 BS_EXCP = 3, /* We reached an exception condition */
489 };
490
491 static const char *regnames[] =
492 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
493 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
494 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
495 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
496
497 static const char *regnames_HI[] =
498 { "HI0", "HI1", "HI2", "HI3", };
499
500 static const char *regnames_LO[] =
501 { "LO0", "LO1", "LO2", "LO3", };
502
503 static const char *regnames_ACX[] =
504 { "ACX0", "ACX1", "ACX2", "ACX3", };
505
506 static const char *fregnames[] =
507 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
511
512 #ifdef MIPS_DEBUG_DISAS
513 #define MIPS_DEBUG(fmt, ...) \
514 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
515 TARGET_FMT_lx ": %08x " fmt "\n", \
516 ctx->pc, ctx->opcode , ## __VA_ARGS__)
517 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
518 #else
519 #define MIPS_DEBUG(fmt, ...) do { } while(0)
520 #define LOG_DISAS(...) do { } while (0)
521 #endif
522
523 #define MIPS_INVAL(op) \
524 do { \
525 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
526 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
527 } while (0)
528
529 /* General purpose registers moves. */
530 static inline void gen_load_gpr (TCGv t, int reg)
531 {
532 if (reg == 0)
533 tcg_gen_movi_tl(t, 0);
534 else
535 tcg_gen_mov_tl(t, cpu_gpr[reg]);
536 }
537
538 static inline void gen_store_gpr (TCGv t, int reg)
539 {
540 if (reg != 0)
541 tcg_gen_mov_tl(cpu_gpr[reg], t);
542 }
543
544 /* Moves to/from ACX register. */
545 static inline void gen_load_ACX (TCGv t, int reg)
546 {
547 tcg_gen_mov_tl(t, cpu_ACX[reg]);
548 }
549
550 static inline void gen_store_ACX (TCGv t, int reg)
551 {
552 tcg_gen_mov_tl(cpu_ACX[reg], t);
553 }
554
555 /* Moves to/from shadow registers. */
556 static inline void gen_load_srsgpr (int from, int to)
557 {
558 TCGv t0 = tcg_temp_new();
559
560 if (from == 0)
561 tcg_gen_movi_tl(t0, 0);
562 else {
563 TCGv_i32 t2 = tcg_temp_new_i32();
564 TCGv_ptr addr = tcg_temp_new_ptr();
565
566 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
567 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
568 tcg_gen_andi_i32(t2, t2, 0xf);
569 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
570 tcg_gen_ext_i32_ptr(addr, t2);
571 tcg_gen_add_ptr(addr, cpu_env, addr);
572
573 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
574 tcg_temp_free_ptr(addr);
575 tcg_temp_free_i32(t2);
576 }
577 gen_store_gpr(t0, to);
578 tcg_temp_free(t0);
579 }
580
581 static inline void gen_store_srsgpr (int from, int to)
582 {
583 if (to != 0) {
584 TCGv t0 = tcg_temp_new();
585 TCGv_i32 t2 = tcg_temp_new_i32();
586 TCGv_ptr addr = tcg_temp_new_ptr();
587
588 gen_load_gpr(t0, from);
589 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
590 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
591 tcg_gen_andi_i32(t2, t2, 0xf);
592 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
593 tcg_gen_ext_i32_ptr(addr, t2);
594 tcg_gen_add_ptr(addr, cpu_env, addr);
595
596 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
597 tcg_temp_free_ptr(addr);
598 tcg_temp_free_i32(t2);
599 tcg_temp_free(t0);
600 }
601 }
602
603 /* Floating point register moves. */
604 static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
605 {
606 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
607 }
608
609 static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
610 {
611 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
612 }
613
614 static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
615 {
616 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
617 }
618
619 static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
620 {
621 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
622 }
623
624 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
625 {
626 if (ctx->hflags & MIPS_HFLAG_F64) {
627 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
628 } else {
629 TCGv_i32 t0 = tcg_temp_new_i32();
630 TCGv_i32 t1 = tcg_temp_new_i32();
631 gen_load_fpr32(t0, reg & ~1);
632 gen_load_fpr32(t1, reg | 1);
633 tcg_gen_concat_i32_i64(t, t0, t1);
634 tcg_temp_free_i32(t0);
635 tcg_temp_free_i32(t1);
636 }
637 }
638
639 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
640 {
641 if (ctx->hflags & MIPS_HFLAG_F64) {
642 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
643 } else {
644 TCGv_i64 t0 = tcg_temp_new_i64();
645 TCGv_i32 t1 = tcg_temp_new_i32();
646 tcg_gen_trunc_i64_i32(t1, t);
647 gen_store_fpr32(t1, reg & ~1);
648 tcg_gen_shri_i64(t0, t, 32);
649 tcg_gen_trunc_i64_i32(t1, t0);
650 gen_store_fpr32(t1, reg | 1);
651 tcg_temp_free_i32(t1);
652 tcg_temp_free_i64(t0);
653 }
654 }
655
656 static inline int get_fp_bit (int cc)
657 {
658 if (cc)
659 return 24 + cc;
660 else
661 return 23;
662 }
663
664 #define FOP_CONDS(type, fmt, bits) \
665 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
666 TCGv_i##bits b, int cc) \
667 { \
668 switch (n) { \
669 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
670 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
671 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
672 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
673 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
674 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
675 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
676 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
677 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
678 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
679 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
680 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
681 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
682 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
683 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
684 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
685 default: abort(); \
686 } \
687 }
688
689 FOP_CONDS(, d, 64)
690 FOP_CONDS(abs, d, 64)
691 FOP_CONDS(, s, 32)
692 FOP_CONDS(abs, s, 32)
693 FOP_CONDS(, ps, 64)
694 FOP_CONDS(abs, ps, 64)
695 #undef FOP_CONDS
696
697 /* Tests */
698 #define OP_COND(name, cond) \
699 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \
700 { \
701 int l1 = gen_new_label(); \
702 int l2 = gen_new_label(); \
703 \
704 tcg_gen_brcond_tl(cond, t0, t1, l1); \
705 tcg_gen_movi_tl(ret, 0); \
706 tcg_gen_br(l2); \
707 gen_set_label(l1); \
708 tcg_gen_movi_tl(ret, 1); \
709 gen_set_label(l2); \
710 }
711 OP_COND(eq, TCG_COND_EQ);
712 OP_COND(ne, TCG_COND_NE);
713 OP_COND(ge, TCG_COND_GE);
714 OP_COND(geu, TCG_COND_GEU);
715 OP_COND(lt, TCG_COND_LT);
716 OP_COND(ltu, TCG_COND_LTU);
717 #undef OP_COND
718
719 #define OP_CONDI(name, cond) \
720 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \
721 { \
722 int l1 = gen_new_label(); \
723 int l2 = gen_new_label(); \
724 \
725 tcg_gen_brcondi_tl(cond, t0, val, l1); \
726 tcg_gen_movi_tl(ret, 0); \
727 tcg_gen_br(l2); \
728 gen_set_label(l1); \
729 tcg_gen_movi_tl(ret, 1); \
730 gen_set_label(l2); \
731 }
732 OP_CONDI(lti, TCG_COND_LT);
733 OP_CONDI(ltiu, TCG_COND_LTU);
734 #undef OP_CONDI
735
736 #define OP_CONDZ(name, cond) \
737 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \
738 { \
739 int l1 = gen_new_label(); \
740 int l2 = gen_new_label(); \
741 \
742 tcg_gen_brcondi_tl(cond, t0, 0, l1); \
743 tcg_gen_movi_tl(ret, 0); \
744 tcg_gen_br(l2); \
745 gen_set_label(l1); \
746 tcg_gen_movi_tl(ret, 1); \
747 gen_set_label(l2); \
748 }
749 OP_CONDZ(gez, TCG_COND_GE);
750 OP_CONDZ(gtz, TCG_COND_GT);
751 OP_CONDZ(lez, TCG_COND_LE);
752 OP_CONDZ(ltz, TCG_COND_LT);
753 #undef OP_CONDZ
754
755 static inline void gen_save_pc(target_ulong pc)
756 {
757 tcg_gen_movi_tl(cpu_PC, pc);
758 }
759
760 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
761 {
762 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
763 if (do_save_pc && ctx->pc != ctx->saved_pc) {
764 gen_save_pc(ctx->pc);
765 ctx->saved_pc = ctx->pc;
766 }
767 if (ctx->hflags != ctx->saved_hflags) {
768 tcg_gen_movi_i32(hflags, ctx->hflags);
769 ctx->saved_hflags = ctx->hflags;
770 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
771 case MIPS_HFLAG_BR:
772 break;
773 case MIPS_HFLAG_BC:
774 case MIPS_HFLAG_BL:
775 case MIPS_HFLAG_B:
776 tcg_gen_movi_tl(btarget, ctx->btarget);
777 break;
778 }
779 }
780 }
781
782 static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
783 {
784 ctx->saved_hflags = ctx->hflags;
785 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
786 case MIPS_HFLAG_BR:
787 break;
788 case MIPS_HFLAG_BC:
789 case MIPS_HFLAG_BL:
790 case MIPS_HFLAG_B:
791 ctx->btarget = env->btarget;
792 break;
793 }
794 }
795
796 static inline void
797 generate_exception_err (DisasContext *ctx, int excp, int err)
798 {
799 TCGv_i32 texcp = tcg_const_i32(excp);
800 TCGv_i32 terr = tcg_const_i32(err);
801 save_cpu_state(ctx, 1);
802 gen_helper_raise_exception_err(texcp, terr);
803 tcg_temp_free_i32(terr);
804 tcg_temp_free_i32(texcp);
805 }
806
807 static inline void
808 generate_exception (DisasContext *ctx, int excp)
809 {
810 save_cpu_state(ctx, 1);
811 gen_helper_0i(raise_exception, excp);
812 }
813
814 /* Addresses computation */
815 static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
816 {
817 tcg_gen_add_tl(ret, arg0, arg1);
818
819 #if defined(TARGET_MIPS64)
820 /* For compatibility with 32-bit code, data reference in user mode
821 with Status_UX = 0 should be casted to 32-bit and sign extended.
822 See the MIPS64 PRA manual, section 4.10. */
823 if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
824 !(ctx->hflags & MIPS_HFLAG_UX)) {
825 tcg_gen_ext32s_i64(ret, ret);
826 }
827 #endif
828 }
829
830 static inline void check_cp0_enabled(DisasContext *ctx)
831 {
832 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
833 generate_exception_err(ctx, EXCP_CpU, 0);
834 }
835
836 static inline void check_cp1_enabled(DisasContext *ctx)
837 {
838 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
839 generate_exception_err(ctx, EXCP_CpU, 1);
840 }
841
842 /* Verify that the processor is running with COP1X instructions enabled.
843 This is associated with the nabla symbol in the MIPS32 and MIPS64
844 opcode tables. */
845
846 static inline void check_cop1x(DisasContext *ctx)
847 {
848 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
849 generate_exception(ctx, EXCP_RI);
850 }
851
852 /* Verify that the processor is running with 64-bit floating-point
853 operations enabled. */
854
855 static inline void check_cp1_64bitmode(DisasContext *ctx)
856 {
857 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
858 generate_exception(ctx, EXCP_RI);
859 }
860
861 /*
862 * Verify if floating point register is valid; an operation is not defined
863 * if bit 0 of any register specification is set and the FR bit in the
864 * Status register equals zero, since the register numbers specify an
865 * even-odd pair of adjacent coprocessor general registers. When the FR bit
866 * in the Status register equals one, both even and odd register numbers
867 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
868 *
869 * Multiple 64 bit wide registers can be checked by calling
870 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
871 */
872 static inline void check_cp1_registers(DisasContext *ctx, int regs)
873 {
874 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
875 generate_exception(ctx, EXCP_RI);
876 }
877
878 /* This code generates a "reserved instruction" exception if the
879 CPU does not support the instruction set corresponding to flags. */
880 static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
881 {
882 if (unlikely(!(env->insn_flags & flags)))
883 generate_exception(ctx, EXCP_RI);
884 }
885
886 /* This code generates a "reserved instruction" exception if 64-bit
887 instructions are not enabled. */
888 static inline void check_mips_64(DisasContext *ctx)
889 {
890 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
891 generate_exception(ctx, EXCP_RI);
892 }
893
894 /* load/store instructions. */
895 #define OP_LD(insn,fname) \
896 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
897 { \
898 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
899 }
900 OP_LD(lb,ld8s);
901 OP_LD(lbu,ld8u);
902 OP_LD(lh,ld16s);
903 OP_LD(lhu,ld16u);
904 OP_LD(lw,ld32s);
905 #if defined(TARGET_MIPS64)
906 OP_LD(lwu,ld32u);
907 OP_LD(ld,ld64);
908 #endif
909 #undef OP_LD
910
911 #define OP_ST(insn,fname) \
912 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
913 { \
914 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
915 }
916 OP_ST(sb,st8);
917 OP_ST(sh,st16);
918 OP_ST(sw,st32);
919 #if defined(TARGET_MIPS64)
920 OP_ST(sd,st64);
921 #endif
922 #undef OP_ST
923
924 #ifdef CONFIG_USER_ONLY
925 #define OP_LD_ATOMIC(insn,fname) \
926 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
927 { \
928 TCGv t0 = tcg_temp_new(); \
929 tcg_gen_mov_tl(t0, arg1); \
930 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
931 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
932 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
933 tcg_temp_free(t0); \
934 }
935 #else
936 #define OP_LD_ATOMIC(insn,fname) \
937 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
938 { \
939 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
940 }
941 #endif
942 OP_LD_ATOMIC(ll,ld32s);
943 #if defined(TARGET_MIPS64)
944 OP_LD_ATOMIC(lld,ld64);
945 #endif
946 #undef OP_LD_ATOMIC
947
948 #ifdef CONFIG_USER_ONLY
949 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
950 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
951 { \
952 TCGv t0 = tcg_temp_new(); \
953 int l1 = gen_new_label(); \
954 int l2 = gen_new_label(); \
955 \
956 tcg_gen_andi_tl(t0, arg2, almask); \
957 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
958 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
959 generate_exception(ctx, EXCP_AdES); \
960 gen_set_label(l1); \
961 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
962 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
963 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
964 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
965 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
966 gen_helper_0i(raise_exception, EXCP_SC); \
967 gen_set_label(l2); \
968 tcg_gen_movi_tl(t0, 0); \
969 gen_store_gpr(t0, rt); \
970 tcg_temp_free(t0); \
971 }
972 #else
973 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
974 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
975 { \
976 TCGv t0 = tcg_temp_new(); \
977 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
978 gen_store_gpr(t0, rt); \
979 tcg_temp_free(t0); \
980 }
981 #endif
982 OP_ST_ATOMIC(sc,st32,ld32s,0x3);
983 #if defined(TARGET_MIPS64)
984 OP_ST_ATOMIC(scd,st64,ld64,0x7);
985 #endif
986 #undef OP_ST_ATOMIC
987
988 static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
989 int base, int16_t offset)
990 {
991 if (base == 0) {
992 tcg_gen_movi_tl(addr, offset);
993 } else if (offset == 0) {
994 gen_load_gpr(addr, base);
995 } else {
996 tcg_gen_movi_tl(addr, offset);
997 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
998 }
999 }
1000
1001 static target_ulong pc_relative_pc (DisasContext *ctx)
1002 {
1003 target_ulong pc = ctx->pc;
1004
1005 if (ctx->hflags & MIPS_HFLAG_BMASK) {
1006 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
1007
1008 pc -= branch_bytes;
1009 }
1010
1011 pc &= ~(target_ulong)3;
1012 return pc;
1013 }
1014
1015 /* Load and store */
1016 static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1017 int base, int16_t offset)
1018 {
1019 const char *opn = "ldst";
1020 TCGv t0 = tcg_temp_new();
1021 TCGv t1 = tcg_temp_new();
1022
1023 gen_base_offset_addr(ctx, t0, base, offset);
1024 /* Don't do NOP if destination is zero: we must perform the actual
1025 memory access. */
1026 switch (opc) {
1027 #if defined(TARGET_MIPS64)
1028 case OPC_LWU:
1029 save_cpu_state(ctx, 0);
1030 op_ldst_lwu(t0, t0, ctx);
1031 gen_store_gpr(t0, rt);
1032 opn = "lwu";
1033 break;
1034 case OPC_LD:
1035 save_cpu_state(ctx, 0);
1036 op_ldst_ld(t0, t0, ctx);
1037 gen_store_gpr(t0, rt);
1038 opn = "ld";
1039 break;
1040 case OPC_LLD:
1041 save_cpu_state(ctx, 0);
1042 op_ldst_lld(t0, t0, ctx);
1043 gen_store_gpr(t0, rt);
1044 opn = "lld";
1045 break;
1046 case OPC_SD:
1047 save_cpu_state(ctx, 0);
1048 gen_load_gpr(t1, rt);
1049 op_ldst_sd(t1, t0, ctx);
1050 opn = "sd";
1051 break;
1052 case OPC_LDL:
1053 save_cpu_state(ctx, 1);
1054 gen_load_gpr(t1, rt);
1055 gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
1056 gen_store_gpr(t1, rt);
1057 opn = "ldl";
1058 break;
1059 case OPC_SDL:
1060 save_cpu_state(ctx, 1);
1061 gen_load_gpr(t1, rt);
1062 gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
1063 opn = "sdl";
1064 break;
1065 case OPC_LDR:
1066 save_cpu_state(ctx, 1);
1067 gen_load_gpr(t1, rt);
1068 gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
1069 gen_store_gpr(t1, rt);
1070 opn = "ldr";
1071 break;
1072 case OPC_SDR:
1073 save_cpu_state(ctx, 1);
1074 gen_load_gpr(t1, rt);
1075 gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
1076 opn = "sdr";
1077 break;
1078 case OPC_LDPC:
1079 save_cpu_state(ctx, 1);
1080 tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
1081 gen_op_addr_add(ctx, t0, t0, t1);
1082 op_ldst_ld(t0, t0, ctx);
1083 gen_store_gpr(t0, rt);
1084 break;
1085 #endif
1086 case OPC_LWPC:
1087 save_cpu_state(ctx, 1);
1088 tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
1089 gen_op_addr_add(ctx, t0, t0, t1);
1090 op_ldst_lw(t0, t0, ctx);
1091 gen_store_gpr(t0, rt);
1092 break;
1093 case OPC_LW:
1094 save_cpu_state(ctx, 0);
1095 op_ldst_lw(t0, t0, ctx);
1096 gen_store_gpr(t0, rt);
1097 opn = "lw";
1098 break;
1099 case OPC_SW:
1100 save_cpu_state(ctx, 0);
1101 gen_load_gpr(t1, rt);
1102 op_ldst_sw(t1, t0, ctx);
1103 opn = "sw";
1104 break;
1105 case OPC_LH:
1106 save_cpu_state(ctx, 0);
1107 op_ldst_lh(t0, t0, ctx);
1108 gen_store_gpr(t0, rt);
1109 opn = "lh";
1110 break;
1111 case OPC_SH:
1112 save_cpu_state(ctx, 0);
1113 gen_load_gpr(t1, rt);
1114 op_ldst_sh(t1, t0, ctx);
1115 opn = "sh";
1116 break;
1117 case OPC_LHU:
1118 save_cpu_state(ctx, 0);
1119 op_ldst_lhu(t0, t0, ctx);
1120 gen_store_gpr(t0, rt);
1121 opn = "lhu";
1122 break;
1123 case OPC_LB:
1124 save_cpu_state(ctx, 0);
1125 op_ldst_lb(t0, t0, ctx);
1126 gen_store_gpr(t0, rt);
1127 opn = "lb";
1128 break;
1129 case OPC_SB:
1130 save_cpu_state(ctx, 0);
1131 gen_load_gpr(t1, rt);
1132 op_ldst_sb(t1, t0, ctx);
1133 opn = "sb";
1134 break;
1135 case OPC_LBU:
1136 save_cpu_state(ctx, 0);
1137 op_ldst_lbu(t0, t0, ctx);
1138 gen_store_gpr(t0, rt);
1139 opn = "lbu";
1140 break;
1141 case OPC_LWL:
1142 save_cpu_state(ctx, 1);
1143 gen_load_gpr(t1, rt);
1144 gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
1145 gen_store_gpr(t1, rt);
1146 opn = "lwl";
1147 break;
1148 case OPC_SWL:
1149 save_cpu_state(ctx, 1);
1150 gen_load_gpr(t1, rt);
1151 gen_helper_2i(swl, t1, t0, ctx->mem_idx);
1152 opn = "swr";
1153 break;
1154 case OPC_LWR:
1155 save_cpu_state(ctx, 1);
1156 gen_load_gpr(t1, rt);
1157 gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
1158 gen_store_gpr(t1, rt);
1159 opn = "lwr";
1160 break;
1161 case OPC_SWR:
1162 save_cpu_state(ctx, 1);
1163 gen_load_gpr(t1, rt);
1164 gen_helper_2i(swr, t1, t0, ctx->mem_idx);
1165 opn = "swr";
1166 break;
1167 case OPC_LL:
1168 save_cpu_state(ctx, 1);
1169 op_ldst_ll(t0, t0, ctx);
1170 gen_store_gpr(t0, rt);
1171 opn = "ll";
1172 break;
1173 }
1174 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1175 tcg_temp_free(t0);
1176 tcg_temp_free(t1);
1177 }
1178
1179 /* Store conditional */
1180 static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
1181 int base, int16_t offset)
1182 {
1183 const char *opn = "st_cond";
1184 TCGv t0, t1;
1185
1186 t0 = tcg_temp_local_new();
1187
1188 gen_base_offset_addr(ctx, t0, base, offset);
1189 /* Don't do NOP if destination is zero: we must perform the actual
1190 memory access. */
1191
1192 t1 = tcg_temp_local_new();
1193 gen_load_gpr(t1, rt);
1194 switch (opc) {
1195 #if defined(TARGET_MIPS64)
1196 case OPC_SCD:
1197 save_cpu_state(ctx, 0);
1198 op_ldst_scd(t1, t0, rt, ctx);
1199 opn = "scd";
1200 break;
1201 #endif
1202 case OPC_SC:
1203 save_cpu_state(ctx, 1);
1204 op_ldst_sc(t1, t0, rt, ctx);
1205 opn = "sc";
1206 break;
1207 }
1208 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1209 tcg_temp_free(t1);
1210 tcg_temp_free(t0);
1211 }
1212
1213 /* Load and store */
1214 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1215 int base, int16_t offset)
1216 {
1217 const char *opn = "flt_ldst";
1218 TCGv t0 = tcg_temp_new();
1219
1220 gen_base_offset_addr(ctx, t0, base, offset);
1221 /* Don't do NOP if destination is zero: we must perform the actual
1222 memory access. */
1223 switch (opc) {
1224 case OPC_LWC1:
1225 {
1226 TCGv_i32 fp0 = tcg_temp_new_i32();
1227
1228 tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
1229 tcg_gen_trunc_tl_i32(fp0, t0);
1230 gen_store_fpr32(fp0, ft);
1231 tcg_temp_free_i32(fp0);
1232 }
1233 opn = "lwc1";
1234 break;
1235 case OPC_SWC1:
1236 {
1237 TCGv_i32 fp0 = tcg_temp_new_i32();
1238 TCGv t1 = tcg_temp_new();
1239
1240 gen_load_fpr32(fp0, ft);
1241 tcg_gen_extu_i32_tl(t1, fp0);
1242 tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
1243 tcg_temp_free(t1);
1244 tcg_temp_free_i32(fp0);
1245 }
1246 opn = "swc1";
1247 break;
1248 case OPC_LDC1:
1249 {
1250 TCGv_i64 fp0 = tcg_temp_new_i64();
1251
1252 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
1253 gen_store_fpr64(ctx, fp0, ft);
1254 tcg_temp_free_i64(fp0);
1255 }
1256 opn = "ldc1";
1257 break;
1258 case OPC_SDC1:
1259 {
1260 TCGv_i64 fp0 = tcg_temp_new_i64();
1261
1262 gen_load_fpr64(ctx, fp0, ft);
1263 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
1264 tcg_temp_free_i64(fp0);
1265 }
1266 opn = "sdc1";
1267 break;
1268 default:
1269 MIPS_INVAL(opn);
1270 generate_exception(ctx, EXCP_RI);
1271 goto out;
1272 }
1273 MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
1274 out:
1275 tcg_temp_free(t0);
1276 }
1277
1278 /* Arithmetic with immediate operand */
1279 static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1280 int rt, int rs, int16_t imm)
1281 {
1282 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1283 const char *opn = "imm arith";
1284
1285 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
1286 /* If no destination, treat it as a NOP.
1287 For addi, we must generate the overflow exception when needed. */
1288 MIPS_DEBUG("NOP");
1289 return;
1290 }
1291 switch (opc) {
1292 case OPC_ADDI:
1293 {
1294 TCGv t0 = tcg_temp_local_new();
1295 TCGv t1 = tcg_temp_new();
1296 TCGv t2 = tcg_temp_new();
1297 int l1 = gen_new_label();
1298
1299 gen_load_gpr(t1, rs);
1300 tcg_gen_addi_tl(t0, t1, uimm);
1301 tcg_gen_ext32s_tl(t0, t0);
1302
1303 tcg_gen_xori_tl(t1, t1, ~uimm);
1304 tcg_gen_xori_tl(t2, t0, uimm);
1305 tcg_gen_and_tl(t1, t1, t2);
1306 tcg_temp_free(t2);
1307 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1308 tcg_temp_free(t1);
1309 /* operands of same sign, result different sign */
1310 generate_exception(ctx, EXCP_OVERFLOW);
1311 gen_set_label(l1);
1312 tcg_gen_ext32s_tl(t0, t0);
1313 gen_store_gpr(t0, rt);
1314 tcg_temp_free(t0);
1315 }
1316 opn = "addi";
1317 break;
1318 case OPC_ADDIU:
1319 if (rs != 0) {
1320 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1321 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
1322 } else {
1323 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1324 }
1325 opn = "addiu";
1326 break;
1327 #if defined(TARGET_MIPS64)
1328 case OPC_DADDI:
1329 {
1330 TCGv t0 = tcg_temp_local_new();
1331 TCGv t1 = tcg_temp_new();
1332 TCGv t2 = tcg_temp_new();
1333 int l1 = gen_new_label();
1334
1335 gen_load_gpr(t1, rs);
1336 tcg_gen_addi_tl(t0, t1, uimm);
1337
1338 tcg_gen_xori_tl(t1, t1, ~uimm);
1339 tcg_gen_xori_tl(t2, t0, uimm);
1340 tcg_gen_and_tl(t1, t1, t2);
1341 tcg_temp_free(t2);
1342 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1343 tcg_temp_free(t1);
1344 /* operands of same sign, result different sign */
1345 generate_exception(ctx, EXCP_OVERFLOW);
1346 gen_set_label(l1);
1347 gen_store_gpr(t0, rt);
1348 tcg_temp_free(t0);
1349 }
1350 opn = "daddi";
1351 break;
1352 case OPC_DADDIU:
1353 if (rs != 0) {
1354 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1355 } else {
1356 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1357 }
1358 opn = "daddiu";
1359 break;
1360 #endif
1361 }
1362 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1363 }
1364
1365 /* Logic with immediate operand */
1366 static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1367 {
1368 target_ulong uimm;
1369 const char *opn = "imm logic";
1370
1371 if (rt == 0) {
1372 /* If no destination, treat it as a NOP. */
1373 MIPS_DEBUG("NOP");
1374 return;
1375 }
1376 uimm = (uint16_t)imm;
1377 switch (opc) {
1378 case OPC_ANDI:
1379 if (likely(rs != 0))
1380 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1381 else
1382 tcg_gen_movi_tl(cpu_gpr[rt], 0);
1383 opn = "andi";
1384 break;
1385 case OPC_ORI:
1386 if (rs != 0)
1387 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1388 else
1389 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1390 opn = "ori";
1391 break;
1392 case OPC_XORI:
1393 if (likely(rs != 0))
1394 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1395 else
1396 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1397 opn = "xori";
1398 break;
1399 case OPC_LUI:
1400 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
1401 opn = "lui";
1402 break;
1403 }
1404 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1405 }
1406
1407 /* Set on less than with immediate operand */
1408 static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1409 {
1410 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1411 const char *opn = "imm arith";
1412 TCGv t0;
1413
1414 if (rt == 0) {
1415 /* If no destination, treat it as a NOP. */
1416 MIPS_DEBUG("NOP");
1417 return;
1418 }
1419 t0 = tcg_temp_new();
1420 gen_load_gpr(t0, rs);
1421 switch (opc) {
1422 case OPC_SLTI:
1423 gen_op_lti(cpu_gpr[rt], t0, uimm);
1424 opn = "slti";
1425 break;
1426 case OPC_SLTIU:
1427 gen_op_ltiu(cpu_gpr[rt], t0, uimm);
1428 opn = "sltiu";
1429 break;
1430 }
1431 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1432 tcg_temp_free(t0);
1433 }
1434
1435 /* Shifts with immediate operand */
1436 static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
1437 int rt, int rs, int16_t imm)
1438 {
1439 target_ulong uimm = ((uint16_t)imm) & 0x1f;
1440 const char *opn = "imm shift";
1441 TCGv t0;
1442
1443 if (rt == 0) {
1444 /* If no destination, treat it as a NOP. */
1445 MIPS_DEBUG("NOP");
1446 return;
1447 }
1448
1449 t0 = tcg_temp_new();
1450 gen_load_gpr(t0, rs);
1451 switch (opc) {
1452 case OPC_SLL:
1453 tcg_gen_shli_tl(t0, t0, uimm);
1454 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1455 opn = "sll";
1456 break;
1457 case OPC_SRA:
1458 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
1459 opn = "sra";
1460 break;
1461 case OPC_SRL:
1462 if (uimm != 0) {
1463 tcg_gen_ext32u_tl(t0, t0);
1464 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1465 } else {
1466 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1467 }
1468 opn = "srl";
1469 break;
1470 case OPC_ROTR:
1471 if (uimm != 0) {
1472 TCGv_i32 t1 = tcg_temp_new_i32();
1473
1474 tcg_gen_trunc_tl_i32(t1, t0);
1475 tcg_gen_rotri_i32(t1, t1, uimm);
1476 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
1477 tcg_temp_free_i32(t1);
1478 } else {
1479 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1480 }
1481 opn = "rotr";
1482 break;
1483 #if defined(TARGET_MIPS64)
1484 case OPC_DSLL:
1485 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
1486 opn = "dsll";
1487 break;
1488 case OPC_DSRA:
1489 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
1490 opn = "dsra";
1491 break;
1492 case OPC_DSRL:
1493 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1494 opn = "dsrl";
1495 break;
1496 case OPC_DROTR:
1497 if (uimm != 0) {
1498 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
1499 } else {
1500 tcg_gen_mov_tl(cpu_gpr[rt], t0);
1501 }
1502 opn = "drotr";
1503 break;
1504 case OPC_DSLL32:
1505 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
1506 opn = "dsll32";
1507 break;
1508 case OPC_DSRA32:
1509 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
1510 opn = "dsra32";
1511 break;
1512 case OPC_DSRL32:
1513 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
1514 opn = "dsrl32";
1515 break;
1516 case OPC_DROTR32:
1517 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
1518 opn = "drotr32";
1519 break;
1520 #endif
1521 }
1522 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1523 tcg_temp_free(t0);
1524 }
1525
1526 /* Arithmetic */
1527 static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1528 int rd, int rs, int rt)
1529 {
1530 const char *opn = "arith";
1531
1532 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
1533 && opc != OPC_DADD && opc != OPC_DSUB) {
1534 /* If no destination, treat it as a NOP.
1535 For add & sub, we must generate the overflow exception when needed. */
1536 MIPS_DEBUG("NOP");
1537 return;
1538 }
1539
1540 switch (opc) {
1541 case OPC_ADD:
1542 {
1543 TCGv t0 = tcg_temp_local_new();
1544 TCGv t1 = tcg_temp_new();
1545 TCGv t2 = tcg_temp_new();
1546 int l1 = gen_new_label();
1547
1548 gen_load_gpr(t1, rs);
1549 gen_load_gpr(t2, rt);
1550 tcg_gen_add_tl(t0, t1, t2);
1551 tcg_gen_ext32s_tl(t0, t0);
1552 tcg_gen_xor_tl(t1, t1, t2);
1553 tcg_gen_not_tl(t1, t1);
1554 tcg_gen_xor_tl(t2, t0, t2);
1555 tcg_gen_and_tl(t1, t1, t2);
1556 tcg_temp_free(t2);
1557 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1558 tcg_temp_free(t1);
1559 /* operands of same sign, result different sign */
1560 generate_exception(ctx, EXCP_OVERFLOW);
1561 gen_set_label(l1);
1562 gen_store_gpr(t0, rd);
1563 tcg_temp_free(t0);
1564 }
1565 opn = "add";
1566 break;
1567 case OPC_ADDU:
1568 if (rs != 0 && rt != 0) {
1569 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1570 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1571 } else if (rs == 0 && rt != 0) {
1572 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1573 } else if (rs != 0 && rt == 0) {
1574 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1575 } else {
1576 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1577 }
1578 opn = "addu";
1579 break;
1580 case OPC_SUB:
1581 {
1582 TCGv t0 = tcg_temp_local_new();
1583 TCGv t1 = tcg_temp_new();
1584 TCGv t2 = tcg_temp_new();
1585 int l1 = gen_new_label();
1586
1587 gen_load_gpr(t1, rs);
1588 gen_load_gpr(t2, rt);
1589 tcg_gen_sub_tl(t0, t1, t2);
1590 tcg_gen_ext32s_tl(t0, t0);
1591 tcg_gen_xor_tl(t2, t1, t2);
1592 tcg_gen_xor_tl(t1, t0, t1);
1593 tcg_gen_and_tl(t1, t1, t2);
1594 tcg_temp_free(t2);
1595 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1596 tcg_temp_free(t1);
1597 /* operands of different sign, first operand and result different sign */
1598 generate_exception(ctx, EXCP_OVERFLOW);
1599 gen_set_label(l1);
1600 gen_store_gpr(t0, rd);
1601 tcg_temp_free(t0);
1602 }
1603 opn = "sub";
1604 break;
1605 case OPC_SUBU:
1606 if (rs != 0 && rt != 0) {
1607 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1608 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1609 } else if (rs == 0 && rt != 0) {
1610 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
1611 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1612 } else if (rs != 0 && rt == 0) {
1613 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1614 } else {
1615 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1616 }
1617 opn = "subu";
1618 break;
1619 #if defined(TARGET_MIPS64)
1620 case OPC_DADD:
1621 {
1622 TCGv t0 = tcg_temp_local_new();
1623 TCGv t1 = tcg_temp_new();
1624 TCGv t2 = tcg_temp_new();
1625 int l1 = gen_new_label();
1626
1627 gen_load_gpr(t1, rs);
1628 gen_load_gpr(t2, rt);
1629 tcg_gen_add_tl(t0, t1, t2);
1630 tcg_gen_xor_tl(t1, t1, t2);
1631 tcg_gen_not_tl(t1, t1);
1632 tcg_gen_xor_tl(t2, t0, t2);
1633 tcg_gen_and_tl(t1, t1, t2);
1634 tcg_temp_free(t2);
1635 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1636 tcg_temp_free(t1);
1637 /* operands of same sign, result different sign */
1638 generate_exception(ctx, EXCP_OVERFLOW);
1639 gen_set_label(l1);
1640 gen_store_gpr(t0, rd);
1641 tcg_temp_free(t0);
1642 }
1643 opn = "dadd";
1644 break;
1645 case OPC_DADDU:
1646 if (rs != 0 && rt != 0) {
1647 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1648 } else if (rs == 0 && rt != 0) {
1649 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1650 } else if (rs != 0 && rt == 0) {
1651 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1652 } else {
1653 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1654 }
1655 opn = "daddu";
1656 break;
1657 case OPC_DSUB:
1658 {
1659 TCGv t0 = tcg_temp_local_new();
1660 TCGv t1 = tcg_temp_new();
1661 TCGv t2 = tcg_temp_new();
1662 int l1 = gen_new_label();
1663
1664 gen_load_gpr(t1, rs);
1665 gen_load_gpr(t2, rt);
1666 tcg_gen_sub_tl(t0, t1, t2);
1667 tcg_gen_xor_tl(t2, t1, t2);
1668 tcg_gen_xor_tl(t1, t0, t1);
1669 tcg_gen_and_tl(t1, t1, t2);
1670 tcg_temp_free(t2);
1671 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1672 tcg_temp_free(t1);
1673 /* operands of different sign, first operand and result different sign */
1674 generate_exception(ctx, EXCP_OVERFLOW);
1675 gen_set_label(l1);
1676 gen_store_gpr(t0, rd);
1677 tcg_temp_free(t0);
1678 }
1679 opn = "dsub";
1680 break;
1681 case OPC_DSUBU:
1682 if (rs != 0 && rt != 0) {
1683 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1684 } else if (rs == 0 && rt != 0) {
1685 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
1686 } else if (rs != 0 && rt == 0) {
1687 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1688 } else {
1689 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1690 }
1691 opn = "dsubu";
1692 break;
1693 #endif
1694 case OPC_MUL:
1695 if (likely(rs != 0 && rt != 0)) {
1696 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1697 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1698 } else {
1699 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1700 }
1701 opn = "mul";
1702 break;
1703 }
1704 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1705 }
1706
1707 /* Conditional move */
1708 static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1709 {
1710 const char *opn = "cond move";
1711 int l1;
1712
1713 if (rd == 0) {
1714 /* If no destination, treat it as a NOP.
1715 For add & sub, we must generate the overflow exception when needed. */
1716 MIPS_DEBUG("NOP");
1717 return;
1718 }
1719
1720 l1 = gen_new_label();
1721 switch (opc) {
1722 case OPC_MOVN:
1723 if (likely(rt != 0))
1724 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1);
1725 else
1726 tcg_gen_br(l1);
1727 opn = "movn";
1728 break;
1729 case OPC_MOVZ:
1730 if (likely(rt != 0))
1731 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1);
1732 opn = "movz";
1733 break;
1734 }
1735 if (rs != 0)
1736 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1737 else
1738 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1739 gen_set_label(l1);
1740
1741 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1742 }
1743
1744 /* Logic */
1745 static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1746 {
1747 const char *opn = "logic";
1748
1749 if (rd == 0) {
1750 /* If no destination, treat it as a NOP. */
1751 MIPS_DEBUG("NOP");
1752 return;
1753 }
1754
1755 switch (opc) {
1756 case OPC_AND:
1757 if (likely(rs != 0 && rt != 0)) {
1758 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1759 } else {
1760 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1761 }
1762 opn = "and";
1763 break;
1764 case OPC_NOR:
1765 if (rs != 0 && rt != 0) {
1766 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1767 } else if (rs == 0 && rt != 0) {
1768 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
1769 } else if (rs != 0 && rt == 0) {
1770 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
1771 } else {
1772 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
1773 }
1774 opn = "nor";
1775 break;
1776 case OPC_OR:
1777 if (likely(rs != 0 && rt != 0)) {
1778 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1779 } else if (rs == 0 && rt != 0) {
1780 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1781 } else if (rs != 0 && rt == 0) {
1782 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1783 } else {
1784 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1785 }
1786 opn = "or";
1787 break;
1788 case OPC_XOR:
1789 if (likely(rs != 0 && rt != 0)) {
1790 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1791 } else if (rs == 0 && rt != 0) {
1792 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1793 } else if (rs != 0 && rt == 0) {
1794 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1795 } else {
1796 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1797 }
1798 opn = "xor";
1799 break;
1800 }
1801 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1802 }
1803
1804 /* Set on lower than */
1805 static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1806 {
1807 const char *opn = "slt";
1808 TCGv t0, t1;
1809
1810 if (rd == 0) {
1811 /* If no destination, treat it as a NOP. */
1812 MIPS_DEBUG("NOP");
1813 return;
1814 }
1815
1816 t0 = tcg_temp_new();
1817 t1 = tcg_temp_new();
1818 gen_load_gpr(t0, rs);
1819 gen_load_gpr(t1, rt);
1820 switch (opc) {
1821 case OPC_SLT:
1822 gen_op_lt(cpu_gpr[rd], t0, t1);
1823 opn = "slt";
1824 break;
1825 case OPC_SLTU:
1826 gen_op_ltu(cpu_gpr[rd], t0, t1);
1827 opn = "sltu";
1828 break;
1829 }
1830 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1831 tcg_temp_free(t0);
1832 tcg_temp_free(t1);
1833 }
1834
1835 /* Shifts */
1836 static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
1837 int rd, int rs, int rt)
1838 {
1839 const char *opn = "shifts";
1840 TCGv t0, t1;
1841
1842 if (rd == 0) {
1843 /* If no destination, treat it as a NOP.
1844 For add & sub, we must generate the overflow exception when needed. */
1845 MIPS_DEBUG("NOP");
1846 return;
1847 }
1848
1849 t0 = tcg_temp_new();
1850 t1 = tcg_temp_new();
1851 gen_load_gpr(t0, rs);
1852 gen_load_gpr(t1, rt);
1853 switch (opc) {
1854 case OPC_SLLV:
1855 tcg_gen_andi_tl(t0, t0, 0x1f);
1856 tcg_gen_shl_tl(t0, t1, t0);
1857 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1858 opn = "sllv";
1859 break;
1860 case OPC_SRAV:
1861 tcg_gen_andi_tl(t0, t0, 0x1f);
1862 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
1863 opn = "srav";
1864 break;
1865 case OPC_SRLV:
1866 tcg_gen_ext32u_tl(t1, t1);
1867 tcg_gen_andi_tl(t0, t0, 0x1f);
1868 tcg_gen_shr_tl(t0, t1, t0);
1869 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1870 opn = "srlv";
1871 break;
1872 case OPC_ROTRV:
1873 {
1874 TCGv_i32 t2 = tcg_temp_new_i32();
1875 TCGv_i32 t3 = tcg_temp_new_i32();
1876
1877 tcg_gen_trunc_tl_i32(t2, t0);
1878 tcg_gen_trunc_tl_i32(t3, t1);
1879 tcg_gen_andi_i32(t2, t2, 0x1f);
1880 tcg_gen_rotr_i32(t2, t3, t2);
1881 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
1882 tcg_temp_free_i32(t2);
1883 tcg_temp_free_i32(t3);
1884 opn = "rotrv";
1885 }
1886 break;
1887 #if defined(TARGET_MIPS64)
1888 case OPC_DSLLV:
1889 tcg_gen_andi_tl(t0, t0, 0x3f);
1890 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
1891 opn = "dsllv";
1892 break;
1893 case OPC_DSRAV:
1894 tcg_gen_andi_tl(t0, t0, 0x3f);
1895 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
1896 opn = "dsrav";
1897 break;
1898 case OPC_DSRLV:
1899 tcg_gen_andi_tl(t0, t0, 0x3f);
1900 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
1901 opn = "dsrlv";
1902 break;
1903 case OPC_DROTRV:
1904 tcg_gen_andi_tl(t0, t0, 0x3f);
1905 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
1906 opn = "drotrv";
1907 break;
1908 #endif
1909 }
1910 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1911 tcg_temp_free(t0);
1912 tcg_temp_free(t1);
1913 }
1914
1915 /* Arithmetic on HI/LO registers */
1916 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1917 {
1918 const char *opn = "hilo";
1919
1920 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1921 /* Treat as NOP. */
1922 MIPS_DEBUG("NOP");
1923 return;
1924 }
1925 switch (opc) {
1926 case OPC_MFHI:
1927 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
1928 opn = "mfhi";
1929 break;
1930 case OPC_MFLO:
1931 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
1932 opn = "mflo";
1933 break;
1934 case OPC_MTHI:
1935 if (reg != 0)
1936 tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
1937 else
1938 tcg_gen_movi_tl(cpu_HI[0], 0);
1939 opn = "mthi";
1940 break;
1941 case OPC_MTLO:
1942 if (reg != 0)
1943 tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
1944 else
1945 tcg_gen_movi_tl(cpu_LO[0], 0);
1946 opn = "mtlo";
1947 break;
1948 }
1949 MIPS_DEBUG("%s %s", opn, regnames[reg]);
1950 }
1951
1952 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1953 int rs, int rt)
1954 {
1955 const char *opn = "mul/div";
1956 TCGv t0, t1;
1957
1958 switch (opc) {
1959 case OPC_DIV:
1960 case OPC_DIVU:
1961 #if defined(TARGET_MIPS64)
1962 case OPC_DDIV:
1963 case OPC_DDIVU:
1964 #endif
1965 t0 = tcg_temp_local_new();
1966 t1 = tcg_temp_local_new();
1967 break;
1968 default:
1969 t0 = tcg_temp_new();
1970 t1 = tcg_temp_new();
1971 break;
1972 }
1973
1974 gen_load_gpr(t0, rs);
1975 gen_load_gpr(t1, rt);
1976 switch (opc) {
1977 case OPC_DIV:
1978 {
1979 int l1 = gen_new_label();
1980 int l2 = gen_new_label();
1981
1982 tcg_gen_ext32s_tl(t0, t0);
1983 tcg_gen_ext32s_tl(t1, t1);
1984 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
1985 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
1986 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
1987
1988 tcg_gen_mov_tl(cpu_LO[0], t0);
1989 tcg_gen_movi_tl(cpu_HI[0], 0);
1990 tcg_gen_br(l1);
1991 gen_set_label(l2);
1992 tcg_gen_div_tl(cpu_LO[0], t0, t1);
1993 tcg_gen_rem_tl(cpu_HI[0], t0, t1);
1994 tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
1995 tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
1996 gen_set_label(l1);
1997 }
1998 opn = "div";
1999 break;
2000 case OPC_DIVU:
2001 {
2002 int l1 = gen_new_label();
2003
2004 tcg_gen_ext32u_tl(t0, t0);
2005 tcg_gen_ext32u_tl(t1, t1);
2006 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2007 tcg_gen_divu_tl(cpu_LO[0], t0, t1);
2008 tcg_gen_remu_tl(cpu_HI[0], t0, t1);
2009 tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
2010 tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
2011 gen_set_label(l1);
2012 }
2013 opn = "divu";
2014 break;
2015 case OPC_MULT:
2016 {
2017 TCGv_i64 t2 = tcg_temp_new_i64();
2018 TCGv_i64 t3 = tcg_temp_new_i64();
2019
2020 tcg_gen_ext_tl_i64(t2, t0);
2021 tcg_gen_ext_tl_i64(t3, t1);
2022 tcg_gen_mul_i64(t2, t2, t3);
2023 tcg_temp_free_i64(t3);
2024 tcg_gen_trunc_i64_tl(t0, t2);
2025 tcg_gen_shri_i64(t2, t2, 32);
2026 tcg_gen_trunc_i64_tl(t1, t2);
2027 tcg_temp_free_i64(t2);
2028 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2029 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2030 }
2031 opn = "mult";
2032 break;
2033 case OPC_MULTU:
2034 {
2035 TCGv_i64 t2 = tcg_temp_new_i64();
2036 TCGv_i64 t3 = tcg_temp_new_i64();
2037
2038 tcg_gen_ext32u_tl(t0, t0);
2039 tcg_gen_ext32u_tl(t1, t1);
2040 tcg_gen_extu_tl_i64(t2, t0);
2041 tcg_gen_extu_tl_i64(t3, t1);
2042 tcg_gen_mul_i64(t2, t2, t3);
2043 tcg_temp_free_i64(t3);
2044 tcg_gen_trunc_i64_tl(t0, t2);
2045 tcg_gen_shri_i64(t2, t2, 32);
2046 tcg_gen_trunc_i64_tl(t1, t2);
2047 tcg_temp_free_i64(t2);
2048 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2049 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2050 }
2051 opn = "multu";
2052 break;
2053 #if defined(TARGET_MIPS64)
2054 case OPC_DDIV:
2055 {
2056 int l1 = gen_new_label();
2057 int l2 = gen_new_label();
2058
2059 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2060 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
2061 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
2062 tcg_gen_mov_tl(cpu_LO[0], t0);
2063 tcg_gen_movi_tl(cpu_HI[0], 0);
2064 tcg_gen_br(l1);
2065 gen_set_label(l2);
2066 tcg_gen_div_i64(cpu_LO[0], t0, t1);
2067 tcg_gen_rem_i64(cpu_HI[0], t0, t1);
2068 gen_set_label(l1);
2069 }
2070 opn = "ddiv";
2071 break;
2072 case OPC_DDIVU:
2073 {
2074 int l1 = gen_new_label();
2075
2076 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2077 tcg_gen_divu_i64(cpu_LO[0], t0, t1);
2078 tcg_gen_remu_i64(cpu_HI[0], t0, t1);
2079 gen_set_label(l1);
2080 }
2081 opn = "ddivu";
2082 break;
2083 case OPC_DMULT:
2084 gen_helper_dmult(t0, t1);
2085 opn = "dmult";
2086 break;
2087 case OPC_DMULTU:
2088 gen_helper_dmultu(t0, t1);
2089 opn = "dmultu";
2090 break;
2091 #endif
2092 case OPC_MADD:
2093 {
2094 TCGv_i64 t2 = tcg_temp_new_i64();
2095 TCGv_i64 t3 = tcg_temp_new_i64();
2096
2097 tcg_gen_ext_tl_i64(t2, t0);
2098 tcg_gen_ext_tl_i64(t3, t1);
2099 tcg_gen_mul_i64(t2, t2, t3);
2100 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2101 tcg_gen_add_i64(t2, t2, t3);
2102 tcg_temp_free_i64(t3);
2103 tcg_gen_trunc_i64_tl(t0, t2);
2104 tcg_gen_shri_i64(t2, t2, 32);
2105 tcg_gen_trunc_i64_tl(t1, t2);
2106 tcg_temp_free_i64(t2);
2107 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2108 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2109 }
2110 opn = "madd";
2111 break;
2112 case OPC_MADDU:
2113 {
2114 TCGv_i64 t2 = tcg_temp_new_i64();
2115 TCGv_i64 t3 = tcg_temp_new_i64();
2116
2117 tcg_gen_ext32u_tl(t0, t0);
2118 tcg_gen_ext32u_tl(t1, t1);
2119 tcg_gen_extu_tl_i64(t2, t0);
2120 tcg_gen_extu_tl_i64(t3, t1);
2121 tcg_gen_mul_i64(t2, t2, t3);
2122 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2123 tcg_gen_add_i64(t2, t2, t3);
2124 tcg_temp_free_i64(t3);
2125 tcg_gen_trunc_i64_tl(t0, t2);
2126 tcg_gen_shri_i64(t2, t2, 32);
2127 tcg_gen_trunc_i64_tl(t1, t2);
2128 tcg_temp_free_i64(t2);
2129 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2130 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2131 }
2132 opn = "maddu";
2133 break;
2134 case OPC_MSUB:
2135 {
2136 TCGv_i64 t2 = tcg_temp_new_i64();
2137 TCGv_i64 t3 = tcg_temp_new_i64();
2138
2139 tcg_gen_ext_tl_i64(t2, t0);
2140 tcg_gen_ext_tl_i64(t3, t1);
2141 tcg_gen_mul_i64(t2, t2, t3);
2142 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2143 tcg_gen_sub_i64(t2, t3, t2);
2144 tcg_temp_free_i64(t3);
2145 tcg_gen_trunc_i64_tl(t0, t2);
2146 tcg_gen_shri_i64(t2, t2, 32);
2147 tcg_gen_trunc_i64_tl(t1, t2);
2148 tcg_temp_free_i64(t2);
2149 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2150 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2151 }
2152 opn = "msub";
2153 break;
2154 case OPC_MSUBU:
2155 {
2156 TCGv_i64 t2 = tcg_temp_new_i64();
2157 TCGv_i64 t3 = tcg_temp_new_i64();
2158
2159 tcg_gen_ext32u_tl(t0, t0);
2160 tcg_gen_ext32u_tl(t1, t1);
2161 tcg_gen_extu_tl_i64(t2, t0);
2162 tcg_gen_extu_tl_i64(t3, t1);
2163 tcg_gen_mul_i64(t2, t2, t3);
2164 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2165 tcg_gen_sub_i64(t2, t3, t2);
2166 tcg_temp_free_i64(t3);
2167 tcg_gen_trunc_i64_tl(t0, t2);
2168 tcg_gen_shri_i64(t2, t2, 32);
2169 tcg_gen_trunc_i64_tl(t1, t2);
2170 tcg_temp_free_i64(t2);
2171 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2172 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2173 }
2174 opn = "msubu";
2175 break;
2176 default:
2177 MIPS_INVAL(opn);
2178 generate_exception(ctx, EXCP_RI);
2179 goto out;
2180 }
2181 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
2182 out:
2183 tcg_temp_free(t0);
2184 tcg_temp_free(t1);
2185 }
2186
2187 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2188 int rd, int rs, int rt)
2189 {
2190 const char *opn = "mul vr54xx";
2191 TCGv t0 = tcg_temp_new();
2192 TCGv t1 = tcg_temp_new();
2193
2194 gen_load_gpr(t0, rs);
2195 gen_load_gpr(t1, rt);
2196
2197 switch (opc) {
2198 case OPC_VR54XX_MULS:
2199 gen_helper_muls(t0, t0, t1);
2200 opn = "muls";
2201 break;
2202 case OPC_VR54XX_MULSU:
2203 gen_helper_mulsu(t0, t0, t1);
2204 opn = "mulsu";
2205 break;
2206 case OPC_VR54XX_MACC:
2207 gen_helper_macc(t0, t0, t1);
2208 opn = "macc";
2209 break;
2210 case OPC_VR54XX_MACCU:
2211 gen_helper_maccu(t0, t0, t1);
2212 opn = "maccu";
2213 break;
2214 case OPC_VR54XX_MSAC:
2215 gen_helper_msac(t0, t0, t1);
2216 opn = "msac";
2217 break;
2218 case OPC_VR54XX_MSACU:
2219 gen_helper_msacu(t0, t0, t1);
2220 opn = "msacu";
2221 break;
2222 case OPC_VR54XX_MULHI:
2223 gen_helper_mulhi(t0, t0, t1);
2224 opn = "mulhi";
2225 break;
2226 case OPC_VR54XX_MULHIU:
2227 gen_helper_mulhiu(t0, t0, t1);
2228 opn = "mulhiu";
2229 break;
2230 case OPC_VR54XX_MULSHI:
2231 gen_helper_mulshi(t0, t0, t1);
2232 opn = "mulshi";
2233 break;
2234 case OPC_VR54XX_MULSHIU:
2235 gen_helper_mulshiu(t0, t0, t1);
2236 opn = "mulshiu";
2237 break;
2238 case OPC_VR54XX_MACCHI:
2239 gen_helper_macchi(t0, t0, t1);
2240 opn = "macchi";
2241 break;
2242 case OPC_VR54XX_MACCHIU:
2243 gen_helper_macchiu(t0, t0, t1);
2244 opn = "macchiu";
2245 break;
2246 case OPC_VR54XX_MSACHI:
2247 gen_helper_msachi(t0, t0, t1);
2248 opn = "msachi";
2249 break;
2250 case OPC_VR54XX_MSACHIU:
2251 gen_helper_msachiu(t0, t0, t1);
2252 opn = "msachiu";
2253 break;
2254 default:
2255 MIPS_INVAL("mul vr54xx");
2256 generate_exception(ctx, EXCP_RI);
2257 goto out;
2258 }
2259 gen_store_gpr(t0, rd);
2260 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
2261
2262 out:
2263 tcg_temp_free(t0);
2264 tcg_temp_free(t1);
2265 }
2266
2267 static void gen_cl (DisasContext *ctx, uint32_t opc,
2268 int rd, int rs)
2269 {
2270 const char *opn = "CLx";
2271 TCGv t0;
2272
2273 if (rd == 0) {
2274 /* Treat as NOP. */
2275 MIPS_DEBUG("NOP");
2276 return;
2277 }
2278 t0 = tcg_temp_new();
2279 gen_load_gpr(t0, rs);
2280 switch (opc) {
2281 case OPC_CLO:
2282 gen_helper_clo(cpu_gpr[rd], t0);
2283 opn = "clo";
2284 break;
2285 case OPC_CLZ:
2286 gen_helper_clz(cpu_gpr[rd], t0);
2287 opn = "clz";
2288 break;
2289 #if defined(TARGET_MIPS64)
2290 case OPC_DCLO:
2291 gen_helper_dclo(cpu_gpr[rd], t0);
2292 opn = "dclo";
2293 break;
2294 case OPC_DCLZ:
2295 gen_helper_dclz(cpu_gpr[rd], t0);
2296 opn = "dclz";
2297 break;
2298 #endif
2299 }
2300 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2301 tcg_temp_free(t0);
2302 }
2303
2304 /* Traps */
2305 static void gen_trap (DisasContext *ctx, uint32_t opc,
2306 int rs, int rt, int16_t imm)
2307 {
2308 int cond;
2309 TCGv t0 = tcg_temp_new();
2310 TCGv t1 = tcg_temp_new();
2311
2312 cond = 0;
2313 /* Load needed operands */
2314 switch (opc) {
2315 case OPC_TEQ:
2316 case OPC_TGE:
2317 case OPC_TGEU:
2318 case OPC_TLT:
2319 case OPC_TLTU:
2320 case OPC_TNE:
2321 /* Compare two registers */
2322 if (rs != rt) {
2323 gen_load_gpr(t0, rs);
2324 gen_load_gpr(t1, rt);
2325 cond = 1;
2326 }
2327 break;
2328 case OPC_TEQI:
2329 case OPC_TGEI:
2330 case OPC_TGEIU:
2331 case OPC_TLTI:
2332 case OPC_TLTIU:
2333 case OPC_TNEI:
2334 /* Compare register to immediate */
2335 if (rs != 0 || imm != 0) {
2336 gen_load_gpr(t0, rs);
2337 tcg_gen_movi_tl(t1, (int32_t)imm);
2338 cond = 1;
2339 }
2340 break;
2341 }
2342 if (cond == 0) {
2343 switch (opc) {
2344 case OPC_TEQ: /* rs == rs */
2345 case OPC_TEQI: /* r0 == 0 */
2346 case OPC_TGE: /* rs >= rs */
2347 case OPC_TGEI: /* r0 >= 0 */
2348 case OPC_TGEU: /* rs >= rs unsigned */
2349 case OPC_TGEIU: /* r0 >= 0 unsigned */
2350 /* Always trap */
2351 generate_exception(ctx, EXCP_TRAP);
2352 break;
2353 case OPC_TLT: /* rs < rs */
2354 case OPC_TLTI: /* r0 < 0 */
2355 case OPC_TLTU: /* rs < rs unsigned */
2356 case OPC_TLTIU: /* r0 < 0 unsigned */
2357 case OPC_TNE: /* rs != rs */
2358 case OPC_TNEI: /* r0 != 0 */
2359 /* Never trap: treat as NOP. */
2360 break;
2361 }
2362 } else {
2363 int l1 = gen_new_label();
2364
2365 switch (opc) {
2366 case OPC_TEQ:
2367 case OPC_TEQI:
2368 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
2369 break;
2370 case OPC_TGE:
2371 case OPC_TGEI:
2372 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
2373 break;
2374 case OPC_TGEU:
2375 case OPC_TGEIU:
2376 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
2377 break;
2378 case OPC_TLT:
2379 case OPC_TLTI:
2380 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
2381 break;
2382 case OPC_TLTU:
2383 case OPC_TLTIU:
2384 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
2385 break;
2386 case OPC_TNE:
2387 case OPC_TNEI:
2388 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
2389 break;
2390 }
2391 generate_exception(ctx, EXCP_TRAP);
2392 gen_set_label(l1);
2393 }
2394 tcg_temp_free(t0);
2395 tcg_temp_free(t1);
2396 }
2397
2398 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2399 {
2400 TranslationBlock *tb;
2401 tb = ctx->tb;
2402 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2403 likely(!ctx->singlestep_enabled)) {
2404 tcg_gen_goto_tb(n);
2405 gen_save_pc(dest);
2406 tcg_gen_exit_tb((long)tb + n);
2407 } else {
2408 gen_save_pc(dest);
2409 if (ctx->singlestep_enabled) {
2410 save_cpu_state(ctx, 0);
2411 gen_helper_0i(raise_exception, EXCP_DEBUG);
2412 }
2413 tcg_gen_exit_tb(0);
2414 }
2415 }
2416
2417 /* Branches (before delay slot) */
2418 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2419 int insn_bytes,
2420 int rs, int rt, int32_t offset)
2421 {
2422 target_ulong btgt = -1;
2423 int blink = 0;
2424 int bcond_compute = 0;
2425 TCGv t0 = tcg_temp_new();
2426 TCGv t1 = tcg_temp_new();
2427
2428 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2429 #ifdef MIPS_DEBUG_DISAS
2430 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
2431 #endif
2432 generate_exception(ctx, EXCP_RI);
2433 goto out;
2434 }
2435
2436 /* Load needed operands */
2437 switch (opc) {
2438 case OPC_BEQ:
2439 case OPC_BEQL:
2440 case OPC_BNE:
2441 case OPC_BNEL:
2442 /* Compare two registers */
2443 if (rs != rt) {
2444 gen_load_gpr(t0, rs);
2445 gen_load_gpr(t1, rt);
2446 bcond_compute = 1;
2447 }
2448 btgt = ctx->pc + insn_bytes + offset;
2449 break;
2450 case OPC_BGEZ:
2451 case OPC_BGEZAL:
2452 case OPC_BGEZALL:
2453 case OPC_BGEZL:
2454 case OPC_BGTZ:
2455 case OPC_BGTZL:
2456 case OPC_BLEZ:
2457 case OPC_BLEZL:
2458 case OPC_BLTZ:
2459 case OPC_BLTZAL:
2460 case OPC_BLTZALL:
2461 case OPC_BLTZL:
2462 /* Compare to zero */
2463 if (rs != 0) {
2464 gen_load_gpr(t0, rs);
2465 bcond_compute = 1;
2466 }
2467 btgt = ctx->pc + insn_bytes + offset;
2468 break;
2469 case OPC_J:
2470 case OPC_JAL:
2471 case OPC_JALX:
2472 /* Jump to immediate */
2473 btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset;
2474 break;
2475 case OPC_JR:
2476 case OPC_JALR:
2477 case OPC_JALRC:
2478 /* Jump to register */
2479 if (offset != 0 && offset != 16) {
2480 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2481 others are reserved. */
2482 MIPS_INVAL("jump hint");
2483 generate_exception(ctx, EXCP_RI);
2484 goto out;
2485 }
2486 gen_load_gpr(btarget, rs);
2487 break;
2488 default:
2489 MIPS_INVAL("branch/jump");
2490 generate_exception(ctx, EXCP_RI);
2491 goto out;
2492 }
2493 if (bcond_compute == 0) {
2494 /* No condition to be computed */
2495 switch (opc) {
2496 case OPC_BEQ: /* rx == rx */
2497 case OPC_BEQL: /* rx == rx likely */
2498 case OPC_BGEZ: /* 0 >= 0 */
2499 case OPC_BGEZL: /* 0 >= 0 likely */
2500 case OPC_BLEZ: /* 0 <= 0 */
2501 case OPC_BLEZL: /* 0 <= 0 likely */
2502 /* Always take */
2503 ctx->hflags |= MIPS_HFLAG_B;
2504 MIPS_DEBUG("balways");
2505 break;
2506 case OPC_BGEZAL: /* 0 >= 0 */
2507 case OPC_BGEZALL: /* 0 >= 0 likely */
2508 /* Always take and link */
2509 blink = 31;
2510 ctx->hflags |= MIPS_HFLAG_B;
2511 MIPS_DEBUG("balways and link");
2512 break;
2513 case OPC_BNE: /* rx != rx */
2514 case OPC_BGTZ: /* 0 > 0 */
2515 case OPC_BLTZ: /* 0 < 0 */
2516 /* Treat as NOP. */
2517 MIPS_DEBUG("bnever (NOP)");
2518 goto out;
2519 case OPC_BLTZAL: /* 0 < 0 */
2520 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2521 MIPS_DEBUG("bnever and link");
2522 goto out;
2523 case OPC_BLTZALL: /* 0 < 0 likely */
2524 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2525 /* Skip the instruction in the delay slot */
2526 MIPS_DEBUG("bnever, link and skip");
2527 ctx->pc += 4;
2528 goto out;
2529 case OPC_BNEL: /* rx != rx likely */
2530 case OPC_BGTZL: /* 0 > 0 likely */
2531 case OPC_BLTZL: /* 0 < 0 likely */
2532 /* Skip the instruction in the delay slot */
2533 MIPS_DEBUG("bnever and skip");
2534 ctx->pc += 4;
2535 goto out;
2536 case OPC_J:
2537 ctx->hflags |= MIPS_HFLAG_B;
2538 MIPS_DEBUG("j " TARGET_FMT_lx, btgt);
2539 break;
2540 case OPC_JALX:
2541 ctx->hflags |= MIPS_HFLAG_BX;
2542 /* Fallthrough */
2543 case OPC_JAL:
2544 blink = 31;
2545 ctx->hflags |= MIPS_HFLAG_B;
2546 ctx->hflags |= (ctx->hflags & MIPS_HFLAG_M16
2547 ? MIPS_HFLAG_BDS16
2548 : MIPS_HFLAG_BDS32);
2549 MIPS_DEBUG("jal " TARGET_FMT_lx, btgt);
2550 break;
2551 case OPC_JR:
2552 ctx->hflags |= MIPS_HFLAG_BR;
2553 if (ctx->hflags & MIPS_HFLAG_M16)
2554 ctx->hflags |= MIPS_HFLAG_BDS16;
2555 MIPS_DEBUG("jr %s", regnames[rs]);
2556 break;
2557 case OPC_JALR:
2558 case OPC_JALRC:
2559 blink = rt;
2560 ctx->hflags |= MIPS_HFLAG_BR;
2561 if (ctx->hflags & MIPS_HFLAG_M16)
2562 ctx->hflags |= MIPS_HFLAG_BDS16;
2563 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
2564 break;
2565 default:
2566 MIPS_INVAL("branch/jump");
2567 generate_exception(ctx, EXCP_RI);
2568 goto out;
2569 }
2570 } else {
2571 switch (opc) {
2572 case OPC_BEQ:
2573 gen_op_eq(bcond, t0, t1);
2574 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2575 regnames[rs], regnames[rt], btgt);
2576 goto not_likely;
2577 case OPC_BEQL:
2578 gen_op_eq(bcond, t0, t1);
2579 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2580 regnames[rs], regnames[rt], btgt);
2581 goto likely;
2582 case OPC_BNE:
2583 gen_op_ne(bcond, t0, t1);
2584 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2585 regnames[rs], regnames[rt], btgt);
2586 goto not_likely;
2587 case OPC_BNEL:
2588 gen_op_ne(bcond, t0, t1);
2589 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2590 regnames[rs], regnames[rt], btgt);
2591 goto likely;
2592 case OPC_BGEZ:
2593 gen_op_gez(bcond, t0);
2594 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2595 goto not_likely;
2596 case OPC_BGEZL:
2597 gen_op_gez(bcond, t0);
2598 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2599 goto likely;
2600 case OPC_BGEZAL:
2601 gen_op_gez(bcond, t0);
2602 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2603 blink = 31;
2604 goto not_likely;
2605 case OPC_BGEZALL:
2606 gen_op_gez(bcond, t0);
2607 blink = 31;
2608 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2609 goto likely;
2610 case OPC_BGTZ:
2611 gen_op_gtz(bcond, t0);
2612 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2613 goto not_likely;
2614 case OPC_BGTZL:
2615 gen_op_gtz(bcond, t0);
2616 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2617 goto likely;
2618 case OPC_BLEZ:
2619 gen_op_lez(bcond, t0);
2620 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2621 goto not_likely;
2622 case OPC_BLEZL:
2623 gen_op_lez(bcond, t0);
2624 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2625 goto likely;
2626 case OPC_BLTZ:
2627 gen_op_ltz(bcond, t0);
2628 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2629 goto not_likely;
2630 case OPC_BLTZL:
2631 gen_op_ltz(bcond, t0);
2632 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2633 goto likely;
2634 case OPC_BLTZAL:
2635 gen_op_ltz(bcond, t0);
2636 blink = 31;
2637 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2638 not_likely:
2639 ctx->hflags |= MIPS_HFLAG_BC;
2640 break;
2641 case OPC_BLTZALL:
2642 gen_op_ltz(bcond, t0);
2643 blink = 31;
2644 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2645 likely:
2646 ctx->hflags |= MIPS_HFLAG_BL;
2647 break;
2648 default:
2649 MIPS_INVAL("conditional branch/jump");
2650 generate_exception(ctx, EXCP_RI);
2651 goto out;
2652 }
2653 }
2654 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
2655 blink, ctx->hflags, btgt);
2656
2657 ctx->btarget = btgt;
2658 if (blink > 0) {
2659 int post_delay = insn_bytes;
2660 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
2661
2662 if (opc != OPC_JALRC)
2663 post_delay += ((ctx->hflags & MIPS_HFLAG_BDS16) ? 2 : 4);
2664
2665 tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit);
2666 }
2667
2668 out:
2669 if (insn_bytes == 2)
2670 ctx->hflags |= MIPS_HFLAG_B16;
2671 tcg_temp_free(t0);
2672 tcg_temp_free(t1);
2673 }
2674
2675 /* special3 bitfield operations */
2676 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2677 int rs, int lsb, int msb)
2678 {
2679 TCGv t0 = tcg_temp_new();
2680 TCGv t1 = tcg_temp_new();
2681 target_ulong mask;
2682
2683 gen_load_gpr(t1, rs);
2684 switch (opc) {
2685 case OPC_EXT:
2686 if (lsb + msb > 31)
2687 goto fail;
2688 tcg_gen_shri_tl(t0, t1, lsb);
2689 if (msb != 31) {
2690 tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
2691 } else {
2692 tcg_gen_ext32s_tl(t0, t0);
2693 }
2694 break;
2695 #if defined(TARGET_MIPS64)
2696 case OPC_DEXTM:
2697 tcg_gen_shri_tl(t0, t1, lsb);
2698 if (msb != 31) {
2699 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1);
2700 }
2701 break;
2702 case OPC_DEXTU:
2703 tcg_gen_shri_tl(t0, t1, lsb + 32);
2704 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
2705 break;
2706 case OPC_DEXT:
2707 tcg_gen_shri_tl(t0, t1, lsb);
2708 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
2709 break;
2710 #endif
2711 case OPC_INS:
2712 if (lsb > msb)
2713 goto fail;
2714 mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb;
2715 gen_load_gpr(t0, rt);
2716 tcg_gen_andi_tl(t0, t0, ~mask);
2717 tcg_gen_shli_tl(t1, t1, lsb);
2718 tcg_gen_andi_tl(t1, t1, mask);
2719 tcg_gen_or_tl(t0, t0, t1);
2720 tcg_gen_ext32s_tl(t0, t0);
2721 break;
2722 #if defined(TARGET_MIPS64)
2723 case OPC_DINSM:
2724 if (lsb > msb)
2725 goto fail;
2726 mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb;
2727 gen_load_gpr(t0, rt);
2728 tcg_gen_andi_tl(t0, t0, ~mask);
2729 tcg_gen_shli_tl(t1, t1, lsb);
2730 tcg_gen_andi_tl(t1, t1, mask);
2731 tcg_gen_or_tl(t0, t0, t1);
2732 break;
2733 case OPC_DINSU:
2734 if (lsb > msb)
2735 goto fail;
2736 mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
2737 gen_load_gpr(t0, rt);
2738 tcg_gen_andi_tl(t0, t0, ~mask);
2739 tcg_gen_shli_tl(t1, t1, lsb + 32);
2740 tcg_gen_andi_tl(t1, t1, mask);
2741 tcg_gen_or_tl(t0, t0, t1);
2742 break;
2743 case OPC_DINS:
2744 if (lsb > msb)
2745 goto fail;
2746 gen_load_gpr(t0, rt);
2747 mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
2748 gen_load_gpr(t0, rt);
2749 tcg_gen_andi_tl(t0, t0, ~mask);
2750 tcg_gen_shli_tl(t1, t1, lsb);
2751 tcg_gen_andi_tl(t1, t1, mask);
2752 tcg_gen_or_tl(t0, t0, t1);
2753 break;
2754 #endif
2755 default:
2756 fail:
2757 MIPS_INVAL("bitops");
2758 generate_exception(ctx, EXCP_RI);
2759 tcg_temp_free(t0);
2760 tcg_temp_free(t1);
2761 return;
2762 }
2763 gen_store_gpr(t0, rt);
2764 tcg_temp_free(t0);
2765 tcg_temp_free(t1);
2766 }
2767
2768 static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
2769 {
2770 TCGv t0;
2771
2772 if (rd == 0) {
2773 /* If no destination, treat it as a NOP. */
2774 MIPS_DEBUG("NOP");
2775 return;
2776 }
2777
2778 t0 = tcg_temp_new();
2779 gen_load_gpr(t0, rt);
2780 switch (op2) {
2781 case OPC_WSBH:
2782 {
2783 TCGv t1 = tcg_temp_new();
2784
2785 tcg_gen_shri_tl(t1, t0, 8);
2786 tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
2787 tcg_gen_shli_tl(t0, t0, 8);
2788 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
2789 tcg_gen_or_tl(t0, t0, t1);
2790 tcg_temp_free(t1);
2791 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2792 }
2793 break;
2794 case OPC_SEB:
2795 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
2796 break;
2797 case OPC_SEH:
2798 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
2799 break;
2800 #if defined(TARGET_MIPS64)
2801 case OPC_DSBH:
2802 {
2803 TCGv t1 = tcg_temp_new();
2804
2805 tcg_gen_shri_tl(t1, t0, 8);
2806 tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
2807 tcg_gen_shli_tl(t0, t0, 8);
2808 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
2809 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
2810 tcg_temp_free(t1);
2811 }
2812 break;
2813 case OPC_DSHD:
2814 {
2815 TCGv t1 = tcg_temp_new();
2816
2817 tcg_gen_shri_tl(t1, t0, 16);
2818 tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
2819 tcg_gen_shli_tl(t0, t0, 16);
2820 tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
2821 tcg_gen_or_tl(t0, t0, t1);
2822 tcg_gen_shri_tl(t1, t0, 32);
2823 tcg_gen_shli_tl(t0, t0, 32);
2824 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
2825 tcg_temp_free(t1);
2826 }
2827 break;
2828 #endif
2829 default:
2830 MIPS_INVAL("bsfhl");
2831 generate_exception(ctx, EXCP_RI);
2832 tcg_temp_free(t0);
2833 return;
2834 }
2835 tcg_temp_free(t0);
2836 }
2837
2838 #ifndef CONFIG_USER_ONLY
2839 /* CP0 (MMU and control) */
2840 static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
2841 {
2842 TCGv_i32 t0 = tcg_temp_new_i32();
2843
2844 tcg_gen_ld_i32(t0, cpu_env, off);
2845 tcg_gen_ext_i32_tl(arg, t0);
2846 tcg_temp_free_i32(t0);
2847 }
2848
2849 static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
2850 {
2851 tcg_gen_ld_tl(arg, cpu_env, off);
2852 tcg_gen_ext32s_tl(arg, arg);
2853 }
2854
2855 static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
2856 {
2857 TCGv_i32 t0 = tcg_temp_new_i32();
2858
2859 tcg_gen_trunc_tl_i32(t0, arg);
2860 tcg_gen_st_i32(t0, cpu_env, off);
2861 tcg_temp_free_i32(t0);
2862 }
2863
2864 static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
2865 {
2866 tcg_gen_ext32s_tl(arg, arg);
2867 tcg_gen_st_tl(arg, cpu_env, off);
2868 }
2869
2870 static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
2871 {
2872 const char *rn = "invalid";
2873
2874 if (sel != 0)
2875 check_insn(env, ctx, ISA_MIPS32);
2876
2877 switch (reg) {
2878 case 0:
2879 switch (sel) {
2880 case 0:
2881 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
2882 rn = "Index";
2883 break;
2884 case 1:
2885 check_insn(env, ctx, ASE_MT);
2886 gen_helper_mfc0_mvpcontrol(arg);
2887 rn = "MVPControl";
2888 break;
2889 case 2:
2890 check_insn(env, ctx, ASE_MT);
2891 gen_helper_mfc0_mvpconf0(arg);
2892 rn = "MVPConf0";
2893 break;
2894 case 3:
2895 check_insn(env, ctx, ASE_MT);
2896 gen_helper_mfc0_mvpconf1(arg);
2897 rn = "MVPConf1";
2898 break;
2899 default:
2900 goto die;
2901 }
2902 break;
2903 case 1:
2904 switch (sel) {
2905 case 0:
2906 gen_helper_mfc0_random(arg);
2907 rn = "Random";
2908 break;
2909 case 1:
2910 check_insn(env, ctx, ASE_MT);
2911 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
2912 rn = "VPEControl";
2913 break;
2914 case 2:
2915 check_insn(env, ctx, ASE_MT);
2916 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
2917 rn = "VPEConf0";
2918 break;
2919 case 3:
2920 check_insn(env, ctx, ASE_MT);
2921 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
2922 rn = "VPEConf1";
2923 break;
2924 case 4:
2925 check_insn(env, ctx, ASE_MT);
2926 gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
2927 rn = "YQMask";
2928 break;
2929 case 5:
2930 check_insn(env, ctx, ASE_MT);
2931 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
2932 rn = "VPESchedule";
2933 break;
2934 case 6:
2935 check_insn(env, ctx, ASE_MT);
2936 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
2937 rn = "VPEScheFBack";
2938 break;
2939 case 7:
2940 check_insn(env, ctx, ASE_MT);
2941 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
2942 rn = "VPEOpt";
2943 break;
2944 default:
2945 goto die;
2946 }
2947 break;
2948 case 2:
2949 switch (sel) {
2950 case 0:
2951 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
2952 tcg_gen_ext32s_tl(arg, arg);
2953 rn = "EntryLo0";
2954 break;
2955 case 1:
2956 check_insn(env, ctx, ASE_MT);
2957 gen_helper_mfc0_tcstatus(arg);
2958 rn = "TCStatus";
2959 break;
2960 case 2:
2961 check_insn(env, ctx, ASE_MT);
2962 gen_helper_mfc0_tcbind(arg);
2963 rn = "TCBind";
2964 break;
2965 case 3:
2966 check_insn(env, ctx, ASE_MT);
2967 gen_helper_mfc0_tcrestart(arg);
2968 rn = "TCRestart";
2969 break;
2970 case 4:
2971 check_insn(env, ctx, ASE_MT);
2972 gen_helper_mfc0_tchalt(arg);
2973 rn = "TCHalt";
2974 break;
2975 case 5:
2976 check_insn(env, ctx, ASE_MT);
2977 gen_helper_mfc0_tccontext(arg);
2978 rn = "TCContext";
2979 break;
2980 case 6:
2981 check_insn(env, ctx, ASE_MT);
2982 gen_helper_mfc0_tcschedule(arg);
2983 rn = "TCSchedule";
2984 break;
2985 case 7:
2986 check_insn(env, ctx, ASE_MT);
2987 gen_helper_mfc0_tcschefback(arg);
2988 rn = "TCScheFBack";
2989 break;
2990 default:
2991 goto die;
2992 }
2993 break;
2994 case 3:
2995 switch (sel) {
2996 case 0:
2997 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
2998 tcg_gen_ext32s_tl(arg, arg);
2999 rn = "EntryLo1";
3000 break;
3001 default:
3002 goto die;
3003 }
3004 break;
3005 case 4:
3006 switch (sel) {
3007 case 0:
3008 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
3009 tcg_gen_ext32s_tl(arg, arg);
3010 rn = "Context";
3011 break;
3012 case 1:
3013 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3014 rn = "ContextConfig";
3015 // break;
3016 default:
3017 goto die;
3018 }
3019 break;
3020 case 5:
3021 switch (sel) {
3022 case 0:
3023 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
3024 rn = "PageMask";
3025 break;
3026 case 1:
3027 check_insn(env, ctx, ISA_MIPS32R2);
3028 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
3029 rn = "PageGrain";
3030 break;
3031 default:
3032 goto die;
3033 }
3034 break;
3035 case 6:
3036 switch (sel) {
3037 case 0:
3038 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
3039 rn = "Wired";
3040 break;
3041 case 1:
3042 check_insn(env, ctx, ISA_MIPS32R2);
3043 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
3044 rn = "SRSConf0";
3045 break;
3046 case 2:
3047 check_insn(env, ctx, ISA_MIPS32R2);
3048 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
3049 rn = "SRSConf1";
3050 break;
3051 case 3:
3052 check_insn(env, ctx, ISA_MIPS32R2);
3053 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
3054 rn = "SRSConf2";
3055 break;
3056 case 4:
3057 check_insn(env, ctx, ISA_MIPS32R2);
3058 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
3059 rn = "SRSConf3";
3060 break;
3061 case 5:
3062 check_insn(env, ctx, ISA_MIPS32R2);
3063 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
3064 rn = "SRSConf4";
3065 break;
3066 default:
3067 goto die;
3068 }
3069 break;
3070 case 7:
3071 switch (sel) {
3072 case 0:
3073 check_insn(env, ctx, ISA_MIPS32R2);
3074 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
3075 rn = "HWREna";
3076 break;
3077 default:
3078 goto die;
3079 }
3080 break;
3081 case 8:
3082 switch (sel) {
3083 case 0:
3084 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3085 tcg_gen_ext32s_tl(arg, arg);
3086 rn = "BadVAddr";
3087 break;
3088 default:
3089 goto die;
3090 }
3091 break;
3092 case 9:
3093 switch (sel) {
3094 case 0:
3095 /* Mark as an IO operation because we read the time. */
3096 if (use_icount)
3097 gen_io_start();
3098 gen_helper_mfc0_count(arg);
3099 if (use_icount) {
3100 gen_io_end();
3101 ctx->bstate = BS_STOP;
3102 }
3103 rn = "Count";
3104 break;
3105 /* 6,7 are implementation dependent */
3106 default:
3107 goto die;
3108 }
3109 break;
3110 case 10:
3111 switch (sel) {
3112 case 0:
3113 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
3114 tcg_gen_ext32s_tl(arg, arg);
3115 rn = "EntryHi";
3116 break;
3117 default:
3118 goto die;
3119 }
3120 break;
3121 case 11:
3122 switch (sel) {
3123 case 0:
3124 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
3125 rn = "Compare";
3126 break;
3127 /* 6,7 are implementation dependent */
3128 default:
3129 goto die;
3130 }
3131 break;
3132 case 12:
3133 switch (sel) {
3134 case 0:
3135 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
3136 rn = "Status";
3137 break;
3138 case 1:
3139 check_insn(env, ctx, ISA_MIPS32R2);
3140 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
3141 rn = "IntCtl";
3142 break;
3143 case 2:
3144 check_insn(env, ctx, ISA_MIPS32R2);
3145 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
3146 rn = "SRSCtl";
3147 break;
3148 case 3:
3149 check_insn(env, ctx, ISA_MIPS32R2);
3150 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
3151 rn = "SRSMap";
3152 break;
3153 default:
3154 goto die;
3155 }
3156 break;
3157 case 13:
3158 switch (sel) {
3159 case 0:
3160 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
3161 rn = "Cause";
3162 break;
3163 default:
3164 goto die;
3165 }
3166 break;
3167 case 14:
3168 switch (sel) {
3169 case 0:
3170 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
3171 tcg_gen_ext32s_tl(arg, arg);
3172 rn = "EPC";
3173 break;
3174 default:
3175 goto die;
3176 }
3177 break;
3178 case 15:
3179 switch (sel) {
3180 case 0:
3181 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
3182 rn = "PRid";
3183 break;
3184 case 1:
3185 check_insn(env, ctx, ISA_MIPS32R2);
3186 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
3187 rn = "EBase";
3188 break;
3189 default:
3190 goto die;
3191 }
3192 break;
3193 case 16:
3194 switch (sel) {
3195 case 0:
3196 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
3197 rn = "Config";
3198 break;
3199 case 1:
3200 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
3201 rn = "Config1";
3202 break;
3203 case 2:
3204 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
3205 rn = "Config2";
3206 break;
3207 case 3:
3208 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
3209 rn = "Config3";
3210 break;
3211 /* 4,5 are reserved */
3212 /* 6,7 are implementation dependent */
3213 case 6:
3214 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
3215 rn = "Config6";
3216 break;
3217 case 7:
3218 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
3219 rn = "Config7";
3220 break;
3221 default:
3222 goto die;
3223 }
3224 break;
3225 case 17:
3226 switch (sel) {
3227 case 0:
3228 gen_helper_mfc0_lladdr(arg);
3229 rn = "LLAddr";
3230 break;
3231 default:
3232 goto die;
3233 }
3234 break;
3235 case 18:
3236 switch (sel) {
3237 case 0 ... 7:
3238 gen_helper_1i(mfc0_watchlo, arg, sel);
3239 rn = "WatchLo";
3240 break;
3241 default:
3242 goto die;
3243 }
3244 break;
3245 case 19:
3246 switch (sel) {
3247 case 0 ...7:
3248 gen_helper_1i(mfc0_watchhi, arg, sel);
3249 rn = "WatchHi";
3250 break;
3251 default:
3252 goto die;
3253 }
3254 break;
3255 case 20:
3256 switch (sel) {
3257 case 0:
3258 #if defined(TARGET_MIPS64)
3259 check_insn(env, ctx, ISA_MIPS3);
3260 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
3261 tcg_gen_ext32s_tl(arg, arg);
3262 rn = "XContext";
3263 break;
3264 #endif
3265 default:
3266 goto die;
3267 }
3268 break;
3269 case 21:
3270 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3271 switch (sel) {
3272 case 0:
3273 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
3274 rn = "Framemask";
3275 break;
3276 default:
3277 goto die;
3278 }
3279 break;
3280 case 22:
3281 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3282 rn = "'Diagnostic"; /* implementation dependent */
3283 break;
3284 case 23:
3285 switch (sel) {
3286 case 0:
3287 gen_helper_mfc0_debug(arg); /* EJTAG support */
3288 rn = "Debug";
3289 break;
3290 case 1:
3291 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3292 rn = "TraceControl";
3293 // break;
3294 case 2:
3295 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3296 rn = "TraceControl2";
3297 // break;
3298 case 3:
3299 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3300 rn = "UserTraceData";
3301 // break;
3302 case 4:
3303 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3304 rn = "TraceBPC";
3305 // break;
3306 default:
3307 goto die;
3308 }
3309 break;
3310 case 24:
3311 switch (sel) {
3312 case 0:
3313 /* EJTAG support */
3314 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
3315 tcg_gen_ext32s_tl(arg, arg);
3316 rn = "DEPC";
3317 break;
3318 default:
3319 goto die;
3320 }
3321 break;
3322 case 25:
3323 switch (sel) {
3324 case 0:
3325 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
3326 rn = "Performance0";
3327 break;
3328 case 1:
3329 // gen_helper_mfc0_performance1(arg);
3330 rn = "Performance1";
3331 // break;
3332 case 2:
3333 // gen_helper_mfc0_performance2(arg);
3334 rn = "Performance2";
3335 // break;
3336 case 3:
3337 // gen_helper_mfc0_performance3(arg);
3338 rn = "Performance3";
3339 // break;
3340 case 4:
3341 // gen_helper_mfc0_performance4(arg);
3342 rn = "Performance4";
3343 // break;
3344 case 5:
3345 // gen_helper_mfc0_performance5(arg);
3346 rn = "Performance5";
3347 // break;
3348 case 6:
3349 // gen_helper_mfc0_performance6(arg);
3350 rn = "Performance6";
3351 // break;
3352 case 7:
3353 // gen_helper_mfc0_performance7(arg);
3354 rn = "Performance7";
3355 // break;
3356 default:
3357 goto die;
3358 }
3359 break;
3360 case 26:
3361 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3362 rn = "ECC";
3363 break;
3364 case 27:
3365 switch (sel) {
3366 case 0 ... 3:
3367 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3368 rn = "CacheErr";
3369 break;
3370 default:
3371 goto die;
3372 }
3373 break;
3374 case 28:
3375 switch (sel) {
3376 case 0:
3377 case 2:
3378 case 4:
3379 case 6:
3380 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
3381 rn = "TagLo";
3382 break;
3383 case 1:
3384 case 3:
3385 case 5:
3386 case 7:
3387 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
3388 rn = "DataLo";
3389 break;
3390 default:
3391 goto die;
3392 }
3393 break;
3394 case 29:
3395 switch (sel) {
3396 case 0:
3397 case 2:
3398 case 4:
3399 case 6:
3400 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
3401 rn = "TagHi";
3402 break;
3403 case 1:
3404 case 3:
3405 case 5:
3406 case 7:
3407 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
3408 rn = "DataHi";
3409 break;
3410 default:
3411 goto die;
3412 }
3413 break;
3414 case 30:
3415 switch (sel) {
3416 case 0:
3417 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3418 tcg_gen_ext32s_tl(arg, arg);
3419 rn = "ErrorEPC";
3420 break;
3421 default:
3422 goto die;
3423 }
3424 break;
3425 case 31:
3426 switch (sel) {
3427 case 0:
3428 /* EJTAG support */
3429 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
3430 rn = "DESAVE";
3431 break;
3432 default:
3433 goto die;
3434 }
3435 break;
3436 default:
3437 goto die;
3438 }
3439 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
3440 return;
3441
3442 die:
3443 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
3444 generate_exception(ctx, EXCP_RI);
3445 }
3446
3447 static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
3448 {
3449 const char *rn = "invalid";
3450
3451 if (sel != 0)
3452 check_insn(env, ctx, ISA_MIPS32);
3453
3454 if (use_icount)
3455 gen_io_start();
3456
3457 switch (reg) {
3458 case 0:
3459 switch (sel) {
3460 case 0:
3461 gen_helper_mtc0_index(arg);
3462 rn = "Index";
3463 break;
3464 case 1:
3465 check_insn(env, ctx, ASE_MT);
3466 gen_helper_mtc0_mvpcontrol(arg);
3467 rn = "MVPControl";
3468 break;
3469 case 2:
3470 check_insn(env, ctx, ASE_MT);
3471 /* ignored */
3472 rn = "MVPConf0";
3473 break;
3474 case 3:
3475 check_insn(env, ctx, ASE_MT);
3476 /* ignored */
3477 rn = "MVPConf1";
3478 break;
3479 default:
3480 goto die;
3481 }
3482 break;
3483 case 1:
3484 switch (sel) {
3485 case 0:
3486 /* ignored */
3487 rn = "Random";
3488 break;
3489 case 1:
3490 check_insn(env, ctx, ASE_MT);
3491 gen_helper_mtc0_vpecontrol(arg);
3492 rn = "VPEControl";
3493 break;
3494 case 2:
3495 check_insn(env, ctx, ASE_MT);
3496 gen_helper_mtc0_vpeconf0(arg);
3497 rn = "VPEConf0";
3498 break;
3499 case 3:
3500 check_insn(env, ctx, ASE_MT);
3501 gen_helper_mtc0_vpeconf1(arg);
3502 rn = "VPEConf1";
3503 break;
3504 case 4:
3505 check_insn(env, ctx, ASE_MT);
3506 gen_helper_mtc0_yqmask(arg);
3507 rn = "YQMask";
3508 break;
3509 case 5:
3510 check_insn(env, ctx, ASE_MT);
3511 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
3512 rn = "VPESchedule";
3513 break;
3514 case 6:
3515 check_insn(env, ctx, ASE_MT);
3516 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
3517 rn = "VPEScheFBack";
3518 break;
3519 case 7:
3520 check_insn(env, ctx, ASE_MT);
3521 gen_helper_mtc0_vpeopt(arg);
3522 rn = "VPEOpt";
3523 break;
3524 default:
3525 goto die;
3526 }
3527 break;
3528 case 2:
3529 switch (sel) {
3530 case 0:
3531 gen_helper_mtc0_entrylo0(arg);
3532 rn = "EntryLo0";
3533 break;
3534 case 1:
3535 check_insn(env, ctx, ASE_MT);
3536 gen_helper_mtc0_tcstatus(arg);
3537 rn = "TCStatus";
3538 break;
3539 case 2:
3540 check_insn(env, ctx, ASE_MT);
3541 gen_helper_mtc0_tcbind(arg);
3542 rn = "TCBind";
3543 break;
3544 case 3:
3545 check_insn(env, ctx, ASE_MT);
3546 gen_helper_mtc0_tcrestart(arg);
3547 rn = "TCRestart";
3548 break;
3549 case 4:
3550 check_insn(env, ctx, ASE_MT);
3551 gen_helper_mtc0_tchalt(arg);
3552 rn = "TCHalt";
3553 break;
3554 case 5:
3555 check_insn(env, ctx, ASE_MT);
3556 gen_helper_mtc0_tccontext(arg);
3557 rn = "TCContext";
3558 break;
3559 case 6:
3560 check_insn(env, ctx, ASE_MT);
3561 gen_helper_mtc0_tcschedule(arg);
3562 rn = "TCSchedule";
3563 break;
3564 case 7:
3565 check_insn(env, ctx, ASE_MT);
3566 gen_helper_mtc0_tcschefback(arg);
3567 rn = "TCScheFBack";
3568 break;
3569 default:
3570 goto die;
3571 }
3572 break;
3573 case 3:
3574 switch (sel) {
3575 case 0:
3576 gen_helper_mtc0_entrylo1(arg);
3577 rn = "EntryLo1";
3578 break;
3579 default:
3580 goto die;
3581 }
3582 break;
3583 case 4:
3584 switch (sel) {
3585 case 0:
3586 gen_helper_mtc0_context(arg);
3587 rn = "Context";
3588 break;
3589 case 1:
3590 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3591 rn = "ContextConfig";
3592 // break;
3593 default:
3594 goto die;
3595 }
3596 break;
3597 case 5:
3598 switch (sel) {
3599 case 0:
3600 gen_helper_mtc0_pagemask(arg);
3601 rn = "PageMask";
3602 break;
3603 case 1:
3604 check_insn(env, ctx, ISA_MIPS32R2);
3605 gen_helper_mtc0_pagegrain(arg);
3606 rn = "PageGrain";
3607 break;
3608 default:
3609 goto die;
3610 }
3611 break;
3612 case 6:
3613 switch (sel) {
3614 case 0:
3615 gen_helper_mtc0_wired(arg);
3616 rn = "Wired";
3617 break;
3618 case 1:
3619 check_insn(env, ctx, ISA_MIPS32R2);
3620 gen_helper_mtc0_srsconf0(arg);
3621 rn = "SRSConf0";
3622 break;
3623 case 2:
3624 check_insn(env, ctx, ISA_MIPS32R2);
3625 gen_helper_mtc0_srsconf1(arg);
3626 rn = "SRSConf1";
3627 break;
3628 case 3:
3629 check_insn(env, ctx, ISA_MIPS32R2);
3630 gen_helper_mtc0_srsconf2(arg);
3631 rn = "SRSConf2";
3632 break;
3633 case 4:
3634 check_insn(env, ctx, ISA_MIPS32R2);
3635 gen_helper_mtc0_srsconf3(arg);
3636 rn = "SRSConf3";
3637 break;
3638 case 5:
3639 check_insn(env, ctx, ISA_MIPS32R2);
3640 gen_helper_mtc0_srsconf4(arg);
3641 rn = "SRSConf4";
3642 break;
3643 default:
3644 goto die;
3645 }
3646 break;
3647 case 7:
3648 switch (sel) {
3649 case 0:
3650 check_insn(env, ctx, ISA_MIPS32R2);
3651 gen_helper_mtc0_hwrena(arg);
3652 rn = "HWREna";
3653 break;
3654 default:
3655 goto die;
3656 }
3657 break;
3658 case 8:
3659 /* ignored */
3660 rn = "BadVAddr";
3661 break;
3662 case 9:
3663 switch (sel) {
3664 case 0:
3665 gen_helper_mtc0_count(arg);
3666 rn = "Count";
3667 break;
3668 /* 6,7 are implementation dependent */
3669 default:
3670 goto die;
3671 }
3672 break;
3673 case 10:
3674 switch (sel) {
3675 case 0:
3676 gen_helper_mtc0_entryhi(arg);
3677 rn = "EntryHi";
3678 break;
3679 default:
3680 goto die;
3681 }
3682 break;
3683 case 11:
3684 switch (sel) {
3685 case 0:
3686 gen_helper_mtc0_compare(arg);
3687 rn = "Compare";
3688 break;
3689 /* 6,7 are implementation dependent */
3690 default:
3691 goto die;
3692 }
3693 break;
3694 case 12:
3695 switch (sel) {
3696 case 0:
3697 save_cpu_state(ctx, 1);
3698 gen_helper_mtc0_status(arg);
3699 /* BS_STOP isn't good enough here, hflags may have changed. */
3700 gen_save_pc(ctx->pc + 4);
3701 ctx->bstate = BS_EXCP;
3702 rn = "Status";
3703 break;
3704 case 1:
3705 check_insn(env, ctx, ISA_MIPS32R2);
3706 gen_helper_mtc0_intctl(arg);
3707 /* Stop translation as we may have switched the execution mode */
3708 ctx->bstate = BS_STOP;
3709 rn = "IntCtl";
3710 break;
3711 case 2:
3712 check_insn(env, ctx, ISA_MIPS32R2);
3713 gen_helper_mtc0_srsctl(arg);
3714 /* Stop translation as we may have switched the execution mode */
3715 ctx->bstate = BS_STOP;
3716 rn = "SRSCtl";
3717 break;
3718 case 3:
3719 check_insn(env, ctx, ISA_MIPS32R2);
3720 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
3721 /* Stop translation as we may have switched the execution mode */
3722 ctx->bstate = BS_STOP;
3723 rn = "SRSMap";
3724 break;
3725 default:
3726 goto die;
3727 }
3728 break;
3729 case 13:
3730 switch (sel) {
3731 case 0:
3732 save_cpu_state(ctx, 1);
3733 gen_helper_mtc0_cause(arg);
3734 rn = "Cause";
3735 break;
3736 default:
3737 goto die;
3738 }
3739 break;
3740 case 14:
3741 switch (sel) {
3742 case 0:
3743 gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
3744 rn = "EPC";
3745 break;
3746 default:
3747 goto die;
3748 }
3749 break;
3750 case 15:
3751 switch (sel) {
3752 case 0:
3753 /* ignored */
3754 rn = "PRid";
3755 break;
3756 case 1:
3757 check_insn(env, ctx, ISA_MIPS32R2);
3758 gen_helper_mtc0_ebase(arg);
3759 rn = "EBase";
3760 break;
3761 default:
3762 goto die;
3763 }
3764 break;
3765 case 16:
3766 switch (sel) {
3767 case 0:
3768 gen_helper_mtc0_config0(arg);
3769 rn = "Config";
3770 /* Stop translation as we may have switched the execution mode */
3771 ctx->bstate = BS_STOP;
3772 break;
3773 case 1:
3774 /* ignored, read only */
3775 rn = "Config1";
3776 break;
3777 case 2:
3778 gen_helper_mtc0_config2(arg);
3779 rn = "Config2";
3780 /* Stop translation as we may have switched the execution mode */
3781 ctx->bstate = BS_STOP;
3782 break;
3783 case 3:
3784 /* ignored, read only */
3785 rn = "Config3";
3786 break;
3787 /* 4,5 are reserved */
3788 /* 6,7 are implementation dependent */
3789 case 6:
3790 /* ignored */
3791 rn = "Config6";
3792 break;
3793 case 7:
3794 /* ignored */
3795 rn = "Config7";
3796 break;
3797 default:
3798 rn = "Invalid config selector";
3799 goto die;
3800 }
3801 break;
3802 case 17:
3803 switch (sel) {
3804 case 0:
3805 gen_helper_mtc0_lladdr(arg);
3806 rn = "LLAddr";
3807 break;
3808 default:
3809 goto die;
3810 }
3811 break;
3812 case 18:
3813 switch (sel) {
3814 case 0 ... 7:
3815 gen_helper_1i(mtc0_watchlo, arg, sel);
3816 rn = "WatchLo";
3817 break;
3818 default:
3819 goto die;
3820 }
3821 break;
3822 case 19:
3823 switch (sel) {
3824 case 0 ... 7:
3825 gen_helper_1i(mtc0_watchhi, arg, sel);
3826 rn = "WatchHi";
3827 break;
3828 default:
3829 goto die;
3830 }
3831 break;
3832 case 20:
3833 switch (sel) {
3834 case 0:
3835 #if defined(TARGET_MIPS64)
3836 check_insn(env, ctx, ISA_MIPS3);
3837 gen_helper_mtc0_xcontext(arg);
3838 rn = "XContext";
3839 break;
3840 #endif
3841 default:
3842 goto die;
3843 }
3844 break;
3845 case 21:
3846 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3847 switch (sel) {
3848 case 0:
3849 gen_helper_mtc0_framemask(arg);
3850 rn = "Framemask";
3851 break;
3852 default:
3853 goto die;
3854 }
3855 break;
3856 case 22:
3857 /* ignored */
3858 rn = "Diagnostic"; /* implementation dependent */
3859 break;
3860 case 23:
3861 switch (sel) {
3862 case 0:
3863 gen_helper_mtc0_debug(arg); /* EJTAG support */
3864 /* BS_STOP isn't good enough here, hflags may have changed. */
3865 gen_save_pc(ctx->pc + 4);
3866 ctx->bstate = BS_EXCP;
3867 rn = "Debug";
3868 break;
3869 case 1:
3870 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3871 rn = "TraceControl";
3872 /* Stop translation as we may have switched the execution mode */
3873 ctx->bstate = BS_STOP;
3874 // break;
3875 case 2:
3876 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3877 rn = "TraceControl2";
3878 /* Stop translation as we may have switched the execution mode */
3879 ctx->bstate = BS_STOP;
3880 // break;
3881 case 3:
3882 /* Stop translation as we may have switched the execution mode */
3883 ctx->bstate = BS_STOP;
3884 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3885 rn = "UserTraceData";
3886 /* Stop translation as we may have switched the execution mode */
3887 ctx->bstate = BS_STOP;
3888 // break;
3889 case 4:
3890 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3891 /* Stop translation as we may have switched the execution mode */
3892 ctx->bstate = BS_STOP;
3893 rn = "TraceBPC";
3894 // break;
3895 default:
3896 goto die;
3897 }
3898 break;
3899 case 24:
3900 switch (sel) {
3901 case 0:
3902 /* EJTAG support */
3903 gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
3904 rn = "DEPC";
3905 break;
3906 default:
3907 goto die;
3908 }
3909 break;
3910 case 25:
3911 switch (sel) {
3912 case 0:
3913 gen_helper_mtc0_performance0(arg);
3914 rn = "Performance0";
3915 break;
3916 case 1:
3917 // gen_helper_mtc0_performance1(arg);
3918 rn = "Performance1";
3919 // break;
3920 case 2:
3921 // gen_helper_mtc0_performance2(arg);
3922 rn = "Performance2";
3923 // break;
3924 case 3:
3925 // gen_helper_mtc0_performance3(arg);
3926 rn = "Performance3";
3927 // break;
3928 case 4:
3929 // gen_helper_mtc0_performance4(arg);
3930 rn = "Performance4";
3931 // break;
3932 case 5:
3933 // gen_helper_mtc0_performance5(arg);
3934 rn = "Performance5";
3935 // break;
3936 case 6:
3937 // gen_helper_mtc0_performance6(arg);
3938 rn = "Performance6";
3939 // break;
3940 case 7:
3941 // gen_helper_mtc0_performance7(arg);
3942 rn = "Performance7";
3943 // break;
3944 default:
3945 goto die;
3946 }
3947 break;
3948 case 26:
3949 /* ignored */
3950 rn = "ECC";
3951 break;
3952 case 27:
3953 switch (sel) {
3954 case 0 ... 3:
3955 /* ignored */
3956 rn = "CacheErr";
3957 break;
3958 default:
3959 goto die;
3960 }
3961 break;
3962 case 28:
3963 switch (sel) {
3964 case 0:
3965 case 2:
3966 case 4:
3967 case 6:
3968 gen_helper_mtc0_taglo(arg);
3969 rn = "TagLo";
3970 break;
3971 case 1:
3972 case 3:
3973 case 5:
3974 case 7:
3975 gen_helper_mtc0_datalo(arg);
3976 rn = "DataLo";
3977 break;
3978 default:
3979 goto die;
3980 }
3981 break;
3982 case 29:
3983 switch (sel) {
3984 case 0:
3985 case 2:
3986 case 4:
3987 case 6:
3988 gen_helper_mtc0_taghi(arg);
3989 rn = "TagHi";
3990 break;
3991 case 1:
3992 case 3:
3993 case 5:
3994 case 7:
3995 gen_helper_mtc0_datahi(arg);
3996 rn = "DataHi";
3997 break;
3998 default:
3999 rn = "invalid sel";
4000 goto die;
4001 }
4002 break;
4003 case 30:
4004 switch (sel) {
4005 case 0:
4006 gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
4007 rn = "ErrorEPC";
4008 break;
4009 default:
4010 goto die;
4011 }
4012 break;
4013 case 31:
4014 switch (sel) {
4015 case 0:
4016 /* EJTAG support */
4017 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
4018 rn = "DESAVE";
4019 break;
4020 default:
4021 goto die;
4022 }
4023 /* Stop translation as we may have switched the execution mode */
4024 ctx->bstate = BS_STOP;
4025 break;
4026 default:
4027 goto die;
4028 }
4029 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
4030 /* For simplicity assume that all writes can cause interrupts. */
4031 if (use_icount) {
4032 gen_io_end();
4033 ctx->bstate = BS_STOP;
4034 }
4035 return;
4036
4037 die:
4038 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
4039 generate_exception(ctx, EXCP_RI);
4040 }
4041
4042 #if defined(TARGET_MIPS64)
4043 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4044 {
4045 const char *rn = "invalid";
4046
4047 if (sel != 0)
4048 check_insn(env, ctx, ISA_MIPS64);
4049
4050 switch (reg) {
4051 case 0:
4052 switch (sel) {
4053 case 0:
4054 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
4055 rn = "Index";
4056 break;
4057 case 1:
4058 check_insn(env, ctx, ASE_MT);
4059 gen_helper_mfc0_mvpcontrol(arg);
4060 rn = "MVPControl";
4061 break;
4062 case 2:
4063 check_insn(env, ctx, ASE_MT);
4064 gen_helper_mfc0_mvpconf0(arg);
4065 rn = "MVPConf0";
4066 break;
4067 case 3:
4068 check_insn(env, ctx, ASE_MT);
4069 gen_helper_mfc0_mvpconf1(arg);
4070 rn = "MVPConf1";
4071 break;
4072 default:
4073 goto die;
4074 }
4075 break;
4076 case 1:
4077 switch (sel) {
4078 case 0:
4079 gen_helper_mfc0_random(arg);
4080 rn = "Random";
4081 break;
4082 case 1:
4083 check_insn(env, ctx, ASE_MT);
4084 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
4085 rn = "VPEControl";
4086 break;
4087 case 2:
4088 check_insn(env, ctx, ASE_MT);
4089 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
4090 rn = "VPEConf0";
4091 break;
4092 case 3:
4093 check_insn(env, ctx, ASE_MT);
4094 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
4095 rn = "VPEConf1";
4096 break;
4097 case 4:
4098 check_insn(env, ctx, ASE_MT);
4099 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
4100 rn = "YQMask";
4101 break;
4102 case 5:
4103 check_insn(env, ctx, ASE_MT);
4104 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4105 rn = "VPESchedule";
4106 break;
4107 case 6:
4108 check_insn(env, ctx, ASE_MT);
4109 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4110 rn = "VPEScheFBack";
4111 break;
4112 case 7:
4113 check_insn(env, ctx, ASE_MT);
4114 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
4115 rn = "VPEOpt";
4116 break;
4117 default:
4118 goto die;
4119 }
4120 break;
4121 case 2:
4122 switch (sel) {
4123 case 0:
4124 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4125 rn = "EntryLo0";
4126 break;
4127 case 1:
4128 check_insn(env, ctx, ASE_MT);
4129 gen_helper_mfc0_tcstatus(arg);
4130 rn = "TCStatus";
4131 break;
4132 case 2:
4133 check_insn(env, ctx, ASE_MT);
4134 gen_helper_mfc0_tcbind(arg);
4135 rn = "TCBind";
4136 break;
4137 case 3:
4138 check_insn(env, ctx, ASE_MT);
4139 gen_helper_dmfc0_tcrestart(arg);
4140 rn = "TCRestart";
4141 break;
4142 case 4:
4143 check_insn(env, ctx, ASE_MT);
4144 gen_helper_dmfc0_tchalt(arg);
4145 rn = "TCHalt";
4146 break;
4147 case 5:
4148 check_insn(env, ctx, ASE_MT);
4149 gen_helper_dmfc0_tccontext(arg);
4150 rn = "TCContext";
4151 break;
4152 case 6:
4153 check_insn(env, ctx, ASE_MT);
4154 gen_helper_dmfc0_tcschedule(arg);
4155 rn = "TCSchedule";
4156 break;
4157 case 7:
4158 check_insn(env, ctx, ASE_MT);
4159 gen_helper_dmfc0_tcschefback(arg);
4160 rn = "TCScheFBack";
4161 break;
4162 default:
4163 goto die;
4164 }
4165 break;
4166 case 3:
4167 switch (sel) {
4168 case 0:
4169 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4170 rn = "EntryLo1";
4171 break;
4172 default:
4173 goto die;
4174 }
4175 break;
4176 case 4:
4177 switch (sel) {
4178 case 0:
4179 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
4180 rn = "Context";
4181 break;
4182 case 1:
4183 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4184 rn = "ContextConfig";
4185 // break;
4186 default:
4187 goto die;
4188 }
4189 break;
4190 case 5:
4191 switch (sel) {
4192 case 0:
4193 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
4194 rn = "PageMask";
4195 break;
4196 case 1:
4197 check_insn(env, ctx, ISA_MIPS32R2);
4198 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
4199 rn = "PageGrain";
4200 break;
4201 default:
4202 goto die;
4203 }
4204 break;
4205 case 6:
4206 switch (sel) {
4207 case 0:
4208 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
4209 rn = "Wired";
4210 break;
4211 case 1:
4212 check_insn(env, ctx, ISA_MIPS32R2);
4213 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
4214 rn = "SRSConf0";
4215 break;
4216 case 2:
4217 check_insn(env, ctx, ISA_MIPS32R2);
4218 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
4219 rn = "SRSConf1";
4220 break;
4221 case 3:
4222 check_insn(env, ctx, ISA_MIPS32R2);
4223 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
4224 rn = "SRSConf2";
4225 break;
4226 case 4:
4227 check_insn(env, ctx, ISA_MIPS32R2);
4228 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
4229 rn = "SRSConf3";
4230 break;
4231 case 5:
4232 check_insn(env, ctx, ISA_MIPS32R2);
4233 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
4234 rn = "SRSConf4";
4235 break;
4236 default:
4237 goto die;
4238 }
4239 break;
4240 case 7:
4241 switch (sel) {
4242 case 0:
4243 check_insn(env, ctx, ISA_MIPS32R2);
4244 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
4245 rn = "HWREna";
4246 break;
4247 default:
4248 goto die;
4249 }
4250 break;
4251 case 8:
4252 switch (sel) {
4253 case 0:
4254 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4255 rn = "BadVAddr";
4256 break;
4257 default:
4258 goto die;
4259 }
4260 break;
4261 case 9:
4262 switch (sel) {
4263 case 0:
4264 /* Mark as an IO operation because we read the time. */
4265 if (use_icount)
4266 gen_io_start();
4267 gen_helper_mfc0_count(arg);
4268 if (use_icount) {
4269 gen_io_end();
4270 ctx->bstate = BS_STOP;
4271 }
4272 rn = "Count";
4273 break;
4274 /* 6,7 are implementation dependent */
4275 default:
4276 goto die;
4277 }
4278 break;
4279 case 10:
4280 switch (sel) {
4281 case 0:
4282 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
4283 rn = "EntryHi";
4284 break;
4285 default:
4286 goto die;
4287 }
4288 break;
4289 case 11:
4290 switch (sel) {
4291 case 0:
4292 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
4293 rn = "Compare";
4294 break;
4295 /* 6,7 are implementation dependent */
4296 default:
4297 goto die;
4298 }
4299 break;
4300 case 12:
4301 switch (sel) {
4302 case 0:
4303 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
4304 rn = "Status";
4305 break;
4306 case 1:
4307 check_insn(env, ctx, ISA_MIPS32R2);
4308 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
4309 rn = "IntCtl";
4310 break;
4311 case 2:
4312 check_insn(env, ctx, ISA_MIPS32R2);
4313 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
4314 rn = "SRSCtl";
4315 break;
4316 case 3:
4317 check_insn(env, ctx, ISA_MIPS32R2);
4318 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
4319 rn = "SRSMap";
4320 break;
4321 default:
4322 goto die;
4323 }
4324 break;
4325 case 13:
4326 switch (sel) {
4327 case 0:
4328 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
4329 rn = "Cause";
4330 break;
4331 default:
4332 goto die;
4333 }
4334 break;
4335 case 14:
4336 switch (sel) {
4337 case 0:
4338 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4339 rn = "EPC";
4340 break;
4341 default:
4342 goto die;
4343 }
4344 break;
4345 case 15:
4346 switch (sel) {
4347 case 0:
4348 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
4349 rn = "PRid";
4350 break;
4351 case 1:
4352 check_insn(env, ctx, ISA_MIPS32R2);
4353 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
4354 rn = "EBase";
4355 break;
4356 default:
4357 goto die;
4358 }
4359 break;
4360 case 16:
4361 switch (sel) {
4362 case 0:
4363 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
4364 rn = "Config";
4365 break;
4366 case 1:
4367 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
4368 rn = "Config1";
4369 break;
4370 case 2:
4371 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
4372 rn = "Config2";
4373 break;
4374 case 3:
4375 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
4376 rn = "Config3";
4377 break;
4378 /* 6,7 are implementation dependent */
4379 case 6:
4380 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
4381 rn = "Config6";
4382 break;
4383 case 7:
4384 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
4385 rn = "Config7";
4386 break;
4387 default:
4388 goto die;
4389 }
4390 break;
4391 case 17:
4392 switch (sel) {
4393 case 0:
4394 gen_helper_dmfc0_lladdr(arg);
4395 rn = "LLAddr";
4396 break;
4397 default:
4398 goto die;
4399 }
4400 break;
4401 case 18:
4402 switch (sel) {
4403 case 0 ... 7:
4404 gen_helper_1i(dmfc0_watchlo, arg, sel);
4405 rn = "WatchLo";
4406 break;
4407 default:
4408 goto die;
4409 }
4410 break;
4411 case 19:
4412 switch (sel) {
4413 case 0 ... 7:
4414 gen_helper_1i(mfc0_watchhi, arg, sel);
4415 rn = "WatchHi";
4416 break;
4417 default:
4418 goto die;
4419 }
4420 break;
4421 case 20:
4422 switch (sel) {
4423 case 0:
4424 check_insn(env, ctx, ISA_MIPS3);
4425 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
4426 rn = "XContext";
4427 break;
4428 default:
4429 goto die;
4430 }
4431 break;
4432 case 21:
4433 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4434 switch (sel) {
4435 case 0:
4436 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
4437 rn = "Framemask";
4438 break;
4439 default:
4440 goto die;
4441 }
4442 break;
4443 case 22:
4444 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4445 rn = "'Diagnostic"; /* implementation dependent */
4446 break;
4447 case 23:
4448 switch (sel) {
4449 case 0:
4450 gen_helper_mfc0_debug(arg); /* EJTAG support */
4451 rn = "Debug";
4452 break;
4453 case 1:
4454 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4455 rn = "TraceControl";
4456 // break;
4457 case 2:
4458 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4459 rn = "TraceControl2";
4460 // break;
4461 case 3:
4462 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4463 rn = "UserTraceData";
4464 // break;
4465 case 4:
4466 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4467 rn = "TraceBPC";
4468 // break;
4469 default:
4470 goto die;
4471 }
4472 break;
4473 case 24:
4474 switch (sel) {
4475 case 0:
4476 /* EJTAG support */
4477 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
4478 rn = "DEPC";
4479 break;
4480 default:
4481 goto die;
4482 }
4483 break;
4484 case 25:
4485 switch (sel) {
4486 case 0:
4487 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
4488 rn = "Performance0";
4489 break;
4490 case 1:
4491 // gen_helper_dmfc0_performance1(arg);
4492 rn = "Performance1";
4493 // break;
4494 case 2:
4495 // gen_helper_dmfc0_performance2(arg);
4496 rn = "Performance2";
4497 // break;
4498 case 3:
4499 // gen_helper_dmfc0_performance3(arg);
4500 rn = "Performance3";
4501 // break;
4502 case 4:
4503 // gen_helper_dmfc0_performance4(arg);
4504 rn = "Performance4";
4505 // break;
4506 case 5:
4507 // gen_helper_dmfc0_performance5(arg);
4508 rn = "Performance5";
4509 // break;
4510 case 6:
4511 // gen_helper_dmfc0_performance6(arg);
4512 rn = "Performance6";
4513 // break;
4514 case 7:
4515 // gen_helper_dmfc0_performance7(arg);
4516 rn = "Performance7";
4517 // break;
4518 default:
4519 goto die;
4520 }
4521 break;
4522 case 26:
4523 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4524 rn = "ECC";
4525 break;
4526 case 27:
4527 switch (sel) {
4528 /* ignored */
4529 case 0 ... 3:
4530 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4531 rn = "CacheErr";
4532 break;
4533 default:
4534 goto die;
4535 }
4536 break;
4537 case 28:
4538 switch (sel) {
4539 case 0:
4540 case 2:
4541 case 4:
4542 case 6:
4543 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
4544 rn = "TagLo";
4545 break;
4546 case 1:
4547 case 3:
4548 case 5:
4549 case 7:
4550 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
4551 rn = "DataLo";
4552 break;
4553 default:
4554 goto die;
4555 }
4556 break;
4557 case 29:
4558 switch (sel) {
4559 case 0:
4560 case 2:
4561 case 4:
4562 case 6:
4563 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
4564 rn = "TagHi";
4565 break;
4566 case 1:
4567 case 3:
4568 case 5:
4569 case 7:
4570 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
4571 rn = "DataHi";
4572 break;
4573 default:
4574 goto die;
4575 }
4576 break;
4577 case 30:
4578 switch (sel) {
4579 case 0:
4580 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4581 rn = "ErrorEPC";
4582 break;
4583 default:
4584 goto die;
4585 }
4586 break;
4587 case 31:
4588 switch (sel) {
4589 case 0:
4590 /* EJTAG support */
4591 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
4592 rn = "DESAVE";
4593 break;
4594 default:
4595 goto die;
4596 }
4597 break;
4598 default:
4599 goto die;
4600 }
4601 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
4602 return;
4603
4604 die:
4605 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
4606 generate_exception(ctx, EXCP_RI);
4607 }
4608
4609 static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4610 {
4611 const char *rn = "invalid";
4612
4613 if (sel != 0)
4614 check_insn(env, ctx, ISA_MIPS64);
4615
4616 if (use_icount)
4617 gen_io_start();
4618
4619 switch (reg) {
4620 case 0:
4621 switch (sel) {
4622 case 0:
4623 gen_helper_mtc0_index(arg);
4624 rn = "Index";
4625 break;
4626 case 1:
4627 check_insn(env, ctx, ASE_MT);
4628 gen_helper_mtc0_mvpcontrol(arg);
4629 rn = "MVPControl";
4630 break;
4631 case 2:
4632 check_insn(env, ctx, ASE_MT);
4633 /* ignored */
4634 rn = "MVPConf0";
4635 break;
4636 case 3:
4637 check_insn(env, ctx, ASE_MT);
4638 /* ignored */
4639 rn = "MVPConf1";
4640 break;
4641 default:
4642 goto die;
4643 }
4644 break;
4645 case 1:
4646 switch (sel) {
4647 case 0:
4648 /* ignored */
4649 rn = "Random";
4650 break;
4651 case 1:
4652 check_insn(env, ctx, ASE_MT);
4653 gen_helper_mtc0_vpecontrol(arg);
4654 rn = "VPEControl";
4655 break;
4656 case 2:
4657 check_insn(env, ctx, ASE_MT);
4658 gen_helper_mtc0_vpeconf0(arg);
4659 rn = "VPEConf0";
4660 break;
4661 case 3:
4662 check_insn(env, ctx, ASE_MT);
4663 gen_helper_mtc0_vpeconf1(arg);
4664 rn = "VPEConf1";
4665 break;
4666 case 4:
4667 check_insn(env, ctx, ASE_MT);
4668 gen_helper_mtc0_yqmask(arg);
4669 rn = "YQMask";
4670 break;
4671 case 5:
4672 check_insn(env, ctx, ASE_MT);
4673 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4674 rn = "VPESchedule";
4675 break;
4676 case 6:
4677 check_insn(env, ctx, ASE_MT);
4678 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4679 rn = "VPEScheFBack";
4680 break;
4681 case 7:
4682 check_insn(env, ctx, ASE_MT);
4683 gen_helper_mtc0_vpeopt(arg);
4684 rn = "VPEOpt";
4685 break;
4686 default:
4687 goto die;
4688 }
4689 break;
4690 case 2:
4691 switch (sel) {
4692 case 0:
4693 gen_helper_mtc0_entrylo0(arg);
4694 rn = "EntryLo0";
4695 break;
4696 case 1:
4697 check_insn(env, ctx, ASE_MT);
4698 gen_helper_mtc0_tcstatus(arg);
4699 rn = "TCStatus";
4700 break;
4701 case 2:
4702 check_insn(env, ctx, ASE_MT);
4703 gen_helper_mtc0_tcbind(arg);
4704 rn = "TCBind";
4705 break;
4706 case 3:
4707 check_insn(env, ctx, ASE_MT);
4708 gen_helper_mtc0_tcrestart(arg);
4709 rn = "TCRestart";
4710 break;
4711 case 4:
4712 check_insn(env, ctx, ASE_MT);
4713 gen_helper_mtc0_tchalt(arg);
4714 rn = "TCHalt";
4715 break;
4716 case 5:
4717 check_insn(env, ctx, ASE_MT);
4718 gen_helper_mtc0_tccontext(arg);
4719 rn = "TCContext";
4720 break;
4721 case 6:
4722 check_insn(env, ctx, ASE_MT);
4723 gen_helper_mtc0_tcschedule(arg);
4724 rn = "TCSchedule";
4725 break;
4726 case 7:
4727 check_insn(env, ctx, ASE_MT);
4728 gen_helper_mtc0_tcschefback(arg);
4729 rn = "TCScheFBack";
4730 break;
4731 default:
4732 goto die;
4733 }
4734 break;
4735 case 3:
4736 switch (sel) {
4737 case 0:
4738 gen_helper_mtc0_entrylo1(arg);
4739 rn = "EntryLo1";
4740 break;
4741 default:
4742 goto die;
4743 }
4744 break;
4745 case 4:
4746 switch (sel) {
4747 case 0:
4748 gen_helper_mtc0_context(arg);
4749 rn = "Context";
4750 break;
4751 case 1:
4752 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4753 rn = "ContextConfig";
4754 // break;
4755 default:
4756 goto die;
4757 }
4758 break;
4759 case 5:
4760 switch (sel) {
4761 case 0:
4762 gen_helper_mtc0_pagemask(arg);
4763 rn = "PageMask";
4764 break;
4765 case 1:
4766 check_insn(env, ctx, ISA_MIPS32R2);
4767 gen_helper_mtc0_pagegrain(arg);
4768 rn = "PageGrain";
4769 break;
4770 default:
4771 goto die;
4772 }
4773 break;
4774 case 6:
4775 switch (sel) {
4776 case 0:
4777 gen_helper_mtc0_wired(arg);
4778 rn = "Wired";
4779 break;
4780 case 1:
4781 check_insn(env, ctx, ISA_MIPS32R2);
4782 gen_helper_mtc0_srsconf0(arg);
4783 rn = "SRSConf0";
4784 break;
4785 case 2:
4786 check_insn(env, ctx, ISA_MIPS32R2);
4787 gen_helper_mtc0_srsconf1(arg);
4788 rn = "SRSConf1";
4789 break;
4790 case 3:
4791 check_insn(env, ctx, ISA_MIPS32R2);
4792 gen_helper_mtc0_srsconf2(arg);
4793 rn = "SRSConf2";
4794 break;
4795 case 4:
4796 check_insn(env, ctx, ISA_MIPS32R2);
4797 gen_helper_mtc0_srsconf3(arg);
4798 rn = "SRSConf3";
4799 break;
4800 case 5:
4801 check_insn(env, ctx, ISA_MIPS32R2);
4802 gen_helper_mtc0_srsconf4(arg);
4803 rn = "SRSConf4";
4804 break;
4805 default:
4806 goto die;
4807 }
4808 break;
4809 case 7:
4810 switch (sel) {
4811 case 0:
4812 check_insn(env, ctx, ISA_MIPS32R2);
4813 gen_helper_mtc0_hwrena(arg);
4814 rn = "HWREna";
4815 break;
4816 default:
4817 goto die;
4818 }
4819 break;
4820 case 8:
4821 /* ignored */
4822 rn = "BadVAddr";
4823 break;
4824 case 9:
4825 switch (sel) {
4826 case 0:
4827 gen_helper_mtc0_count(arg);
4828 rn = "Count";
4829 break;
4830 /* 6,7 are implementation dependent */
4831 default:
4832 goto die;
4833 }
4834 /* Stop translation as we may have switched the execution mode */
4835 ctx->bstate = BS_STOP;
4836 break;
4837 case 10:
4838 switch (sel) {
4839 case 0:
4840 gen_helper_mtc0_entryhi(arg);
4841 rn = "EntryHi";
4842 break;
4843 default:
4844 goto die;
4845 }
4846 break;
4847 case 11:
4848 switch (sel) {
4849 case 0:
4850 gen_helper_mtc0_compare(arg);
4851 rn = "Compare";
4852 break;
4853 /* 6,7 are implementation dependent */
4854 default:
4855 goto die;
4856 }
4857 /* Stop translation as we may have switched the execution mode */
4858 ctx->bstate = BS_STOP;
4859 break;
4860 case 12:
4861 switch (sel) {
4862 case 0:
4863 save_cpu_state(ctx, 1);
4864 gen_helper_mtc0_status(arg);
4865 /* BS_STOP isn't good enough here, hflags may have changed. */
4866 gen_save_pc(ctx->pc + 4);
4867 ctx->bstate = BS_EXCP;
4868 rn = "Status";
4869 break;
4870 case 1:
4871 check_insn(env, ctx, ISA_MIPS32R2);
4872 gen_helper_mtc0_intctl(arg);
4873 /* Stop translation as we may have switched the execution mode */
4874 ctx->bstate = BS_STOP;
4875 rn = "IntCtl";
4876 break;
4877 case 2:
4878 check_insn(env, ctx, ISA_MIPS32R2);
4879 gen_helper_mtc0_srsctl(arg);
4880 /* Stop translation as we may have switched the execution mode */
4881 ctx->bstate = BS_STOP;
4882 rn = "SRSCtl";
4883 break;
4884 case 3:
4885 check_insn(env, ctx, ISA_MIPS32R2);
4886 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
4887 /* Stop translation as we may have switched the execution mode */
4888 ctx->bstate = BS_STOP;
4889 rn = "SRSMap";
4890 break;
4891 default:
4892 goto die;
4893 }
4894 break;
4895 case 13:
4896 switch (sel) {
4897 case 0:
4898 save_cpu_state(ctx, 1);
4899 gen_helper_mtc0_cause(arg);
4900 rn = "Cause";
4901 break;
4902 default:
4903 goto die;
4904 }
4905 break;
4906 case 14:
4907 switch (sel) {
4908 case 0:
4909 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4910 rn = "EPC";
4911 break;
4912 default:
4913 goto die;
4914 }
4915 break;
4916 case 15:
4917 switch (sel) {
4918 case 0:
4919 /* ignored */
4920 rn = "PRid";
4921 break;
4922 case 1:
4923 check_insn(env, ctx, ISA_MIPS32R2);
4924 gen_helper_mtc0_ebase(arg);
4925 rn = "EBase";
4926 break;
4927 default:
4928 goto die;
4929 }
4930 break;
4931 case 16:
4932 switch (sel) {
4933 case 0:
4934 gen_helper_mtc0_config0(arg);
4935 rn = "Config";
4936 /* Stop translation as we may have switched the execution mode */
4937 ctx->bstate = BS_STOP;
4938 break;
4939 case 1:
4940 /* ignored, read only */
4941 rn = "Config1";
4942 break;
4943 case 2:
4944 gen_helper_mtc0_config2(arg);
4945 rn = "Config2";
4946 /* Stop translation as we may have switched the execution mode */
4947 ctx->bstate = BS_STOP;
4948 break;
4949 case 3:
4950 /* ignored */
4951 rn = "Config3";
4952 break;
4953 /* 6,7 are implementation dependent */
4954 default:
4955 rn = "Invalid config selector";
4956 goto die;
4957 }
4958 break;
4959 case 17:
4960 switch (sel) {
4961 case 0:
4962 gen_helper_mtc0_lladdr(arg);
4963 rn = "LLAddr";
4964 break;
4965 default:
4966 goto die;
4967 }
4968 break;
4969 case 18:
4970 switch (sel) {
4971 case 0 ... 7:
4972 gen_helper_1i(mtc0_watchlo, arg, sel);
4973 rn = "WatchLo";
4974 break;
4975 default:
4976 goto die;
4977 }
4978 break;
4979 case 19:
4980 switch (sel) {
4981 case 0 ... 7:
4982 gen_helper_1i(mtc0_watchhi, arg, sel);
4983 rn = "WatchHi";
4984 break;
4985 default:
4986 goto die;
4987 }
4988 break;
4989 case 20:
4990 switch (sel) {
4991 case 0:
4992 check_insn(env, ctx, ISA_MIPS3);
4993 gen_helper_mtc0_xcontext(arg);
4994 rn = "XContext";
4995 break;
4996 default:
4997 goto die;
4998 }
4999 break;
5000 case 21:
5001 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5002 switch (sel) {
5003 case 0:
5004 gen_helper_mtc0_framemask(arg);
5005 rn = "Framemask";
5006 break;
5007 default:
5008 goto die;
5009 }
5010 break;
5011 case 22:
5012 /* ignored */
5013 rn = "Diagnostic"; /* implementation dependent */
5014 break;
5015 case 23:
5016 switch (sel) {
5017 case 0:
5018 gen_helper_mtc0_debug(arg); /* EJTAG support */
5019 /* BS_STOP isn't good enough here, hflags may have changed. */
5020 gen_save_pc(ctx->pc + 4);
5021 ctx->bstate = BS_EXCP;
5022 rn = "Debug";
5023 break;
5024 case 1:
5025 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5026 /* Stop translation as we may have switched the execution mode */
5027 ctx->bstate = BS_STOP;
5028 rn = "TraceControl";
5029 // break;
5030 case 2:
5031 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5032 /* Stop translation as we may have switched the execution mode */
5033 ctx->bstate = BS_STOP;
5034 rn = "TraceControl2";
5035 // break;
5036 case 3:
5037 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5038 /* Stop translation as we may have switched the execution mode */
5039 ctx->bstate = BS_STOP;
5040 rn = "UserTraceData";
5041 // break;
5042 case 4:
5043 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5044 /* Stop translation as we may have switched the execution mode */
5045 ctx->bstate = BS_STOP;
5046 rn = "TraceBPC";
5047 // break;
5048 default:
5049 goto die;
5050 }
5051 break;
5052 case 24:
5053 switch (sel) {
5054 case 0:
5055 /* EJTAG support */
5056 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
5057 rn = "DEPC";
5058 break;
5059 default:
5060 goto die;
5061 }
5062 break;
5063 case 25:
5064 switch (sel) {
5065 case 0:
5066 gen_helper_mtc0_performance0(arg);
5067 rn = "Performance0";
5068 break;
5069 case 1:
5070 // gen_helper_mtc0_performance1(arg);
5071 rn = "Performance1";
5072 // break;
5073 case 2:
5074 // gen_helper_mtc0_performance2(arg);
5075 rn = "Performance2";
5076 // break;
5077 case 3:
5078 // gen_helper_mtc0_performance3(arg);
5079 rn = "Performance3";
5080 // break;
5081 case 4:
5082 // gen_helper_mtc0_performance4(arg);
5083 rn = "Performance4";
5084 // break;
5085 case 5:
5086 // gen_helper_mtc0_performance5(arg);
5087 rn = "Performance5";
5088 // break;
5089 case 6:
5090 // gen_helper_mtc0_performance6(arg);
5091 rn = "Performance6";
5092 // break;
5093 case 7:
5094 // gen_helper_mtc0_performance7(arg);
5095 rn = "Performance7";
5096 // break;
5097 default:
5098 goto die;
5099 }
5100 break;
5101 case 26:
5102 /* ignored */
5103 rn = "ECC";
5104 break;
5105 case 27:
5106 switch (sel) {
5107 case 0 ... 3:
5108 /* ignored */
5109 rn = "CacheErr";
5110 break;
5111 default:
5112 goto die;
5113 }
5114 break;
5115 case 28:
5116 switch (sel) {
5117 case 0:
5118 case 2:
5119 case 4:
5120 case 6:
5121 gen_helper_mtc0_taglo(arg);
5122 rn = "TagLo";
5123 break;
5124 case 1:
5125 case 3:
5126 case 5:
5127 case 7:
5128 gen_helper_mtc0_datalo(arg);
5129 rn = "DataLo";
5130 break;
5131 default:
5132 goto die;
5133 }
5134 break;
5135 case 29:
5136 switch (sel) {
5137 case 0:
5138 case 2:
5139 case 4:
5140 case 6:
5141 gen_helper_mtc0_taghi(arg);
5142 rn = "TagHi";
5143 break;
5144 case 1:
5145 case 3:
5146 case 5:
5147 case 7:
5148 gen_helper_mtc0_datahi(arg);
5149 rn = "DataHi";
5150 break;
5151 default:
5152 rn = "invalid sel";
5153 goto die;
5154 }
5155 break;
5156 case 30:
5157 switch (sel) {
5158 case 0:
5159 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5160 rn = "ErrorEPC";
5161 break;
5162 default:
5163 goto die;
5164 }
5165 break;
5166 case 31:
5167 switch (sel) {
5168 case 0:
5169 /* EJTAG support */
5170 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
5171 rn = "DESAVE";
5172 break;
5173 default:
5174 goto die;
5175 }
5176 /* Stop translation as we may have switched the execution mode */
5177 ctx->bstate = BS_STOP;
5178 break;
5179 default:
5180 goto die;
5181 }
5182 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
5183 /* For simplicity assume that all writes can cause interrupts. */
5184 if (use_icount) {
5185 gen_io_end();
5186 ctx->bstate = BS_STOP;
5187 }
5188 return;
5189
5190 die:
5191 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
5192 generate_exception(ctx, EXCP_RI);
5193 }
5194 #endif /* TARGET_MIPS64 */
5195
5196 static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5197 int u, int sel, int h)
5198 {
5199 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5200 TCGv t0 = tcg_temp_local_new();
5201
5202 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5203 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
5204 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
5205 tcg_gen_movi_tl(t0, -1);
5206 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5207 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5208 tcg_gen_movi_tl(t0, -1);
5209 else if (u == 0) {
5210 switch (rt) {
5211 case 2:
5212 switch (sel) {
5213 case 1:
5214 gen_helper_mftc0_tcstatus(t0);
5215 break;
5216 case 2:
5217 gen_helper_mftc0_tcbind(t0);
5218 break;
5219 case 3:
5220 gen_helper_mftc0_tcrestart(t0);
5221 break;
5222 case 4:
5223 gen_helper_mftc0_tchalt(t0);
5224 break;
5225 case 5:
5226 gen_helper_mftc0_tccontext(t0);
5227 break;
5228 case 6:
5229 gen_helper_mftc0_tcschedule(t0);
5230 break;
5231 case 7:
5232 gen_helper_mftc0_tcschefback(t0);
5233 break;
5234 default:
5235 gen_mfc0(env, ctx, t0, rt, sel);
5236 break;
5237 }
5238 break;
5239 case 10:
5240 switch (sel) {
5241 case 0:
5242 gen_helper_mftc0_entryhi(t0);
5243 break;
5244 default:
5245 gen_mfc0(env, ctx, t0, rt, sel);
5246 break;
5247 }
5248 case 12:
5249 switch (sel) {
5250 case 0:
5251 gen_helper_mftc0_status(t0);
5252 break;
5253 default:
5254 gen_mfc0(env, ctx, t0, rt, sel);
5255 break;
5256 }
5257 case 23:
5258 switch (sel) {
5259 case 0:
5260 gen_helper_mftc0_debug(t0);
5261 break;
5262 default:
5263 gen_mfc0(env, ctx, t0, rt, sel);
5264 break;
5265 }
5266 break;
5267 default:
5268 gen_mfc0(env, ctx, t0, rt, sel);
5269 }
5270 } else switch (sel) {
5271 /* GPR registers. */
5272 case 0:
5273 gen_helper_1i(mftgpr, t0, rt);
5274 break;
5275 /* Auxiliary CPU registers */
5276 case 1:
5277 switch (rt) {
5278 case 0:
5279 gen_helper_1i(mftlo, t0, 0);
5280 break;
5281 case 1:
5282 gen_helper_1i(mfthi, t0, 0);
5283 break;
5284 case 2:
5285 gen_helper_1i(mftacx, t0, 0);
5286 break;
5287 case 4:
5288 gen_helper_1i(mftlo, t0, 1);
5289 break;
5290 case 5:
5291 gen_helper_1i(mfthi, t0, 1);
5292 break;
5293 case 6:
5294 gen_helper_1i(mftacx, t0, 1);
5295 break;
5296 case 8:
5297 gen_helper_1i(mftlo, t0, 2);
5298 break;
5299 case 9:
5300 gen_helper_1i(mfthi, t0, 2);
5301 break;
5302 case 10:
5303 gen_helper_1i(mftacx, t0, 2);
5304 break;
5305 case 12:
5306 gen_helper_1i(mftlo, t0, 3);
5307 break;
5308 case 13:
5309 gen_helper_1i(mfthi, t0, 3);
5310 break;
5311 case 14:
5312 gen_helper_1i(mftacx, t0, 3);
5313 break;
5314 case 16:
5315 gen_helper_mftdsp(t0);
5316 break;
5317 default:
5318 goto die;
5319 }
5320 break;
5321 /* Floating point (COP1). */
5322 case 2:
5323 /* XXX: For now we support only a single FPU context. */
5324 if (h == 0) {
5325 TCGv_i32 fp0 = tcg_temp_new_i32();
5326
5327 gen_load_fpr32(fp0, rt);
5328 tcg_gen_ext_i32_tl(t0, fp0);
5329 tcg_temp_free_i32(fp0);
5330 } else {
5331 TCGv_i32 fp0 = tcg_temp_new_i32();
5332
5333 gen_load_fpr32h(fp0, rt);
5334 tcg_gen_ext_i32_tl(t0, fp0);
5335 tcg_temp_free_i32(fp0);
5336 }
5337 break;
5338 case 3:
5339 /* XXX: For now we support only a single FPU context. */
5340 gen_helper_1i(cfc1, t0, rt);
5341 break;
5342 /* COP2: Not implemented. */
5343 case 4:
5344 case 5:
5345 /* fall through */
5346 default:
5347 goto die;
5348 }
5349 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
5350 gen_store_gpr(t0, rd);
5351 tcg_temp_free(t0);
5352 return;
5353
5354 die:
5355 tcg_temp_free(t0);
5356 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
5357 generate_exception(ctx, EXCP_RI);
5358 }
5359
5360 static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5361 int u, int sel, int h)
5362 {
5363 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5364 TCGv t0 = tcg_temp_local_new();
5365
5366 gen_load_gpr(t0, rt);
5367 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5368 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
5369 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
5370 /* NOP */ ;
5371 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5372 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5373 /* NOP */ ;
5374 else if (u == 0) {
5375 switch (rd) {
5376 case 2:
5377 switch (sel) {
5378 case 1:
5379 gen_helper_mttc0_tcstatus(t0);
5380 break;
5381 case 2:
5382 gen_helper_mttc0_tcbind(t0);
5383 break;
5384 case 3:
5385 gen_helper_mttc0_tcrestart(t0);
5386 break;
5387 case 4:
5388 gen_helper_mttc0_tchalt(t0);
5389 break;
5390 case 5:
5391 gen_helper_mttc0_tccontext(t0);
5392 break;
5393 case 6:
5394 gen_helper_mttc0_tcschedule(t0);
5395 break;
5396 case 7:
5397 gen_helper_mttc0_tcschefback(t0);
5398 break;
5399 default:
5400 gen_mtc0(env, ctx, t0, rd, sel);
5401 break;
5402 }
5403 break;
5404 case 10:
5405 switch (sel) {
5406 case 0:
5407 gen_helper_mttc0_entryhi(t0);
5408 break;
5409 default:
5410 gen_mtc0(env, ctx, t0, rd, sel);
5411 break;
5412 }
5413 case 12:
5414 switch (sel) {
5415 case 0:
5416 gen_helper_mttc0_status(t0);
5417 break;
5418 default:
5419 gen_mtc0(env, ctx, t0, rd, sel);
5420 break;
5421 }
5422 case 23:
5423 switch (sel) {
5424 case 0:
5425 gen_helper_mttc0_debug(t0);
5426 break;
5427 default:
5428 gen_mtc0(env, ctx, t0, rd, sel);
5429 break;
5430 }
5431 break;
5432 default:
5433 gen_mtc0(env, ctx, t0, rd, sel);
5434 }
5435 } else switch (sel) {
5436 /* GPR registers. */
5437 case 0:
5438 gen_helper_1i(mttgpr, t0, rd);
5439 break;
5440 /* Auxiliary CPU registers */
5441 case 1:
5442 switch (rd) {
5443 case 0:
5444 gen_helper_1i(mttlo, t0, 0);
5445 break;
5446 case 1:
5447 gen_helper_1i(mtthi, t0, 0);
5448 break;
5449 case 2:
5450 gen_helper_1i(mttacx, t0, 0);
5451 break;
5452 case 4:
5453 gen_helper_1i(mttlo, t0, 1);
5454 break;
5455 case 5:
5456 gen_helper_1i(mtthi, t0, 1);
5457 break;
5458 case 6:
5459 gen_helper_1i(mttacx, t0, 1);
5460 break;
5461 case 8:
5462 gen_helper_1i(mttlo, t0, 2);
5463 break;
5464 case 9:
5465 gen_helper_1i(mtthi, t0, 2);
5466 break;
5467 case 10:
5468 gen_helper_1i(mttacx, t0, 2);
5469 break;
5470 case 12:
5471 gen_helper_1i(mttlo, t0, 3);
5472 break;
5473 case 13:
5474 gen_helper_1i(mtthi, t0, 3);
5475 break;
5476 case 14:
5477 gen_helper_1i(mttacx, t0, 3);
5478 break;
5479 case 16:
5480 gen_helper_mttdsp(t0);
5481 break;
5482 default:
5483 goto die;
5484 }
5485 break;
5486 /* Floating point (COP1). */
5487 case 2:
5488 /* XXX: For now we support only a single FPU context. */
5489 if (h == 0) {
5490 TCGv_i32 fp0 = tcg_temp_new_i32();
5491
5492 tcg_gen_trunc_tl_i32(fp0, t0);
5493 gen_store_fpr32(fp0, rd);
5494 tcg_temp_free_i32(fp0);
5495 } else {
5496 TCGv_i32 fp0 = tcg_temp_new_i32();
5497
5498 tcg_gen_trunc_tl_i32(fp0, t0);
5499 gen_store_fpr32h(fp0, rd);
5500 tcg_temp_free_i32(fp0);
5501 }
5502 break;
5503 case 3:
5504 /* XXX: For now we support only a single FPU context. */
5505 gen_helper_1i(ctc1, t0, rd);
5506 break;
5507 /* COP2: Not implemented. */
5508 case 4:
5509 case 5:
5510 /* fall through */
5511 default:
5512 goto die;
5513 }
5514 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
5515 tcg_temp_free(t0);
5516 return;
5517
5518 die:
5519 tcg_temp_free(t0);
5520 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
5521 generate_exception(ctx, EXCP_RI);
5522 }
5523
5524 static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
5525 {
5526 const char *opn = "ldst";
5527
5528 switch (opc) {
5529 case OPC_MFC0:
5530 if (rt == 0) {
5531 /* Treat as NOP. */
5532 return;
5533 }
5534 gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
5535 opn = "mfc0";
5536 break;
5537 case OPC_MTC0:
5538 {
5539 TCGv t0 = tcg_temp_new();
5540
5541 gen_load_gpr(t0, rt);
5542 gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5543 tcg_temp_free(t0);
5544 }
5545 opn = "mtc0";
5546 break;
5547 #if defined(TARGET_MIPS64)
5548 case OPC_DMFC0:
5549 check_insn(env, ctx, ISA_MIPS3);
5550 if (rt == 0) {
5551 /* Treat as NOP. */
5552 return;
5553 }
5554 gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
5555 opn = "dmfc0";
5556 break;
5557 case OPC_DMTC0:
5558 check_insn(env, ctx, ISA_MIPS3);
5559 {
5560 TCGv t0 = tcg_temp_new();
5561
5562 gen_load_gpr(t0, rt);
5563 gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5564 tcg_temp_free(t0);
5565 }
5566 opn = "dmtc0";
5567 break;
5568 #endif
5569 case OPC_MFTR:
5570 check_insn(env, ctx, ASE_MT);
5571 if (rd == 0) {
5572 /* Treat as NOP. */
5573 return;
5574 }
5575 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
5576 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5577 opn = "mftr";
5578 break;
5579 case OPC_MTTR:
5580 check_insn(env, ctx, ASE_MT);
5581 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
5582 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5583 opn = "mttr";
5584 break;
5585 case OPC_TLBWI:
5586 opn = "tlbwi";
5587 if (!env->tlb->helper_tlbwi)
5588 goto die;
5589 gen_helper_tlbwi();
5590 break;
5591 case OPC_TLBWR:
5592 opn = "tlbwr";
5593 if (!env->tlb->helper_tlbwr)
5594 goto die;
5595 gen_helper_tlbwr();
5596 break;
5597 case OPC_TLBP:
5598 opn = "tlbp";
5599 if (!env->tlb->helper_tlbp)
5600 goto die;
5601 gen_helper_tlbp();
5602 break;
5603 case OPC_TLBR:
5604 opn = "tlbr";
5605 if (!env->tlb->helper_tlbr)
5606 goto die;
5607 gen_helper_tlbr();
5608 break;
5609 case OPC_ERET:
5610 opn = "eret";
5611 check_insn(env, ctx, ISA_MIPS2);
5612 gen_helper_eret();
5613 ctx->bstate = BS_EXCP;
5614 break;
5615 case OPC_DERET:
5616 opn = "deret";
5617 check_insn(env, ctx, ISA_MIPS32);
5618 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
5619 MIPS_INVAL(opn);
5620 generate_exception(ctx, EXCP_RI);
5621 } else {
5622 gen_helper_deret();
5623 ctx->bstate = BS_EXCP;
5624 }
5625 break;
5626 case OPC_WAIT:
5627 opn = "wait";
5628 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
5629 /* If we get an exception, we want to restart at next instruction */
5630 ctx->pc += 4;
5631 save_cpu_state(ctx, 1);
5632 ctx->pc -= 4;
5633 gen_helper_wait();
5634 ctx->bstate = BS_EXCP;
5635 break;
5636 default:
5637 die:
5638 MIPS_INVAL(opn);
5639 generate_exception(ctx, EXCP_RI);
5640 return;
5641 }
5642 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
5643 }
5644 #endif /* !CONFIG_USER_ONLY */
5645
5646 /* CP1 Branches (before delay slot) */
5647 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5648 int32_t cc, int32_t offset)
5649 {
5650 target_ulong btarget;
5651 const char *opn = "cp1 cond branch";
5652 TCGv_i32 t0 = tcg_temp_new_i32();
5653
5654 if (cc != 0)
5655 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
5656
5657 btarget = ctx->pc + 4 + offset;
5658
5659 switch (op) {
5660 case OPC_BC1F:
5661 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5662 tcg_gen_not_i32(t0, t0);
5663 tcg_gen_andi_i32(t0, t0, 1);
5664 tcg_gen_extu_i32_tl(bcond, t0);
5665 opn = "bc1f";
5666 goto not_likely;
5667 case OPC_BC1FL:
5668 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5669 tcg_gen_not_i32(t0, t0);
5670 tcg_gen_andi_i32(t0, t0, 1);
5671 tcg_gen_extu_i32_tl(bcond, t0);
5672 opn = "bc1fl";
5673 goto likely;
5674 case OPC_BC1T:
5675 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5676 tcg_gen_andi_i32(t0, t0, 1);
5677 tcg_gen_extu_i32_tl(bcond, t0);
5678 opn = "bc1t";
5679 goto not_likely;
5680 case OPC_BC1TL:
5681 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5682 tcg_gen_andi_i32(t0, t0, 1);
5683 tcg_gen_extu_i32_tl(bcond, t0);
5684 opn = "bc1tl";
5685 likely:
5686 ctx->hflags |= MIPS_HFLAG_BL;
5687 break;
5688 case OPC_BC1FANY2:
5689 {
5690 TCGv_i32 t1 = tcg_temp_new_i32();
5691 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5692 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5693 tcg_gen_or_i32(t0, t0, t1);
5694 tcg_temp_free_i32(t1);
5695 tcg_gen_not_i32(t0, t0);
5696 tcg_gen_andi_i32(t0, t0, 1);
5697 tcg_gen_extu_i32_tl(bcond, t0);
5698 }
5699 opn = "bc1any2f";
5700 goto not_likely;
5701 case OPC_BC1TANY2:
5702 {
5703 TCGv_i32 t1 = tcg_temp_new_i32();
5704 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5705 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5706 tcg_gen_or_i32(t0, t0, t1);
5707 tcg_temp_free_i32(t1);
5708 tcg_gen_andi_i32(t0, t0, 1);
5709 tcg_gen_extu_i32_tl(bcond, t0);
5710 }
5711 opn = "bc1any2t";
5712 goto not_likely;
5713 case OPC_BC1FANY4:
5714 {
5715 TCGv_i32 t1 = tcg_temp_new_i32();
5716 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5717 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5718 tcg_gen_or_i32(t0, t0, t1);
5719 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
5720 tcg_gen_or_i32(t0, t0, t1);
5721 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
5722 tcg_gen_or_i32(t0, t0, t1);
5723 tcg_temp_free_i32(t1);
5724 tcg_gen_not_i32(t0, t0);
5725 tcg_gen_andi_i32(t0, t0, 1);
5726 tcg_gen_extu_i32_tl(bcond, t0);
5727 }
5728 opn = "bc1any4f";
5729 goto not_likely;
5730 case OPC_BC1TANY4:
5731 {
5732 TCGv_i32 t1 = tcg_temp_new_i32();
5733 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5734 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5735 tcg_gen_or_i32(t0, t0, t1);
5736 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
5737 tcg_gen_or_i32(t0, t0, t1);
5738 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
5739 tcg_gen_or_i32(t0, t0, t1);
5740 tcg_temp_free_i32(t1);
5741 tcg_gen_andi_i32(t0, t0, 1);
5742 tcg_gen_extu_i32_tl(bcond, t0);
5743 }
5744 opn = "bc1any4t";
5745 not_likely:
5746 ctx->hflags |= MIPS_HFLAG_BC;
5747 break;
5748 default:
5749 MIPS_INVAL(opn);
5750 generate_exception (ctx, EXCP_RI);
5751 goto out;
5752 }
5753 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
5754 ctx->hflags, btarget);
5755 ctx->btarget = btarget;
5756
5757 out:
5758 tcg_temp_free_i32(t0);
5759 }
5760
5761 /* Coprocessor 1 (FPU) */
5762
5763 #define FOP(func, fmt) (((fmt) << 21) | (func))
5764
5765 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5766 {
5767 const char *opn = "cp1 move";
5768 TCGv t0 = tcg_temp_new();
5769
5770 switch (opc) {
5771 case OPC_MFC1:
5772 {
5773 TCGv_i32 fp0 = tcg_temp_new_i32();
5774
5775 gen_load_fpr32(fp0, fs);
5776 tcg_gen_ext_i32_tl(t0, fp0);
5777 tcg_temp_free_i32(fp0);
5778 }
5779 gen_store_gpr(t0, rt);
5780 opn = "mfc1";
5781 break;
5782 case OPC_MTC1:
5783 gen_load_gpr(t0, rt);
5784 {
5785 TCGv_i32 fp0 = tcg_temp_new_i32();
5786
5787 tcg_gen_trunc_tl_i32(fp0, t0);
5788 gen_store_fpr32(fp0, fs);
5789 tcg_temp_free_i32(fp0);
5790 }
5791 opn = "mtc1";
5792 break;
5793 case OPC_CFC1:
5794 gen_helper_1i(cfc1, t0, fs);
5795 gen_store_gpr(t0, rt);
5796 opn = "cfc1";
5797 break;
5798 case OPC_CTC1:
5799 gen_load_gpr(t0, rt);
5800 gen_helper_1i(ctc1, t0, fs);
5801 opn = "ctc1";
5802 break;
5803 #if defined(TARGET_MIPS64)
5804 case OPC_DMFC1:
5805 gen_load_fpr64(ctx, t0, fs);
5806 gen_store_gpr(t0, rt);
5807 opn = "dmfc1";
5808 break;
5809 case OPC_DMTC1:
5810 gen_load_gpr(t0, rt);
5811 gen_store_fpr64(ctx, t0, fs);
5812 opn = "dmtc1";
5813 break;
5814 #endif
5815 case OPC_MFHC1:
5816 {
5817 TCGv_i32 fp0 = tcg_temp_new_i32();
5818
5819 gen_load_fpr32h(fp0, fs);
5820 tcg_gen_ext_i32_tl(t0, fp0);
5821 tcg_temp_free_i32(fp0);
5822 }
5823 gen_store_gpr(t0, rt);
5824 opn = "mfhc1";
5825 break;
5826 case OPC_MTHC1:
5827 gen_load_gpr(t0, rt);
5828 {
5829 TCGv_i32 fp0 = tcg_temp_new_i32();
5830
5831 tcg_gen_trunc_tl_i32(fp0, t0);
5832 gen_store_fpr32h(fp0, fs);
5833 tcg_temp_free_i32(fp0);
5834 }
5835 opn = "mthc1";
5836 break;
5837 default:
5838 MIPS_INVAL(opn);
5839 generate_exception (ctx, EXCP_RI);
5840 goto out;
5841 }
5842 MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
5843
5844 out:
5845 tcg_temp_free(t0);
5846 }
5847
5848 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5849 {
5850 int l1;
5851 TCGCond cond;
5852 TCGv_i32 t0;
5853
5854 if (rd == 0) {
5855 /* Treat as NOP. */
5856 return;
5857 }
5858
5859 if (tf)
5860 cond = TCG_COND_EQ;
5861 else
5862 cond = TCG_COND_NE;
5863
5864 l1 = gen_new_label();
5865 t0 = tcg_temp_new_i32();
5866 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
5867 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5868 tcg_temp_free_i32(t0);
5869 if (rs == 0) {
5870 tcg_gen_movi_tl(cpu_gpr[rd], 0);
5871 } else {
5872 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
5873 }
5874 gen_set_label(l1);
5875 }
5876
5877 static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
5878 {
5879 int cond;
5880 TCGv_i32 t0 = tcg_temp_new_i32();
5881 int l1 = gen_new_label();
5882
5883 if (tf)
5884 cond = TCG_COND_EQ;
5885 else
5886 cond = TCG_COND_NE;
5887
5888 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
5889 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5890 gen_load_fpr32(t0, fs);
5891 gen_store_fpr32(t0, fd);
5892 gen_set_label(l1);
5893 tcg_temp_free_i32(t0);
5894 }
5895
5896 static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
5897 {
5898 int cond;
5899 TCGv_i32 t0 = tcg_temp_new_i32();
5900 TCGv_i64 fp0;
5901 int l1 = gen_new_label();
5902
5903 if (tf)
5904 cond = TCG_COND_EQ;
5905 else
5906 cond = TCG_COND_NE;
5907
5908 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
5909 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5910 tcg_temp_free_i32(t0);
5911 fp0 = tcg_temp_new_i64();
5912 gen_load_fpr64(ctx, fp0, fs);
5913 gen_store_fpr64(ctx, fp0, fd);
5914 tcg_temp_free_i64(fp0);
5915 gen_set_label(l1);
5916 }
5917
5918 static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
5919 {
5920 int cond;
5921 TCGv_i32 t0 = tcg_temp_new_i32();
5922 int l1 = gen_new_label();
5923 int l2 = gen_new_label();
5924
5925 if (tf)
5926 cond = TCG_COND_EQ;
5927 else
5928 cond = TCG_COND_NE;
5929
5930 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
5931 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5932 gen_load_fpr32(t0, fs);
5933 gen_store_fpr32(t0, fd);
5934 gen_set_label(l1);
5935
5936 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
5937 tcg_gen_brcondi_i32(cond, t0, 0, l2);
5938 gen_load_fpr32h(t0, fs);
5939 gen_store_fpr32h(t0, fd);
5940 tcg_temp_free_i32(t0);
5941 gen_set_label(l2);
5942 }
5943
5944
5945 static void gen_farith (DisasContext *ctx, uint32_t op1,
5946 int ft, int fs, int fd, int cc)
5947 {
5948 const char *opn = "farith";
5949 const char *condnames[] = {
5950 "c.f",
5951 "c.un",
5952 "c.eq",
5953 "c.ueq",
5954 "c.olt",
5955 "c.ult",
5956 "c.ole",
5957 "c.ule",
5958 "c.sf",
5959 "c.ngle",
5960 "c.seq",
5961 "c.ngl",
5962 "c.lt",
5963 "c.nge",
5964 "c.le",
5965 "c.ngt",
5966 };
5967 const char *condnames_abs[] = {
5968 "cabs.f",
5969 "cabs.un",
5970 "cabs.eq",
5971 "cabs.ueq",
5972 "cabs.olt",
5973 "cabs.ult",
5974 "cabs.ole",
5975 "cabs.ule",
5976 "cabs.sf",
5977 "cabs.ngle",
5978 "cabs.seq",
5979 "cabs.ngl",
5980 "cabs.lt",
5981 "cabs.nge",
5982 "cabs.le",
5983 "cabs.ngt",
5984 };
5985 enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
5986 uint32_t func = ctx->opcode & 0x3f;
5987
5988 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
5989 case FOP(0, 16):
5990 {
5991 TCGv_i32 fp0 = tcg_temp_new_i32();
5992 TCGv_i32 fp1 = tcg_temp_new_i32();
5993
5994 gen_load_fpr32(fp0, fs);
5995 gen_load_fpr32(fp1, ft);
5996 gen_helper_float_add_s(fp0, fp0, fp1);
5997 tcg_temp_free_i32(fp1);
5998 gen_store_fpr32(fp0, fd);
5999 tcg_temp_free_i32(fp0);
6000 }
6001 opn = "add.s";
6002 optype = BINOP;
6003 break;
6004 case FOP(1, 16):
6005 {
6006 TCGv_i32 fp0 = tcg_temp_new_i32();
6007 TCGv_i32 fp1 = tcg_temp_new_i32();
6008
6009 gen_load_fpr32(fp0, fs);
6010 gen_load_fpr32(fp1, ft);
6011 gen_helper_float_sub_s(fp0, fp0, fp1);
6012 tcg_temp_free_i32(fp1);
6013 gen_store_fpr32(fp0, fd);
6014 tcg_temp_free_i32(fp0);
6015 }
6016 opn = "sub.s";
6017 optype = BINOP;
6018 break;
6019 case FOP(2, 16):
6020 {
6021 TCGv_i32 fp0 = tcg_temp_new_i32();
6022 TCGv_i32 fp1 = tcg_temp_new_i32();
6023
6024 gen_load_fpr32(fp0, fs);
6025 gen_load_fpr32(fp1, ft);
6026 gen_helper_float_mul_s(fp0, fp0, fp1);
6027 tcg_temp_free_i32(fp1);
6028 gen_store_fpr32(fp0, fd);
6029 tcg_temp_free_i32(fp0);
6030 }
6031 opn = "mul.s";
6032 optype = BINOP;
6033 break;
6034 case FOP(3, 16):
6035 {
6036 TCGv_i32 fp0 = tcg_temp_new_i32();
6037 TCGv_i32 fp1 = tcg_temp_new_i32();
6038
6039 gen_load_fpr32(fp0, fs);
6040 gen_load_fpr32(fp1, ft);
6041 gen_helper_float_div_s(fp0, fp0, fp1);
6042 tcg_temp_free_i32(fp1);
6043 gen_store_fpr32(fp0, fd);
6044 tcg_temp_free_i32(fp0);
6045 }
6046 opn = "div.s";
6047 optype = BINOP;
6048 break;
6049 case FOP(4, 16):
6050 {
6051 TCGv_i32 fp0 = tcg_temp_new_i32();
6052
6053 gen_load_fpr32(fp0, fs);
6054 gen_helper_float_sqrt_s(fp0, fp0);
6055 gen_store_fpr32(fp0, fd);
6056 tcg_temp_free_i32(fp0);
6057 }
6058 opn = "sqrt.s";
6059 break;
6060 case FOP(5, 16):
6061 {
6062 TCGv_i32 fp0 = tcg_temp_new_i32();
6063
6064 gen_load_fpr32(fp0, fs);
6065 gen_helper_float_abs_s(fp0, fp0);
6066 gen_store_fpr32(fp0, fd);
6067 tcg_temp_free_i32(fp0);
6068 }
6069 opn = "abs.s";
6070 break;
6071 case FOP(6, 16):
6072 {
6073 TCGv_i32 fp0 = tcg_temp_new_i32();
6074
6075 gen_load_fpr32(fp0, fs);
6076 gen_store_fpr32(fp0, fd);
6077 tcg_temp_free_i32(fp0);
6078 }
6079 opn = "mov.s";
6080 break;
6081 case FOP(7, 16):
6082 {
6083 TCGv_i32 fp0 = tcg_temp_new_i32();
6084
6085 gen_load_fpr32(fp0, fs);
6086 gen_helper_float_chs_s(fp0, fp0);
6087 gen_store_fpr32(fp0, fd);
6088 tcg_temp_free_i32(fp0);
6089 }
6090 opn = "neg.s";
6091 break;
6092 case FOP(8, 16):
6093 check_cp1_64bitmode(ctx);
6094 {
6095 TCGv_i32 fp32 = tcg_temp_new_i32();
6096 TCGv_i64 fp64 = tcg_temp_new_i64();
6097
6098 gen_load_fpr32(fp32, fs);
6099 gen_helper_float_roundl_s(fp64, fp32);
6100 tcg_temp_free_i32(fp32);
6101 gen_store_fpr64(ctx, fp64, fd);
6102 tcg_temp_free_i64(fp64);
6103 }
6104 opn = "round.l.s";
6105 break;
6106 case FOP(9, 16):
6107 check_cp1_64bitmode(ctx);
6108 {
6109 TCGv_i32 fp32 = tcg_temp_new_i32();
6110 TCGv_i64 fp64 = tcg_temp_new_i64();
6111
6112 gen_load_fpr32(fp32, fs);
6113 gen_helper_float_truncl_s(fp64, fp32);
6114 tcg_temp_free_i32(fp32);
6115 gen_store_fpr64(ctx, fp64, fd);
6116 tcg_temp_free_i64(fp64);
6117 }
6118 opn = "trunc.l.s";
6119 break;
6120 case FOP(10, 16):
6121 check_cp1_64bitmode(ctx);
6122 {
6123 TCGv_i32 fp32 = tcg_temp_new_i32();
6124 TCGv_i64 fp64 = tcg_temp_new_i64();
6125
6126 gen_load_fpr32(fp32, fs);
6127 gen_helper_float_ceill_s(fp64, fp32);
6128 tcg_temp_free_i32(fp32);
6129 gen_store_fpr64(ctx, fp64, fd);
6130 tcg_temp_free_i64(fp64);
6131 }
6132 opn = "ceil.l.s";
6133 break;
6134 case FOP(11, 16):
6135 check_cp1_64bitmode(ctx);
6136 {
6137 TCGv_i32 fp32 = tcg_temp_new_i32();
6138 TCGv_i64 fp64 = tcg_temp_new_i64();
6139
6140 gen_load_fpr32(fp32, fs);
6141 gen_helper_float_floorl_s(fp64, fp32);
6142 tcg_temp_free_i32(fp32);
6143 gen_store_fpr64(ctx, fp64, fd);
6144 tcg_temp_free_i64(fp64);
6145 }
6146 opn = "floor.l.s";
6147 break;
6148 case FOP(12, 16):
6149 {
6150 TCGv_i32 fp0 = tcg_temp_new_i32();
6151
6152 gen_load_fpr32(fp0, fs);
6153 gen_helper_float_roundw_s(fp0, fp0);
6154 gen_store_fpr32(fp0, fd);
6155 tcg_temp_free_i32(fp0);
6156 }
6157 opn = "round.w.s";
6158 break;
6159 case FOP(13, 16):
6160 {
6161 TCGv_i32 fp0 = tcg_temp_new_i32();
6162
6163 gen_load_fpr32(fp0, fs);
6164 gen_helper_float_truncw_s(fp0, fp0);
6165 gen_store_fpr32(fp0, fd);
6166 tcg_temp_free_i32(fp0);
6167 }
6168 opn = "trunc.w.s";
6169 break;
6170 case FOP(14, 16):
6171 {
6172 TCGv_i32 fp0 = tcg_temp_new_i32();
6173
6174 gen_load_fpr32(fp0, fs);
6175 gen_helper_float_ceilw_s(fp0, fp0);
6176 gen_store_fpr32(fp0, fd);
6177 tcg_temp_free_i32(fp0);
6178 }
6179 opn = "ceil.w.s";
6180 break;
6181 case FOP(15, 16):
6182 {
6183 TCGv_i32 fp0 = tcg_temp_new_i32();
6184
6185 gen_load_fpr32(fp0, fs);
6186 gen_helper_float_floorw_s(fp0, fp0);
6187 gen_store_fpr32(fp0, fd);
6188 tcg_temp_free_i32(fp0);
6189 }
6190 opn = "floor.w.s";
6191 break;
6192 case FOP(17, 16):
6193 gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6194 opn = "movcf.s";
6195 break;
6196 case FOP(18, 16):
6197 {
6198 int l1 = gen_new_label();
6199 TCGv_i32 fp0;
6200
6201 if (ft != 0) {
6202 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
6203 }
6204 fp0 = tcg_temp_new_i32();
6205 gen_load_fpr32(fp0, fs);
6206 gen_store_fpr32(fp0, fd);
6207 tcg_temp_free_i32(fp0);
6208 gen_set_label(l1);
6209 }
6210 opn = "movz.s";
6211 break;
6212 case FOP(19, 16):
6213 {
6214 int l1 = gen_new_label();
6215 TCGv_i32 fp0;
6216
6217 if (ft != 0) {
6218 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
6219 fp0 = tcg_temp_new_i32();
6220 gen_load_fpr32(fp0, fs);
6221 gen_store_fpr32(fp0, fd);
6222 tcg_temp_free_i32(fp0);
6223 gen_set_label(l1);
6224 }
6225 }
6226 opn = "movn.s";
6227 break;
6228 case FOP(21, 16):
6229 check_cop1x(ctx);
6230 {
6231 TCGv_i32 fp0 = tcg_temp_new_i32();
6232
6233 gen_load_fpr32(fp0, fs);
6234 gen_helper_float_recip_s(fp0, fp0);
6235 gen_store_fpr32(fp0, fd);
6236 tcg_temp_free_i32(fp0);
6237 }
6238 opn = "recip.s";
6239 break;
6240 case FOP(22, 16):
6241 check_cop1x(ctx);
6242 {
6243 TCGv_i32 fp0 = tcg_temp_new_i32();
6244
6245 gen_load_fpr32(fp0, fs);
6246 gen_helper_float_rsqrt_s(fp0, fp0);
6247 gen_store_fpr32(fp0, fd);
6248 tcg_temp_free_i32(fp0);
6249 }
6250 opn = "rsqrt.s";
6251 break;
6252 case FOP(28, 16):
6253 check_cp1_64bitmode(ctx);
6254 {
6255 TCGv_i32 fp0 = tcg_temp_new_i32();
6256 TCGv_i32 fp1 = tcg_temp_new_i32();
6257
6258 gen_load_fpr32(fp0, fs);
6259 gen_load_fpr32(fp1, fd);
6260 gen_helper_float_recip2_s(fp0, fp0, fp1);
6261 tcg_temp_free_i32(fp1);
6262 gen_store_fpr32(fp0, fd);
6263 tcg_temp_free_i32(fp0);
6264 }
6265 opn = "recip2.s";
6266 break;
6267 case FOP(29, 16):
6268 check_cp1_64bitmode(ctx);
6269 {
6270 TCGv_i32 fp0 = tcg_temp_new_i32();
6271
6272 gen_load_fpr32(fp0, fs);
6273 gen_helper_float_recip1_s(fp0, fp0);
6274 gen_store_fpr32(fp0, fd);
6275 tcg_temp_free_i32(fp0);
6276 }
6277 opn = "recip1.s";
6278 break;
6279 case FOP(30, 16):
6280 check_cp1_64bitmode(ctx);
6281 {
6282 TCGv_i32 fp0 = tcg_temp_new_i32();
6283
6284 gen_load_fpr32(fp0, fs);
6285 gen_helper_float_rsqrt1_s(fp0, fp0);
6286 gen_store_fpr32(fp0, fd);
6287 tcg_temp_free_i32(fp0);
6288 }
6289 opn = "rsqrt1.s";
6290 break;
6291 case FOP(31, 16):
6292 check_cp1_64bitmode(ctx);
6293 {
6294 TCGv_i32 fp0 = tcg_temp_new_i32();
6295 TCGv_i32 fp1 = tcg_temp_new_i32();
6296
6297 gen_load_fpr32(fp0, fs);
6298 gen_load_fpr32(fp1, ft);
6299 gen_helper_float_rsqrt2_s(fp0, fp0, fp1);
6300 tcg_temp_free_i32(fp1);
6301 gen_store_fpr32(fp0, fd);
6302 tcg_temp_free_i32(fp0);
6303 }
6304 opn = "rsqrt2.s";
6305 break;
6306 case FOP(33, 16):
6307 check_cp1_registers(ctx, fd);
6308 {
6309 TCGv_i32 fp32 = tcg_temp_new_i32();
6310 TCGv_i64 fp64 = tcg_temp_new_i64();
6311
6312 gen_load_fpr32(fp32, fs);
6313 gen_helper_float_cvtd_s(fp64, fp32);
6314 tcg_temp_free_i32(fp32);
6315 gen_store_fpr64(ctx, fp64, fd);
6316 tcg_temp_free_i64(fp64);
6317 }
6318 opn = "cvt.d.s";
6319 break;
6320 case FOP(36, 16):
6321 {
6322 TCGv_i32 fp0 = tcg_temp_new_i32();
6323
6324 gen_load_fpr32(fp0, fs);
6325 gen_helper_float_cvtw_s(fp0, fp0);
6326 gen_store_fpr32(fp0, fd);
6327 tcg_temp_free_i32(fp0);
6328 }
6329 opn = "cvt.w.s";
6330 break;
6331 case FOP(37, 16):
6332 check_cp1_64bitmode(ctx);
6333 {
6334 TCGv_i32 fp32 = tcg_temp_new_i32();
6335 TCGv_i64 fp64 = tcg_temp_new_i64();
6336
6337 gen_load_fpr32(fp32, fs);
6338 gen_helper_float_cvtl_s(fp64, fp32);
6339 tcg_temp_free_i32(fp32);
6340 gen_store_fpr64(ctx, fp64, fd);
6341 tcg_temp_free_i64(fp64);
6342 }
6343 opn = "cvt.l.s";
6344 break;
6345 case FOP(38, 16):
6346 check_cp1_64bitmode(ctx);
6347 {
6348 TCGv_i64 fp64 = tcg_temp_new_i64();
6349 TCGv_i32 fp32_0 = tcg_temp_new_i32();
6350 TCGv_i32 fp32_1 = tcg_temp_new_i32();
6351
6352 gen_load_fpr32(fp32_0, fs);
6353 gen_load_fpr32(fp32_1, ft);
6354 tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1);
6355 tcg_temp_free_i32(fp32_1);
6356 tcg_temp_free_i32(fp32_0);
6357 gen_store_fpr64(ctx, fp64, fd);
6358 tcg_temp_free_i64(fp64);
6359 }
6360 opn = "cvt.ps.s";
6361 break;
6362 case FOP(48, 16):
6363 case FOP(49, 16):
6364 case FOP(50, 16):
6365 case FOP(51, 16):
6366 case FOP(52, 16):
6367 case FOP(53, 16):
6368 case FOP(54, 16):
6369 case FOP(55, 16):
6370 case FOP(56, 16):
6371 case FOP(57, 16):
6372 case FOP(58, 16):
6373 case FOP(59, 16):
6374 case FOP(60, 16):
6375 case FOP(61, 16):
6376 case FOP(62, 16):
6377 case FOP(63, 16):
6378 {
6379 TCGv_i32 fp0 = tcg_temp_new_i32();
6380 TCGv_i32 fp1 = tcg_temp_new_i32();
6381
6382 gen_load_fpr32(fp0, fs);
6383 gen_load_fpr32(fp1, ft);
6384 if (ctx->opcode & (1 << 6)) {
6385 check_cop1x(ctx);
6386 gen_cmpabs_s(func-48, fp0, fp1, cc);
6387 opn = condnames_abs[func-48];
6388 } else {
6389 gen_cmp_s(func-48, fp0, fp1, cc);
6390 opn = condnames[func-48];
6391 }
6392 tcg_temp_free_i32(fp0);
6393 tcg_temp_free_i32(fp1);
6394 }
6395 break;
6396 case FOP(0, 17):
6397 check_cp1_registers(ctx, fs | ft | fd);
6398 {
6399 TCGv_i64 fp0 = tcg_temp_new_i64();
6400 TCGv_i64 fp1 = tcg_temp_new_i64();
6401
6402 gen_load_fpr64(ctx, fp0, fs);
6403 gen_load_fpr64(ctx, fp1, ft);
6404 gen_helper_float_add_d(fp0, fp0, fp1);
6405 tcg_temp_free_i64(fp1);
6406 gen_store_fpr64(ctx, fp0, fd);
6407 tcg_temp_free_i64(fp0);
6408 }
6409 opn = "add.d";
6410 optype = BINOP;
6411 break;
6412 case FOP(1, 17):
6413 check_cp1_registers(ctx, fs | ft | fd);
6414 {
6415 TCGv_i64 fp0 = tcg_temp_new_i64();
6416 TCGv_i64 fp1 = tcg_temp_new_i64();
6417
6418 gen_load_fpr64(ctx, fp0, fs);
6419 gen_load_fpr64(ctx, fp1, ft);
6420 gen_helper_float_sub_d(fp0, fp0, fp1);
6421 tcg_temp_free_i64(fp1);
6422 gen_store_fpr64(ctx, fp0, fd);
6423 tcg_temp_free_i64(fp0);
6424 }
6425 opn = "sub.d";
6426 optype = BINOP;
6427 break;
6428 case FOP(2, 17):
6429 check_cp1_registers(ctx, fs | ft | fd);
6430 {
6431 TCGv_i64 fp0 = tcg_temp_new_i64();
6432 TCGv_i64 fp1 = tcg_temp_new_i64();
6433
6434 gen_load_fpr64(ctx, fp0, fs);
6435 gen_load_fpr64(ctx, fp1, ft);
6436 gen_helper_float_mul_d(fp0, fp0, fp1);
6437 tcg_temp_free_i64(fp1);
6438 gen_store_fpr64(ctx, fp0, fd);
6439 tcg_temp_free_i64(fp0);
6440 }
6441 opn = "mul.d";
6442 optype = BINOP;
6443 break;
6444 case FOP(3, 17):
6445 check_cp1_registers(ctx, fs | ft | fd);
6446 {
6447 TCGv_i64 fp0 = tcg_temp_new_i64();
6448 TCGv_i64 fp1 = tcg_temp_new_i64();
6449
6450 gen_load_fpr64(ctx, fp0, fs);
6451 gen_load_fpr64(ctx, fp1, ft);
6452 gen_helper_float_div_d(fp0, fp0, fp1);
6453 tcg_temp_free_i64(fp1);
6454 gen_store_fpr64(ctx, fp0, fd);
6455 tcg_temp_free_i64(fp0);
6456 }
6457 opn = "div.d";
6458 optype = BINOP;
6459 break;
6460 case FOP(4, 17):
6461 check_cp1_registers(ctx, fs | fd);
6462 {
6463 TCGv_i64 fp0 = tcg_temp_new_i64();
6464
6465 gen_load_fpr64(ctx, fp0, fs);
6466 gen_helper_float_sqrt_d(fp0, fp0);
6467 gen_store_fpr64(ctx, fp0, fd);
6468 tcg_temp_free_i64(fp0);
6469 }
6470 opn = "sqrt.d";
6471 break;
6472 case FOP(5, 17):
6473 check_cp1_registers(ctx, fs | fd);
6474 {
6475 TCGv_i64 fp0 = tcg_temp_new_i64();
6476
6477 gen_load_fpr64(ctx, fp0, fs);
6478 gen_helper_float_abs_d(fp0, fp0);
6479 gen_store_fpr64(ctx, fp0, fd);
6480 tcg_temp_free_i64(fp0);
6481 }
6482 opn = "abs.d";
6483 break;
6484 case FOP(6, 17):
6485 check_cp1_registers(ctx, fs | fd);
6486 {
6487 TCGv_i64 fp0 = tcg_temp_new_i64();
6488
6489 gen_load_fpr64(ctx, fp0, fs);
6490 gen_store_fpr64(ctx, fp0, fd);
6491 tcg_temp_free_i64(fp0);
6492 }
6493 opn = "mov.d";
6494 break;
6495 case FOP(7, 17):
6496 check_cp1_registers(ctx, fs | fd);
6497 {
6498 TCGv_i64 fp0 = tcg_temp_new_i64();
6499
6500 gen_load_fpr64(ctx, fp0, fs);
6501 gen_helper_float_chs_d(fp0, fp0);
6502 gen_store_fpr64(ctx, fp0, fd);
6503 tcg_temp_free_i64(fp0);
6504 }
6505 opn = "neg.d";
6506 break;
6507 case FOP(8, 17):
6508 check_cp1_64bitmode(ctx);
6509 {
6510 TCGv_i64 fp0 = tcg_temp_new_i64();
6511
6512 gen_load_fpr64(ctx, fp0, fs);
6513 gen_helper_float_roundl_d(fp0, fp0);
6514 gen_store_fpr64(ctx, fp0, fd);
6515 tcg_temp_free_i64(fp0);
6516 }
6517 opn = "round.l.d";
6518 break;
6519 case FOP(9, 17):
6520 check_cp1_64bitmode(ctx);
6521 {
6522 TCGv_i64 fp0 = tcg_temp_new_i64();
6523
6524 gen_load_fpr64(ctx, fp0, fs);
6525 gen_helper_float_truncl_d(fp0, fp0);
6526 gen_store_fpr64(ctx, fp0, fd);
6527 tcg_temp_free_i64(fp0);
6528 }
6529 opn = "trunc.l.d";
6530 break;
6531 case FOP(10, 17):
6532 check_cp1_64bitmode(ctx);
6533 {
6534 TCGv_i64 fp0 = tcg_temp_new_i64();
6535
6536 gen_load_fpr64(ctx, fp0, fs);
6537 gen_helper_float_ceill_d(fp0, fp0);
6538 gen_store_fpr64(ctx, fp0, fd);
6539 tcg_temp_free_i64(fp0);
6540 }
6541 opn = "ceil.l.d";
6542 break;
6543 case FOP(11, 17):
6544 check_cp1_64bitmode(ctx);
6545 {
6546 TCGv_i64 fp0 = tcg_temp_new_i64();
6547
6548 gen_load_fpr64(ctx, fp0, fs);
6549 gen_helper_float_floorl_d(fp0, fp0);
6550 gen_store_fpr64(ctx, fp0, fd);
6551 tcg_temp_free_i64(fp0);
6552 }
6553 opn = "floor.l.d";
6554 break;
6555 case FOP(12, 17):
6556 check_cp1_registers(ctx, fs);
6557 {
6558 TCGv_i32 fp32 = tcg_temp_new_i32();
6559 TCGv_i64 fp64 = tcg_temp_new_i64();
6560
6561 gen_load_fpr64(ctx, fp64, fs);
6562 gen_helper_float_roundw_d(fp32, fp64);
6563 tcg_temp_free_i64(fp64);
6564 gen_store_fpr32(fp32, fd);
6565 tcg_temp_free_i32(fp32);
6566 }
6567 opn = "round.w.d";
6568 break;
6569 case FOP(13, 17):
6570 check_cp1_registers(ctx, fs);
6571 {
6572 TCGv_i32 fp32 = tcg_temp_new_i32();
6573 TCGv_i64 fp64 = tcg_temp_new_i64();
6574
6575 gen_load_fpr64(ctx, fp64, fs);
6576 gen_helper_float_truncw_d(fp32, fp64);
6577 tcg_temp_free_i64(fp64);
6578 gen_store_fpr32(fp32, fd);
6579 tcg_temp_free_i32(fp32);
6580 }
6581 opn = "trunc.w.d";
6582 break;
6583 case FOP(14, 17):
6584 check_cp1_registers(ctx, fs);
6585 {
6586 TCGv_i32 fp32 = tcg_temp_new_i32();
6587 TCGv_i64 fp64 = tcg_temp_new_i64();
6588
6589 gen_load_fpr64(ctx, fp64, fs);
6590 gen_helper_float_ceilw_d(fp32, fp64);
6591 tcg_temp_free_i64(fp64);
6592 gen_store_fpr32(fp32, fd);
6593 tcg_temp_free_i32(fp32);
6594 }
6595 opn = "ceil.w.d";
6596 break;
6597 case FOP(15, 17):
6598 check_cp1_registers(ctx, fs);
6599 {
6600 TCGv_i32 fp32 = tcg_temp_new_i32();
6601 TCGv_i64 fp64 = tcg_temp_new_i64();
6602
6603 gen_load_fpr64(ctx, fp64, fs);
6604 gen_helper_float_floorw_d(fp32, fp64);
6605 tcg_temp_free_i64(fp64);
6606 gen_store_fpr32(fp32, fd);
6607 tcg_temp_free_i32(fp32);
6608 }
6609 opn = "floor.w.d";
6610 break;
6611 case FOP(17, 17):
6612 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6613 opn = "movcf.d";
6614 break;
6615 case FOP(18, 17):
6616 {
6617 int l1 = gen_new_label();
6618 TCGv_i64 fp0;
6619
6620 if (ft != 0) {
6621 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
6622 }
6623 fp0 = tcg_temp_new_i64();
6624 gen_load_fpr64(ctx, fp0, fs);
6625 gen_store_fpr64(ctx, fp0, fd);
6626 tcg_temp_free_i64(fp0);
6627 gen_set_label(l1);
6628 }
6629 opn = "movz.d";
6630 break;
6631 case FOP(19, 17):
6632 {
6633 int l1 = gen_new_label();
6634 TCGv_i64 fp0;
6635
6636 if (ft != 0) {
6637 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
6638 fp0 = tcg_temp_new_i64();
6639 gen_load_fpr64(ctx, fp0, fs);
6640 gen_store_fpr64(ctx, fp0, fd);
6641 tcg_temp_free_i64(fp0);
6642 gen_set_label(l1);
6643 }
6644 }
6645 opn = "movn.d";
6646 break;
6647 case FOP(21, 17):
6648 check_cp1_64bitmode(ctx);
6649 {
6650 TCGv_i64 fp0 = tcg_temp_new_i64();
6651
6652 gen_load_fpr64(ctx, fp0, fs);
6653 gen_helper_float_recip_d(fp0, fp0);
6654 gen_store_fpr64(ctx, fp0, fd);
6655 tcg_temp_free_i64(fp0);
6656 }
6657 opn = "recip.d";
6658 break;
6659 case FOP(22, 17):
6660 check_cp1_64bitmode(ctx);
6661 {
6662 TCGv_i64 fp0 = tcg_temp_new_i64();
6663
6664 gen_load_fpr64(ctx, fp0, fs);
6665 gen_helper_float_rsqrt_d(fp0, fp0);
6666 gen_store_fpr64(ctx, fp0, fd);
6667 tcg_temp_free_i64(fp0);
6668 }
6669 opn = "rsqrt.d";
6670 break;
6671 case FOP(28, 17):
6672 check_cp1_64bitmode(ctx);
6673 {
6674 TCGv_i64 fp0 = tcg_temp_new_i64();
6675 TCGv_i64 fp1 = tcg_temp_new_i64();
6676
6677 gen_load_fpr64(ctx, fp0, fs);
6678 gen_load_fpr64(ctx, fp1, ft);
6679 gen_helper_float_recip2_d(fp0, fp0, fp1);
6680 tcg_temp_free_i64(fp1);
6681 gen_store_fpr64(ctx, fp0, fd);
6682 tcg_temp_free_i64(fp0);
6683 }
6684 opn = "recip2.d";
6685 break;
6686 case FOP(29, 17):
6687 check_cp1_64bitmode(ctx);
6688 {
6689 TCGv_i64 fp0 = tcg_temp_new_i64();
6690
6691 gen_load_fpr64(ctx, fp0, fs);
6692 gen_helper_float_recip1_d(fp0, fp0);
6693 gen_store_fpr64(ctx, fp0, fd);
6694 tcg_temp_free_i64(fp0);
6695 }
6696 opn = "recip1.d";
6697 break;
6698 case FOP(30, 17):
6699 check_cp1_64bitmode(ctx);
6700 {
6701 TCGv_i64 fp0 = tcg_temp_new_i64();
6702
6703 gen_load_fpr64(ctx, fp0, fs);
6704 gen_helper_float_rsqrt1_d(fp0, fp0);
6705 gen_store_fpr64(ctx, fp0, fd);
6706 tcg_temp_free_i64(fp0);
6707 }
6708 opn = "rsqrt1.d";
6709 break;
6710 case FOP(31, 17):
6711 check_cp1_64bitmode(ctx);
6712 {
6713 TCGv_i64 fp0 = tcg_temp_new_i64();
6714 TCGv_i64 fp1 = tcg_temp_new_i64();
6715
6716 gen_load_fpr64(ctx, fp0, fs);
6717 gen_load_fpr64(ctx, fp1, ft);
6718 gen_helper_float_rsqrt2_d(fp0, fp0, fp1);
6719 tcg_temp_free_i64(fp1);
6720 gen_store_fpr64(ctx, fp0, fd);
6721 tcg_temp_free_i64(fp0);
6722 }
6723 opn = "rsqrt2.d";
6724 break;
6725 case FOP(48, 17):
6726 case FOP(49, 17):
6727 case FOP(50, 17):
6728 case FOP(51, 17):
6729 case FOP(52, 17):
6730 case FOP(53, 17):
6731 case FOP(54, 17):
6732 case FOP(55, 17):
6733 case FOP(56, 17):
6734 case FOP(57, 17):
6735 case FOP(58, 17):
6736 case FOP(59, 17):
6737 case FOP(60, 17):
6738 case FOP(61, 17):
6739 case FOP(62, 17):
6740 case FOP(63, 17):
6741 {
6742 TCGv_i64 fp0 = tcg_temp_new_i64();
6743 TCGv_i64 fp1 = tcg_temp_new_i64();
6744
6745 gen_load_fpr64(ctx, fp0, fs);
6746 gen_load_fpr64(ctx, fp1, ft);
6747 if (ctx->opcode & (1 << 6)) {
6748 check_cop1x(ctx);
6749 check_cp1_registers(ctx, fs | ft);
6750 gen_cmpabs_d(func-48, fp0, fp1, cc);
6751 opn = condnames_abs[func-48];
6752 } else {
6753 check_cp1_registers(ctx, fs | ft);
6754 gen_cmp_d(func-48, fp0, fp1, cc);
6755 opn = condnames[func-48];
6756 }
6757 tcg_temp_free_i64(fp0);
6758 tcg_temp_free_i64(fp1);
6759 }
6760 break;
6761 case FOP(32, 17):
6762 check_cp1_registers(ctx, fs);
6763 {
6764 TCGv_i32 fp32 = tcg_temp_new_i32();
6765 TCGv_i64 fp64 = tcg_temp_new_i64();
6766
6767 gen_load_fpr64(ctx, fp64, fs);
6768 gen_helper_float_cvts_d(fp32, fp64);
6769 tcg_temp_free_i64(fp64);
6770 gen_store_fpr32(fp32, fd);
6771 tcg_temp_free_i32(fp32);
6772 }
6773 opn = "cvt.s.d";
6774 break;
6775 case FOP(36, 17):
6776 check_cp1_registers(ctx, fs);
6777 {
6778 TCGv_i32 fp32 = tcg_temp_new_i32();
6779 TCGv_i64 fp64 = tcg_temp_new_i64();
6780
6781 gen_load_fpr64(ctx, fp64, fs);
6782 gen_helper_float_cvtw_d(fp32, fp64);
6783 tcg_temp_free_i64(fp64);
6784 gen_store_fpr32(fp32, fd);
6785 tcg_temp_free_i32(fp32);
6786 }
6787 opn = "cvt.w.d";
6788 break;
6789 case FOP(37, 17):
6790 check_cp1_64bitmode(ctx);
6791 {
6792 TCGv_i64 fp0 = tcg_temp_new_i64();
6793
6794 gen_load_fpr64(ctx, fp0, fs);
6795 gen_helper_float_cvtl_d(fp0, fp0);
6796 gen_store_fpr64(ctx, fp0, fd);
6797 tcg_temp_free_i64(fp0);
6798 }
6799 opn = "cvt.l.d";
6800 break;
6801 case FOP(32, 20):
6802 {
6803 TCGv_i32 fp0 = tcg_temp_new_i32();
6804
6805 gen_load_fpr32(fp0, fs);
6806 gen_helper_float_cvts_w(fp0, fp0);
6807 gen_store_fpr32(fp0, fd);
6808 tcg_temp_free_i32(fp0);
6809 }
6810 opn = "cvt.s.w";
6811 break;
6812 case FOP(33, 20):
6813 check_cp1_registers(ctx, fd);
6814 {
6815 TCGv_i32 fp32 = tcg_temp_new_i32();
6816 TCGv_i64 fp64 = tcg_temp_new_i64();
6817
6818 gen_load_fpr32(fp32, fs);
6819 gen_helper_float_cvtd_w(fp64, fp32);
6820 tcg_temp_free_i32(fp32);
6821 gen_store_fpr64(ctx, fp64, fd);
6822 tcg_temp_free_i64(fp64);
6823 }
6824 opn = "cvt.d.w";
6825 break;
6826 case FOP(32, 21):
6827 check_cp1_64bitmode(ctx);
6828 {
6829 TCGv_i32 fp32 = tcg_temp_new_i32();
6830 TCGv_i64 fp64 = tcg_temp_new_i64();
6831
6832 gen_load_fpr64(ctx, fp64, fs);
6833 gen_helper_float_cvts_l(fp32, fp64);
6834 tcg_temp_free_i64(fp64);
6835 gen_store_fpr32(fp32, fd);
6836 tcg_temp_free_i32(fp32);
6837 }
6838 opn = "cvt.s.l";
6839 break;
6840 case FOP(33, 21):
6841 check_cp1_64bitmode(ctx);
6842 {
6843 TCGv_i64 fp0 = tcg_temp_new_i64();
6844
6845 gen_load_fpr64(ctx, fp0, fs);
6846 gen_helper_float_cvtd_l(fp0, fp0);
6847 gen_store_fpr64(ctx, fp0, fd);
6848 tcg_temp_free_i64(fp0);
6849 }
6850 opn = "cvt.d.l";
6851 break;
6852 case FOP(38, 20):
6853 check_cp1_64bitmode(ctx);
6854 {
6855 TCGv_i64 fp0 = tcg_temp_new_i64();
6856
6857 gen_load_fpr64(ctx, fp0, fs);
6858 gen_helper_float_cvtps_pw(fp0, fp0);
6859 gen_store_fpr64(ctx, fp0, fd);
6860 tcg_temp_free_i64(fp0);
6861 }
6862 opn = "cvt.ps.pw";
6863 break;
6864 case FOP(0, 22):
6865 check_cp1_64bitmode(ctx);
6866 {
6867 TCGv_i64 fp0 = tcg_temp_new_i64();
6868 TCGv_i64 fp1 = tcg_temp_new_i64();
6869
6870 gen_load_fpr64(ctx, fp0, fs);
6871 gen_load_fpr64(ctx, fp1, ft);
6872 gen_helper_float_add_ps(fp0, fp0, fp1);
6873 tcg_temp_free_i64(fp1);
6874 gen_store_fpr64(ctx, fp0, fd);
6875 tcg_temp_free_i64(fp0);
6876 }
6877 opn = "add.ps";
6878 break;
6879 case FOP(1, 22):
6880 check_cp1_64bitmode(ctx);
6881 {
6882 TCGv_i64 fp0 = tcg_temp_new_i64();
6883 TCGv_i64 fp1 = tcg_temp_new_i64();
6884
6885 gen_load_fpr64(ctx, fp0, fs);
6886 gen_load_fpr64(ctx, fp1, ft);
6887 gen_helper_float_sub_ps(fp0, fp0, fp1);
6888 tcg_temp_free_i64(fp1);
6889 gen_store_fpr64(ctx, fp0, fd);
6890 tcg_temp_free_i64(fp0);
6891 }
6892 opn = "sub.ps";
6893 break;
6894 case FOP(2, 22):
6895 check_cp1_64bitmode(ctx);
6896 {
6897 TCGv_i64 fp0 = tcg_temp_new_i64();
6898 TCGv_i64 fp1 = tcg_temp_new_i64();
6899
6900 gen_load_fpr64(ctx, fp0, fs);
6901 gen_load_fpr64(ctx, fp1, ft);
6902 gen_helper_float_mul_ps(fp0, fp0, fp1);
6903 tcg_temp_free_i64(fp1);
6904 gen_store_fpr64(ctx, fp0, fd);
6905 tcg_temp_free_i64(fp0);
6906 }
6907 opn = "mul.ps";
6908 break;
6909 case FOP(5, 22):
6910 check_cp1_64bitmode(ctx);
6911 {
6912 TCGv_i64 fp0 = tcg_temp_new_i64();
6913
6914 gen_load_fpr64(ctx, fp0, fs);
6915 gen_helper_float_abs_ps(fp0, fp0);
6916 gen_store_fpr64(ctx, fp0, fd);
6917 tcg_temp_free_i64(fp0);
6918 }
6919 opn = "abs.ps";
6920 break;
6921 case FOP(6, 22):
6922 check_cp1_64bitmode(ctx);
6923 {
6924 TCGv_i64 fp0 = tcg_temp_new_i64();
6925
6926 gen_load_fpr64(ctx, fp0, fs);
6927 gen_store_fpr64(ctx, fp0, fd);
6928 tcg_temp_free_i64(fp0);
6929 }
6930 opn = "mov.ps";
6931 break;
6932 case FOP(7, 22):
6933 check_cp1_64bitmode(ctx);
6934 {
6935 TCGv_i64 fp0 = tcg_temp_new_i64();
6936
6937 gen_load_fpr64(ctx, fp0, fs);
6938 gen_helper_float_chs_ps(fp0, fp0);
6939 gen_store_fpr64(ctx, fp0, fd);
6940 tcg_temp_free_i64(fp0);
6941 }
6942 opn = "neg.ps";
6943 break;
6944 case FOP(17, 22):
6945 check_cp1_64bitmode(ctx);
6946 gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6947 opn = "movcf.ps";
6948 break;
6949 case FOP(18, 22):
6950 check_cp1_64bitmode(ctx);
6951 {
6952 int l1 = gen_new_label();
6953 TCGv_i64 fp0;
6954
6955 if (ft != 0)
6956 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
6957 fp0 = tcg_temp_new_i64();
6958 gen_load_fpr64(ctx, fp0, fs);
6959 gen_store_fpr64(ctx, fp0, fd);
6960 tcg_temp_free_i64(fp0);
6961 gen_set_label(l1);
6962 }
6963 opn = "movz.ps";
6964 break;
6965 case FOP(19, 22):
6966 check_cp1_64bitmode(ctx);
6967 {
6968 int l1 = gen_new_label();
6969 TCGv_i64 fp0;
6970
6971 if (ft != 0) {
6972 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
6973 fp0 = tcg_temp_new_i64();
6974 gen_load_fpr64(ctx, fp0, fs);
6975 gen_store_fpr64(ctx, fp0, fd);
6976 tcg_temp_free_i64(fp0);
6977 gen_set_label(l1);
6978 }
6979 }
6980 opn = "movn.ps";
6981 break;
6982 case FOP(24, 22):
6983 check_cp1_64bitmode(ctx);
6984 {
6985 TCGv_i64 fp0 = tcg_temp_new_i64();
6986 TCGv_i64 fp1 = tcg_temp_new_i64();
6987
6988 gen_load_fpr64(ctx, fp0, ft);
6989 gen_load_fpr64(ctx, fp1, fs);
6990 gen_helper_float_addr_ps(fp0, fp0, fp1);
6991 tcg_temp_free_i64(fp1);
6992 gen_store_fpr64(ctx, fp0, fd);
6993 tcg_temp_free_i64(fp0);
6994 }
6995 opn = "addr.ps";
6996 break;
6997 case FOP(26, 22):
6998 check_cp1_64bitmode(ctx);
6999 {
7000 TCGv_i64 fp0 = tcg_temp_new_i64();
7001 TCGv_i64 fp1 = tcg_temp_new_i64();
7002
7003 gen_load_fpr64(ctx, fp0, ft);
7004 gen_load_fpr64(ctx, fp1, fs);
7005 gen_helper_float_mulr_ps(fp0, fp0, fp1);
7006 tcg_temp_free_i64(fp1);
7007 gen_store_fpr64(ctx, fp0, fd);
7008 tcg_temp_free_i64(fp0);
7009 }
7010 opn = "mulr.ps";
7011 break;
7012 case FOP(28, 22):
7013 check_cp1_64bitmode(ctx);
7014 {
7015 TCGv_i64 fp0 = tcg_temp_new_i64();
7016 TCGv_i64 fp1 = tcg_temp_new_i64();
7017
7018 gen_load_fpr64(ctx, fp0, fs);
7019 gen_load_fpr64(ctx, fp1, fd);
7020 gen_helper_float_recip2_ps(fp0, fp0, fp1);
7021 tcg_temp_free_i64(fp1);
7022 gen_store_fpr64(ctx, fp0, fd);
7023 tcg_temp_free_i64(fp0);
7024 }
7025 opn = "recip2.ps";
7026 break;
7027 case FOP(29, 22):
7028 check_cp1_64bitmode(ctx);
7029 {
7030 TCGv_i64 fp0 = tcg_temp_new_i64();
7031
7032 gen_load_fpr64(ctx, fp0, fs);
7033 gen_helper_float_recip1_ps(fp0, fp0);
7034 gen_store_fpr64(ctx, fp0, fd);
7035 tcg_temp_free_i64(fp0);
7036 }
7037 opn = "recip1.ps";
7038 break;
7039 case FOP(30, 22):
7040 check_cp1_64bitmode(ctx);
7041 {
7042 TCGv_i64 fp0 = tcg_temp_new_i64();
7043
7044 gen_load_fpr64(ctx, fp0, fs);
7045 gen_helper_float_rsqrt1_ps(fp0, fp0);
7046 gen_store_fpr64(ctx, fp0, fd);
7047 tcg_temp_free_i64(fp0);
7048 }
7049 opn = "rsqrt1.ps";
7050 break;
7051 case FOP(31, 22):
7052 check_cp1_64bitmode(ctx);
7053 {
7054 TCGv_i64 fp0 = tcg_temp_new_i64();
7055 TCGv_i64 fp1 = tcg_temp_new_i64();
7056
7057 gen_load_fpr64(ctx, fp0, fs);
7058 gen_load_fpr64(ctx, fp1, ft);
7059 gen_helper_float_rsqrt2_ps(fp0, fp0, fp1);
7060 tcg_temp_free_i64(fp1);
7061 gen_store_fpr64(ctx, fp0, fd);
7062 tcg_temp_free_i64(fp0);
7063 }
7064 opn = "rsqrt2.ps";
7065 break;
7066 case FOP(32, 22):
7067 check_cp1_64bitmode(ctx);
7068 {
7069 TCGv_i32 fp0 = tcg_temp_new_i32();
7070
7071 gen_load_fpr32h(fp0, fs);
7072 gen_helper_float_cvts_pu(fp0, fp0);
7073 gen_store_fpr32(fp0, fd);
7074 tcg_temp_free_i32(fp0);
7075 }
7076 opn = "cvt.s.pu";
7077 break;
7078 case FOP(36, 22):
7079 check_cp1_64bitmode(ctx);
7080 {
7081 TCGv_i64 fp0 = tcg_temp_new_i64();
7082
7083 gen_load_fpr64(ctx, fp0, fs);
7084 gen_helper_float_cvtpw_ps(fp0, fp0);
7085 gen_store_fpr64(ctx, fp0, fd);
7086 tcg_temp_free_i64(fp0);
7087 }
7088 opn = "cvt.pw.ps";
7089 break;
7090 case FOP(40, 22):
7091 check_cp1_64bitmode(ctx);
7092 {
7093 TCGv_i32 fp0 = tcg_temp_new_i32();
7094
7095 gen_load_fpr32(fp0, fs);
7096 gen_helper_float_cvts_pl(fp0, fp0);
7097 gen_store_fpr32(fp0, fd);
7098 tcg_temp_free_i32(fp0);
7099 }
7100 opn = "cvt.s.pl";
7101 break;
7102 case FOP(44, 22):
7103 check_cp1_64bitmode(ctx);
7104 {
7105 TCGv_i32 fp0 = tcg_temp_new_i32();
7106 TCGv_i32 fp1 = tcg_temp_new_i32();
7107
7108 gen_load_fpr32(fp0, fs);
7109 gen_load_fpr32(fp1, ft);
7110 gen_store_fpr32h(fp0, fd);
7111 gen_store_fpr32(fp1, fd);
7112 tcg_temp_free_i32(fp0);
7113 tcg_temp_free_i32(fp1);
7114 }
7115 opn = "pll.ps";
7116 break;
7117 case FOP(45, 22):
7118 check_cp1_64bitmode(ctx);
7119 {
7120 TCGv_i32 fp0 = tcg_temp_new_i32();
7121 TCGv_i32 fp1 = tcg_temp_new_i32();
7122
7123 gen_load_fpr32(fp0, fs);
7124 gen_load_fpr32h(fp1, ft);
7125 gen_store_fpr32(fp1, fd);
7126 gen_store_fpr32h(fp0, fd);
7127 tcg_temp_free_i32(fp0);
7128 tcg_temp_free_i32(fp1);
7129 }
7130 opn = "plu.ps";
7131 break;
7132 case FOP(46, 22):
7133 check_cp1_64bitmode(ctx);
7134 {
7135 TCGv_i32 fp0 = tcg_temp_new_i32();
7136 TCGv_i32 fp1 = tcg_temp_new_i32();
7137
7138 gen_load_fpr32h(fp0, fs);
7139 gen_load_fpr32(fp1, ft);
7140 gen_store_fpr32(fp1, fd);
7141 gen_store_fpr32h(fp0, fd);
7142 tcg_temp_free_i32(fp0);
7143 tcg_temp_free_i32(fp1);
7144 }
7145 opn = "pul.ps";
7146 break;
7147 case FOP(47, 22):
7148 check_cp1_64bitmode(ctx);
7149 {
7150 TCGv_i32 fp0 = tcg_temp_new_i32();
7151 TCGv_i32 fp1 = tcg_temp_new_i32();
7152
7153 gen_load_fpr32h(fp0, fs);
7154 gen_load_fpr32h(fp1, ft);
7155 gen_store_fpr32(fp1, fd);
7156 gen_store_fpr32h(fp0, fd);
7157 tcg_temp_free_i32(fp0);
7158 tcg_temp_free_i32(fp1);
7159 }
7160 opn = "puu.ps";
7161 break;
7162 case FOP(48, 22):
7163 case FOP(49, 22):
7164 case FOP(50, 22):
7165 case FOP(51, 22):
7166 case FOP(52, 22):
7167 case FOP(53, 22):
7168 case FOP(54, 22):
7169 case FOP(55, 22):
7170 case FOP(56, 22):
7171 case FOP(57, 22):
7172 case FOP(58, 22):
7173 case FOP(59, 22):
7174 case FOP(60, 22):
7175 case FOP(61, 22):
7176 case FOP(62, 22):
7177 case FOP(63, 22):
7178 check_cp1_64bitmode(ctx);
7179 {
7180 TCGv_i64 fp0 = tcg_temp_new_i64();
7181 TCGv_i64 fp1 = tcg_temp_new_i64();
7182
7183 gen_load_fpr64(ctx, fp0, fs);
7184 gen_load_fpr64(ctx, fp1, ft);
7185 if (ctx->opcode & (1 << 6)) {
7186 gen_cmpabs_ps(func-48, fp0, fp1, cc);
7187 opn = condnames_abs[func-48];
7188 } else {
7189 gen_cmp_ps(func-48, fp0, fp1, cc);
7190 opn = condnames[func-48];
7191 }
7192 tcg_temp_free_i64(fp0);
7193 tcg_temp_free_i64(fp1);
7194 }
7195 break;
7196 default:
7197 MIPS_INVAL(opn);
7198 generate_exception (ctx, EXCP_RI);
7199 return;
7200 }
7201 switch (optype) {
7202 case BINOP:
7203 MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
7204 break;
7205 case CMPOP:
7206 MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]);
7207 break;
7208 default:
7209 MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
7210 break;
7211 }
7212 }
7213
7214 /* Coprocessor 3 (FPU) */
7215 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7216 int fd, int fs, int base, int index)
7217 {
7218 const char *opn = "extended float load/store";
7219 int store = 0;
7220 TCGv t0 = tcg_temp_new();
7221
7222 if (base == 0) {
7223 gen_load_gpr(t0, index);
7224 } else if (index == 0) {
7225 gen_load_gpr(t0, base);
7226 } else {
7227 gen_load_gpr(t0, index);
7228 gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
7229 }
7230 /* Don't do NOP if destination is zero: we must perform the actual
7231 memory access. */
7232 save_cpu_state(ctx, 0);
7233 switch (opc) {
7234 case OPC_LWXC1:
7235 check_cop1x(ctx);
7236 {
7237 TCGv_i32 fp0 = tcg_temp_new_i32();
7238
7239 tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
7240 tcg_gen_trunc_tl_i32(fp0, t0);
7241 gen_store_fpr32(fp0, fd);
7242 tcg_temp_free_i32(fp0);
7243 }
7244 opn = "lwxc1";
7245 break;
7246 case OPC_LDXC1:
7247 check_cop1x(ctx);
7248 check_cp1_registers(ctx, fd);
7249 {
7250 TCGv_i64 fp0 = tcg_temp_new_i64();
7251
7252 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
7253 gen_store_fpr64(ctx, fp0, fd);
7254 tcg_temp_free_i64(fp0);
7255 }
7256 opn = "ldxc1";
7257 break;
7258 case OPC_LUXC1:
7259 check_cp1_64bitmode(ctx);
7260 tcg_gen_andi_tl(t0, t0, ~0x7);
7261 {
7262 TCGv_i64 fp0 = tcg_temp_new_i64();
7263
7264 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
7265 gen_store_fpr64(ctx, fp0, fd);
7266 tcg_temp_free_i64(fp0);
7267 }
7268 opn = "luxc1";
7269 break;
7270 case OPC_SWXC1:
7271 check_cop1x(ctx);
7272 {
7273 TCGv_i32 fp0 = tcg_temp_new_i32();
7274 TCGv t1 = tcg_temp_new();
7275
7276 gen_load_fpr32(fp0, fs);
7277 tcg_gen_extu_i32_tl(t1, fp0);
7278 tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
7279 tcg_temp_free_i32(fp0);
7280 tcg_temp_free(t1);
7281 }
7282 opn = "swxc1";
7283 store = 1;
7284 break;
7285 case OPC_SDXC1:
7286 check_cop1x(ctx);
7287 check_cp1_registers(ctx, fs);
7288 {
7289 TCGv_i64 fp0 = tcg_temp_new_i64();
7290
7291 gen_load_fpr64(ctx, fp0, fs);
7292 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
7293 tcg_temp_free_i64(fp0);
7294 }
7295 opn = "sdxc1";
7296 store = 1;
7297 break;
7298 case OPC_SUXC1:
7299 check_cp1_64bitmode(ctx);
7300 tcg_gen_andi_tl(t0, t0, ~0x7);
7301 {
7302 TCGv_i64 fp0 = tcg_temp_new_i64();
7303
7304 gen_load_fpr64(ctx, fp0, fs);
7305 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
7306 tcg_temp_free_i64(fp0);
7307 }
7308 opn = "suxc1";
7309 store = 1;
7310 break;
7311 }
7312 tcg_temp_free(t0);
7313 MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
7314 regnames[index], regnames[base]);
7315 }
7316
7317 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
7318 int fd, int fr, int fs, int ft)
7319 {
7320 const char *opn = "flt3_arith";
7321
7322 switch (opc) {
7323 case OPC_ALNV_PS:
7324 check_cp1_64bitmode(ctx);
7325 {
7326 TCGv t0 = tcg_temp_local_new();
7327 TCGv_i32 fp = tcg_temp_new_i32();
7328 TCGv_i32 fph = tcg_temp_new_i32();
7329 int l1 = gen_new_label();
7330 int l2 = gen_new_label();
7331
7332 gen_load_gpr(t0, fr);
7333 tcg_gen_andi_tl(t0, t0, 0x7);
7334
7335 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
7336 gen_load_fpr32(fp, fs);
7337 gen_load_fpr32h(fph, fs);
7338 gen_store_fpr32(fp, fd);
7339 gen_store_fpr32h(fph, fd);
7340 tcg_gen_br(l2);
7341 gen_set_label(l1);
7342 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
7343 tcg_temp_free(t0);
7344 #ifdef TARGET_WORDS_BIGENDIAN
7345 gen_load_fpr32(fp, fs);
7346 gen_load_fpr32h(fph, ft);
7347 gen_store_fpr32h(fp, fd);
7348 gen_store_fpr32(fph, fd);
7349 #else
7350 gen_load_fpr32h(fph, fs);
7351 gen_load_fpr32(fp, ft);
7352 gen_store_fpr32(fph, fd);
7353 gen_store_fpr32h(fp, fd);
7354 #endif
7355 gen_set_label(l2);
7356 tcg_temp_free_i32(fp);
7357 tcg_temp_free_i32(fph);
7358 }
7359 opn = "alnv.ps";
7360 break;
7361 case OPC_MADD_S:
7362 check_cop1x(ctx);
7363 {
7364 TCGv_i32 fp0 = tcg_temp_new_i32();
7365 TCGv_i32 fp1 = tcg_temp_new_i32();
7366 TCGv_i32 fp2 = tcg_temp_new_i32();
7367
7368 gen_load_fpr32(fp0, fs);
7369 gen_load_fpr32(fp1, ft);
7370 gen_load_fpr32(fp2, fr);
7371 gen_helper_float_muladd_s(fp2, fp0, fp1, fp2);
7372 tcg_temp_free_i32(fp0);
7373 tcg_temp_free_i32(fp1);
7374 gen_store_fpr32(fp2, fd);
7375 tcg_temp_free_i32(fp2);
7376 }
7377 opn = "madd.s";
7378 break;
7379 case OPC_MADD_D:
7380 check_cop1x(ctx);
7381 check_cp1_registers(ctx, fd | fs | ft | fr);
7382 {
7383 TCGv_i64 fp0 = tcg_temp_new_i64();
7384 TCGv_i64 fp1 = tcg_temp_new_i64();
7385 TCGv_i64 fp2 = tcg_temp_new_i64();
7386
7387 gen_load_fpr64(ctx, fp0, fs);
7388 gen_load_fpr64(ctx, fp1, ft);
7389 gen_load_fpr64(ctx, fp2, fr);
7390 gen_helper_float_muladd_d(fp2, fp0, fp1, fp2);
7391 tcg_temp_free_i64(fp0);
7392 tcg_temp_free_i64(fp1);
7393 gen_store_fpr64(ctx, fp2, fd);
7394 tcg_temp_free_i64(fp2);
7395 }
7396 opn = "madd.d";
7397 break;
7398 case OPC_MADD_PS:
7399 check_cp1_64bitmode(ctx);
7400 {
7401 TCGv_i64 fp0 = tcg_temp_new_i64();
7402 TCGv_i64 fp1 = tcg_temp_new_i64();
7403 TCGv_i64 fp2 = tcg_temp_new_i64();
7404
7405 gen_load_fpr64(ctx, fp0, fs);
7406 gen_load_fpr64(ctx, fp1, ft);
7407 gen_load_fpr64(ctx, fp2, fr);
7408 gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2);
7409 tcg_temp_free_i64(fp0);
7410 tcg_temp_free_i64(fp1);
7411 gen_store_fpr64(ctx, fp2, fd);
7412 tcg_temp_free_i64(fp2);
7413 }
7414 opn = "madd.ps";
7415 break;
7416 case OPC_MSUB_S:
7417 check_cop1x(ctx);
7418 {
7419 TCGv_i32 fp0 = tcg_temp_new_i32();
7420 TCGv_i32 fp1 = tcg_temp_new_i32();
7421 TCGv_i32 fp2 = tcg_temp_new_i32();
7422
7423 gen_load_fpr32(fp0, fs);
7424 gen_load_fpr32(fp1, ft);
7425 gen_load_fpr32(fp2, fr);
7426 gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2);
7427 tcg_temp_free_i32(fp0);
7428 tcg_temp_free_i32(fp1);
7429 gen_store_fpr32(fp2, fd);
7430 tcg_temp_free_i32(fp2);
7431 }
7432 opn = "msub.s";
7433 break;
7434 case OPC_MSUB_D:
7435 check_cop1x(ctx);
7436 check_cp1_registers(ctx, fd | fs | ft | fr);
7437 {
7438 TCGv_i64 fp0 = tcg_temp_new_i64();
7439 TCGv_i64 fp1 = tcg_temp_new_i64();
7440 TCGv_i64 fp2 = tcg_temp_new_i64();
7441
7442 gen_load_fpr64(ctx, fp0, fs);
7443 gen_load_fpr64(ctx, fp1, ft);
7444 gen_load_fpr64(ctx, fp2, fr);
7445 gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2);
7446 tcg_temp_free_i64(fp0);
7447 tcg_temp_free_i64(fp1);
7448 gen_store_fpr64(ctx, fp2, fd);
7449 tcg_temp_free_i64(fp2);
7450 }
7451 opn = "msub.d";
7452 break;
7453 case OPC_MSUB_PS:
7454 check_cp1_64bitmode(ctx);
7455 {
7456 TCGv_i64 fp0 = tcg_temp_new_i64();
7457 TCGv_i64 fp1 = tcg_temp_new_i64();
7458 TCGv_i64 fp2 = tcg_temp_new_i64();
7459
7460 gen_load_fpr64(ctx, fp0, fs);
7461 gen_load_fpr64(ctx, fp1, ft);
7462 gen_load_fpr64(ctx, fp2, fr);
7463 gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2);
7464 tcg_temp_free_i64(fp0);
7465 tcg_temp_free_i64(fp1);
7466 gen_store_fpr64(ctx, fp2, fd);
7467 tcg_temp_free_i64(fp2);
7468 }
7469 opn = "msub.ps";
7470 break;
7471 case OPC_NMADD_S:
7472 check_cop1x(ctx);
7473 {
7474 TCGv_i32 fp0 = tcg_temp_new_i32();
7475 TCGv_i32 fp1 = tcg_temp_new_i32();
7476 TCGv_i32 fp2 = tcg_temp_new_i32();
7477
7478 gen_load_fpr32(fp0, fs);
7479 gen_load_fpr32(fp1, ft);
7480 gen_load_fpr32(fp2, fr);
7481 gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2);
7482 tcg_temp_free_i32(fp0);
7483 tcg_temp_free_i32(fp1);
7484 gen_store_fpr32(fp2, fd);
7485 tcg_temp_free_i32(fp2);
7486 }
7487 opn = "nmadd.s";
7488 break;
7489 case OPC_NMADD_D:
7490 check_cop1x(ctx);
7491 check_cp1_registers(ctx, fd | fs | ft | fr);
7492 {
7493 TCGv_i64 fp0 = tcg_temp_new_i64();
7494 TCGv_i64 fp1 = tcg_temp_new_i64();
7495 TCGv_i64 fp2 = tcg_temp_new_i64();
7496
7497 gen_load_fpr64(ctx, fp0, fs);
7498 gen_load_fpr64(ctx, fp1, ft);
7499 gen_load_fpr64(ctx, fp2, fr);
7500 gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2);
7501 tcg_temp_free_i64(fp0);
7502 tcg_temp_free_i64(fp1);
7503 gen_store_fpr64(ctx, fp2, fd);
7504 tcg_temp_free_i64(fp2);
7505 }
7506 opn = "nmadd.d";
7507 break;
7508 case OPC_NMADD_PS:
7509 check_cp1_64bitmode(ctx);
7510 {
7511 TCGv_i64 fp0 = tcg_temp_new_i64();
7512 TCGv_i64 fp1 = tcg_temp_new_i64();
7513 TCGv_i64 fp2 = tcg_temp_new_i64();
7514
7515 gen_load_fpr64(ctx, fp0, fs);
7516 gen_load_fpr64(ctx, fp1, ft);
7517 gen_load_fpr64(ctx, fp2, fr);
7518 gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2);
7519 tcg_temp_free_i64(fp0);
7520 tcg_temp_free_i64(fp1);
7521 gen_store_fpr64(ctx, fp2, fd);
7522 tcg_temp_free_i64(fp2);
7523 }
7524 opn = "nmadd.ps";
7525 break;
7526 case OPC_NMSUB_S:
7527 check_cop1x(ctx);
7528 {
7529 TCGv_i32 fp0 = tcg_temp_new_i32();
7530 TCGv_i32 fp1 = tcg_temp_new_i32();
7531 TCGv_i32 fp2 = tcg_temp_new_i32();
7532
7533 gen_load_fpr32(fp0, fs);
7534 gen_load_fpr32(fp1, ft);
7535 gen_load_fpr32(fp2, fr);
7536 gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2);
7537 tcg_temp_free_i32(fp0);
7538 tcg_temp_free_i32(fp1);
7539 gen_store_fpr32(fp2, fd);
7540 tcg_temp_free_i32(fp2);
7541 }
7542 opn = "nmsub.s";
7543 break;
7544 case OPC_NMSUB_D:
7545 check_cop1x(ctx);
7546 check_cp1_registers(ctx, fd | fs | ft | fr);
7547 {
7548 TCGv_i64 fp0 = tcg_temp_new_i64();
7549 TCGv_i64 fp1 = tcg_temp_new_i64();
7550 TCGv_i64 fp2 = tcg_temp_new_i64();
7551
7552 gen_load_fpr64(ctx, fp0, fs);
7553 gen_load_fpr64(ctx, fp1, ft);
7554 gen_load_fpr64(ctx, fp2, fr);
7555 gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2);
7556 tcg_temp_free_i64(fp0);
7557 tcg_temp_free_i64(fp1);
7558 gen_store_fpr64(ctx, fp2, fd);
7559 tcg_temp_free_i64(fp2);
7560 }
7561 opn = "nmsub.d";
7562 break;
7563 case OPC_NMSUB_PS:
7564 check_cp1_64bitmode(ctx);
7565 {
7566 TCGv_i64 fp0 = tcg_temp_new_i64();
7567 TCGv_i64 fp1 = tcg_temp_new_i64();
7568 TCGv_i64 fp2 = tcg_temp_new_i64();
7569
7570 gen_load_fpr64(ctx, fp0, fs);
7571 gen_load_fpr64(ctx, fp1, ft);
7572 gen_load_fpr64(ctx, fp2, fr);
7573 gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2);
7574 tcg_temp_free_i64(fp0);
7575 tcg_temp_free_i64(fp1);
7576 gen_store_fpr64(ctx, fp2, fd);
7577 tcg_temp_free_i64(fp2);
7578 }
7579 opn = "nmsub.ps";
7580 break;
7581 default:
7582 MIPS_INVAL(opn);
7583 generate_exception (ctx, EXCP_RI);
7584 return;
7585 }
7586 MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr],
7587 fregnames[fs], fregnames[ft]);
7588 }
7589
7590 static void handle_delay_slot (CPUState *env, DisasContext *ctx,
7591 int insn_bytes)
7592 {
7593 if (ctx->hflags & MIPS_HFLAG_BMASK) {
7594 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
7595 /* Branches completion */
7596 ctx->hflags &= ~MIPS_HFLAG_BMASK;
7597 ctx->bstate = BS_BRANCH;
7598 save_cpu_state(ctx, 0);
7599 /* FIXME: Need to clear can_do_io. */
7600 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
7601 case MIPS_HFLAG_B:
7602 /* unconditional branch */
7603 MIPS_DEBUG("unconditional branch");
7604 if (proc_hflags & MIPS_HFLAG_BX) {
7605 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16);
7606 }
7607 gen_goto_tb(ctx, 0, ctx->btarget);
7608 break;
7609 case MIPS_HFLAG_BL:
7610 /* blikely taken case */
7611 MIPS_DEBUG("blikely branch taken");
7612 gen_goto_tb(ctx, 0, ctx->btarget);
7613 break;
7614 case MIPS_HFLAG_BC:
7615 /* Conditional branch */
7616 MIPS_DEBUG("conditional branch");
7617 {
7618 int l1 = gen_new_label();
7619
7620 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
7621 gen_goto_tb(ctx, 1, ctx->pc + insn_bytes);
7622 gen_set_label(l1);
7623 gen_goto_tb(ctx, 0, ctx->btarget);
7624 }
7625 break;
7626 case MIPS_HFLAG_BR:
7627 /* unconditional branch to register */
7628 MIPS_DEBUG("branch to register");
7629 if (env->insn_flags & ASE_MIPS16) {
7630 TCGv t0 = tcg_temp_new();
7631 TCGv_i32 t1 = tcg_temp_new_i32();
7632
7633 tcg_gen_andi_tl(t0, btarget, 0x1);
7634 tcg_gen_trunc_tl_i32(t1, t0);
7635 tcg_temp_free(t0);
7636 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
7637 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
7638 tcg_gen_or_i32(hflags, hflags, t1);
7639 tcg_temp_free_i32(t1);
7640
7641 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
7642 } else {
7643 tcg_gen_mov_tl(cpu_PC, btarget);
7644 }
7645 if (ctx->singlestep_enabled) {
7646 save_cpu_state(ctx, 0);
7647 gen_helper_0i(raise_exception, EXCP_DEBUG);
7648 }
7649 tcg_gen_exit_tb(0);
7650 break;
7651 default:
7652 MIPS_DEBUG("unknown branch");
7653 break;
7654 }
7655 }
7656 }
7657
7658 /* ISA extensions (ASEs) */
7659 /* MIPS16 extension to MIPS32 */
7660
7661 /* MIPS16 major opcodes */
7662 enum {
7663 M16_OPC_ADDIUSP = 0x00,
7664 M16_OPC_ADDIUPC = 0x01,
7665 M16_OPC_B = 0x02,
7666 M16_OPC_JAL = 0x03,
7667 M16_OPC_BEQZ = 0x04,
7668 M16_OPC_BNEQZ = 0x05,
7669 M16_OPC_SHIFT = 0x06,
7670 M16_OPC_LD = 0x07,
7671 M16_OPC_RRIA = 0x08,
7672 M16_OPC_ADDIU8 = 0x09,
7673 M16_OPC_SLTI = 0x0a,
7674 M16_OPC_SLTIU = 0x0b,
7675 M16_OPC_I8 = 0x0c,
7676 M16_OPC_LI = 0x0d,
7677 M16_OPC_CMPI = 0x0e,
7678 M16_OPC_SD = 0x0f,
7679 M16_OPC_LB = 0x10,
7680 M16_OPC_LH = 0x11,
7681 M16_OPC_LWSP = 0x12,
7682 M16_OPC_LW = 0x13,
7683 M16_OPC_LBU = 0x14,
7684 M16_OPC_LHU = 0x15,
7685 M16_OPC_LWPC = 0x16,
7686 M16_OPC_LWU = 0x17,
7687 M16_OPC_SB = 0x18,
7688 M16_OPC_SH = 0x19,
7689 M16_OPC_SWSP = 0x1a,
7690 M16_OPC_SW = 0x1b,
7691 M16_OPC_RRR = 0x1c,
7692 M16_OPC_RR = 0x1d,
7693 M16_OPC_EXTEND = 0x1e,
7694 M16_OPC_I64 = 0x1f
7695 };
7696
7697 /* I8 funct field */
7698 enum {
7699 I8_BTEQZ = 0x0,
7700 I8_BTNEZ = 0x1,
7701 I8_SWRASP = 0x2,
7702 I8_ADJSP = 0x3,
7703 I8_SVRS = 0x4,
7704 I8_MOV32R = 0x5,
7705 I8_MOVR32 = 0x7
7706 };
7707
7708 /* RRR f field */
7709 enum {
7710 RRR_DADDU = 0x0,
7711 RRR_ADDU = 0x1,
7712 RRR_DSUBU = 0x2,
7713 RRR_SUBU = 0x3
7714 };
7715
7716 /* RR funct field */
7717 enum {
7718 RR_JR = 0x00,
7719 RR_SDBBP = 0x01,
7720 RR_SLT = 0x02,
7721 RR_SLTU = 0x03,
7722 RR_SLLV = 0x04,
7723 RR_BREAK = 0x05,
7724 RR_SRLV = 0x06,
7725 RR_SRAV = 0x07,
7726 RR_DSRL = 0x08,
7727 RR_CMP = 0x0a,
7728 RR_NEG = 0x0b,
7729 RR_AND = 0x0c,
7730 RR_OR = 0x0d,
7731 RR_XOR = 0x0e,
7732 RR_NOT = 0x0f,
7733 RR_MFHI = 0x10,
7734 RR_CNVT = 0x11,
7735 RR_MFLO = 0x12,
7736 RR_DSRA = 0x13,
7737 RR_DSLLV = 0x14,
7738 RR_DSRLV = 0x16,
7739 RR_DSRAV = 0x17,
7740 RR_MULT = 0x18,
7741 RR_MULTU = 0x19,
7742 RR_DIV = 0x1a,
7743 RR_DIVU = 0x1b,
7744 RR_DMULT = 0x1c,
7745 RR_DMULTU = 0x1d,
7746 RR_DDIV = 0x1e,
7747 RR_DDIVU = 0x1f
7748 };
7749
7750 /* I64 funct field */
7751 enum {
7752 I64_LDSP = 0x0,
7753 I64_SDSP = 0x1,
7754 I64_SDRASP = 0x2,
7755 I64_DADJSP = 0x3,
7756 I64_LDPC = 0x4,
7757 I64_DADDIU5 = 0x5,
7758 I64_DADDIUPC = 0x6,
7759 I64_DADDIUSP = 0x7
7760 };
7761
7762 /* RR ry field for CNVT */
7763 enum {
7764 RR_RY_CNVT_ZEB = 0x0,
7765 RR_RY_CNVT_ZEH = 0x1,
7766 RR_RY_CNVT_ZEW = 0x2,
7767 RR_RY_CNVT_SEB = 0x4,
7768 RR_RY_CNVT_SEH = 0x5,
7769 RR_RY_CNVT_SEW = 0x6,
7770 };
7771
7772 static int xlat (int r)
7773 {
7774 static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
7775
7776 return map[r];
7777 }
7778
7779 static void gen_mips16_save (DisasContext *ctx,
7780 int xsregs, int aregs,
7781 int do_ra, int do_s0, int do_s1,
7782 int framesize)
7783 {
7784 TCGv t0 = tcg_temp_new();
7785 TCGv t1 = tcg_temp_new();
7786 int args, astatic;
7787
7788 switch (aregs) {
7789 case 0:
7790 case 1:
7791 case 2:
7792 case 3:
7793 case 11:
7794 args = 0;
7795 break;
7796 case 4:
7797 case 5:
7798 case 6:
7799 case 7:
7800 args = 1;
7801 break;
7802 case 8:
7803 case 9:
7804 case 10:
7805 args = 2;
7806 break;
7807 case 12:
7808 case 13:
7809 args = 3;
7810 break;
7811 case 14:
7812 args = 4;
7813 break;
7814 default:
7815 generate_exception(ctx, EXCP_RI);
7816 return;
7817 }
7818
7819 switch (args) {
7820 case 4:
7821 gen_base_offset_addr(ctx, t0, 29, 12);
7822 gen_load_gpr(t1, 7);
7823 op_ldst_sw(t1, t0, ctx);
7824 /* Fall through */
7825 case 3:
7826 gen_base_offset_addr(ctx, t0, 29, 8);
7827 gen_load_gpr(t1, 6);
7828 op_ldst_sw(t1, t0, ctx);
7829 /* Fall through */
7830 case 2:
7831 gen_base_offset_addr(ctx, t0, 29, 4);
7832 gen_load_gpr(t1, 5);
7833 op_ldst_sw(t1, t0, ctx);
7834 /* Fall through */
7835 case 1:
7836 gen_base_offset_addr(ctx, t0, 29, 0);
7837 gen_load_gpr(t1, 4);
7838 op_ldst_sw(t1, t0, ctx);
7839 }
7840
7841 gen_load_gpr(t0, 29);
7842
7843 #define DECR_AND_STORE(reg) do { \
7844 tcg_gen_subi_tl(t0, t0, 4); \
7845 gen_load_gpr(t1, reg); \
7846 op_ldst_sw(t1, t0, ctx); \
7847 } while (0)
7848
7849 if (do_ra) {
7850 DECR_AND_STORE(31);
7851 }
7852
7853 switch (xsregs) {
7854 case 7:
7855 DECR_AND_STORE(30);
7856 /* Fall through */
7857 case 6:
7858 DECR_AND_STORE(23);
7859 /* Fall through */
7860 case 5:
7861 DECR_AND_STORE(22);
7862 /* Fall through */
7863 case 4:
7864 DECR_AND_STORE(21);
7865 /* Fall through */
7866 case 3:
7867 DECR_AND_STORE(20);
7868 /* Fall through */
7869 case 2:
7870 DECR_AND_STORE(19);
7871 /* Fall through */
7872 case 1:
7873 DECR_AND_STORE(18);
7874 }
7875
7876 if (do_s1) {
7877 DECR_AND_STORE(17);
7878 }
7879 if (do_s0) {
7880 DECR_AND_STORE(16);
7881 }
7882
7883 switch (aregs) {
7884 case 0:
7885 case 4:
7886 case 8:
7887 case 12:
7888 case 14:
7889 astatic = 0;
7890 break;
7891 case 1:
7892 case 5:
7893 case 9:
7894 case 13:
7895 astatic = 1;
7896 break;
7897 case 2:
7898 case 6:
7899 case 10:
7900 astatic = 2;
7901 break;
7902 case 3:
7903 case 7:
7904 astatic = 3;
7905 break;
7906 case 11:
7907 astatic = 4;
7908 break;
7909 default:
7910 generate_exception(ctx, EXCP_RI);
7911 return;
7912 }
7913
7914 if (astatic > 0) {
7915 DECR_AND_STORE(7);
7916 if (astatic > 1) {
7917 DECR_AND_STORE(6);
7918 if (astatic > 2) {
7919 DECR_AND_STORE(5);
7920 if (astatic > 3) {
7921 DECR_AND_STORE(4);
7922 }
7923 }
7924 }
7925 }
7926 #undef DECR_AND_STORE
7927
7928 tcg_gen_subi_tl(cpu_gpr[29], cpu_gpr[29], framesize);
7929 tcg_temp_free(t0);
7930 tcg_temp_free(t1);
7931 }
7932
7933 static void gen_mips16_restore (DisasContext *ctx,
7934 int xsregs, int aregs,
7935 int do_ra, int do_s0, int do_s1,
7936 int framesize)
7937 {
7938 int astatic;
7939 TCGv t0 = tcg_temp_new();
7940 TCGv t1 = tcg_temp_new();
7941
7942 tcg_gen_addi_tl(t0, cpu_gpr[29], framesize);
7943
7944 #define DECR_AND_LOAD(reg) do { \
7945 tcg_gen_subi_tl(t0, t0, 4); \
7946 op_ldst_lw(t1, t0, ctx); \
7947 gen_store_gpr(t1, reg); \
7948 } while (0)
7949
7950 if (do_ra) {
7951 DECR_AND_LOAD(31);
7952 }
7953
7954 switch (xsregs) {
7955 case 7:
7956 DECR_AND_LOAD(30);
7957 /* Fall through */
7958 case 6:
7959 DECR_AND_LOAD(23);
7960 /* Fall through */
7961 case 5:
7962 DECR_AND_LOAD(22);
7963 /* Fall through */
7964 case 4:
7965 DECR_AND_LOAD(21);
7966 /* Fall through */
7967 case 3:
7968 DECR_AND_LOAD(20);
7969 /* Fall through */
7970 case 2:
7971 DECR_AND_LOAD(19);
7972 /* Fall through */
7973 case 1:
7974 DECR_AND_LOAD(18);
7975 }
7976
7977 if (do_s1) {
7978 DECR_AND_LOAD(17);
7979 }
7980 if (do_s0) {
7981 DECR_AND_LOAD(16);
7982 }
7983
7984 switch (aregs) {
7985 case 0:
7986 case 4:
7987 case 8:
7988 case 12:
7989 case 14:
7990 astatic = 0;
7991 break;
7992 case 1:
7993 case 5:
7994 case 9:
7995 case 13:
7996 astatic = 1;
7997 break;
7998 case 2:
7999 case 6:
8000 case 10:
8001 astatic = 2;
8002 break;
8003 case 3:
8004 case 7:
8005 astatic = 3;
8006 break;
8007 case 11:
8008 astatic = 4;
8009 break;
8010 default:
8011 generate_exception(ctx, EXCP_RI);
8012 return;
8013 }
8014
8015 if (astatic > 0) {
8016 DECR_AND_LOAD(7);
8017 if (astatic > 1) {
8018 DECR_AND_LOAD(6);
8019 if (astatic > 2) {
8020 DECR_AND_LOAD(5);
8021 if (astatic > 3) {
8022 DECR_AND_LOAD(4);
8023 }
8024 }
8025 }
8026 }
8027 #undef DECR_AND_LOAD
8028
8029 tcg_gen_addi_tl(cpu_gpr[29], cpu_gpr[29], framesize);
8030 tcg_temp_free(t0);
8031 tcg_temp_free(t1);
8032 }
8033
8034 static void gen_addiupc (DisasContext *ctx, int rx, int imm,
8035 int is_64_bit, int extended)
8036 {
8037 TCGv t0;
8038
8039 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
8040 generate_exception(ctx, EXCP_RI);
8041 return;
8042 }
8043
8044 t0 = tcg_temp_new();
8045
8046 tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
8047 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
8048 if (!is_64_bit) {
8049 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
8050 }
8051
8052 tcg_temp_free(t0);
8053 }
8054
8055 #if defined(TARGET_MIPS64)
8056 static void decode_i64_mips16 (CPUState *env, DisasContext *ctx,
8057 int ry, int funct, int16_t offset,
8058 int extended)
8059 {
8060 switch (funct) {
8061 case I64_LDSP:
8062 check_mips_64(ctx);
8063 offset = extended ? offset : offset << 3;
8064 gen_ldst(ctx, OPC_LD, ry, 29, offset);
8065 break;
8066 case I64_SDSP:
8067 check_mips_64(ctx);
8068 offset = extended ? offset : offset << 3;
8069 gen_ldst(ctx, OPC_SD, ry, 29, offset);
8070 break;
8071 case I64_SDRASP:
8072 check_mips_64(ctx);
8073 offset = extended ? offset : (ctx->opcode & 0xff) << 3;
8074 gen_ldst(ctx, OPC_SD, 31, 29, offset);
8075 break;
8076 case I64_DADJSP:
8077 check_mips_64(ctx);
8078 offset = extended ? offset : ((int8_t)ctx->opcode) << 3;
8079 gen_arith_imm(env, ctx, OPC_DADDIU, 29, 29, offset);
8080 break;
8081 case I64_LDPC:
8082 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
8083 generate_exception(ctx, EXCP_RI);
8084 } else {
8085 offset = extended ? offset : offset << 3;
8086 gen_ldst(ctx, OPC_LDPC, ry, 0, offset);
8087 }
8088 break;
8089 case I64_DADDIU5:
8090 check_mips_64(ctx);
8091 offset = extended ? offset : ((int8_t)(offset << 3)) >> 3;
8092 gen_arith_imm(env, ctx, OPC_DADDIU, ry, ry, offset);
8093 break;
8094 case I64_DADDIUPC:
8095 check_mips_64(ctx);
8096 offset = extended ? offset : offset << 2;
8097 gen_addiupc(ctx, ry, offset, 1, extended);
8098 break;
8099 case I64_DADDIUSP:
8100 check_mips_64(ctx);
8101 offset = extended ? offset : offset << 2;
8102 gen_arith_imm(env, ctx, OPC_DADDIU, ry, 29, offset);
8103 break;
8104 }
8105 }
8106 #endif
8107
8108 static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx,
8109 int *is_branch)
8110 {
8111 int extend = lduw_code(ctx->pc + 2);
8112 int op, rx, ry, funct, sa;
8113 int16_t imm, offset;
8114
8115 ctx->opcode = (ctx->opcode << 16) | extend;
8116 op = (ctx->opcode >> 11) & 0x1f;
8117 sa = (ctx->opcode >> 22) & 0x1f;
8118 funct = (ctx->opcode >> 8) & 0x7;
8119 rx = xlat((ctx->opcode >> 8) & 0x7);
8120 ry = xlat((ctx->opcode >> 5) & 0x7);
8121 offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11
8122 | ((ctx->opcode >> 21) & 0x3f) << 5
8123 | (ctx->opcode & 0x1f));
8124
8125 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
8126 counterparts. */
8127 switch (op) {
8128 case M16_OPC_ADDIUSP:
8129 gen_arith_imm(env, ctx, OPC_ADDIU, rx, 29, imm);
8130 break;
8131 case M16_OPC_ADDIUPC:
8132 gen_addiupc(ctx, rx, imm, 0, 1);
8133 break;
8134 case M16_OPC_B:
8135 gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, offset << 1);
8136 /* No delay slot, so just process as a normal instruction */
8137 break;
8138 case M16_OPC_BEQZ:
8139 gen_compute_branch(ctx, OPC_BEQ, 4, rx, 0, offset << 1);
8140 /* No delay slot, so just process as a normal instruction */
8141 break;
8142 case M16_OPC_BNEQZ:
8143 gen_compute_branch(ctx, OPC_BNE, 4, rx, 0, offset << 1);
8144 /* No delay slot, so just process as a normal instruction */
8145 break;
8146 case M16_OPC_SHIFT:
8147 switch (ctx->opcode & 0x3) {
8148 case 0x0:
8149 gen_shift_imm(env, ctx, OPC_SLL, rx, ry, sa);
8150 break;
8151 case 0x1:
8152 #if defined(TARGET_MIPS64)
8153 check_mips_64(ctx);
8154 gen_shift_imm(env, ctx, OPC_DSLL, rx, ry, sa);
8155 #else
8156 generate_exception(ctx, EXCP_RI);
8157 #endif
8158 break;
8159 case 0x2:
8160 gen_shift_imm(env, ctx, OPC_SRL, rx, ry, sa);
8161 break;
8162 case 0x3:
8163 gen_shift_imm(env, ctx, OPC_SRA, rx, ry, sa);
8164 break;
8165 }
8166 break;
8167 #if defined(TARGET_MIPS64)
8168 case M16_OPC_LD:
8169 check_mips_64(ctx);
8170 gen_ldst(ctx, OPC_LD, ry, rx, offset);
8171 break;
8172 #endif
8173 case M16_OPC_RRIA:
8174 imm = ctx->opcode & 0xf;
8175 imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4;
8176 imm = imm | ((ctx->opcode >> 16) & 0xf) << 11;
8177 imm = (int16_t) (imm << 1) >> 1;
8178 if ((ctx->opcode >> 4) & 0x1) {
8179 #if defined(TARGET_MIPS64)
8180 check_mips_64(ctx);
8181 gen_arith_imm(env, ctx, OPC_DADDIU, ry, rx, imm);
8182 #else
8183 generate_exception(ctx, EXCP_RI);
8184 #endif
8185 } else {
8186 gen_arith_imm(env, ctx, OPC_ADDIU, ry, rx, imm);
8187 }
8188 break;
8189 case M16_OPC_ADDIU8:
8190 gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm);
8191 break;
8192 case M16_OPC_SLTI:
8193 gen_slt_imm(env, OPC_SLTI, 24, rx, imm);
8194 break;
8195 case M16_OPC_SLTIU:
8196 gen_slt_imm(env, OPC_SLTIU, 24, rx, imm);
8197 break;
8198 case M16_OPC_I8:
8199 switch (funct) {
8200 case I8_BTEQZ:
8201 gen_compute_branch(ctx, OPC_BEQ, 4, 24, 0, offset << 1);
8202 break;
8203 case I8_BTNEZ:
8204 gen_compute_branch(ctx, OPC_BNE, 4, 24, 0, offset << 1);
8205 break;
8206 case I8_SWRASP:
8207 gen_ldst(ctx, OPC_SW, 31, 29, imm);
8208 break;
8209 case I8_ADJSP:
8210 gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, imm);
8211 break;
8212 case I8_SVRS:
8213 {
8214 int xsregs = (ctx->opcode >> 24) & 0x7;
8215 int aregs = (ctx->opcode >> 16) & 0xf;
8216 int do_ra = (ctx->opcode >> 6) & 0x1;
8217 int do_s0 = (ctx->opcode >> 5) & 0x1;
8218 int do_s1 = (ctx->opcode >> 4) & 0x1;
8219 int framesize = (((ctx->opcode >> 20) & 0xf) << 4
8220 | (ctx->opcode & 0xf)) << 3;
8221
8222 if (ctx->opcode & (1 << 7)) {
8223 gen_mips16_save(ctx, xsregs, aregs,
8224 do_ra, do_s0, do_s1,
8225 framesize);
8226 } else {
8227 gen_mips16_restore(ctx, xsregs, aregs,
8228 do_ra, do_s0, do_s1,
8229 framesize);
8230 }
8231 }
8232 break;
8233 default:
8234 generate_exception(ctx, EXCP_RI);
8235 break;
8236 }
8237 break;
8238 case M16_OPC_LI:
8239 tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
8240 break;
8241 case M16_OPC_CMPI:
8242 tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
8243 break;
8244 #if defined(TARGET_MIPS64)
8245 case M16_OPC_SD:
8246 gen_ldst(ctx, OPC_SD, ry, rx, offset);
8247 break;
8248 #endif
8249 case M16_OPC_LB:
8250 gen_ldst(ctx, OPC_LB, ry, rx, offset);
8251 break;
8252 case M16_OPC_LH:
8253 gen_ldst(ctx, OPC_LH, ry, rx, offset);
8254 break;
8255 case M16_OPC_LWSP:
8256 gen_ldst(ctx, OPC_LW, rx, 29, offset);
8257 break;
8258 case M16_OPC_LW:
8259 gen_ldst(ctx, OPC_LW, ry, rx, offset);
8260 break;
8261 case M16_OPC_LBU:
8262 gen_ldst(ctx, OPC_LBU, ry, rx, offset);
8263 break;
8264 case M16_OPC_LHU:
8265 gen_ldst(ctx, OPC_LHU, ry, rx, offset);
8266 break;
8267 case M16_OPC_LWPC:
8268 gen_ldst(ctx, OPC_LWPC, rx, 0, offset);
8269 break;
8270 #if defined(TARGET_MIPS64)
8271 case M16_OPC_LWU:
8272 gen_ldst(ctx, OPC_LWU, ry, rx, offset);
8273 break;
8274 #endif
8275 case M16_OPC_SB:
8276 gen_ldst(ctx, OPC_SB, ry, rx, offset);
8277 break;
8278 case M16_OPC_SH:
8279 gen_ldst(ctx, OPC_SH, ry, rx, offset);
8280 break;
8281 case M16_OPC_SWSP:
8282 gen_ldst(ctx, OPC_SW, rx, 29, offset);
8283 break;
8284 case M16_OPC_SW:
8285 gen_ldst(ctx, OPC_SW, ry, rx, offset);
8286 break;
8287 #if defined(TARGET_MIPS64)
8288 case M16_OPC_I64:
8289 decode_i64_mips16(env, ctx, ry, funct, offset, 1);
8290 break;
8291 #endif
8292 default:
8293 generate_exception(ctx, EXCP_RI);
8294 break;
8295 }
8296
8297 return 4;
8298 }
8299
8300 static int decode_mips16_opc (CPUState *env, DisasContext *ctx,
8301 int *is_branch)
8302 {
8303 int rx, ry;
8304 int sa;
8305 int op, cnvt_op, op1, offset;
8306 int funct;
8307 int n_bytes;
8308
8309 op = (ctx->opcode >> 11) & 0x1f;
8310 sa = (ctx->opcode >> 2) & 0x7;
8311 sa = sa == 0 ? 8 : sa;
8312 rx = xlat((ctx->opcode >> 8) & 0x7);
8313 cnvt_op = (ctx->opcode >> 5) & 0x7;
8314 ry = xlat((ctx->opcode >> 5) & 0x7);
8315 op1 = offset = ctx->opcode & 0x1f;
8316
8317 n_bytes = 2;
8318
8319 switch (op) {
8320 case M16_OPC_ADDIUSP:
8321 {
8322 int16_t imm = ((uint8_t) ctx->opcode) << 2;
8323
8324 gen_arith_imm(env, ctx, OPC_ADDIU, rx, 29, imm);
8325 }
8326 break;
8327 case M16_OPC_ADDIUPC:
8328 gen_addiupc(ctx, rx, ((uint8_t) ctx->opcode) << 2, 0, 0);
8329 break;
8330 case M16_OPC_B:
8331 offset = (ctx->opcode & 0x7ff) << 1;
8332 offset = (int16_t)(offset << 4) >> 4;
8333 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, offset);
8334 /* No delay slot, so just process as a normal instruction */
8335 break;
8336 case M16_OPC_JAL:
8337 offset = lduw_code(ctx->pc + 2);
8338 offset = (((ctx->opcode & 0x1f) << 21)
8339 | ((ctx->opcode >> 5) & 0x1f) << 16
8340 | offset) << 2;
8341 op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALX : OPC_JAL;
8342 gen_compute_branch(ctx, op, 4, rx, ry, offset);
8343 n_bytes = 4;
8344 *is_branch = 1;
8345 break;
8346 case M16_OPC_BEQZ:
8347 gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0, ((int8_t)ctx->opcode) << 1);
8348 /* No delay slot, so just process as a normal instruction */
8349 break;
8350 case M16_OPC_BNEQZ:
8351 gen_compute_branch(ctx, OPC_BNE, 2, rx, 0, ((int8_t)ctx->opcode) << 1);
8352 /* No delay slot, so just process as a normal instruction */
8353 break;
8354 case M16_OPC_SHIFT:
8355 switch (ctx->opcode & 0x3) {
8356 case 0x0:
8357 gen_shift_imm(env, ctx, OPC_SLL, rx, ry, sa);
8358 break;
8359 case 0x1:
8360 #if defined(TARGET_MIPS64)
8361 check_mips_64(ctx);
8362 gen_shift_imm(env, ctx, OPC_DSLL, rx, ry, sa);
8363 #else
8364 generate_exception(ctx, EXCP_RI);
8365 #endif
8366 break;
8367 case 0x2:
8368 gen_shift_imm(env, ctx, OPC_SRL, rx, ry, sa);
8369 break;
8370 case 0x3:
8371 gen_shift_imm(env, ctx, OPC_SRA, rx, ry, sa);
8372 break;
8373 }
8374 break;
8375 #if defined(TARGET_MIPS64)
8376 case M16_OPC_LD:
8377 check_mips_64(ctx);
8378 gen_ldst(ctx, OPC_LD, ry, rx, offset << 3);
8379 break;
8380 #endif
8381 case M16_OPC_RRIA:
8382 {
8383 int16_t imm = (int8_t)((ctx->opcode & 0xf) << 4) >> 4;
8384
8385 if ((ctx->opcode >> 4) & 1) {
8386 #if defined(TARGET_MIPS64)
8387 check_mips_64(ctx);
8388 gen_arith_imm(env, ctx, OPC_DADDIU, ry, rx, imm);
8389 #else
8390 generate_exception(ctx, EXCP_RI);
8391 #endif
8392 } else {
8393 gen_arith_imm(env, ctx, OPC_ADDIU, ry, rx, imm);
8394 }
8395 }
8396 break;
8397 case M16_OPC_ADDIU8:
8398 {
8399 int16_t imm = (int8_t) ctx->opcode;
8400
8401 gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm);
8402 }
8403 break;
8404 case M16_OPC_SLTI:
8405 {
8406 int16_t imm = (uint8_t) ctx->opcode;
8407
8408 gen_slt_imm(env, OPC_SLTI, 24, rx, imm);
8409 }
8410 break;
8411 case M16_OPC_SLTIU:
8412 {
8413 int16_t imm = (uint8_t) ctx->opcode;
8414
8415 gen_slt_imm(env, OPC_SLTIU, 24, rx, imm);
8416 }
8417 break;
8418 case M16_OPC_I8:
8419 {
8420 int reg32;
8421
8422 funct = (ctx->opcode >> 8) & 0x7;
8423 switch (funct) {
8424 case I8_BTEQZ:
8425 gen_compute_branch(ctx, OPC_BEQ, 2, 24, 0,
8426 ((int8_t)ctx->opcode) << 1);
8427 break;
8428 case I8_BTNEZ:
8429 gen_compute_branch(ctx, OPC_BNE, 2, 24, 0,
8430 ((int8_t)ctx->opcode) << 1);
8431 break;
8432 case I8_SWRASP:
8433 gen_ldst(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2);
8434 break;
8435 case I8_ADJSP:
8436 gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29,
8437 ((int8_t)ctx->opcode) << 3);
8438 break;
8439 case I8_SVRS:
8440 {
8441 int do_ra = ctx->opcode & (1 << 6);
8442 int do_s0 = ctx->opcode & (1 << 5);
8443 int do_s1 = ctx->opcode & (1 << 4);
8444 int framesize = ctx->opcode & 0xf;
8445
8446 if (framesize == 0) {
8447 framesize = 128;
8448 } else {
8449 framesize = framesize << 3;
8450 }
8451
8452 if (ctx->opcode & (1 << 7)) {
8453 gen_mips16_save(ctx, 0, 0,
8454 do_ra, do_s0, do_s1, framesize);
8455 } else {
8456 gen_mips16_restore(ctx, 0, 0,
8457 do_ra, do_s0, do_s1, framesize);
8458 }
8459 }
8460 break;
8461 case I8_MOV32R:
8462 {
8463 int rz = xlat(ctx->opcode & 0x7);
8464
8465 reg32 = (((ctx->opcode >> 3) & 0x3) << 3) |
8466 ((ctx->opcode >> 5) & 0x7);
8467 gen_arith(env, ctx, OPC_ADDU, reg32, rz, 0);
8468 }
8469 break;
8470 case I8_MOVR32:
8471 reg32 = ctx->opcode & 0x1f;
8472 gen_arith(env, ctx, OPC_ADDU, ry, reg32, 0);
8473 break;
8474 default:
8475 generate_exception(ctx, EXCP_RI);
8476 break;
8477 }
8478 }
8479 break;
8480 case M16_OPC_LI:
8481 {
8482 int16_t imm = (uint8_t) ctx->opcode;
8483
8484 gen_arith_imm(env, ctx, OPC_ADDIU, rx, 0, imm);
8485 }
8486 break;
8487 case M16_OPC_CMPI:
8488 {
8489 int16_t imm = (uint8_t) ctx->opcode;
8490
8491 gen_logic_imm(env, OPC_XORI, 24, rx, imm);
8492 }
8493 break;
8494 #if defined(TARGET_MIPS64)
8495 case M16_OPC_SD:
8496 check_mips_64(ctx);
8497 gen_ldst(ctx, OPC_SD, ry, rx, offset << 3);
8498 break;
8499 #endif
8500 case M16_OPC_LB:
8501 gen_ldst(ctx, OPC_LB, ry, rx, offset);
8502 break;
8503 case M16_OPC_LH:
8504 gen_ldst(ctx, OPC_LH, ry, rx, offset << 1);
8505 break;
8506 case M16_OPC_LWSP:
8507 gen_ldst(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2);
8508 break;
8509 case M16_OPC_LW:
8510 gen_ldst(ctx, OPC_LW, ry, rx, offset << 2);
8511 break;
8512 case M16_OPC_LBU:
8513 gen_ldst(ctx, OPC_LBU, ry, rx, offset);
8514 break;
8515 case M16_OPC_LHU:
8516 gen_ldst(ctx, OPC_LHU, ry, rx, offset << 1);
8517 break;
8518 case M16_OPC_LWPC:
8519 gen_ldst(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
8520 break;
8521 #if defined (TARGET_MIPS64)
8522 case M16_OPC_LWU:
8523 check_mips_64(ctx);
8524 gen_ldst(ctx, OPC_LWU, ry, rx, offset << 2);
8525 break;
8526 #endif
8527 case M16_OPC_SB:
8528 gen_ldst(ctx, OPC_SB, ry, rx, offset);
8529 break;
8530 case M16_OPC_SH:
8531 gen_ldst(ctx, OPC_SH, ry, rx, offset << 1);
8532 break;
8533 case M16_OPC_SWSP:
8534 gen_ldst(ctx, OPC_SW, rx, 29, ((uint8_t)ctx->opcode) << 2);
8535 break;
8536 case M16_OPC_SW:
8537 gen_ldst(ctx, OPC_SW, ry, rx, offset << 2);
8538 break;
8539 case M16_OPC_RRR:
8540 {
8541 int rz = xlat((ctx->opcode >> 2) & 0x7);
8542 int mips32_op;
8543
8544 switch (ctx->opcode & 0x3) {
8545 case RRR_ADDU:
8546 mips32_op = OPC_ADDU;
8547 break;
8548 case RRR_SUBU:
8549 mips32_op = OPC_SUBU;
8550 break;
8551 #if defined(TARGET_MIPS64)
8552 case RRR_DADDU:
8553 mips32_op = OPC_DADDU;
8554 check_mips_64(ctx);
8555 break;
8556 case RRR_DSUBU:
8557 mips32_op = OPC_DSUBU;
8558 check_mips_64(ctx);
8559 break;
8560 #endif
8561 default:
8562 generate_exception(ctx, EXCP_RI);
8563 goto done;
8564 }
8565
8566 gen_arith(env, ctx, mips32_op, rz, rx, ry);
8567 done:
8568 ;
8569 }
8570 break;
8571 case M16_OPC_RR:
8572 switch (op1) {
8573 case RR_JR:
8574 {
8575 int nd = (ctx->opcode >> 7) & 0x1;
8576 int link = (ctx->opcode >> 6) & 0x1;
8577 int ra = (ctx->opcode >> 5) & 0x1;
8578
8579 if (link) {
8580 op = nd ? OPC_JALRC : OPC_JALR;
8581 } else {
8582 op = OPC_JR;
8583 }
8584
8585 gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0);
8586 if (!nd) {
8587 *is_branch = 1;
8588 }
8589 }
8590 break;
8591 case RR_SDBBP:
8592 /* XXX: not clear which exception should be raised
8593 * when in debug mode...
8594 */
8595 check_insn(env, ctx, ISA_MIPS32);
8596 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
8597 generate_exception(ctx, EXCP_DBp);
8598 } else {
8599 generate_exception(ctx, EXCP_DBp);
8600 }
8601 break;
8602 case RR_SLT:
8603 gen_slt(env, OPC_SLT, 24, rx, ry);
8604 break;
8605 case RR_SLTU:
8606 gen_slt(env, OPC_SLTU, 24, rx, ry);
8607 break;
8608 case RR_BREAK:
8609 generate_exception(ctx, EXCP_BREAK);
8610 break;
8611 case RR_SLLV:
8612 gen_shift(env, ctx, OPC_SLLV, ry, rx, ry);
8613 break;
8614 case RR_SRLV:
8615 gen_shift(env, ctx, OPC_SRLV, ry, rx, ry);
8616 break;
8617 case RR_SRAV:
8618 gen_shift(env, ctx, OPC_SRAV, ry, rx, ry);
8619 break;
8620 #if defined (TARGET_MIPS64)
8621 case RR_DSRL:
8622 check_mips_64(ctx);
8623 gen_shift_imm(env, ctx, OPC_DSRL, ry, ry, sa);
8624 break;
8625 #endif
8626 case RR_CMP:
8627 gen_logic(env, OPC_XOR, 24, rx, ry);
8628 break;
8629 case RR_NEG:
8630 gen_arith(env, ctx, OPC_SUBU, rx, 0, ry);
8631 break;
8632 case RR_AND:
8633 gen_logic(env, OPC_AND, rx, rx, ry);
8634 break;
8635 case RR_OR:
8636 gen_logic(env, OPC_OR, rx, rx, ry);
8637 break;
8638 case RR_XOR:
8639 gen_logic(env, OPC_XOR, rx, rx, ry);
8640 break;
8641 case RR_NOT:
8642 gen_logic(env, OPC_NOR, rx, ry, 0);
8643 break;
8644 case RR_MFHI:
8645 gen_HILO(ctx, OPC_MFHI, rx);
8646 break;
8647 case RR_CNVT:
8648 switch (cnvt_op) {
8649 case RR_RY_CNVT_ZEB:
8650 tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
8651 break;
8652 case RR_RY_CNVT_ZEH:
8653 tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]);
8654 break;
8655 case RR_RY_CNVT_SEB:
8656 tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]);
8657 break;
8658 case RR_RY_CNVT_SEH:
8659 tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
8660 break;
8661 #if defined (TARGET_MIPS64)
8662 case RR_RY_CNVT_ZEW:
8663 check_mips_64(ctx);
8664 tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
8665 break;
8666 case RR_RY_CNVT_SEW:
8667 check_mips_64(ctx);
8668 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
8669 break;
8670 #endif
8671 default:
8672 generate_exception(ctx, EXCP_RI);
8673 break;
8674 }
8675 break;
8676 case RR_MFLO:
8677 gen_HILO(ctx, OPC_MFLO, rx);
8678 break;
8679 #if defined (TARGET_MIPS64)
8680 case RR_DSRA:
8681 check_mips_64(ctx);
8682 gen_shift_imm(env, ctx, OPC_DSRA, ry, ry, sa);
8683 break;
8684 case RR_DSLLV:
8685 check_mips_64(ctx);
8686 gen_shift(env, ctx, OPC_DSLLV, ry, rx, ry);
8687 break;
8688 case RR_DSRLV:
8689 check_mips_64(ctx);
8690 gen_shift(env, ctx, OPC_DSRLV, ry, rx, ry);
8691 break;
8692 case RR_DSRAV:
8693 check_mips_64(ctx);
8694 gen_shift(env, ctx, OPC_DSRAV, ry, rx, ry);
8695 break;
8696 #endif
8697 case RR_MULT:
8698 gen_muldiv(ctx, OPC_MULT, rx, ry);
8699 break;
8700 case RR_MULTU:
8701 gen_muldiv(ctx, OPC_MULTU, rx, ry);
8702 break;
8703 case RR_DIV:
8704 gen_muldiv(ctx, OPC_DIV, rx, ry);
8705 break;
8706 case RR_DIVU:
8707 gen_muldiv(ctx, OPC_DIVU, rx, ry);
8708 break;
8709 #if defined (TARGET_MIPS64)
8710 case RR_DMULT:
8711 check_mips_64(ctx);
8712 gen_muldiv(ctx, OPC_DMULT, rx, ry);
8713 break;
8714 case RR_DMULTU:
8715 check_mips_64(ctx);
8716 gen_muldiv(ctx, OPC_DMULTU, rx, ry);
8717 break;
8718 case RR_DDIV:
8719 check_mips_64(ctx);
8720 gen_muldiv(ctx, OPC_DDIV, rx, ry);
8721 break;
8722 case RR_DDIVU:
8723 check_mips_64(ctx);
8724 gen_muldiv(ctx, OPC_DDIVU, rx, ry);
8725 break;
8726 #endif
8727 default:
8728 generate_exception(ctx, EXCP_RI);
8729 break;
8730 }
8731 break;
8732 case M16_OPC_EXTEND:
8733 decode_extended_mips16_opc(env, ctx, is_branch);
8734 n_bytes = 4;
8735 break;
8736 #if defined(TARGET_MIPS64)
8737 case M16_OPC_I64:
8738 funct = (ctx->opcode >> 8) & 0x7;
8739 decode_i64_mips16(env, ctx, ry, funct, offset, 0);
8740 break;
8741 #endif
8742 default:
8743 generate_exception(ctx, EXCP_RI);
8744 break;
8745 }
8746
8747 return n_bytes;
8748 }
8749
8750 /* SmartMIPS extension to MIPS32 */
8751
8752 #if defined(TARGET_MIPS64)
8753
8754 /* MDMX extension to MIPS64 */
8755
8756 #endif
8757
8758 static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
8759 {
8760 int32_t offset;
8761 int rs, rt, rd, sa;
8762 uint32_t op, op1, op2;
8763 int16_t imm;
8764
8765 /* make sure instructions are on a word boundary */
8766 if (ctx->pc & 0x3) {
8767 env->CP0_BadVAddr = ctx->pc;
8768 generate_exception(ctx, EXCP_AdEL);
8769 return;
8770 }
8771
8772 /* Handle blikely not taken case */
8773 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
8774 int l1 = gen_new_label();
8775
8776 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
8777 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
8778 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
8779 gen_goto_tb(ctx, 1, ctx->pc + 4);
8780 gen_set_label(l1);
8781 }
8782
8783 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
8784 tcg_gen_debug_insn_start(ctx->pc);
8785
8786 op = MASK_OP_MAJOR(ctx->opcode);
8787 rs = (ctx->opcode >> 21) & 0x1f;
8788 rt = (ctx->opcode >> 16) & 0x1f;
8789 rd = (ctx->opcode >> 11) & 0x1f;
8790 sa = (ctx->opcode >> 6) & 0x1f;
8791 imm = (int16_t)ctx->opcode;
8792 switch (op) {
8793 case OPC_SPECIAL:
8794 op1 = MASK_SPECIAL(ctx->opcode);
8795 switch (op1) {
8796 case OPC_SLL: /* Shift with immediate */
8797 case OPC_SRA:
8798 gen_shift_imm(env, ctx, op1, rd, rt, sa);
8799 break;
8800 case OPC_SRL:
8801 switch ((ctx->opcode >> 21) & 0x1f) {
8802 case 1:
8803 /* rotr is decoded as srl on non-R2 CPUs */
8804 if (env->insn_flags & ISA_MIPS32R2) {
8805 op1 = OPC_ROTR;
8806 }
8807 /* Fallthrough */
8808 case 0:
8809 gen_shift_imm(env, ctx, op1, rd, rt, sa);
8810 break;
8811 default:
8812 generate_exception(ctx, EXCP_RI);
8813 break;
8814 }
8815 break;
8816 case OPC_MOVN: /* Conditional move */
8817 case OPC_MOVZ:
8818 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
8819 gen_cond_move(env, op1, rd, rs, rt);
8820 break;
8821 case OPC_ADD ... OPC_SUBU:
8822 gen_arith(env, ctx, op1, rd, rs, rt);
8823 break;
8824 case OPC_SLLV: /* Shifts */
8825 case OPC_SRAV:
8826 gen_shift(env, ctx, op1, rd, rs, rt);
8827 break;
8828 case OPC_SRLV:
8829 switch ((ctx->opcode >> 6) & 0x1f) {
8830 case 1:
8831 /* rotrv is decoded as srlv on non-R2 CPUs */
8832 if (env->insn_flags & ISA_MIPS32R2) {
8833 op1 = OPC_ROTRV;
8834 }
8835 /* Fallthrough */
8836 case 0:
8837 gen_shift(env, ctx, op1, rd, rs, rt);
8838 break;
8839 default:
8840 generate_exception(ctx, EXCP_RI);
8841 break;
8842 }
8843 break;
8844 case OPC_SLT: /* Set on less than */
8845 case OPC_SLTU:
8846 gen_slt(env, op1, rd, rs, rt);
8847 break;
8848 case OPC_AND: /* Logic*/
8849 case OPC_OR:
8850 case OPC_NOR:
8851 case OPC_XOR:
8852 gen_logic(env, op1, rd, rs, rt);
8853 break;
8854 case OPC_MULT ... OPC_DIVU:
8855 if (sa) {
8856 check_insn(env, ctx, INSN_VR54XX);
8857 op1 = MASK_MUL_VR54XX(ctx->opcode);
8858 gen_mul_vr54xx(ctx, op1, rd, rs, rt);
8859 } else
8860 gen_muldiv(ctx, op1, rs, rt);
8861 break;
8862 case OPC_JR ... OPC_JALR:
8863 gen_compute_branch(ctx, op1, 4, rs, rd, sa);
8864 *is_branch = 1;
8865 break;
8866 case OPC_TGE ... OPC_TEQ: /* Traps */
8867 case OPC_TNE:
8868 gen_trap(ctx, op1, rs, rt, -1);
8869 break;
8870 case OPC_MFHI: /* Move from HI/LO */
8871 case OPC_MFLO:
8872 gen_HILO(ctx, op1, rd);
8873 break;
8874 case OPC_MTHI:
8875 case OPC_MTLO: /* Move to HI/LO */
8876 gen_HILO(ctx, op1, rs);
8877 break;
8878 case OPC_PMON: /* Pmon entry point, also R4010 selsl */
8879 #ifdef MIPS_STRICT_STANDARD
8880 MIPS_INVAL("PMON / selsl");
8881 generate_exception(ctx, EXCP_RI);
8882 #else
8883 gen_helper_0i(pmon, sa);
8884 #endif
8885 break;
8886 case OPC_SYSCALL:
8887 generate_exception(ctx, EXCP_SYSCALL);
8888 ctx->bstate = BS_STOP;
8889 break;
8890 case OPC_BREAK:
8891 generate_exception(ctx, EXCP_BREAK);
8892 break;
8893 case OPC_SPIM:
8894 #ifdef MIPS_STRICT_STANDARD
8895 MIPS_INVAL("SPIM");
8896 generate_exception(ctx, EXCP_RI);
8897 #else
8898 /* Implemented as RI exception for now. */
8899 MIPS_INVAL("spim (unofficial)");
8900 generate_exception(ctx, EXCP_RI);
8901 #endif
8902 break;
8903 case OPC_SYNC:
8904 /* Treat as NOP. */
8905 break;
8906
8907 case OPC_MOVCI:
8908 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
8909 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8910 check_cp1_enabled(ctx);
8911 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
8912 (ctx->opcode >> 16) & 1);
8913 } else {
8914 generate_exception_err(ctx, EXCP_CpU, 1);
8915 }
8916 break;
8917
8918 #if defined(TARGET_MIPS64)
8919 /* MIPS64 specific opcodes */
8920 case OPC_DSLL:
8921 case OPC_DSRA:
8922 case OPC_DSLL32:
8923 case OPC_DSRA32:
8924 check_insn(env, ctx, ISA_MIPS3);
8925 check_mips_64(ctx);
8926 gen_shift_imm(env, ctx, op1, rd, rt, sa);
8927 break;
8928 case OPC_DSRL:
8929 switch ((ctx->opcode >> 21) & 0x1f) {
8930 case 1:
8931 /* drotr is decoded as dsrl on non-R2 CPUs */
8932 if (env->insn_flags & ISA_MIPS32R2) {
8933 op1 = OPC_DROTR;
8934 }
8935 /* Fallthrough */
8936 case 0:
8937 check_insn(env, ctx, ISA_MIPS3);
8938 check_mips_64(ctx);
8939 gen_shift_imm(env, ctx, op1, rd, rt, sa);
8940 break;
8941 default:
8942 generate_exception(ctx, EXCP_RI);
8943 break;
8944 }
8945 break;
8946 case OPC_DSRL32:
8947 switch ((ctx->opcode >> 21) & 0x1f) {
8948 case 1:
8949 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
8950 if (env->insn_flags & ISA_MIPS32R2) {
8951 op1 = OPC_DROTR32;
8952 }
8953 /* Fallthrough */
8954 case 0:
8955 check_insn(env, ctx, ISA_MIPS3);
8956 check_mips_64(ctx);
8957 gen_shift_imm(env, ctx, op1, rd, rt, sa);
8958 break;
8959 default:
8960 generate_exception(ctx, EXCP_RI);
8961 break;
8962 }
8963 break;
8964 case OPC_DADD ... OPC_DSUBU:
8965 check_insn(env, ctx, ISA_MIPS3);
8966 check_mips_64(ctx);
8967 gen_arith(env, ctx, op1, rd, rs, rt);
8968 break;
8969 case OPC_DSLLV:
8970 case OPC_DSRAV:
8971 check_insn(env, ctx, ISA_MIPS3);
8972 check_mips_64(ctx);
8973 gen_shift(env, ctx, op1, rd, rs, rt);
8974 break;
8975 case OPC_DSRLV:
8976 switch ((ctx->opcode >> 6) & 0x1f) {
8977 case 1:
8978 /* drotrv is decoded as dsrlv on non-R2 CPUs */
8979 if (env->insn_flags & ISA_MIPS32R2) {
8980 op1 = OPC_DROTRV;
8981 }
8982 /* Fallthrough */
8983 case 0:
8984 check_insn(env, ctx, ISA_MIPS3);
8985 check_mips_64(ctx);
8986 gen_shift(env, ctx, op1, rd, rs, rt);
8987 break;
8988 default:
8989 generate_exception(ctx, EXCP_RI);
8990 break;
8991 }
8992 break;
8993 case OPC_DMULT ... OPC_DDIVU:
8994 check_insn(env, ctx, ISA_MIPS3);
8995 check_mips_64(ctx);
8996 gen_muldiv(ctx, op1, rs, rt);
8997 break;
8998 #endif
8999 default: /* Invalid */
9000 MIPS_INVAL("special");
9001 generate_exception(ctx, EXCP_RI);
9002 break;
9003 }
9004 break;
9005 case OPC_SPECIAL2:
9006 op1 = MASK_SPECIAL2(ctx->opcode);
9007 switch (op1) {
9008 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
9009 case OPC_MSUB ... OPC_MSUBU:
9010 check_insn(env, ctx, ISA_MIPS32);
9011 gen_muldiv(ctx, op1, rs, rt);
9012 break;
9013 case OPC_MUL:
9014 gen_arith(env, ctx, op1, rd, rs, rt);
9015 break;
9016 case OPC_CLO:
9017 case OPC_CLZ:
9018 check_insn(env, ctx, ISA_MIPS32);
9019 gen_cl(ctx, op1, rd, rs);
9020 break;
9021 case OPC_SDBBP:
9022 /* XXX: not clear which exception should be raised
9023 * when in debug mode...
9024 */
9025 check_insn(env, ctx, ISA_MIPS32);
9026 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
9027 generate_exception(ctx, EXCP_DBp);
9028 } else {
9029 generate_exception(ctx, EXCP_DBp);
9030 }
9031 /* Treat as NOP. */
9032 break;
9033 #if defined(TARGET_MIPS64)
9034 case OPC_DCLO:
9035 case OPC_DCLZ:
9036 check_insn(env, ctx, ISA_MIPS64);
9037 check_mips_64(ctx);
9038 gen_cl(ctx, op1, rd, rs);
9039 break;
9040 #endif
9041 default: /* Invalid */
9042 MIPS_INVAL("special2");
9043 generate_exception(ctx, EXCP_RI);
9044 break;
9045 }
9046 break;
9047 case OPC_SPECIAL3:
9048 op1 = MASK_SPECIAL3(ctx->opcode);
9049 switch (op1) {
9050 case OPC_EXT:
9051 case OPC_INS:
9052 check_insn(env, ctx, ISA_MIPS32R2);
9053 gen_bitops(ctx, op1, rt, rs, sa, rd);
9054 break;
9055 case OPC_BSHFL:
9056 check_insn(env, ctx, ISA_MIPS32R2);
9057 op2 = MASK_BSHFL(ctx->opcode);
9058 gen_bshfl(ctx, op2, rt, rd);
9059 break;
9060 case OPC_RDHWR:
9061 check_insn(env, ctx, ISA_MIPS32R2);
9062 {
9063 TCGv t0 = tcg_temp_new();
9064
9065 switch (rd) {
9066 case 0:
9067 save_cpu_state(ctx, 1);
9068 gen_helper_rdhwr_cpunum(t0);
9069 gen_store_gpr(t0, rt);
9070 break;
9071 case 1:
9072 save_cpu_state(ctx, 1);
9073 gen_helper_rdhwr_synci_step(t0);
9074 gen_store_gpr(t0, rt);
9075 break;
9076 case 2:
9077 save_cpu_state(ctx, 1);
9078 gen_helper_rdhwr_cc(t0);
9079 gen_store_gpr(t0, rt);
9080 break;
9081 case 3:
9082 save_cpu_state(ctx, 1);
9083 gen_helper_rdhwr_ccres(t0);
9084 gen_store_gpr(t0, rt);
9085 break;
9086 case 29:
9087 #if defined(CONFIG_USER_ONLY)
9088 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
9089 gen_store_gpr(t0, rt);
9090 break;
9091 #else
9092 /* XXX: Some CPUs implement this in hardware.
9093 Not supported yet. */
9094 #endif
9095 default: /* Invalid */
9096 MIPS_INVAL("rdhwr");
9097 generate_exception(ctx, EXCP_RI);
9098 break;
9099 }
9100 tcg_temp_free(t0);
9101 }
9102 break;
9103 case OPC_FORK:
9104 check_insn(env, ctx, ASE_MT);
9105 {
9106 TCGv t0 = tcg_temp_new();
9107 TCGv t1 = tcg_temp_new();
9108
9109 gen_load_gpr(t0, rt);
9110 gen_load_gpr(t1, rs);
9111 gen_helper_fork(t0, t1);
9112 tcg_temp_free(t0);
9113 tcg_temp_free(t1);
9114 }
9115 break;
9116 case OPC_YIELD:
9117 check_insn(env, ctx, ASE_MT);
9118 {
9119 TCGv t0 = tcg_temp_new();
9120
9121 save_cpu_state(ctx, 1);
9122 gen_load_gpr(t0, rs);
9123 gen_helper_yield(t0, t0);
9124 gen_store_gpr(t0, rd);
9125 tcg_temp_free(t0);
9126 }
9127 break;
9128 #if defined(TARGET_MIPS64)
9129 case OPC_DEXTM ... OPC_DEXT:
9130 case OPC_DINSM ... OPC_DINS:
9131 check_insn(env, ctx, ISA_MIPS64R2);
9132 check_mips_64(ctx);
9133 gen_bitops(ctx, op1, rt, rs, sa, rd);
9134 break;
9135 case OPC_DBSHFL:
9136 check_insn(env, ctx, ISA_MIPS64R2);
9137 check_mips_64(ctx);
9138 op2 = MASK_DBSHFL(ctx->opcode);
9139 gen_bshfl(ctx, op2, rt, rd);
9140 break;
9141 #endif
9142 default: /* Invalid */
9143 MIPS_INVAL("special3");
9144 generate_exception(ctx, EXCP_RI);
9145 break;
9146 }
9147 break;
9148 case OPC_REGIMM:
9149 op1 = MASK_REGIMM(ctx->opcode);
9150 switch (op1) {
9151 case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
9152 case OPC_BLTZAL ... OPC_BGEZALL:
9153 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
9154 *is_branch = 1;
9155 break;
9156 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
9157 case OPC_TNEI:
9158 gen_trap(ctx, op1, rs, -1, imm);
9159 break;
9160 case OPC_SYNCI:
9161 check_insn(env, ctx, ISA_MIPS32R2);
9162 /* Treat as NOP. */
9163 break;
9164 default: /* Invalid */
9165 MIPS_INVAL("regimm");
9166 generate_exception(ctx, EXCP_RI);
9167 break;
9168 }
9169 break;
9170 case OPC_CP0:
9171 check_cp0_enabled(ctx);
9172 op1 = MASK_CP0(ctx->opcode);
9173 switch (op1) {
9174 case OPC_MFC0:
9175 case OPC_MTC0:
9176 case OPC_MFTR:
9177 case OPC_MTTR:
9178 #if defined(TARGET_MIPS64)
9179 case OPC_DMFC0:
9180 case OPC_DMTC0:
9181 #endif
9182 #ifndef CONFIG_USER_ONLY
9183 gen_cp0(env, ctx, op1, rt, rd);
9184 #endif /* !CONFIG_USER_ONLY */
9185 break;
9186 case OPC_C0_FIRST ... OPC_C0_LAST:
9187 #ifndef CONFIG_USER_ONLY
9188 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
9189 #endif /* !CONFIG_USER_ONLY */
9190 break;
9191 case OPC_MFMC0:
9192 #ifndef CONFIG_USER_ONLY
9193 {
9194 TCGv t0 = tcg_temp_new();
9195
9196 op2 = MASK_MFMC0(ctx->opcode);
9197 switch (op2) {
9198 case OPC_DMT:
9199 check_insn(env, ctx, ASE_MT);
9200 gen_helper_dmt(t0, t0);
9201 gen_store_gpr(t0, rt);
9202 break;
9203 case OPC_EMT:
9204 check_insn(env, ctx, ASE_MT);
9205 gen_helper_emt(t0, t0);
9206 gen_store_gpr(t0, rt);
9207 break;
9208 case OPC_DVPE:
9209 check_insn(env, ctx, ASE_MT);
9210 gen_helper_dvpe(t0, t0);
9211 gen_store_gpr(t0, rt);
9212 break;
9213 case OPC_EVPE:
9214 check_insn(env, ctx, ASE_MT);
9215 gen_helper_evpe(t0, t0);
9216 gen_store_gpr(t0, rt);
9217 break;
9218 case OPC_DI:
9219 check_insn(env, ctx, ISA_MIPS32R2);
9220 save_cpu_state(ctx, 1);
9221 gen_helper_di(t0);
9222 gen_store_gpr(t0, rt);
9223 /* Stop translation as we may have switched the execution mode */
9224 ctx->bstate = BS_STOP;
9225 break;
9226 case OPC_EI:
9227 check_insn(env, ctx, ISA_MIPS32R2);
9228 save_cpu_state(ctx, 1);
9229 gen_helper_ei(t0);
9230 gen_store_gpr(t0, rt);
9231 /* Stop translation as we may have switched the execution mode */
9232 ctx->bstate = BS_STOP;
9233 break;
9234 default: /* Invalid */
9235 MIPS_INVAL("mfmc0");
9236 generate_exception(ctx, EXCP_RI);
9237 break;
9238 }
9239 tcg_temp_free(t0);
9240 }
9241 #endif /* !CONFIG_USER_ONLY */
9242 break;
9243 case OPC_RDPGPR:
9244 check_insn(env, ctx, ISA_MIPS32R2);
9245 gen_load_srsgpr(rt, rd);
9246 break;
9247 case OPC_WRPGPR:
9248 check_insn(env, ctx, ISA_MIPS32R2);
9249 gen_store_srsgpr(rt, rd);
9250 break;
9251 default:
9252 MIPS_INVAL("cp0");
9253 generate_exception(ctx, EXCP_RI);
9254 break;
9255 }
9256 break;
9257 case OPC_ADDI: /* Arithmetic with immediate opcode */
9258 case OPC_ADDIU:
9259 gen_arith_imm(env, ctx, op, rt, rs, imm);
9260 break;
9261 case OPC_SLTI: /* Set on less than with immediate opcode */
9262 case OPC_SLTIU:
9263 gen_slt_imm(env, op, rt, rs, imm);
9264 break;
9265 case OPC_ANDI: /* Arithmetic with immediate opcode */
9266 case OPC_LUI:
9267 case OPC_ORI:
9268 case OPC_XORI:
9269 gen_logic_imm(env, op, rt, rs, imm);
9270 break;
9271 case OPC_J ... OPC_JAL: /* Jump */
9272 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
9273 gen_compute_branch(ctx, op, 4, rs, rt, offset);
9274 *is_branch = 1;
9275 break;
9276 case OPC_BEQ ... OPC_BGTZ: /* Branch */
9277 case OPC_BEQL ... OPC_BGTZL:
9278 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
9279 *is_branch = 1;
9280 break;
9281 case OPC_LB ... OPC_LWR: /* Load and stores */
9282 case OPC_SB ... OPC_SW:
9283 case OPC_SWR:
9284 case OPC_LL:
9285 gen_ldst(ctx, op, rt, rs, imm);
9286 break;
9287 case OPC_SC:
9288 gen_st_cond(ctx, op, rt, rs, imm);
9289 break;
9290 case OPC_CACHE:
9291 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
9292 /* Treat as NOP. */
9293 break;
9294 case OPC_PREF:
9295 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
9296 /* Treat as NOP. */
9297 break;
9298
9299 /* Floating point (COP1). */
9300 case OPC_LWC1:
9301 case OPC_LDC1:
9302 case OPC_SWC1:
9303 case OPC_SDC1:
9304 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
9305 check_cp1_enabled(ctx);
9306 gen_flt_ldst(ctx, op, rt, rs, imm);
9307 } else {
9308 generate_exception_err(ctx, EXCP_CpU, 1);
9309 }
9310 break;
9311
9312 case OPC_CP1:
9313 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
9314 check_cp1_enabled(ctx);
9315 op1 = MASK_CP1(ctx->opcode);
9316 switch (op1) {
9317 case OPC_MFHC1:
9318 case OPC_MTHC1:
9319 check_insn(env, ctx, ISA_MIPS32R2);
9320 case OPC_MFC1:
9321 case OPC_CFC1:
9322 case OPC_MTC1:
9323 case OPC_CTC1:
9324 gen_cp1(ctx, op1, rt, rd);
9325 break;
9326 #if defined(TARGET_MIPS64)
9327 case OPC_DMFC1:
9328 case OPC_DMTC1:
9329 check_insn(env, ctx, ISA_MIPS3);
9330 gen_cp1(ctx, op1, rt, rd);
9331 break;
9332 #endif
9333 case OPC_BC1ANY2:
9334 case OPC_BC1ANY4:
9335 check_cop1x(ctx);
9336 check_insn(env, ctx, ASE_MIPS3D);
9337 /* fall through */
9338 case OPC_BC1:
9339 gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
9340 (rt >> 2) & 0x7, imm << 2);
9341 *is_branch = 1;
9342 break;
9343 case OPC_S_FMT:
9344 case OPC_D_FMT:
9345 case OPC_W_FMT:
9346 case OPC_L_FMT:
9347 case OPC_PS_FMT:
9348 gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
9349 (imm >> 8) & 0x7);
9350 break;
9351 default:
9352 MIPS_INVAL("cp1");
9353 generate_exception (ctx, EXCP_RI);
9354 break;
9355 }
9356 } else {
9357 generate_exception_err(ctx, EXCP_CpU, 1);
9358 }
9359 break;
9360
9361 /* COP2. */
9362 case OPC_LWC2:
9363 case OPC_LDC2:
9364 case OPC_SWC2:
9365 case OPC_SDC2:
9366 case OPC_CP2:
9367 /* COP2: Not implemented. */
9368 generate_exception_err(ctx, EXCP_CpU, 2);
9369 break;
9370
9371 case OPC_CP3:
9372 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
9373 check_cp1_enabled(ctx);
9374 op1 = MASK_CP3(ctx->opcode);
9375 switch (op1) {
9376 case OPC_LWXC1:
9377 case OPC_LDXC1:
9378 case OPC_LUXC1:
9379 case OPC_SWXC1:
9380 case OPC_SDXC1:
9381 case OPC_SUXC1:
9382 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
9383 break;
9384 case OPC_PREFX:
9385 /* Treat as NOP. */
9386 break;
9387 case OPC_ALNV_PS:
9388 case OPC_MADD_S:
9389 case OPC_MADD_D:
9390 case OPC_MADD_PS:
9391 case OPC_MSUB_S:
9392 case OPC_MSUB_D:
9393 case OPC_MSUB_PS:
9394 case OPC_NMADD_S:
9395 case OPC_NMADD_D:
9396 case OPC_NMADD_PS:
9397 case OPC_NMSUB_S:
9398 case OPC_NMSUB_D:
9399 case OPC_NMSUB_PS:
9400 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
9401 break;
9402 default:
9403 MIPS_INVAL("cp3");
9404 generate_exception (ctx, EXCP_RI);
9405 break;
9406 }
9407 } else {
9408 generate_exception_err(ctx, EXCP_CpU, 1);
9409 }
9410 break;
9411
9412 #if defined(TARGET_MIPS64)
9413 /* MIPS64 opcodes */
9414 case OPC_LWU:
9415 case OPC_LDL ... OPC_LDR:
9416 case OPC_SDL ... OPC_SDR:
9417 case OPC_LLD:
9418 case OPC_LD:
9419 case OPC_SD:
9420 check_insn(env, ctx, ISA_MIPS3);
9421 check_mips_64(ctx);
9422 gen_ldst(ctx, op, rt, rs, imm);
9423 break;
9424 case OPC_SCD:
9425 check_insn(env, ctx, ISA_MIPS3);
9426 check_mips_64(ctx);
9427 gen_st_cond(ctx, op, rt, rs, imm);
9428 break;
9429 case OPC_DADDI:
9430 case OPC_DADDIU:
9431 check_insn(env, ctx, ISA_MIPS3);
9432 check_mips_64(ctx);
9433 gen_arith_imm(env, ctx, op, rt, rs, imm);
9434 break;
9435 #endif
9436 case OPC_JALX:
9437 check_insn(env, ctx, ASE_MIPS16);
9438 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
9439 gen_compute_branch(ctx, op, 4, rs, rt, offset);
9440 *is_branch = 1;
9441 break;
9442 case OPC_MDMX:
9443 check_insn(env, ctx, ASE_MDMX);
9444 /* MDMX: Not implemented. */
9445 default: /* Invalid */
9446 MIPS_INVAL("major opcode");
9447 generate_exception(ctx, EXCP_RI);
9448 break;
9449 }
9450 }
9451
9452 static inline void
9453 gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
9454 int search_pc)
9455 {
9456 DisasContext ctx;
9457 target_ulong pc_start;
9458 uint16_t *gen_opc_end;
9459 CPUBreakpoint *bp;
9460 int j, lj = -1;
9461 int num_insns;
9462 int max_insns;
9463 int insn_bytes;
9464 int is_branch;
9465
9466 if (search_pc)
9467 qemu_log("search pc %d\n", search_pc);
9468
9469 pc_start = tb->pc;
9470 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9471 ctx.pc = pc_start;
9472 ctx.saved_pc = -1;
9473 ctx.singlestep_enabled = env->singlestep_enabled;
9474 ctx.tb = tb;
9475 ctx.bstate = BS_NONE;
9476 /* Restore delay slot state from the tb context. */
9477 ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
9478 restore_cpu_state(env, &ctx);
9479 #ifdef CONFIG_USER_ONLY
9480 ctx.mem_idx = MIPS_HFLAG_UM;
9481 #else
9482 ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
9483 #endif
9484 num_insns = 0;
9485 max_insns = tb->cflags & CF_COUNT_MASK;
9486 if (max_insns == 0)
9487 max_insns = CF_COUNT_MASK;
9488 #ifdef DEBUG_DISAS
9489 qemu_log_mask(CPU_LOG_TB_CPU, "------------------------------------------------\n");
9490 /* FIXME: This may print out stale hflags from env... */
9491 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
9492 #endif
9493 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
9494 gen_icount_start();
9495 while (ctx.bstate == BS_NONE) {
9496 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9497 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9498 if (bp->pc == ctx.pc) {
9499 save_cpu_state(&ctx, 1);
9500 ctx.bstate = BS_BRANCH;
9501 gen_helper_0i(raise_exception, EXCP_DEBUG);
9502 /* Include the breakpoint location or the tb won't
9503 * be flushed when it must be. */
9504 ctx.pc += 4;
9505 goto done_generating;
9506 }
9507 }
9508 }
9509
9510 if (search_pc) {
9511 j = gen_opc_ptr - gen_opc_buf;
9512 if (lj < j) {
9513 lj++;
9514 while (lj < j)
9515 gen_opc_instr_start[lj++] = 0;
9516 }
9517 gen_opc_pc[lj] = ctx.pc;
9518 gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
9519 gen_opc_instr_start[lj] = 1;
9520 gen_opc_icount[lj] = num_insns;
9521 }
9522 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9523 gen_io_start();
9524
9525 is_branch = 0;
9526 if (!(ctx.hflags & MIPS_HFLAG_M16)) {
9527 ctx.opcode = ldl_code(ctx.pc);
9528 insn_bytes = 4;
9529 decode_opc(env, &ctx, &is_branch);
9530 } else if (env->insn_flags & ASE_MIPS16) {
9531 ctx.opcode = lduw_code(ctx.pc);
9532 insn_bytes = decode_mips16_opc(env, &ctx, &is_branch);
9533 } else {
9534 generate_exception(&ctx, EXCP_RI);
9535 break;
9536 }
9537 if (!is_branch) {
9538 handle_delay_slot(env, &ctx, insn_bytes);
9539 }
9540 ctx.pc += insn_bytes;
9541
9542 num_insns++;
9543
9544 /* Execute a branch and its delay slot as a single instruction.
9545 This is what GDB expects and is consistent with what the
9546 hardware does (e.g. if a delay slot instruction faults, the
9547 reported PC is the PC of the branch). */
9548 if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
9549 break;
9550
9551 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
9552 break;
9553
9554 if (gen_opc_ptr >= gen_opc_end)
9555 break;
9556
9557 if (num_insns >= max_insns)
9558 break;
9559
9560 if (singlestep)
9561 break;
9562 }
9563 if (tb->cflags & CF_LAST_IO)
9564 gen_io_end();
9565 if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
9566 save_cpu_state(&ctx, ctx.bstate == BS_NONE);
9567 gen_helper_0i(raise_exception, EXCP_DEBUG);
9568 } else {
9569 switch (ctx.bstate) {
9570 case BS_STOP:
9571 gen_helper_interrupt_restart();
9572 gen_goto_tb(&ctx, 0, ctx.pc);
9573 break;
9574 case BS_NONE:
9575 save_cpu_state(&ctx, 0);
9576 gen_goto_tb(&ctx, 0, ctx.pc);
9577 break;
9578 case BS_EXCP:
9579 gen_helper_interrupt_restart();
9580 tcg_gen_exit_tb(0);
9581 break;
9582 case BS_BRANCH:
9583 default:
9584 break;
9585 }
9586 }
9587 done_generating:
9588 gen_icount_end(tb, num_insns);
9589 *gen_opc_ptr = INDEX_op_end;
9590 if (search_pc) {
9591 j = gen_opc_ptr - gen_opc_buf;
9592 lj++;
9593 while (lj <= j)
9594 gen_opc_instr_start[lj++] = 0;
9595 } else {
9596 tb->size = ctx.pc - pc_start;
9597 tb->icount = num_insns;
9598 }
9599 #ifdef DEBUG_DISAS
9600 LOG_DISAS("\n");
9601 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9602 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9603 log_target_disas(pc_start, ctx.pc - pc_start, 0);
9604 qemu_log("\n");
9605 }
9606 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
9607 #endif
9608 }
9609
9610 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
9611 {
9612 gen_intermediate_code_internal(env, tb, 0);
9613 }
9614
9615 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
9616 {
9617 gen_intermediate_code_internal(env, tb, 1);
9618 }
9619
9620 static void fpu_dump_state(CPUState *env, FILE *f,
9621 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
9622 int flags)
9623 {
9624 int i;
9625 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
9626
9627 #define printfpr(fp) \
9628 do { \
9629 if (is_fpu64) \
9630 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
9631 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
9632 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
9633 else { \
9634 fpr_t tmp; \
9635 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
9636 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
9637 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
9638 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
9639 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
9640 } \
9641 } while(0)
9642
9643
9644 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
9645 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
9646 get_float_exception_flags(&env->active_fpu.fp_status));
9647 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
9648 fpu_fprintf(f, "%3s: ", fregnames[i]);
9649 printfpr(&env->active_fpu.fpr[i]);
9650 }
9651
9652 #undef printfpr
9653 }
9654
9655 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
9656 /* Debug help: The architecture requires 32bit code to maintain proper
9657 sign-extended values on 64bit machines. */
9658
9659 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
9660
9661 static void
9662 cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
9663 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
9664 int flags)
9665 {
9666 int i;
9667
9668 if (!SIGN_EXT_P(env->active_tc.PC))
9669 cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC);
9670 if (!SIGN_EXT_P(env->active_tc.HI[0]))
9671 cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]);
9672 if (!SIGN_EXT_P(env->active_tc.LO[0]))
9673 cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]);
9674 if (!SIGN_EXT_P(env->btarget))
9675 cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
9676
9677 for (i = 0; i < 32; i++) {
9678 if (!SIGN_EXT_P(env->active_tc.gpr[i]))
9679 cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]);
9680 }
9681
9682 if (!SIGN_EXT_P(env->CP0_EPC))
9683 cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC);
9684 if (!SIGN_EXT_P(env->lladdr))
9685 cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->lladdr);
9686 }
9687 #endif
9688
9689 void cpu_dump_state (CPUState *env, FILE *f,
9690 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
9691 int flags)
9692 {
9693 int i;
9694
9695 cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
9696 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
9697 env->hflags, env->btarget, env->bcond);
9698 for (i = 0; i < 32; i++) {
9699 if ((i & 3) == 0)
9700 cpu_fprintf(f, "GPR%02d:", i);
9701 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);
9702 if ((i & 3) == 3)
9703 cpu_fprintf(f, "\n");
9704 }
9705
9706 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
9707 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
9708 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
9709 env->CP0_Config0, env->CP0_Config1, env->lladdr);
9710 if (env->hflags & MIPS_HFLAG_FPU)
9711 fpu_dump_state(env, f, cpu_fprintf, flags);
9712 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
9713 cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
9714 #endif
9715 }
9716
9717 static void mips_tcg_init(void)
9718 {
9719 int i;
9720 static int inited;
9721
9722 /* Initialize various static tables. */
9723 if (inited)
9724 return;
9725
9726 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
9727 TCGV_UNUSED(cpu_gpr[0]);
9728 for (i = 1; i < 32; i++)
9729 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
9730 offsetof(CPUState, active_tc.gpr[i]),
9731 regnames[i]);
9732 cpu_PC = tcg_global_mem_new(TCG_AREG0,
9733 offsetof(CPUState, active_tc.PC), "PC");
9734 for (i = 0; i < MIPS_DSP_ACC; i++) {
9735 cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
9736 offsetof(CPUState, active_tc.HI[i]),
9737 regnames_HI[i]);
9738 cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
9739 offsetof(CPUState, active_tc.LO[i]),
9740 regnames_LO[i]);
9741 cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
9742 offsetof(CPUState, active_tc.ACX[i]),
9743 regnames_ACX[i]);
9744 }
9745 cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
9746 offsetof(CPUState, active_tc.DSPControl),
9747 "DSPControl");
9748 bcond = tcg_global_mem_new(TCG_AREG0,
9749 offsetof(CPUState, bcond), "bcond");
9750 btarget = tcg_global_mem_new(TCG_AREG0,
9751 offsetof(CPUState, btarget), "btarget");
9752 hflags = tcg_global_mem_new_i32(TCG_AREG0,
9753 offsetof(CPUState, hflags), "hflags");
9754
9755 fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
9756 offsetof(CPUState, active_fpu.fcr0),
9757 "fcr0");
9758 fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0,
9759 offsetof(CPUState, active_fpu.fcr31),
9760 "fcr31");
9761
9762 /* register helpers */
9763 #define GEN_HELPER 2
9764 #include "helper.h"
9765
9766 inited = 1;
9767 }
9768
9769 #include "translate_init.c"
9770
9771 CPUMIPSState *cpu_mips_init (const char *cpu_model)
9772 {
9773 CPUMIPSState *env;
9774 const mips_def_t *def;
9775
9776 def = cpu_mips_find_by_name(cpu_model);
9777 if (!def)
9778 return NULL;
9779 env = qemu_mallocz(sizeof(CPUMIPSState));
9780 env->cpu_model = def;
9781 env->cpu_model_str = cpu_model;
9782
9783 cpu_exec_init(env);
9784 #ifndef CONFIG_USER_ONLY
9785 mmu_init(env, def);
9786 #endif
9787 fpu_init(env, def);
9788 mvp_init(env, def);
9789 mips_tcg_init();
9790 cpu_reset(env);
9791 qemu_init_vcpu(env);
9792 return env;
9793 }
9794
9795 void cpu_reset (CPUMIPSState *env)
9796 {
9797 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
9798 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
9799 log_cpu_state(env, 0);
9800 }
9801
9802 memset(env, 0, offsetof(CPUMIPSState, breakpoints));
9803 tlb_flush(env, 1);
9804
9805 /* Reset registers to their default values */
9806 env->CP0_PRid = env->cpu_model->CP0_PRid;
9807 env->CP0_Config0 = env->cpu_model->CP0_Config0;
9808 #ifdef TARGET_WORDS_BIGENDIAN
9809 env->CP0_Config0 |= (1 << CP0C0_BE);
9810 #endif
9811 env->CP0_Config1 = env->cpu_model->CP0_Config1;
9812 env->CP0_Config2 = env->cpu_model->CP0_Config2;
9813 env->CP0_Config3 = env->cpu_model->CP0_Config3;
9814 env->CP0_Config6 = env->cpu_model->CP0_Config6;
9815 env->CP0_Config7 = env->cpu_model->CP0_Config7;
9816 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
9817 << env->cpu_model->CP0_LLAddr_shift;
9818 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
9819 env->SYNCI_Step = env->cpu_model->SYNCI_Step;
9820 env->CCRes = env->cpu_model->CCRes;
9821 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
9822 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
9823 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
9824 env->current_tc = 0;
9825 env->SEGBITS = env->cpu_model->SEGBITS;
9826 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
9827 #if defined(TARGET_MIPS64)
9828 if (env->cpu_model->insn_flags & ISA_MIPS3) {
9829 env->SEGMask |= 3ULL << 62;
9830 }
9831 #endif
9832 env->PABITS = env->cpu_model->PABITS;
9833 env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1);
9834 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
9835 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
9836 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
9837 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
9838 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
9839 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
9840 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
9841 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
9842 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
9843 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
9844 env->insn_flags = env->cpu_model->insn_flags;
9845
9846 #if defined(CONFIG_USER_ONLY)
9847 env->hflags = MIPS_HFLAG_UM;
9848 /* Enable access to the SYNCI_Step register. */
9849 env->CP0_HWREna |= (1 << 1);
9850 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
9851 env->hflags |= MIPS_HFLAG_FPU;
9852 }
9853 #ifdef TARGET_MIPS64
9854 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
9855 env->hflags |= MIPS_HFLAG_F64;
9856 }
9857 #endif
9858 #else
9859 if (env->hflags & MIPS_HFLAG_BMASK) {
9860 /* If the exception was raised from a delay slot,
9861 come back to the jump. */
9862 env->CP0_ErrorEPC = env->active_tc.PC - 4;
9863 } else {
9864 env->CP0_ErrorEPC = env->active_tc.PC;
9865 }
9866 env->active_tc.PC = (int32_t)0xBFC00000;
9867 env->CP0_Random = env->tlb->nb_tlb - 1;
9868 env->tlb->tlb_in_use = env->tlb->nb_tlb;
9869 env->CP0_Wired = 0;
9870 /* SMP not implemented */
9871 env->CP0_EBase = 0x80000000;
9872 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
9873 /* vectored interrupts not implemented, timer on int 7,
9874 no performance counters. */
9875 env->CP0_IntCtl = 0xe0000000;
9876 {
9877 int i;
9878
9879 for (i = 0; i < 7; i++) {
9880 env->CP0_WatchLo[i] = 0;
9881 env->CP0_WatchHi[i] = 0x80000000;
9882 }
9883 env->CP0_WatchLo[7] = 0;
9884 env->CP0_WatchHi[7] = 0;
9885 }
9886 /* Count register increments in debug mode, EJTAG version 1 */
9887 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
9888 env->hflags = MIPS_HFLAG_CP0;
9889 #endif
9890 #if defined(TARGET_MIPS64)
9891 if (env->cpu_model->insn_flags & ISA_MIPS3) {
9892 env->hflags |= MIPS_HFLAG_64;
9893 }
9894 #endif
9895 env->exception_index = EXCP_NONE;
9896 }
9897
9898 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9899 unsigned long searched_pc, int pc_pos, void *puc)
9900 {
9901 env->active_tc.PC = gen_opc_pc[pc_pos];
9902 env->hflags &= ~MIPS_HFLAG_BMASK;
9903 env->hflags |= gen_opc_hflags[pc_pos];
9904 }
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