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tcg/arm: fix div2/divu2
[qemu/aliguori-queue.git] / tcg / ppc / tcg-target.c
blobb40246d411c94bd20231497341dd4256783d2e88
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef _CALL_DARWIN
28 #define LINKAGE_AREA_SIZE 24
29 #define LR_OFFSET 8
30 #elif defined _CALL_AIX
31 #define LINKAGE_AREA_SIZE 52
32 #define LR_OFFSET 8
33 #else
34 #define LINKAGE_AREA_SIZE 8
35 #define LR_OFFSET 4
36 #endif
37
38 #define FAST_PATH
39 #if TARGET_PHYS_ADDR_BITS <= 32
40 #define ADDEND_OFFSET 0
41 #else
42 #define ADDEND_OFFSET 4
43 #endif
44
45 #ifndef GUEST_BASE
46 #define GUEST_BASE 0
47 #endif
48
49 #ifdef CONFIG_USE_GUEST_BASE
50 #define TCG_GUEST_BASE_REG 30
51 #else
52 #define TCG_GUEST_BASE_REG 0
53 #endif
54
55 #ifndef NDEBUG
56 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r0",
58 "r1",
59 "rp",
60 "r3",
61 "r4",
62 "r5",
63 "r6",
64 "r7",
65 "r8",
66 "r9",
67 "r10",
68 "r11",
69 "r12",
70 "r13",
71 "r14",
72 "r15",
73 "r16",
74 "r17",
75 "r18",
76 "r19",
77 "r20",
78 "r21",
79 "r22",
80 "r23",
81 "r24",
82 "r25",
83 "r26",
84 "r27",
85 "r28",
86 "r29",
87 "r30",
88 "r31"
89 };
90 #endif
91
92 static const int tcg_target_reg_alloc_order[] = {
93 TCG_REG_R14,
94 TCG_REG_R15,
95 TCG_REG_R16,
96 TCG_REG_R17,
97 TCG_REG_R18,
98 TCG_REG_R19,
99 TCG_REG_R20,
100 TCG_REG_R21,
101 TCG_REG_R22,
102 TCG_REG_R23,
103 TCG_REG_R28,
104 TCG_REG_R29,
105 TCG_REG_R30,
106 TCG_REG_R31,
107 #ifdef _CALL_DARWIN
108 TCG_REG_R2,
109 #endif
110 TCG_REG_R3,
111 TCG_REG_R4,
112 TCG_REG_R5,
113 TCG_REG_R6,
114 TCG_REG_R7,
115 TCG_REG_R8,
116 TCG_REG_R9,
117 TCG_REG_R10,
118 #ifndef _CALL_DARWIN
119 TCG_REG_R11,
120 #endif
121 TCG_REG_R12,
122 #ifndef _CALL_SYSV
123 TCG_REG_R13,
124 #endif
125 TCG_REG_R24,
126 TCG_REG_R25,
127 TCG_REG_R26,
128 TCG_REG_R27
129 };
130
131 static const int tcg_target_call_iarg_regs[] = {
132 TCG_REG_R3,
133 TCG_REG_R4,
134 TCG_REG_R5,
135 TCG_REG_R6,
136 TCG_REG_R7,
137 TCG_REG_R8,
138 TCG_REG_R9,
139 TCG_REG_R10
140 };
141
142 static const int tcg_target_call_oarg_regs[2] = {
143 TCG_REG_R3,
144 TCG_REG_R4
145 };
146
147 static const int tcg_target_callee_save_regs[] = {
148 #ifdef _CALL_DARWIN
149 TCG_REG_R11,
150 TCG_REG_R13,
151 #endif
152 #ifdef _CALL_AIX
153 TCG_REG_R13,
154 #endif
155 TCG_REG_R14,
156 TCG_REG_R15,
157 TCG_REG_R16,
158 TCG_REG_R17,
159 TCG_REG_R18,
160 TCG_REG_R19,
161 TCG_REG_R20,
162 TCG_REG_R21,
163 TCG_REG_R22,
164 TCG_REG_R23,
165 TCG_REG_R24,
166 TCG_REG_R25,
167 TCG_REG_R26,
168 /* TCG_REG_R27, */ /* currently used for the global env, so no
169 need to save */
170 TCG_REG_R28,
171 TCG_REG_R29,
172 TCG_REG_R30,
173 TCG_REG_R31
174 };
175
176 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
177 {
178 tcg_target_long disp;
179
180 disp = target - (tcg_target_long) pc;
181 if ((disp << 6) >> 6 != disp)
182 tcg_abort ();
183
184 return disp & 0x3fffffc;
185 }
186
187 static void reloc_pc24 (void *pc, tcg_target_long target)
188 {
189 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
190 | reloc_pc24_val (pc, target);
191 }
192
193 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
194 {
195 tcg_target_long disp;
196
197 disp = target - (tcg_target_long) pc;
198 if (disp != (int16_t) disp)
199 tcg_abort ();
200
201 return disp & 0xfffc;
202 }
203
204 static void reloc_pc14 (void *pc, tcg_target_long target)
205 {
206 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
207 | reloc_pc14_val (pc, target);
208 }
209
210 static void patch_reloc(uint8_t *code_ptr, int type,
211 tcg_target_long value, tcg_target_long addend)
212 {
213 value += addend;
214 switch (type) {
215 case R_PPC_REL14:
216 reloc_pc14 (code_ptr, value);
217 break;
218 case R_PPC_REL24:
219 reloc_pc24 (code_ptr, value);
220 break;
221 default:
222 tcg_abort();
223 }
224 }
225
226 /* maximum number of register used for input function arguments */
227 static int tcg_target_get_call_iarg_regs_count(int flags)
228 {
229 return ARRAY_SIZE (tcg_target_call_iarg_regs);
230 }
231
232 /* parse target specific constraints */
233 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
234 {
235 const char *ct_str;
236
237 ct_str = *pct_str;
238 switch (ct_str[0]) {
239 case 'A': case 'B': case 'C': case 'D':
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
242 break;
243 case 'r':
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 break;
247 #ifdef CONFIG_SOFTMMU
248 case 'L': /* qemu_ld constraint */
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 break;
254 case 'K': /* qemu_st[8..32] constraint */
255 ct->ct |= TCG_CT_REG;
256 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
260 #if TARGET_LONG_BITS == 64
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
262 #endif
263 break;
264 case 'M': /* qemu_st64 constraint */
265 ct->ct |= TCG_CT_REG;
266 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
270 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
271 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
272 break;
273 #else
274 case 'L':
275 case 'K':
276 ct->ct |= TCG_CT_REG;
277 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
278 break;
279 case 'M':
280 ct->ct |= TCG_CT_REG;
281 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
282 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
283 break;
284 #endif
285 default:
286 return -1;
287 }
288 ct_str++;
289 *pct_str = ct_str;
290 return 0;
291 }
292
293 /* test if a constant matches the constraint */
294 static int tcg_target_const_match(tcg_target_long val,
295 const TCGArgConstraint *arg_ct)
296 {
297 int ct;
298
299 ct = arg_ct->ct;
300 if (ct & TCG_CT_CONST)
301 return 1;
302 return 0;
303 }
304
305 #define OPCD(opc) ((opc)<<26)
306 #define XO31(opc) (OPCD(31)|((opc)<<1))
307 #define XO19(opc) (OPCD(19)|((opc)<<1))
308
309 #define B OPCD(18)
310 #define BC OPCD(16)
311 #define LBZ OPCD(34)
312 #define LHZ OPCD(40)
313 #define LHA OPCD(42)
314 #define LWZ OPCD(32)
315 #define STB OPCD(38)
316 #define STH OPCD(44)
317 #define STW OPCD(36)
318
319 #define ADDIC OPCD(12)
320 #define ADDI OPCD(14)
321 #define ADDIS OPCD(15)
322 #define ORI OPCD(24)
323 #define ORIS OPCD(25)
324 #define XORI OPCD(26)
325 #define XORIS OPCD(27)
326 #define ANDI OPCD(28)
327 #define ANDIS OPCD(29)
328 #define MULLI OPCD( 7)
329 #define CMPLI OPCD(10)
330 #define CMPI OPCD(11)
331 #define SUBFIC OPCD( 8)
332
333 #define LWZU OPCD(33)
334 #define STWU OPCD(37)
335
336 #define RLWINM OPCD(21)
337 #define RLWNM OPCD(23)
338
339 #define BCLR XO19( 16)
340 #define BCCTR XO19(528)
341 #define CRAND XO19(257)
342 #define CRANDC XO19(129)
343 #define CRNAND XO19(225)
344 #define CROR XO19(449)
345 #define CRNOR XO19( 33)
346
347 #define EXTSB XO31(954)
348 #define EXTSH XO31(922)
349 #define ADD XO31(266)
350 #define ADDE XO31(138)
351 #define ADDC XO31( 10)
352 #define AND XO31( 28)
353 #define SUBF XO31( 40)
354 #define SUBFC XO31( 8)
355 #define SUBFE XO31(136)
356 #define OR XO31(444)
357 #define XOR XO31(316)
358 #define MULLW XO31(235)
359 #define MULHWU XO31( 11)
360 #define DIVW XO31(491)
361 #define DIVWU XO31(459)
362 #define CMP XO31( 0)
363 #define CMPL XO31( 32)
364 #define LHBRX XO31(790)
365 #define LWBRX XO31(534)
366 #define STHBRX XO31(918)
367 #define STWBRX XO31(662)
368 #define MFSPR XO31(339)
369 #define MTSPR XO31(467)
370 #define SRAWI XO31(824)
371 #define NEG XO31(104)
372 #define MFCR XO31( 19)
373 #define CNTLZW XO31( 26)
374 #define NOR XO31(124)
375 #define ANDC XO31( 60)
376 #define ORC XO31(412)
377
378 #define LBZX XO31( 87)
379 #define LHZX XO31(279)
380 #define LHAX XO31(343)
381 #define LWZX XO31( 23)
382 #define STBX XO31(215)
383 #define STHX XO31(407)
384 #define STWX XO31(151)
385
386 #define SPR(a,b) ((((a)<<5)|(b))<<11)
387 #define LR SPR(8, 0)
388 #define CTR SPR(9, 0)
389
390 #define SLW XO31( 24)
391 #define SRW XO31(536)
392 #define SRAW XO31(792)
393
394 #define TW XO31(4)
395 #define TRAP (TW | TO (31))
396
397 #define RT(r) ((r)<<21)
398 #define RS(r) ((r)<<21)
399 #define RA(r) ((r)<<16)
400 #define RB(r) ((r)<<11)
401 #define TO(t) ((t)<<21)
402 #define SH(s) ((s)<<11)
403 #define MB(b) ((b)<<6)
404 #define ME(e) ((e)<<1)
405 #define BO(o) ((o)<<21)
406
407 #define LK 1
408
409 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
410 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
411
412 #define BF(n) ((n)<<23)
413 #define BI(n, c) (((c)+((n)*4))<<16)
414 #define BT(n, c) (((c)+((n)*4))<<21)
415 #define BA(n, c) (((c)+((n)*4))<<16)
416 #define BB(n, c) (((c)+((n)*4))<<11)
417
418 #define BO_COND_TRUE BO (12)
419 #define BO_COND_FALSE BO (4)
420 #define BO_ALWAYS BO (20)
421
422 enum {
423 CR_LT,
424 CR_GT,
425 CR_EQ,
426 CR_SO
427 };
428
429 static const uint32_t tcg_to_bc[10] = {
430 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
431 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
432 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
433 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
434 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
435 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
436 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
437 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
438 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
439 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
440 };
441
442 static void tcg_out_mov(TCGContext *s, int ret, int arg)
443 {
444 tcg_out32 (s, OR | SAB (arg, ret, arg));
445 }
446
447 static void tcg_out_movi(TCGContext *s, TCGType type,
448 int ret, tcg_target_long arg)
449 {
450 if (arg == (int16_t) arg)
451 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
452 else {
453 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
454 if (arg & 0xffff)
455 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
456 }
457 }
458
459 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
460 int offset, int op1, int op2)
461 {
462 if (offset == (int16_t) offset)
463 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 else {
465 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
466 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
467 }
468 }
469
470 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
471 {
472 tcg_target_long disp;
473
474 disp = target - (tcg_target_long) s->code_ptr;
475 if ((disp << 6) >> 6 == disp)
476 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
477 else {
478 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
479 tcg_out32 (s, MTSPR | RS (0) | CTR);
480 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
481 }
482 }
483
484 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
485 {
486 #ifdef _CALL_AIX
487 int reg;
488
489 if (const_arg) {
490 reg = 2;
491 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
492 }
493 else reg = arg;
494
495 tcg_out32 (s, LWZ | RT (0) | RA (reg));
496 tcg_out32 (s, MTSPR | RA (0) | CTR);
497 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
498 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
499 #else
500 if (const_arg) {
501 tcg_out_b (s, LK, arg);
502 }
503 else {
504 tcg_out32 (s, MTSPR | RS (arg) | LR);
505 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
506 }
507 #endif
508 }
509
510 #if defined(CONFIG_SOFTMMU)
511
512 #include "../../softmmu_defs.h"
513
514 static void *qemu_ld_helpers[4] = {
515 __ldb_mmu,
516 __ldw_mmu,
517 __ldl_mmu,
518 __ldq_mmu,
519 };
520
521 static void *qemu_st_helpers[4] = {
522 __stb_mmu,
523 __stw_mmu,
524 __stl_mmu,
525 __stq_mmu,
526 };
527 #endif
528
529 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
530 {
531 int addr_reg, data_reg, data_reg2, r0, r1, rbase, mem_index, s_bits, bswap;
532 #ifdef CONFIG_SOFTMMU
533 int r2;
534 void *label1_ptr, *label2_ptr;
535 #endif
536 #if TARGET_LONG_BITS == 64
537 int addr_reg2;
538 #endif
539
540 data_reg = *args++;
541 if (opc == 3)
542 data_reg2 = *args++;
543 else
544 data_reg2 = 0;
545 addr_reg = *args++;
546 #if TARGET_LONG_BITS == 64
547 addr_reg2 = *args++;
548 #endif
549 mem_index = *args;
550 s_bits = opc & 3;
551
552 #ifdef CONFIG_SOFTMMU
553 r0 = 3;
554 r1 = 4;
555 r2 = 0;
556 rbase = 0;
557
558 tcg_out32 (s, (RLWINM
559 | RA (r0)
560 | RS (addr_reg)
561 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
562 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
563 | ME (31 - CPU_TLB_ENTRY_BITS)
564 )
565 );
566 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
567 tcg_out32 (s, (LWZU
568 | RT (r1)
569 | RA (r0)
570 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
571 )
572 );
573 tcg_out32 (s, (RLWINM
574 | RA (r2)
575 | RS (addr_reg)
576 | SH (0)
577 | MB ((32 - s_bits) & 31)
578 | ME (31 - TARGET_PAGE_BITS)
579 )
580 );
581
582 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
583 #if TARGET_LONG_BITS == 64
584 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
585 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
586 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
587 #endif
588
589 label1_ptr = s->code_ptr;
590 #ifdef FAST_PATH
591 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
592 #endif
593
594 /* slow path */
595 #if TARGET_LONG_BITS == 32
596 tcg_out_mov (s, 3, addr_reg);
597 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
598 #else
599 tcg_out_mov (s, 3, addr_reg2);
600 tcg_out_mov (s, 4, addr_reg);
601 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
602 #endif
603
604 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
605 switch (opc) {
606 case 0|4:
607 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
608 break;
609 case 1|4:
610 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
611 break;
612 case 0:
613 case 1:
614 case 2:
615 if (data_reg != 3)
616 tcg_out_mov (s, data_reg, 3);
617 break;
618 case 3:
619 if (data_reg == 3) {
620 if (data_reg2 == 4) {
621 tcg_out_mov (s, 0, 4);
622 tcg_out_mov (s, 4, 3);
623 tcg_out_mov (s, 3, 0);
624 }
625 else {
626 tcg_out_mov (s, data_reg2, 3);
627 tcg_out_mov (s, 3, 4);
628 }
629 }
630 else {
631 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
632 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
633 }
634 break;
635 }
636 label2_ptr = s->code_ptr;
637 tcg_out32 (s, B);
638
639 /* label1: fast path */
640 #ifdef FAST_PATH
641 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
642 #endif
643
644 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
645 tcg_out32 (s, (LWZ
646 | RT (r0)
647 | RA (r0)
648 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
649 - offsetof (CPUTLBEntry, addr_read))
650 ));
651 /* r0 = env->tlb_table[mem_index][index].addend */
652 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
653 /* r0 = env->tlb_table[mem_index][index].addend + addr */
654
655 #else /* !CONFIG_SOFTMMU */
656 r0 = addr_reg;
657 r1 = 3;
658 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
659 #endif
660
661 #ifdef TARGET_WORDS_BIGENDIAN
662 bswap = 0;
663 #else
664 bswap = 1;
665 #endif
666
667 switch (opc) {
668 default:
669 case 0:
670 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
671 break;
672 case 0|4:
673 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
674 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
675 break;
676 case 1:
677 if (bswap)
678 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
679 else
680 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
681 break;
682 case 1|4:
683 if (bswap) {
684 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
685 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
686 }
687 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
688 break;
689 case 2:
690 if (bswap)
691 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
692 else
693 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
694 break;
695 case 3:
696 if (bswap) {
697 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
698 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
699 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
700 }
701 else {
702 #ifdef CONFIG_USE_GUEST_BASE
703 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
704 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
705 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
706 #else
707 if (r0 == data_reg2) {
708 tcg_out32 (s, LWZ | RT (0) | RA (r0));
709 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
710 tcg_out_mov (s, data_reg2, 0);
711 }
712 else {
713 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
714 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
715 }
716 #endif
717 }
718 break;
719 }
720
721 #ifdef CONFIG_SOFTMMU
722 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
723 #endif
724 }
725
726 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
727 {
728 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap, rbase;
729 #ifdef CONFIG_SOFTMMU
730 int r2, ir;
731 void *label1_ptr, *label2_ptr;
732 #endif
733 #if TARGET_LONG_BITS == 64
734 int addr_reg2;
735 #endif
736
737 data_reg = *args++;
738 if (opc == 3)
739 data_reg2 = *args++;
740 else
741 data_reg2 = 0;
742 addr_reg = *args++;
743 #if TARGET_LONG_BITS == 64
744 addr_reg2 = *args++;
745 #endif
746 mem_index = *args;
747
748 #ifdef CONFIG_SOFTMMU
749 r0 = 3;
750 r1 = 4;
751 r2 = 0;
752 rbase = 0;
753
754 tcg_out32 (s, (RLWINM
755 | RA (r0)
756 | RS (addr_reg)
757 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
758 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
759 | ME (31 - CPU_TLB_ENTRY_BITS)
760 )
761 );
762 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
763 tcg_out32 (s, (LWZU
764 | RT (r1)
765 | RA (r0)
766 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
767 )
768 );
769 tcg_out32 (s, (RLWINM
770 | RA (r2)
771 | RS (addr_reg)
772 | SH (0)
773 | MB ((32 - opc) & 31)
774 | ME (31 - TARGET_PAGE_BITS)
775 )
776 );
777
778 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
779 #if TARGET_LONG_BITS == 64
780 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
781 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
782 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
783 #endif
784
785 label1_ptr = s->code_ptr;
786 #ifdef FAST_PATH
787 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
788 #endif
789
790 /* slow path */
791 #if TARGET_LONG_BITS == 32
792 tcg_out_mov (s, 3, addr_reg);
793 ir = 4;
794 #else
795 tcg_out_mov (s, 3, addr_reg2);
796 tcg_out_mov (s, 4, addr_reg);
797 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
798 ir = 5;
799 #else
800 ir = 4;
801 #endif
802 #endif
803
804 switch (opc) {
805 case 0:
806 tcg_out32 (s, (RLWINM
807 | RA (ir)
808 | RS (data_reg)
809 | SH (0)
810 | MB (24)
811 | ME (31)));
812 break;
813 case 1:
814 tcg_out32 (s, (RLWINM
815 | RA (ir)
816 | RS (data_reg)
817 | SH (0)
818 | MB (16)
819 | ME (31)));
820 break;
821 case 2:
822 tcg_out_mov (s, ir, data_reg);
823 break;
824 case 3:
825 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
826 ir = 5;
827 #endif
828 tcg_out_mov (s, ir++, data_reg2);
829 tcg_out_mov (s, ir, data_reg);
830 break;
831 }
832 ir++;
833
834 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
835 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
836 label2_ptr = s->code_ptr;
837 tcg_out32 (s, B);
838
839 /* label1: fast path */
840 #ifdef FAST_PATH
841 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
842 #endif
843
844 tcg_out32 (s, (LWZ
845 | RT (r0)
846 | RA (r0)
847 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
848 - offsetof (CPUTLBEntry, addr_write))
849 ));
850 /* r0 = env->tlb_table[mem_index][index].addend */
851 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
852 /* r0 = env->tlb_table[mem_index][index].addend + addr */
853
854 #else /* !CONFIG_SOFTMMU */
855 r0 = addr_reg;
856 r1 = 3;
857 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
858 #endif
859
860 #ifdef TARGET_WORDS_BIGENDIAN
861 bswap = 0;
862 #else
863 bswap = 1;
864 #endif
865 switch (opc) {
866 case 0:
867 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
868 break;
869 case 1:
870 if (bswap)
871 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
872 else
873 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
874 break;
875 case 2:
876 if (bswap)
877 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
878 else
879 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
880 break;
881 case 3:
882 if (bswap) {
883 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
884 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
885 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
886 }
887 else {
888 #ifdef CONFIG_USE_GUEST_BASE
889 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
890 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
891 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
892 #else
893 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
894 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
895 #endif
896 }
897 break;
898 }
899
900 #ifdef CONFIG_SOFTMMU
901 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
902 #endif
903 }
904
905 void tcg_target_qemu_prologue (TCGContext *s)
906 {
907 int i, frame_size;
908
909 frame_size = 0
910 + LINKAGE_AREA_SIZE
911 + TCG_STATIC_CALL_ARGS_SIZE
912 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
913 ;
914 frame_size = (frame_size + 15) & ~15;
915
916 #ifdef _CALL_AIX
917 {
918 uint32_t addr;
919
920 /* First emit adhoc function descriptor */
921 addr = (uint32_t) s->code_ptr + 12;
922 tcg_out32 (s, addr); /* entry point */
923 s->code_ptr += 8; /* skip TOC and environment pointer */
924 }
925 #endif
926 tcg_out32 (s, MFSPR | RT (0) | LR);
927 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
928 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
929 tcg_out32 (s, (STW
930 | RS (tcg_target_callee_save_regs[i])
931 | RA (1)
932 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
933 )
934 );
935 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
936
937 #ifdef CONFIG_USE_GUEST_BASE
938 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
939 #endif
940
941 tcg_out32 (s, MTSPR | RS (3) | CTR);
942 tcg_out32 (s, BCCTR | BO_ALWAYS);
943 tb_ret_addr = s->code_ptr;
944
945 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
946 tcg_out32 (s, (LWZ
947 | RT (tcg_target_callee_save_regs[i])
948 | RA (1)
949 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
950 )
951 );
952 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
953 tcg_out32 (s, MTSPR | RS (0) | LR);
954 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
955 tcg_out32 (s, BCLR | BO_ALWAYS);
956 }
957
958 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
959 tcg_target_long arg2)
960 {
961 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
962 }
963
964 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
965 tcg_target_long arg2)
966 {
967 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
968 }
969
970 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
971 {
972 if (!si && rt == ra)
973 return;
974
975 if (si == (int16_t) si)
976 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
977 else {
978 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
979 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
980 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
981 }
982 }
983
984 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
985 {
986 ppc_addi (s, reg, reg, val);
987 }
988
989 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
990 int const_arg2, int cr)
991 {
992 int imm;
993 uint32_t op;
994
995 switch (cond) {
996 case TCG_COND_EQ:
997 case TCG_COND_NE:
998 if (const_arg2) {
999 if ((int16_t) arg2 == arg2) {
1000 op = CMPI;
1001 imm = 1;
1002 break;
1003 }
1004 else if ((uint16_t) arg2 == arg2) {
1005 op = CMPLI;
1006 imm = 1;
1007 break;
1008 }
1009 }
1010 op = CMPL;
1011 imm = 0;
1012 break;
1013
1014 case TCG_COND_LT:
1015 case TCG_COND_GE:
1016 case TCG_COND_LE:
1017 case TCG_COND_GT:
1018 if (const_arg2) {
1019 if ((int16_t) arg2 == arg2) {
1020 op = CMPI;
1021 imm = 1;
1022 break;
1023 }
1024 }
1025 op = CMP;
1026 imm = 0;
1027 break;
1028
1029 case TCG_COND_LTU:
1030 case TCG_COND_GEU:
1031 case TCG_COND_LEU:
1032 case TCG_COND_GTU:
1033 if (const_arg2) {
1034 if ((uint16_t) arg2 == arg2) {
1035 op = CMPLI;
1036 imm = 1;
1037 break;
1038 }
1039 }
1040 op = CMPL;
1041 imm = 0;
1042 break;
1043
1044 default:
1045 tcg_abort ();
1046 }
1047 op |= BF (cr);
1048
1049 if (imm)
1050 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1051 else {
1052 if (const_arg2) {
1053 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1054 tcg_out32 (s, op | RA (arg1) | RB (0));
1055 }
1056 else
1057 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1058 }
1059
1060 }
1061
1062 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1063 {
1064 TCGLabel *l = &s->labels[label_index];
1065
1066 if (l->has_value)
1067 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1068 else {
1069 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1070
1071 /* Thanks to Andrzej Zaborowski */
1072 tcg_out32 (s, bc | (val & 0xfffc));
1073 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1074 }
1075 }
1076
1077 static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1078 const int *const_args)
1079 {
1080 int cond = args[4], op;
1081 struct { int bit1; int bit2; int cond2; } bits[] = {
1082 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1083 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1084 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1085 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1086 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1087 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1088 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1089 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1090 }, *b = &bits[cond];
1091
1092 switch (cond) {
1093 case TCG_COND_EQ:
1094 case TCG_COND_NE:
1095 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1096 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1097 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1098 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1099 break;
1100 case TCG_COND_LT:
1101 case TCG_COND_LE:
1102 case TCG_COND_GT:
1103 case TCG_COND_GE:
1104 case TCG_COND_LTU:
1105 case TCG_COND_LEU:
1106 case TCG_COND_GTU:
1107 case TCG_COND_GEU:
1108 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1109 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1110 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1111 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1112 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1113 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1114 break;
1115 default:
1116 tcg_abort();
1117 }
1118 }
1119
1120 static void tcg_out_setcond (TCGContext *s, int cond, TCGArg arg0,
1121 TCGArg arg1, TCGArg arg2, int const_arg2)
1122 {
1123 int crop, sh, arg;
1124
1125 switch (cond) {
1126 case TCG_COND_EQ:
1127 if (const_arg2) {
1128 if (!arg2) {
1129 arg = arg1;
1130 }
1131 else {
1132 arg = 0;
1133 if ((uint16_t) arg2 == arg2) {
1134 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1135 }
1136 else {
1137 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1138 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1139 }
1140 }
1141 }
1142 else {
1143 arg = 0;
1144 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1145 }
1146 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1147 tcg_out32 (s, (RLWINM
1148 | RA (arg0)
1149 | RS (0)
1150 | SH (27)
1151 | MB (5)
1152 | ME (31)
1153 )
1154 );
1155 break;
1156
1157 case TCG_COND_NE:
1158 if (const_arg2) {
1159 if (!arg2) {
1160 arg = arg1;
1161 }
1162 else {
1163 arg = 0;
1164 if ((uint16_t) arg2 == arg2) {
1165 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1166 }
1167 else {
1168 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1169 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1170 }
1171 }
1172 }
1173 else {
1174 arg = 0;
1175 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1176 }
1177
1178 if (arg == arg1 && arg1 == arg0) {
1179 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1180 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1181 }
1182 else {
1183 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1184 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1185 }
1186 break;
1187
1188 case TCG_COND_GT:
1189 case TCG_COND_GTU:
1190 sh = 30;
1191 crop = 0;
1192 goto crtest;
1193
1194 case TCG_COND_LT:
1195 case TCG_COND_LTU:
1196 sh = 29;
1197 crop = 0;
1198 goto crtest;
1199
1200 case TCG_COND_GE:
1201 case TCG_COND_GEU:
1202 sh = 31;
1203 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1204 goto crtest;
1205
1206 case TCG_COND_LE:
1207 case TCG_COND_LEU:
1208 sh = 31;
1209 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1210 crtest:
1211 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1212 if (crop) tcg_out32 (s, crop);
1213 tcg_out32 (s, MFCR | RT (0));
1214 tcg_out32 (s, (RLWINM
1215 | RA (arg0)
1216 | RS (0)
1217 | SH (sh)
1218 | MB (31)
1219 | ME (31)
1220 )
1221 );
1222 break;
1223
1224 default:
1225 tcg_abort ();
1226 }
1227 }
1228
1229 static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1230 const int *const_args)
1231 {
1232 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1233 tcg_out32 (s, MFCR | RT (0));
1234 tcg_out32 (s, (RLWINM
1235 | RA (args[0])
1236 | RS (0)
1237 | SH (31)
1238 | MB (31)
1239 | ME (31)
1240 )
1241 );
1242 }
1243
1244 static void tcg_out_brcond (TCGContext *s, int cond,
1245 TCGArg arg1, TCGArg arg2, int const_arg2,
1246 int label_index)
1247 {
1248 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1249 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1250 }
1251
1252 /* XXX: we implement it at the target level to avoid having to
1253 handle cross basic blocks temporaries */
1254 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1255 const int *const_args)
1256 {
1257 tcg_out_cr7eq_from_cond (s, args, const_args);
1258 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
1259 }
1260
1261 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1262 {
1263 uint32_t *ptr;
1264 long disp = addr - jmp_addr;
1265 unsigned long patch_size;
1266
1267 ptr = (uint32_t *)jmp_addr;
1268
1269 if ((disp << 6) >> 6 != disp) {
1270 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1271 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1272 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1273 ptr[3] = 0x4e800420; /* brctr */
1274 patch_size = 16;
1275 } else {
1276 /* patch the branch destination */
1277 if (disp != 16) {
1278 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1279 patch_size = 4;
1280 } else {
1281 ptr[0] = 0x60000000; /* nop */
1282 ptr[1] = 0x60000000;
1283 ptr[2] = 0x60000000;
1284 ptr[3] = 0x60000000;
1285 patch_size = 16;
1286 }
1287 }
1288 /* flush icache */
1289 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1290 }
1291
1292 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1293 const int *const_args)
1294 {
1295 switch (opc) {
1296 case INDEX_op_exit_tb:
1297 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1298 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1299 break;
1300 case INDEX_op_goto_tb:
1301 if (s->tb_jmp_offset) {
1302 /* direct jump method */
1303
1304 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1305 s->code_ptr += 16;
1306 }
1307 else {
1308 tcg_abort ();
1309 }
1310 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1311 break;
1312 case INDEX_op_br:
1313 {
1314 TCGLabel *l = &s->labels[args[0]];
1315
1316 if (l->has_value) {
1317 tcg_out_b (s, 0, l->u.value);
1318 }
1319 else {
1320 uint32_t val = *(uint32_t *) s->code_ptr;
1321
1322 /* Thanks to Andrzej Zaborowski */
1323 tcg_out32 (s, B | (val & 0x3fffffc));
1324 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1325 }
1326 }
1327 break;
1328 case INDEX_op_call:
1329 tcg_out_call (s, args[0], const_args[0]);
1330 break;
1331 case INDEX_op_jmp:
1332 if (const_args[0]) {
1333 tcg_out_b (s, 0, args[0]);
1334 }
1335 else {
1336 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1337 tcg_out32 (s, BCCTR | BO_ALWAYS);
1338 }
1339 break;
1340 case INDEX_op_movi_i32:
1341 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1342 break;
1343 case INDEX_op_ld8u_i32:
1344 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1345 break;
1346 case INDEX_op_ld8s_i32:
1347 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1348 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1349 break;
1350 case INDEX_op_ld16u_i32:
1351 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1352 break;
1353 case INDEX_op_ld16s_i32:
1354 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1355 break;
1356 case INDEX_op_ld_i32:
1357 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1358 break;
1359 case INDEX_op_st8_i32:
1360 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1361 break;
1362 case INDEX_op_st16_i32:
1363 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1364 break;
1365 case INDEX_op_st_i32:
1366 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1367 break;
1368
1369 case INDEX_op_add_i32:
1370 if (const_args[2])
1371 ppc_addi (s, args[0], args[1], args[2]);
1372 else
1373 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1374 break;
1375 case INDEX_op_sub_i32:
1376 if (const_args[2])
1377 ppc_addi (s, args[0], args[1], -args[2]);
1378 else
1379 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1380 break;
1381
1382 case INDEX_op_and_i32:
1383 if (const_args[2]) {
1384 uint32_t c;
1385
1386 c = args[2];
1387
1388 if (!c) {
1389 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1390 break;
1391 }
1392 #ifdef __PPU__
1393 uint32_t t, n;
1394 int mb, me;
1395
1396 n = c ^ -(c & 1);
1397 t = n + (n & -n);
1398
1399 if ((t & (t - 1)) == 0) {
1400 int lzc, tzc;
1401
1402 if ((c & 0x80000001) == 0x80000001) {
1403 lzc = clz32 (n);
1404 tzc = ctz32 (n);
1405
1406 mb = 32 - tzc;
1407 me = lzc - 1;
1408 }
1409 else {
1410 lzc = clz32 (c);
1411 tzc = ctz32 (c);
1412
1413 mb = lzc;
1414 me = 31 - tzc;
1415 }
1416
1417 tcg_out32 (s, (RLWINM
1418 | RA (args[0])
1419 | RS (args[1])
1420 | SH (0)
1421 | MB (mb)
1422 | ME (me)
1423 )
1424 );
1425 }
1426 else
1427 #endif /* !__PPU__ */
1428 {
1429 if ((c & 0xffff) == c)
1430 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1431 else if ((c & 0xffff0000) == c)
1432 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1433 | ((c >> 16) & 0xffff));
1434 else {
1435 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1436 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1437 }
1438 }
1439 }
1440 else
1441 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1442 break;
1443 case INDEX_op_or_i32:
1444 if (const_args[2]) {
1445 if (args[2] & 0xffff) {
1446 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1447 | (args[2] & 0xffff));
1448 if (args[2] >> 16)
1449 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1450 | ((args[2] >> 16) & 0xffff));
1451 }
1452 else {
1453 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1454 | ((args[2] >> 16) & 0xffff));
1455 }
1456 }
1457 else
1458 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1459 break;
1460 case INDEX_op_xor_i32:
1461 if (const_args[2]) {
1462 if ((args[2] & 0xffff) == args[2])
1463 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1464 | (args[2] & 0xffff));
1465 else if ((args[2] & 0xffff0000) == args[2])
1466 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1467 | ((args[2] >> 16) & 0xffff));
1468 else {
1469 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1470 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1471 }
1472 }
1473 else
1474 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1475 break;
1476 case INDEX_op_andc_i32:
1477 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1478 break;
1479 case INDEX_op_orc_i32:
1480 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1481 break;
1482
1483 case INDEX_op_mul_i32:
1484 if (const_args[2]) {
1485 if (args[2] == (int16_t) args[2])
1486 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1487 | (args[2] & 0xffff));
1488 else {
1489 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1490 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1491 }
1492 }
1493 else
1494 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1495 break;
1496
1497 case INDEX_op_div_i32:
1498 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1499 break;
1500
1501 case INDEX_op_divu_i32:
1502 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1503 break;
1504
1505 case INDEX_op_rem_i32:
1506 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1507 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1508 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1509 break;
1510
1511 case INDEX_op_remu_i32:
1512 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1513 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1514 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1515 break;
1516
1517 case INDEX_op_mulu2_i32:
1518 if (args[0] == args[2] || args[0] == args[3]) {
1519 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1520 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1521 tcg_out_mov (s, args[0], 0);
1522 }
1523 else {
1524 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1525 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1526 }
1527 break;
1528
1529 case INDEX_op_shl_i32:
1530 if (const_args[2]) {
1531 tcg_out32 (s, (RLWINM
1532 | RA (args[0])
1533 | RS (args[1])
1534 | SH (args[2])
1535 | MB (0)
1536 | ME (31 - args[2])
1537 )
1538 );
1539 }
1540 else
1541 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1542 break;
1543 case INDEX_op_shr_i32:
1544 if (const_args[2]) {
1545 tcg_out32 (s, (RLWINM
1546 | RA (args[0])
1547 | RS (args[1])
1548 | SH (32 - args[2])
1549 | MB (args[2])
1550 | ME (31)
1551 )
1552 );
1553 }
1554 else
1555 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1556 break;
1557 case INDEX_op_sar_i32:
1558 if (const_args[2])
1559 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1560 else
1561 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1562 break;
1563 case INDEX_op_rotl_i32:
1564 {
1565 int op = 0
1566 | RA (args[0])
1567 | RS (args[1])
1568 | MB (0)
1569 | ME (31)
1570 | (const_args[2] ? RLWINM | SH (args[2])
1571 : RLWNM | RB (args[2]))
1572 ;
1573 tcg_out32 (s, op);
1574 }
1575 break;
1576 case INDEX_op_rotr_i32:
1577 if (const_args[2]) {
1578 if (!args[2]) {
1579 tcg_out_mov (s, args[0], args[1]);
1580 }
1581 else {
1582 tcg_out32 (s, RLWINM
1583 | RA (args[0])
1584 | RS (args[1])
1585 | SH (32 - args[2])
1586 | MB (0)
1587 | ME (31)
1588 );
1589 }
1590 }
1591 else {
1592 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
1593 tcg_out32 (s, RLWNM
1594 | RA (args[0])
1595 | RS (args[1])
1596 | RB (0)
1597 | MB (0)
1598 | ME (31)
1599 );
1600 }
1601 break;
1602
1603 case INDEX_op_add2_i32:
1604 if (args[0] == args[3] || args[0] == args[5]) {
1605 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1606 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1607 tcg_out_mov (s, args[0], 0);
1608 }
1609 else {
1610 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1611 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1612 }
1613 break;
1614 case INDEX_op_sub2_i32:
1615 if (args[0] == args[3] || args[0] == args[5]) {
1616 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1617 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1618 tcg_out_mov (s, args[0], 0);
1619 }
1620 else {
1621 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1622 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1623 }
1624 break;
1625
1626 case INDEX_op_brcond_i32:
1627 /*
1628 args[0] = r0
1629 args[1] = r1
1630 args[2] = cond
1631 args[3] = r1 is const
1632 args[4] = label_index
1633 */
1634 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1635 break;
1636 case INDEX_op_brcond2_i32:
1637 tcg_out_brcond2(s, args, const_args);
1638 break;
1639
1640 case INDEX_op_neg_i32:
1641 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1642 break;
1643
1644 case INDEX_op_not_i32:
1645 tcg_out32 (s, NOR | SAB (args[1], args[0], args[0]));
1646 break;
1647
1648 case INDEX_op_qemu_ld8u:
1649 tcg_out_qemu_ld(s, args, 0);
1650 break;
1651 case INDEX_op_qemu_ld8s:
1652 tcg_out_qemu_ld(s, args, 0 | 4);
1653 break;
1654 case INDEX_op_qemu_ld16u:
1655 tcg_out_qemu_ld(s, args, 1);
1656 break;
1657 case INDEX_op_qemu_ld16s:
1658 tcg_out_qemu_ld(s, args, 1 | 4);
1659 break;
1660 case INDEX_op_qemu_ld32u:
1661 tcg_out_qemu_ld(s, args, 2);
1662 break;
1663 case INDEX_op_qemu_ld64:
1664 tcg_out_qemu_ld(s, args, 3);
1665 break;
1666 case INDEX_op_qemu_st8:
1667 tcg_out_qemu_st(s, args, 0);
1668 break;
1669 case INDEX_op_qemu_st16:
1670 tcg_out_qemu_st(s, args, 1);
1671 break;
1672 case INDEX_op_qemu_st32:
1673 tcg_out_qemu_st(s, args, 2);
1674 break;
1675 case INDEX_op_qemu_st64:
1676 tcg_out_qemu_st(s, args, 3);
1677 break;
1678
1679 case INDEX_op_ext8s_i32:
1680 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1681 break;
1682 case INDEX_op_ext8u_i32:
1683 tcg_out32 (s, RLWINM
1684 | RA (args[0])
1685 | RS (args[1])
1686 | SH (0)
1687 | MB (24)
1688 | ME (31)
1689 );
1690 break;
1691 case INDEX_op_ext16s_i32:
1692 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1693 break;
1694 case INDEX_op_ext16u_i32:
1695 tcg_out32 (s, RLWINM
1696 | RA (args[0])
1697 | RS (args[1])
1698 | SH (0)
1699 | MB (16)
1700 | ME (31)
1701 );
1702 break;
1703
1704 case INDEX_op_setcond_i32:
1705 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1706 break;
1707 case INDEX_op_setcond2_i32:
1708 tcg_out_setcond2 (s, args, const_args);
1709 break;
1710
1711 default:
1712 tcg_dump_ops (s, stderr);
1713 tcg_abort ();
1714 }
1715 }
1716
1717 static const TCGTargetOpDef ppc_op_defs[] = {
1718 { INDEX_op_exit_tb, { } },
1719 { INDEX_op_goto_tb, { } },
1720 { INDEX_op_call, { "ri" } },
1721 { INDEX_op_jmp, { "ri" } },
1722 { INDEX_op_br, { } },
1723
1724 { INDEX_op_mov_i32, { "r", "r" } },
1725 { INDEX_op_movi_i32, { "r" } },
1726 { INDEX_op_ld8u_i32, { "r", "r" } },
1727 { INDEX_op_ld8s_i32, { "r", "r" } },
1728 { INDEX_op_ld16u_i32, { "r", "r" } },
1729 { INDEX_op_ld16s_i32, { "r", "r" } },
1730 { INDEX_op_ld_i32, { "r", "r" } },
1731 { INDEX_op_st8_i32, { "r", "r" } },
1732 { INDEX_op_st16_i32, { "r", "r" } },
1733 { INDEX_op_st_i32, { "r", "r" } },
1734
1735 { INDEX_op_add_i32, { "r", "r", "ri" } },
1736 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1737 { INDEX_op_div_i32, { "r", "r", "r" } },
1738 { INDEX_op_divu_i32, { "r", "r", "r" } },
1739 { INDEX_op_rem_i32, { "r", "r", "r" } },
1740 { INDEX_op_remu_i32, { "r", "r", "r" } },
1741 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1742 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1743 { INDEX_op_and_i32, { "r", "r", "ri" } },
1744 { INDEX_op_or_i32, { "r", "r", "ri" } },
1745 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1746
1747 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1748 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1749 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1750
1751 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1752 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1753
1754 { INDEX_op_brcond_i32, { "r", "ri" } },
1755
1756 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1757 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1758 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1759
1760 { INDEX_op_neg_i32, { "r", "r" } },
1761 { INDEX_op_not_i32, { "r", "r" } },
1762
1763 { INDEX_op_andc_i32, { "r", "r", "r" } },
1764 { INDEX_op_orc_i32, { "r", "r", "r" } },
1765
1766 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1767 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1768
1769 #if TARGET_LONG_BITS == 32
1770 { INDEX_op_qemu_ld8u, { "r", "L" } },
1771 { INDEX_op_qemu_ld8s, { "r", "L" } },
1772 { INDEX_op_qemu_ld16u, { "r", "L" } },
1773 { INDEX_op_qemu_ld16s, { "r", "L" } },
1774 { INDEX_op_qemu_ld32u, { "r", "L" } },
1775 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1776
1777 { INDEX_op_qemu_st8, { "K", "K" } },
1778 { INDEX_op_qemu_st16, { "K", "K" } },
1779 { INDEX_op_qemu_st32, { "K", "K" } },
1780 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1781 #else
1782 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1783 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1784 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1785 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1786 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1787 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1788
1789 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1790 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1791 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1792 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1793 #endif
1794
1795 { INDEX_op_ext8s_i32, { "r", "r" } },
1796 { INDEX_op_ext8u_i32, { "r", "r" } },
1797 { INDEX_op_ext16s_i32, { "r", "r" } },
1798 { INDEX_op_ext16u_i32, { "r", "r" } },
1799
1800 { -1 },
1801 };
1802
1803 void tcg_target_init(TCGContext *s)
1804 {
1805 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1806 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1807 (1 << TCG_REG_R0) |
1808 #ifdef _CALL_DARWIN
1809 (1 << TCG_REG_R2) |
1810 #endif
1811 (1 << TCG_REG_R3) |
1812 (1 << TCG_REG_R4) |
1813 (1 << TCG_REG_R5) |
1814 (1 << TCG_REG_R6) |
1815 (1 << TCG_REG_R7) |
1816 (1 << TCG_REG_R8) |
1817 (1 << TCG_REG_R9) |
1818 (1 << TCG_REG_R10) |
1819 (1 << TCG_REG_R11) |
1820 (1 << TCG_REG_R12)
1821 );
1822
1823 tcg_regset_clear(s->reserved_regs);
1824 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1825 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1826 #ifndef _CALL_DARWIN
1827 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1828 #endif
1829 #ifdef _CALL_SYSV
1830 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1831 #endif
1832 #ifdef CONFIG_USE_GUEST_BASE
1833 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1834 #endif
1835
1836 tcg_add_target_add_op_defs(ppc_op_defs);
1837 }
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