hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21
  22 #define MP_MISC_BASE            0x80002000
  23 #define MP_MISC_SIZE            0x00001000
  24
  25 #define MP_ETH_BASE             0x80008000
  26 #define MP_ETH_SIZE             0x00001000
  27
  28 #define MP_WLAN_BASE            0x8000C000
  29 #define MP_WLAN_SIZE            0x00000800
  30
  31 #define MP_UART1_BASE           0x8000C840
  32 #define MP_UART2_BASE           0x8000C940
  33
  34 #define MP_GPIO_BASE            0x8000D000
  35 #define MP_GPIO_SIZE            0x00001000
  36
  37 #define MP_FLASHCFG_BASE        0x90006000
  38 #define MP_FLASHCFG_SIZE        0x00001000
  39
  40 #define MP_AUDIO_BASE           0x90007000
  41
  42 #define MP_PIC_BASE             0x90008000
  43 #define MP_PIC_SIZE             0x00001000
  44
  45 #define MP_PIT_BASE             0x90009000
  46 #define MP_PIT_SIZE             0x00001000
  47
  48 #define MP_LCD_BASE             0x9000c000
  49 #define MP_LCD_SIZE             0x00001000
  50
  51 #define MP_SRAM_BASE            0xC0000000
  52 #define MP_SRAM_SIZE            0x00020000
  53
  54 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  55 #define MP_FLASH_SIZE_MAX       32*1024*1024
  56
  57 #define MP_TIMER1_IRQ           4
  58 #define MP_TIMER2_IRQ           5
  59 #define MP_TIMER3_IRQ           6
  60 #define MP_TIMER4_IRQ           7
  61 #define MP_EHCI_IRQ             8
  62 #define MP_ETH_IRQ              9
  63 #define MP_UART1_IRQ            11
  64 #define MP_UART2_IRQ            11
  65 #define MP_GPIO_IRQ             12
  66 #define MP_RTC_IRQ              28
  67 #define MP_AUDIO_IRQ            30
  68
  69 /* Wolfson 8750 I2C address */
  70 #define MP_WM_ADDR              0x34
  71
  72 /* Ethernet register offsets */
  73 #define MP_ETH_SMIR             0x010
  74 #define MP_ETH_PCXR             0x408
  75 #define MP_ETH_SDCMR            0x448
  76 #define MP_ETH_ICR              0x450
  77 #define MP_ETH_IMR              0x458
  78 #define MP_ETH_FRDP0            0x480
  79 #define MP_ETH_FRDP1            0x484
  80 #define MP_ETH_FRDP2            0x488
  81 #define MP_ETH_FRDP3            0x48C
  82 #define MP_ETH_CRDP0            0x4A0
  83 #define MP_ETH_CRDP1            0x4A4
  84 #define MP_ETH_CRDP2            0x4A8
  85 #define MP_ETH_CRDP3            0x4AC
  86 #define MP_ETH_CTDP0            0x4E0
  87 #define MP_ETH_CTDP1            0x4E4
  88 #define MP_ETH_CTDP2            0x4E8
  89 #define MP_ETH_CTDP3            0x4EC
  90
  91 /* MII PHY access */
  92 #define MP_ETH_SMIR_DATA        0x0000FFFF
  93 #define MP_ETH_SMIR_ADDR        0x03FF0000
  94 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  95 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  96
  97 /* PHY registers */
  98 #define MP_ETH_PHY1_BMSR        0x00210000
  99 #define MP_ETH_PHY1_PHYSID1     0x00410000
 100 #define MP_ETH_PHY1_PHYSID2     0x00610000
 101
 102 #define MP_PHY_BMSR_LINK        0x0004
 103 #define MP_PHY_BMSR_AUTONEG     0x0008
 104
 105 #define MP_PHY_88E3015          0x01410E20
 106
 107 /* TX descriptor status */
 108 #define MP_ETH_TX_OWN           (1 << 31)
 109
 110 /* RX descriptor status */
 111 #define MP_ETH_RX_OWN           (1 << 31)
 112
 113 /* Interrupt cause/mask bits */
 114 #define MP_ETH_IRQ_RX_BIT       0
 115 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 116 #define MP_ETH_IRQ_TXHI_BIT     2
 117 #define MP_ETH_IRQ_TXLO_BIT     3
 118
 119 /* Port config bits */
 120 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 121
 122 /* SDMA command bits */
 123 #define MP_ETH_CMD_TXHI         (1 << 23)
 124 #define MP_ETH_CMD_TXLO         (1 << 22)
 125
 126 typedef struct mv88w8618_tx_desc {
 127     uint32_t cmdstat;
 128     uint16_t res;
 129     uint16_t bytes;
 130     uint32_t buffer;
 131     uint32_t next;
 132 } mv88w8618_tx_desc;
 133
 134 typedef struct mv88w8618_rx_desc {
 135     uint32_t cmdstat;
 136     uint16_t bytes;
 137     uint16_t buffer_size;
 138     uint32_t buffer;
 139     uint32_t next;
 140 } mv88w8618_rx_desc;
 141
 142 typedef struct mv88w8618_eth_state {
 143     SysBusDevice busdev;
 144     qemu_irq irq;
 145     uint32_t smir;
 146     uint32_t icr;
 147     uint32_t imr;
 148     int mmio_index;
 149     uint32_t vlan_header;
 150     uint32_t tx_queue[2];
 151     uint32_t rx_queue[4];
 152     uint32_t frx_queue[4];
 153     uint32_t cur_rx[4];
 154     NICState *nic;
 155     NICConf conf;
 156 } mv88w8618_eth_state;
 157
 158 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 159 {
 160     cpu_to_le32s(&desc->cmdstat);
 161     cpu_to_le16s(&desc->bytes);
 162     cpu_to_le16s(&desc->buffer_size);
 163     cpu_to_le32s(&desc->buffer);
 164     cpu_to_le32s(&desc->next);
 165     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 166 }
 167
 168 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 169 {
 170     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 171     le32_to_cpus(&desc->cmdstat);
 172     le16_to_cpus(&desc->bytes);
 173     le16_to_cpus(&desc->buffer_size);
 174     le32_to_cpus(&desc->buffer);
 175     le32_to_cpus(&desc->next);
 176 }
 177
 178 static int eth_can_receive(VLANClientState *nc)
 179 {
 180     return 1;
 181 }
 182
 183 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 184 {
 185     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 186     uint32_t desc_addr;
 187     mv88w8618_rx_desc desc;
 188     int i;
 189
 190     for (i = 0; i < 4; i++) {
 191         desc_addr = s->cur_rx[i];
 192         if (!desc_addr) {
 193             continue;
 194         }
 195         do {
 196             eth_rx_desc_get(desc_addr, &desc);
 197             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 198                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 199                                           buf, size);
 200                 desc.bytes = size + s->vlan_header;
 201                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 202                 s->cur_rx[i] = desc.next;
 203
 204                 s->icr |= MP_ETH_IRQ_RX;
 205                 if (s->icr & s->imr) {
 206                     qemu_irq_raise(s->irq);
 207                 }
 208                 eth_rx_desc_put(desc_addr, &desc);
 209                 return size;
 210             }
 211             desc_addr = desc.next;
 212         } while (desc_addr != s->rx_queue[i]);
 213     }
 214     return size;
 215 }
 216
 217 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 218 {
 219     cpu_to_le32s(&desc->cmdstat);
 220     cpu_to_le16s(&desc->res);
 221     cpu_to_le16s(&desc->bytes);
 222     cpu_to_le32s(&desc->buffer);
 223     cpu_to_le32s(&desc->next);
 224     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 225 }
 226
 227 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 228 {
 229     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 230     le32_to_cpus(&desc->cmdstat);
 231     le16_to_cpus(&desc->res);
 232     le16_to_cpus(&desc->bytes);
 233     le32_to_cpus(&desc->buffer);
 234     le32_to_cpus(&desc->next);
 235 }
 236
 237 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 238 {
 239     uint32_t desc_addr = s->tx_queue[queue_index];
 240     mv88w8618_tx_desc desc;
 241     uint8_t buf[2048];
 242     int len;
 243
 244     if (!desc_addr) {
 245         return;
 246     }
 247     do {
 248         eth_tx_desc_get(desc_addr, &desc);
 249         if (desc.cmdstat & MP_ETH_TX_OWN) {
 250             len = desc.bytes;
 251             if (len < 2048) {
 252                 cpu_physical_memory_read(desc.buffer, buf, len);
 253                 qemu_send_packet(&s->nic->nc, buf, len);
 254             }
 255             desc.cmdstat &= ~MP_ETH_TX_OWN;
 256             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 257             eth_tx_desc_put(desc_addr, &desc);
 258         }
 259         desc_addr = desc.next;
 260     } while (desc_addr != s->tx_queue[queue_index]);
 261 }
 262
 263 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 264 {
 265     mv88w8618_eth_state *s = opaque;
 266
 267     switch (offset) {
 268     case MP_ETH_SMIR:
 269         if (s->smir & MP_ETH_SMIR_OPCODE) {
 270             switch (s->smir & MP_ETH_SMIR_ADDR) {
 271             case MP_ETH_PHY1_BMSR:
 272                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 273                        MP_ETH_SMIR_RDVALID;
 274             case MP_ETH_PHY1_PHYSID1:
 275                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 276             case MP_ETH_PHY1_PHYSID2:
 277                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 278             default:
 279                 return MP_ETH_SMIR_RDVALID;
 280             }
 281         }
 282         return 0;
 283
 284     case MP_ETH_ICR:
 285         return s->icr;
 286
 287     case MP_ETH_IMR:
 288         return s->imr;
 289
 290     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 291         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 292
 293     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 294         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 295
 296     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 297         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 298
 299     default:
 300         return 0;
 301     }
 302 }
 303
 304 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 305                                 uint32_t value)
 306 {
 307     mv88w8618_eth_state *s = opaque;
 308
 309     switch (offset) {
 310     case MP_ETH_SMIR:
 311         s->smir = value;
 312         break;
 313
 314     case MP_ETH_PCXR:
 315         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 316         break;
 317
 318     case MP_ETH_SDCMR:
 319         if (value & MP_ETH_CMD_TXHI) {
 320             eth_send(s, 1);
 321         }
 322         if (value & MP_ETH_CMD_TXLO) {
 323             eth_send(s, 0);
 324         }
 325         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 326             qemu_irq_raise(s->irq);
 327         }
 328         break;
 329
 330     case MP_ETH_ICR:
 331         s->icr &= value;
 332         break;
 333
 334     case MP_ETH_IMR:
 335         s->imr = value;
 336         if (s->icr & s->imr) {
 337             qemu_irq_raise(s->irq);
 338         }
 339         break;
 340
 341     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 342         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 343         break;
 344
 345     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 346         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 347             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 348         break;
 349
 350     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 351         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 352         break;
 353     }
 354 }
 355
 356 static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
 357     mv88w8618_eth_read,
 358     mv88w8618_eth_read,
 359     mv88w8618_eth_read
 360 };
 361
 362 static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
 363     mv88w8618_eth_write,
 364     mv88w8618_eth_write,
 365     mv88w8618_eth_write
 366 };
 367
 368 static void eth_cleanup(VLANClientState *nc)
 369 {
 370     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 371
 372     s->nic = NULL;
 373 }
 374
 375 static NetClientInfo net_mv88w8618_info = {
 376     .type = NET_CLIENT_TYPE_NIC,
 377     .size = sizeof(NICState),
 378     .can_receive = eth_can_receive,
 379     .receive = eth_receive,
 380     .cleanup = eth_cleanup,
 381 };
 382
 383 static int mv88w8618_eth_init(SysBusDevice *dev)
 384 {
 385     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 386
 387     sysbus_init_irq(dev, &s->irq);
 388     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 389                           dev->qdev.info->name, dev->qdev.id, s);
 390     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 391                                            mv88w8618_eth_writefn, s);
 392     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 393     return 0;
 394 }
 395
 396 static const VMStateDescription mv88w8618_eth_vmsd = {
 397     .name = "mv88w8618_eth",
 398     .version_id = 1,
 399     .minimum_version_id = 1,
 400     .minimum_version_id_old = 1,
 401     .fields = (VMStateField[]) {
 402         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 403         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 404         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 405         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 406         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 407         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 408         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 409         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 410         VMSTATE_END_OF_LIST()
 411     }
 412 };
 413
 414 static SysBusDeviceInfo mv88w8618_eth_info = {
 415     .init = mv88w8618_eth_init,
 416     .qdev.name = "mv88w8618_eth",
 417     .qdev.size = sizeof(mv88w8618_eth_state),
 418     .qdev.vmsd = &mv88w8618_eth_vmsd,
 419     .qdev.props = (Property[]) {
 420         DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 421         DEFINE_PROP_END_OF_LIST(),
 422     },
 423 };
 424
 425 /* LCD register offsets */
 426 #define MP_LCD_IRQCTRL          0x180
 427 #define MP_LCD_IRQSTAT          0x184
 428 #define MP_LCD_SPICTRL          0x1ac
 429 #define MP_LCD_INST             0x1bc
 430 #define MP_LCD_DATA             0x1c0
 431
 432 /* Mode magics */
 433 #define MP_LCD_SPI_DATA         0x00100011
 434 #define MP_LCD_SPI_CMD          0x00104011
 435 #define MP_LCD_SPI_INVALID      0x00000000
 436
 437 /* Commmands */
 438 #define MP_LCD_INST_SETPAGE0    0xB0
 439 /* ... */
 440 #define MP_LCD_INST_SETPAGE7    0xB7
 441
 442 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 443
 444 typedef struct musicpal_lcd_state {
 445     SysBusDevice busdev;
 446     uint32_t brightness;
 447     uint32_t mode;
 448     uint32_t irqctrl;
 449     uint32_t page;
 450     uint32_t page_off;
 451     DisplayState *ds;
 452     uint8_t video_ram[128*64/8];
 453 } musicpal_lcd_state;
 454
 455 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 456 {
 457     switch (s->brightness) {
 458     case 7:
 459         return col;
 460     case 0:
 461         return 0;
 462     default:
 463         return (col * s->brightness) / 7;
 464     }
 465 }
 466
 467 #define SET_LCD_PIXEL(depth, type) \
 468 static inline void glue(set_lcd_pixel, depth) \
 469         (musicpal_lcd_state *s, int x, int y, type col) \
 470 { \
 471     int dx, dy; \
 472     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 473 \
 474     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 475         for (dx = 0; dx < 3; dx++, pixel++) \
 476             *pixel = col; \
 477 }
 478 SET_LCD_PIXEL(8, uint8_t)
 479 SET_LCD_PIXEL(16, uint16_t)
 480 SET_LCD_PIXEL(32, uint32_t)
 481
 482 #include "pixel_ops.h"
 483
 484 static void lcd_refresh(void *opaque)
 485 {
 486     musicpal_lcd_state *s = opaque;
 487     int x, y, col;
 488
 489     switch (ds_get_bits_per_pixel(s->ds)) {
 490     case 0:
 491         return;
 492 #define LCD_REFRESH(depth, func) \
 493     case depth: \
 494         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 495                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 496                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 497         for (x = 0; x < 128; x++) { \
 498             for (y = 0; y < 64; y++) { \
 499                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 500                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 501                 } else { \
 502                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 503                 } \
 504             } \
 505         } \
 506         break;
 507     LCD_REFRESH(8, rgb_to_pixel8)
 508     LCD_REFRESH(16, rgb_to_pixel16)
 509     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 510                      rgb_to_pixel32bgr : rgb_to_pixel32))
 511     default:
 512         hw_error("unsupported colour depth %i\n",
 513                   ds_get_bits_per_pixel(s->ds));
 514     }
 515
 516     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 517 }
 518
 519 static void lcd_invalidate(void *opaque)
 520 {
 521 }
 522
 523 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 524 {
 525     musicpal_lcd_state *s = opaque;
 526     s->brightness &= ~(1 << irq);
 527     s->brightness |= level << irq;
 528 }
 529
 530 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 531 {
 532     musicpal_lcd_state *s = opaque;
 533
 534     switch (offset) {
 535     case MP_LCD_IRQCTRL:
 536         return s->irqctrl;
 537
 538     default:
 539         return 0;
 540     }
 541 }
 542
 543 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 544                                uint32_t value)
 545 {
 546     musicpal_lcd_state *s = opaque;
 547
 548     switch (offset) {
 549     case MP_LCD_IRQCTRL:
 550         s->irqctrl = value;
 551         break;
 552
 553     case MP_LCD_SPICTRL:
 554         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 555             s->mode = value;
 556         } else {
 557             s->mode = MP_LCD_SPI_INVALID;
 558         }
 559         break;
 560
 561     case MP_LCD_INST:
 562         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 563             s->page = value - MP_LCD_INST_SETPAGE0;
 564             s->page_off = 0;
 565         }
 566         break;
 567
 568     case MP_LCD_DATA:
 569         if (s->mode == MP_LCD_SPI_CMD) {
 570             if (value >= MP_LCD_INST_SETPAGE0 &&
 571                 value <= MP_LCD_INST_SETPAGE7) {
 572                 s->page = value - MP_LCD_INST_SETPAGE0;
 573                 s->page_off = 0;
 574             }
 575         } else if (s->mode == MP_LCD_SPI_DATA) {
 576             s->video_ram[s->page*128 + s->page_off] = value;
 577             s->page_off = (s->page_off + 1) & 127;
 578         }
 579         break;
 580     }
 581 }
 582
 583 static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
 584     musicpal_lcd_read,
 585     musicpal_lcd_read,
 586     musicpal_lcd_read
 587 };
 588
 589 static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
 590     musicpal_lcd_write,
 591     musicpal_lcd_write,
 592     musicpal_lcd_write
 593 };
 594
 595 static int musicpal_lcd_init(SysBusDevice *dev)
 596 {
 597     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 598     int iomemtype;
 599
 600     s->brightness = 7;
 601
 602     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 603                                        musicpal_lcd_writefn, s);
 604     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 605
 606     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 607                                  NULL, NULL, s);
 608     qemu_console_resize(s->ds, 128*3, 64*3);
 609
 610     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 611
 612     return 0;
 613 }
 614
 615 static const VMStateDescription musicpal_lcd_vmsd = {
 616     .name = "musicpal_lcd",
 617     .version_id = 1,
 618     .minimum_version_id = 1,
 619     .minimum_version_id_old = 1,
 620     .fields = (VMStateField[]) {
 621         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 622         VMSTATE_UINT32(mode, musicpal_lcd_state),
 623         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 624         VMSTATE_UINT32(page, musicpal_lcd_state),
 625         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 626         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 627         VMSTATE_END_OF_LIST()
 628     }
 629 };
 630
 631 static SysBusDeviceInfo musicpal_lcd_info = {
 632     .init = musicpal_lcd_init,
 633     .qdev.name = "musicpal_lcd",
 634     .qdev.size = sizeof(musicpal_lcd_state),
 635     .qdev.vmsd = &musicpal_lcd_vmsd,
 636 };
 637
 638 /* PIC register offsets */
 639 #define MP_PIC_STATUS           0x00
 640 #define MP_PIC_ENABLE_SET       0x08
 641 #define MP_PIC_ENABLE_CLR       0x0C
 642
 643 typedef struct mv88w8618_pic_state
 644 {
 645     SysBusDevice busdev;
 646     uint32_t level;
 647     uint32_t enabled;
 648     qemu_irq parent_irq;
 649 } mv88w8618_pic_state;
 650
 651 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 652 {
 653     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 654 }
 655
 656 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 657 {
 658     mv88w8618_pic_state *s = opaque;
 659
 660     if (level) {
 661         s->level |= 1 << irq;
 662     } else {
 663         s->level &= ~(1 << irq);
 664     }
 665     mv88w8618_pic_update(s);
 666 }
 667
 668 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 669 {
 670     mv88w8618_pic_state *s = opaque;
 671
 672     switch (offset) {
 673     case MP_PIC_STATUS:
 674         return s->level & s->enabled;
 675
 676     default:
 677         return 0;
 678     }
 679 }
 680
 681 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 682                                 uint32_t value)
 683 {
 684     mv88w8618_pic_state *s = opaque;
 685
 686     switch (offset) {
 687     case MP_PIC_ENABLE_SET:
 688         s->enabled |= value;
 689         break;
 690
 691     case MP_PIC_ENABLE_CLR:
 692         s->enabled &= ~value;
 693         s->level &= ~value;
 694         break;
 695     }
 696     mv88w8618_pic_update(s);
 697 }
 698
 699 static void mv88w8618_pic_reset(DeviceState *d)
 700 {
 701     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 702                                          sysbus_from_qdev(d));
 703
 704     s->level = 0;
 705     s->enabled = 0;
 706 }
 707
 708 static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
 709     mv88w8618_pic_read,
 710     mv88w8618_pic_read,
 711     mv88w8618_pic_read
 712 };
 713
 714 static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
 715     mv88w8618_pic_write,
 716     mv88w8618_pic_write,
 717     mv88w8618_pic_write
 718 };
 719
 720 static int mv88w8618_pic_init(SysBusDevice *dev)
 721 {
 722     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 723     int iomemtype;
 724
 725     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 726     sysbus_init_irq(dev, &s->parent_irq);
 727     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
 728                                        mv88w8618_pic_writefn, s);
 729     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
 730     return 0;
 731 }
 732
 733 static const VMStateDescription mv88w8618_pic_vmsd = {
 734     .name = "mv88w8618_pic",
 735     .version_id = 1,
 736     .minimum_version_id = 1,
 737     .minimum_version_id_old = 1,
 738     .fields = (VMStateField[]) {
 739         VMSTATE_UINT32(level, mv88w8618_pic_state),
 740         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 741         VMSTATE_END_OF_LIST()
 742     }
 743 };
 744
 745 static SysBusDeviceInfo mv88w8618_pic_info = {
 746     .init = mv88w8618_pic_init,
 747     .qdev.name = "mv88w8618_pic",
 748     .qdev.size = sizeof(mv88w8618_pic_state),
 749     .qdev.reset = mv88w8618_pic_reset,
 750     .qdev.vmsd = &mv88w8618_pic_vmsd,
 751 };
 752
 753 /* PIT register offsets */
 754 #define MP_PIT_TIMER1_LENGTH    0x00
 755 /* ... */
 756 #define MP_PIT_TIMER4_LENGTH    0x0C
 757 #define MP_PIT_CONTROL          0x10
 758 #define MP_PIT_TIMER1_VALUE     0x14
 759 /* ... */
 760 #define MP_PIT_TIMER4_VALUE     0x20
 761 #define MP_BOARD_RESET          0x34
 762
 763 /* Magic board reset value (probably some watchdog behind it) */
 764 #define MP_BOARD_RESET_MAGIC    0x10000
 765
 766 typedef struct mv88w8618_timer_state {
 767     ptimer_state *ptimer;
 768     uint32_t limit;
 769     int freq;
 770     qemu_irq irq;
 771 } mv88w8618_timer_state;
 772
 773 typedef struct mv88w8618_pit_state {
 774     SysBusDevice busdev;
 775     mv88w8618_timer_state timer[4];
 776 } mv88w8618_pit_state;
 777
 778 static void mv88w8618_timer_tick(void *opaque)
 779 {
 780     mv88w8618_timer_state *s = opaque;
 781
 782     qemu_irq_raise(s->irq);
 783 }
 784
 785 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 786                                  uint32_t freq)
 787 {
 788     QEMUBH *bh;
 789
 790     sysbus_init_irq(dev, &s->irq);
 791     s->freq = freq;
 792
 793     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 794     s->ptimer = ptimer_init(bh);
 795 }
 796
 797 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
 798 {
 799     mv88w8618_pit_state *s = opaque;
 800     mv88w8618_timer_state *t;
 801
 802     switch (offset) {
 803     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 804         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 805         return ptimer_get_count(t->ptimer);
 806
 807     default:
 808         return 0;
 809     }
 810 }
 811
 812 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 813                                 uint32_t value)
 814 {
 815     mv88w8618_pit_state *s = opaque;
 816     mv88w8618_timer_state *t;
 817     int i;
 818
 819     switch (offset) {
 820     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 821         t = &s->timer[offset >> 2];
 822         t->limit = value;
 823         if (t->limit > 0) {
 824             ptimer_set_limit(t->ptimer, t->limit, 1);
 825         } else {
 826             ptimer_stop(t->ptimer);
 827         }
 828         break;
 829
 830     case MP_PIT_CONTROL:
 831         for (i = 0; i < 4; i++) {
 832             t = &s->timer[i];
 833             if (value & 0xf && t->limit > 0) {
 834                 ptimer_set_limit(t->ptimer, t->limit, 0);
 835                 ptimer_set_freq(t->ptimer, t->freq);
 836                 ptimer_run(t->ptimer, 0);
 837             } else {
 838                 ptimer_stop(t->ptimer);
 839             }
 840             value >>= 4;
 841         }
 842         break;
 843
 844     case MP_BOARD_RESET:
 845         if (value == MP_BOARD_RESET_MAGIC) {
 846             qemu_system_reset_request();
 847         }
 848         break;
 849     }
 850 }
 851
 852 static void mv88w8618_pit_reset(DeviceState *d)
 853 {
 854     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 855                                          sysbus_from_qdev(d));
 856     int i;
 857
 858     for (i = 0; i < 4; i++) {
 859         ptimer_stop(s->timer[i].ptimer);
 860         s->timer[i].limit = 0;
 861     }
 862 }
 863
 864 static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
 865     mv88w8618_pit_read,
 866     mv88w8618_pit_read,
 867     mv88w8618_pit_read
 868 };
 869
 870 static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
 871     mv88w8618_pit_write,
 872     mv88w8618_pit_write,
 873     mv88w8618_pit_write
 874 };
 875
 876 static int mv88w8618_pit_init(SysBusDevice *dev)
 877 {
 878     int iomemtype;
 879     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 880     int i;
 881
 882     /* Letting them all run at 1 MHz is likely just a pragmatic
 883      * simplification. */
 884     for (i = 0; i < 4; i++) {
 885         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 886     }
 887
 888     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
 889                                        mv88w8618_pit_writefn, s);
 890     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
 891     return 0;
 892 }
 893
 894 static const VMStateDescription mv88w8618_timer_vmsd = {
 895     .name = "timer",
 896     .version_id = 1,
 897     .minimum_version_id = 1,
 898     .minimum_version_id_old = 1,
 899     .fields = (VMStateField[]) {
 900         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 901         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 902         VMSTATE_END_OF_LIST()
 903     }
 904 };
 905
 906 static const VMStateDescription mv88w8618_pit_vmsd = {
 907     .name = "mv88w8618_pit",
 908     .version_id = 1,
 909     .minimum_version_id = 1,
 910     .minimum_version_id_old = 1,
 911     .fields = (VMStateField[]) {
 912         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 913                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 914         VMSTATE_END_OF_LIST()
 915     }
 916 };
 917
 918 static SysBusDeviceInfo mv88w8618_pit_info = {
 919     .init = mv88w8618_pit_init,
 920     .qdev.name  = "mv88w8618_pit",
 921     .qdev.size  = sizeof(mv88w8618_pit_state),
 922     .qdev.reset = mv88w8618_pit_reset,
 923     .qdev.vmsd  = &mv88w8618_pit_vmsd,
 924 };
 925
 926 /* Flash config register offsets */
 927 #define MP_FLASHCFG_CFGR0    0x04
 928
 929 typedef struct mv88w8618_flashcfg_state {
 930     SysBusDevice busdev;
 931     uint32_t cfgr0;
 932 } mv88w8618_flashcfg_state;
 933
 934 static uint32_t mv88w8618_flashcfg_read(void *opaque,
 935                                         target_phys_addr_t offset)
 936 {
 937     mv88w8618_flashcfg_state *s = opaque;
 938
 939     switch (offset) {
 940     case MP_FLASHCFG_CFGR0:
 941         return s->cfgr0;
 942
 943     default:
 944         return 0;
 945     }
 946 }
 947
 948 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 949                                      uint32_t value)
 950 {
 951     mv88w8618_flashcfg_state *s = opaque;
 952
 953     switch (offset) {
 954     case MP_FLASHCFG_CFGR0:
 955         s->cfgr0 = value;
 956         break;
 957     }
 958 }
 959
 960 static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
 961     mv88w8618_flashcfg_read,
 962     mv88w8618_flashcfg_read,
 963     mv88w8618_flashcfg_read
 964 };
 965
 966 static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
 967     mv88w8618_flashcfg_write,
 968     mv88w8618_flashcfg_write,
 969     mv88w8618_flashcfg_write
 970 };
 971
 972 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 973 {
 974     int iomemtype;
 975     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 976
 977     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 978     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
 979                                        mv88w8618_flashcfg_writefn, s);
 980     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
 981     return 0;
 982 }
 983
 984 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
 985     .name = "mv88w8618_flashcfg",
 986     .version_id = 1,
 987     .minimum_version_id = 1,
 988     .minimum_version_id_old = 1,
 989     .fields = (VMStateField[]) {
 990         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
 991         VMSTATE_END_OF_LIST()
 992     }
 993 };
 994
 995 static SysBusDeviceInfo mv88w8618_flashcfg_info = {
 996     .init = mv88w8618_flashcfg_init,
 997     .qdev.name  = "mv88w8618_flashcfg",
 998     .qdev.size  = sizeof(mv88w8618_flashcfg_state),
 999     .qdev.vmsd  = &mv88w8618_flashcfg_vmsd,
1000 };
1001
1002 /* Misc register offsets */
1003 #define MP_MISC_BOARD_REVISION  0x18
1004
1005 #define MP_BOARD_REVISION       0x31
1006
1007 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1008 {
1009     switch (offset) {
1010     case MP_MISC_BOARD_REVISION:
1011         return MP_BOARD_REVISION;
1012
1013     default:
1014         return 0;
1015     }
1016 }
1017
1018 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1019                                 uint32_t value)
1020 {
1021 }
1022
1023 static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
1024     musicpal_misc_read,
1025     musicpal_misc_read,
1026     musicpal_misc_read,
1027 };
1028
1029 static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
1030     musicpal_misc_write,
1031     musicpal_misc_write,
1032     musicpal_misc_write,
1033 };
1034
1035 static void musicpal_misc_init(void)
1036 {
1037     int iomemtype;
1038
1039     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
1040                                        musicpal_misc_writefn, NULL);
1041     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1042 }
1043
1044 /* WLAN register offsets */
1045 #define MP_WLAN_MAGIC1          0x11c
1046 #define MP_WLAN_MAGIC2          0x124
1047
1048 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1049 {
1050     switch (offset) {
1051     /* Workaround to allow loading the binary-only wlandrv.ko crap
1052      * from the original Freecom firmware. */
1053     case MP_WLAN_MAGIC1:
1054         return ~3;
1055     case MP_WLAN_MAGIC2:
1056         return -1;
1057
1058     default:
1059         return 0;
1060     }
1061 }
1062
1063 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1064                                  uint32_t value)
1065 {
1066 }
1067
1068 static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
1069     mv88w8618_wlan_read,
1070     mv88w8618_wlan_read,
1071     mv88w8618_wlan_read,
1072 };
1073
1074 static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
1075     mv88w8618_wlan_write,
1076     mv88w8618_wlan_write,
1077     mv88w8618_wlan_write,
1078 };
1079
1080 static int mv88w8618_wlan_init(SysBusDevice *dev)
1081 {
1082     int iomemtype;
1083
1084     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
1085                                        mv88w8618_wlan_writefn, NULL);
1086     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
1087     return 0;
1088 }
1089
1090 /* GPIO register offsets */
1091 #define MP_GPIO_OE_LO           0x008
1092 #define MP_GPIO_OUT_LO          0x00c
1093 #define MP_GPIO_IN_LO           0x010
1094 #define MP_GPIO_IER_LO          0x014
1095 #define MP_GPIO_IMR_LO          0x018
1096 #define MP_GPIO_ISR_LO          0x020
1097 #define MP_GPIO_OE_HI           0x508
1098 #define MP_GPIO_OUT_HI          0x50c
1099 #define MP_GPIO_IN_HI           0x510
1100 #define MP_GPIO_IER_HI          0x514
1101 #define MP_GPIO_IMR_HI          0x518
1102 #define MP_GPIO_ISR_HI          0x520
1103
1104 /* GPIO bits & masks */
1105 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1106 #define MP_GPIO_I2C_DATA_BIT    29
1107 #define MP_GPIO_I2C_CLOCK_BIT   30
1108
1109 /* LCD brightness bits in GPIO_OE_HI */
1110 #define MP_OE_LCD_BRIGHTNESS    0x0007
1111
1112 typedef struct musicpal_gpio_state {
1113     SysBusDevice busdev;
1114     uint32_t lcd_brightness;
1115     uint32_t out_state;
1116     uint32_t in_state;
1117     uint32_t ier;
1118     uint32_t imr;
1119     uint32_t isr;
1120     qemu_irq irq;
1121     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1122 } musicpal_gpio_state;
1123
1124 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1125     int i;
1126     uint32_t brightness;
1127
1128     /* compute brightness ratio */
1129     switch (s->lcd_brightness) {
1130     case 0x00000007:
1131         brightness = 0;
1132         break;
1133
1134     case 0x00020000:
1135         brightness = 1;
1136         break;
1137
1138     case 0x00020001:
1139         brightness = 2;
1140         break;
1141
1142     case 0x00040000:
1143         brightness = 3;
1144         break;
1145
1146     case 0x00010006:
1147         brightness = 4;
1148         break;
1149
1150     case 0x00020005:
1151         brightness = 5;
1152         break;
1153
1154     case 0x00040003:
1155         brightness = 6;
1156         break;
1157
1158     case 0x00030004:
1159     default:
1160         brightness = 7;
1161     }
1162
1163     /* set lcd brightness GPIOs  */
1164     for (i = 0; i <= 2; i++) {
1165         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1166     }
1167 }
1168
1169 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1170 {
1171     musicpal_gpio_state *s = opaque;
1172     uint32_t mask = 1 << pin;
1173     uint32_t delta = level << pin;
1174     uint32_t old = s->in_state & mask;
1175
1176     s->in_state &= ~mask;
1177     s->in_state |= delta;
1178
1179     if ((old ^ delta) &&
1180         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1181         s->isr = mask;
1182         qemu_irq_raise(s->irq);
1183     }
1184 }
1185
1186 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1187 {
1188     musicpal_gpio_state *s = opaque;
1189
1190     switch (offset) {
1191     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1192         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1193
1194     case MP_GPIO_OUT_LO:
1195         return s->out_state & 0xFFFF;
1196     case MP_GPIO_OUT_HI:
1197         return s->out_state >> 16;
1198
1199     case MP_GPIO_IN_LO:
1200         return s->in_state & 0xFFFF;
1201     case MP_GPIO_IN_HI:
1202         return s->in_state >> 16;
1203
1204     case MP_GPIO_IER_LO:
1205         return s->ier & 0xFFFF;
1206     case MP_GPIO_IER_HI:
1207         return s->ier >> 16;
1208
1209     case MP_GPIO_IMR_LO:
1210         return s->imr & 0xFFFF;
1211     case MP_GPIO_IMR_HI:
1212         return s->imr >> 16;
1213
1214     case MP_GPIO_ISR_LO:
1215         return s->isr & 0xFFFF;
1216     case MP_GPIO_ISR_HI:
1217         return s->isr >> 16;
1218
1219     default:
1220         return 0;
1221     }
1222 }
1223
1224 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1225                                 uint32_t value)
1226 {
1227     musicpal_gpio_state *s = opaque;
1228     switch (offset) {
1229     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1230         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1231                          (value & MP_OE_LCD_BRIGHTNESS);
1232         musicpal_gpio_brightness_update(s);
1233         break;
1234
1235     case MP_GPIO_OUT_LO:
1236         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1237         break;
1238     case MP_GPIO_OUT_HI:
1239         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1240         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1241                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1242         musicpal_gpio_brightness_update(s);
1243         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1244         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1245         break;
1246
1247     case MP_GPIO_IER_LO:
1248         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1249         break;
1250     case MP_GPIO_IER_HI:
1251         s->ier = (s->ier & 0xFFFF) | (value << 16);
1252         break;
1253
1254     case MP_GPIO_IMR_LO:
1255         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1256         break;
1257     case MP_GPIO_IMR_HI:
1258         s->imr = (s->imr & 0xFFFF) | (value << 16);
1259         break;
1260     }
1261 }
1262
1263 static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
1264     musicpal_gpio_read,
1265     musicpal_gpio_read,
1266     musicpal_gpio_read,
1267 };
1268
1269 static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
1270     musicpal_gpio_write,
1271     musicpal_gpio_write,
1272     musicpal_gpio_write,
1273 };
1274
1275 static void musicpal_gpio_reset(DeviceState *d)
1276 {
1277     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1278                                          sysbus_from_qdev(d));
1279
1280     s->lcd_brightness = 0;
1281     s->out_state = 0;
1282     s->in_state = 0xffffffff;
1283     s->ier = 0;
1284     s->imr = 0;
1285     s->isr = 0;
1286 }
1287
1288 static int musicpal_gpio_init(SysBusDevice *dev)
1289 {
1290     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1291     int iomemtype;
1292
1293     sysbus_init_irq(dev, &s->irq);
1294
1295     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1296                                        musicpal_gpio_writefn, s);
1297     sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1298
1299     musicpal_gpio_reset(&dev->qdev);
1300
1301     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1302
1303     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1304
1305     return 0;
1306 }
1307
1308 static const VMStateDescription musicpal_gpio_vmsd = {
1309     .name = "musicpal_gpio",
1310     .version_id = 1,
1311     .minimum_version_id = 1,
1312     .minimum_version_id_old = 1,
1313     .fields = (VMStateField[]) {
1314         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1315         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1316         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1317         VMSTATE_UINT32(ier, musicpal_gpio_state),
1318         VMSTATE_UINT32(imr, musicpal_gpio_state),
1319         VMSTATE_UINT32(isr, musicpal_gpio_state),
1320         VMSTATE_END_OF_LIST()
1321     }
1322 };
1323
1324 static SysBusDeviceInfo musicpal_gpio_info = {
1325     .init = musicpal_gpio_init,
1326     .qdev.name  = "musicpal_gpio",
1327     .qdev.size  = sizeof(musicpal_gpio_state),
1328     .qdev.reset = musicpal_gpio_reset,
1329     .qdev.vmsd  = &musicpal_gpio_vmsd,
1330 };
1331
1332 /* Keyboard codes & masks */
1333 #define KEY_RELEASED            0x80
1334 #define KEY_CODE                0x7f
1335
1336 #define KEYCODE_TAB             0x0f
1337 #define KEYCODE_ENTER           0x1c
1338 #define KEYCODE_F               0x21
1339 #define KEYCODE_M               0x32
1340
1341 #define KEYCODE_EXTENDED        0xe0
1342 #define KEYCODE_UP              0x48
1343 #define KEYCODE_DOWN            0x50
1344 #define KEYCODE_LEFT            0x4b
1345 #define KEYCODE_RIGHT           0x4d
1346
1347 #define MP_KEY_WHEEL_VOL       (1 << 0)
1348 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1349 #define MP_KEY_WHEEL_NAV       (1 << 2)
1350 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1351 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1352 #define MP_KEY_BTN_MENU        (1 << 5)
1353 #define MP_KEY_BTN_VOLUME      (1 << 6)
1354 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1355
1356 typedef struct musicpal_key_state {
1357     SysBusDevice busdev;
1358     uint32_t kbd_extended;
1359     uint32_t pressed_keys;
1360     qemu_irq out[8];
1361 } musicpal_key_state;
1362
1363 static void musicpal_key_event(void *opaque, int keycode)
1364 {
1365     musicpal_key_state *s = opaque;
1366     uint32_t event = 0;
1367     int i;
1368
1369     if (keycode == KEYCODE_EXTENDED) {
1370         s->kbd_extended = 1;
1371         return;
1372     }
1373
1374     if (s->kbd_extended) {
1375         switch (keycode & KEY_CODE) {
1376         case KEYCODE_UP:
1377             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1378             break;
1379
1380         case KEYCODE_DOWN:
1381             event = MP_KEY_WHEEL_NAV;
1382             break;
1383
1384         case KEYCODE_LEFT:
1385             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1386             break;
1387
1388         case KEYCODE_RIGHT:
1389             event = MP_KEY_WHEEL_VOL;
1390             break;
1391         }
1392     } else {
1393         switch (keycode & KEY_CODE) {
1394         case KEYCODE_F:
1395             event = MP_KEY_BTN_FAVORITS;
1396             break;
1397
1398         case KEYCODE_TAB:
1399             event = MP_KEY_BTN_VOLUME;
1400             break;
1401
1402         case KEYCODE_ENTER:
1403             event = MP_KEY_BTN_NAVIGATION;
1404             break;
1405
1406         case KEYCODE_M:
1407             event = MP_KEY_BTN_MENU;
1408             break;
1409         }
1410         /* Do not repeat already pressed buttons */
1411         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1412             event = 0;
1413         }
1414     }
1415
1416     if (event) {
1417         /* Raise GPIO pin first if repeating a key */
1418         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1419             for (i = 0; i <= 7; i++) {
1420                 if (event & (1 << i)) {
1421                     qemu_set_irq(s->out[i], 1);
1422                 }
1423             }
1424         }
1425         for (i = 0; i <= 7; i++) {
1426             if (event & (1 << i)) {
1427                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1428             }
1429         }
1430         if (keycode & KEY_RELEASED) {
1431             s->pressed_keys &= ~event;
1432         } else {
1433             s->pressed_keys |= event;
1434         }
1435     }
1436
1437     s->kbd_extended = 0;
1438 }
1439
1440 static int musicpal_key_init(SysBusDevice *dev)
1441 {
1442     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1443
1444     sysbus_init_mmio(dev, 0x0, 0);
1445
1446     s->kbd_extended = 0;
1447     s->pressed_keys = 0;
1448
1449     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1450
1451     qemu_add_kbd_event_handler(musicpal_key_event, s);
1452
1453     return 0;
1454 }
1455
1456 static const VMStateDescription musicpal_key_vmsd = {
1457     .name = "musicpal_key",
1458     .version_id = 1,
1459     .minimum_version_id = 1,
1460     .minimum_version_id_old = 1,
1461     .fields = (VMStateField[]) {
1462         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1463         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1464         VMSTATE_END_OF_LIST()
1465     }
1466 };
1467
1468 static SysBusDeviceInfo musicpal_key_info = {
1469     .init = musicpal_key_init,
1470     .qdev.name  = "musicpal_key",
1471     .qdev.size  = sizeof(musicpal_key_state),
1472     .qdev.vmsd  = &musicpal_key_vmsd,
1473 };
1474
1475 static struct arm_boot_info musicpal_binfo = {
1476     .loader_start = 0x0,
1477     .board_id = 0x20e,
1478 };
1479
1480 static void musicpal_init(ram_addr_t ram_size,
1481                const char *boot_device,
1482                const char *kernel_filename, const char *kernel_cmdline,
1483                const char *initrd_filename, const char *cpu_model)
1484 {
1485     CPUState *env;
1486     qemu_irq *cpu_pic;
1487     qemu_irq pic[32];
1488     DeviceState *dev;
1489     DeviceState *i2c_dev;
1490     DeviceState *lcd_dev;
1491     DeviceState *key_dev;
1492 #ifdef HAS_AUDIO
1493     DeviceState *wm8750_dev;
1494     SysBusDevice *s;
1495 #endif
1496     i2c_bus *i2c;
1497     int i;
1498     unsigned long flash_size;
1499     DriveInfo *dinfo;
1500     ram_addr_t sram_off;
1501
1502     if (!cpu_model) {
1503         cpu_model = "arm926";
1504     }
1505     env = cpu_init(cpu_model);
1506     if (!env) {
1507         fprintf(stderr, "Unable to find CPU definition\n");
1508         exit(1);
1509     }
1510     cpu_pic = arm_pic_init_cpu(env);
1511
1512     /* For now we use a fixed - the original - RAM size */
1513     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1514                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1515
1516     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1517     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1518
1519     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1520                                cpu_pic[ARM_PIC_CPU_IRQ]);
1521     for (i = 0; i < 32; i++) {
1522         pic[i] = qdev_get_gpio_in(dev, i);
1523     }
1524     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1525                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1526                           pic[MP_TIMER4_IRQ], NULL);
1527
1528     if (serial_hds[0]) {
1529         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1530                    serial_hds[0], 1);
1531     }
1532     if (serial_hds[1]) {
1533         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1534                    serial_hds[1], 1);
1535     }
1536
1537     /* Register flash */
1538     dinfo = drive_get(IF_PFLASH, 0, 0);
1539     if (dinfo) {
1540         flash_size = bdrv_getlength(dinfo->bdrv);
1541         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1542             flash_size != 32*1024*1024) {
1543             fprintf(stderr, "Invalid flash image size\n");
1544             exit(1);
1545         }
1546
1547         /*
1548          * The original U-Boot accesses the flash at 0xFE000000 instead of
1549          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1550          * image is smaller than 32 MB.
1551          */
1552         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1553                               dinfo->bdrv, 0x10000,
1554                               (flash_size + 0xffff) >> 16,
1555                               MP_FLASH_SIZE_MAX / flash_size,
1556                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1557                               0x5555, 0x2AAA);
1558     }
1559     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1560
1561     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1562     dev = qdev_create(NULL, "mv88w8618_eth");
1563     qdev_set_nic_properties(dev, &nd_table[0]);
1564     qdev_init_nofail(dev);
1565     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1566     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1567
1568     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1569
1570     musicpal_misc_init();
1571
1572     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1573     i2c_dev = sysbus_create_simple("gpio_i2c", 0, NULL);
1574     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1575
1576     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1577     key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
1578
1579     /* I2C read data */
1580     qdev_connect_gpio_out(i2c_dev, 0,
1581                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1582     /* I2C data */
1583     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1584     /* I2C clock */
1585     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1586
1587     for (i = 0; i < 3; i++) {
1588         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1589     }
1590     for (i = 0; i < 4; i++) {
1591         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1592     }
1593     for (i = 4; i < 8; i++) {
1594         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1595     }
1596
1597 #ifdef HAS_AUDIO
1598     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1599     dev = qdev_create(NULL, "mv88w8618_audio");
1600     s = sysbus_from_qdev(dev);
1601     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1602     qdev_init_nofail(dev);
1603     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1604     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1605 #endif
1606
1607     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1608     musicpal_binfo.kernel_filename = kernel_filename;
1609     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1610     musicpal_binfo.initrd_filename = initrd_filename;
1611     arm_load_kernel(env, &musicpal_binfo);
1612 }
1613
1614 static QEMUMachine musicpal_machine = {
1615     .name = "musicpal",
1616     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1617     .init = musicpal_init,
1618 };
1619
1620 static void musicpal_machine_init(void)
1621 {
1622     qemu_register_machine(&musicpal_machine);
1623 }
1624
1625 machine_init(musicpal_machine_init);
1626
1627 static void musicpal_register_devices(void)
1628 {
1629     sysbus_register_withprop(&mv88w8618_pic_info);
1630     sysbus_register_withprop(&mv88w8618_pit_info);
1631     sysbus_register_withprop(&mv88w8618_flashcfg_info);
1632     sysbus_register_withprop(&mv88w8618_eth_info);
1633     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1634                         mv88w8618_wlan_init);
1635     sysbus_register_withprop(&musicpal_lcd_info);
1636     sysbus_register_withprop(&musicpal_gpio_info);
1637     sysbus_register_withprop(&musicpal_key_info);
1638 }
1639
1640 device_init(musicpal_register_devices)