target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  20  */
  21 #ifndef CPU_CRIS_H
  22 #define CPU_CRIS_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #define CPUState struct CPUCRISState
  27
  28 #include "cpu-defs.h"
  29
  30 #define TARGET_HAS_ICE 1
  31
  32 #define ELF_MACHINE     EM_CRIS
  33
  34 #define EXCP_NMI        1
  35 #define EXCP_GURU       2
  36 #define EXCP_BUSFAULT   3
  37 #define EXCP_IRQ        4
  38 #define EXCP_BREAK      5
  39
  40 /* Register aliases. R0 - R15 */
  41 #define R_FP  8
  42 #define R_SP  14
  43 #define R_ACR 15
  44
  45 /* Support regs, P0 - P15  */
  46 #define PR_BZ  0
  47 #define PR_VR  1
  48 #define PR_PID 2
  49 #define PR_SRS 3
  50 #define PR_WZ  4
  51 #define PR_EXS 5
  52 #define PR_EDA 6
  53 #define PR_MOF 7
  54 #define PR_DZ  8
  55 #define PR_EBP 9
  56 #define PR_ERP 10
  57 #define PR_SRP 11
  58 #define PR_NRP 12
  59 #define PR_CCS 13
  60 #define PR_USP 14
  61 #define PR_SPC 15
  62
  63 /* CPU flags.  */
  64 #define Q_FLAG 0x80000000
  65 #define M_FLAG 0x40000000
  66 #define S_FLAG 0x200
  67 #define R_FLAG 0x100
  68 #define P_FLAG 0x80
  69 #define U_FLAG 0x40
  70 #define I_FLAG 0x20
  71 #define X_FLAG 0x10
  72 #define N_FLAG 0x08
  73 #define Z_FLAG 0x04
  74 #define V_FLAG 0x02
  75 #define C_FLAG 0x01
  76 #define ALU_FLAGS 0x1F
  77
  78 /* Condition codes.  */
  79 #define CC_CC   0
  80 #define CC_CS   1
  81 #define CC_NE   2
  82 #define CC_EQ   3
  83 #define CC_VC   4
  84 #define CC_VS   5
  85 #define CC_PL   6
  86 #define CC_MI   7
  87 #define CC_LS   8
  88 #define CC_HI   9
  89 #define CC_GE  10
  90 #define CC_LT  11
  91 #define CC_GT  12
  92 #define CC_LE  13
  93 #define CC_A   14
  94 #define CC_P   15
  95
  96 #define NB_MMU_MODES 2
  97
  98 typedef struct CPUCRISState {
  99         uint32_t regs[16];
 100         /* P0 - P15 are referred to as special registers in the docs.  */
 101         uint32_t pregs[16];
 102
 103         /* Pseudo register for the PC. Not directly accessable on CRIS.  */
 104         uint32_t pc;
 105
 106         /* Pseudo register for the kernel stack.  */
 107         uint32_t ksp;
 108
 109         /* Branch.  */
 110         int dslot;
 111         int btaken;
 112         uint32_t btarget;
 113
 114         /* Condition flag tracking.  */
 115         uint32_t cc_op;
 116         uint32_t cc_mask;
 117         uint32_t cc_dest;
 118         uint32_t cc_src;
 119         uint32_t cc_result;
 120         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 121         int cc_size;
 122         /* X flag at the time of cc snapshot.  */
 123         int cc_x;
 124
 125         int interrupt_vector;
 126         int fault_vector;
 127         int trap_vector;
 128
 129         /* FIXME: add a check in the translator to avoid writing to support
 130            register sets beyond the 4th. The ISA allows up to 256! but in
 131            practice there is no core that implements more than 4.
 132
 133            Support function registers are used to control units close to the
 134            core. Accesses do not pass down the normal hierarchy.
 135         */
 136         uint32_t sregs[4][16];
 137
 138         /* Linear feedback shift reg in the mmu. Used to provide pseudo
 139            randomness for the 'hint' the mmu gives to sw for chosing valid
 140            sets on TLB refills.  */
 141         uint32_t mmu_rand_lfsr;
 142
 143         /*
 144          * We just store the stores to the tlbset here for later evaluation
 145          * when the hw needs access to them.
 146          *
 147          * One for I and another for D.
 148          */
 149         struct
 150         {
 151                 uint32_t hi;
 152                 uint32_t lo;
 153         } tlbsets[2][4][16];
 154
 155         CPU_COMMON
 156 } CPUCRISState;
 157
 158 CPUCRISState *cpu_cris_init(const char *cpu_model);
 159 int cpu_cris_exec(CPUCRISState *s);
 160 void cpu_cris_close(CPUCRISState *s);
 161 void do_interrupt(CPUCRISState *env);
 162 /* you can call this signal handler from your SIGBUS and SIGSEGV
 163    signal handlers to inform the virtual CPU of exceptions. non zero
 164    is returned if the signal was handled by the virtual CPU.  */
 165 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 166                            void *puc);
 167
 168 enum {
 169     CC_OP_DYNAMIC, /* Use env->cc_op  */
 170     CC_OP_FLAGS,
 171     CC_OP_CMP,
 172     CC_OP_MOVE,
 173     CC_OP_ADD,
 174     CC_OP_ADDC,
 175     CC_OP_MCP,
 176     CC_OP_ADDU,
 177     CC_OP_SUB,
 178     CC_OP_SUBU,
 179     CC_OP_NEG,
 180     CC_OP_BTST,
 181     CC_OP_MULS,
 182     CC_OP_MULU,
 183     CC_OP_DSTEP,
 184     CC_OP_BOUND,
 185
 186     CC_OP_OR,
 187     CC_OP_AND,
 188     CC_OP_XOR,
 189     CC_OP_LSL,
 190     CC_OP_LSR,
 191     CC_OP_ASR,
 192     CC_OP_LZ
 193 };
 194
 195 /* CRIS uses 8k pages.  */
 196 #define TARGET_PAGE_BITS 13
 197 #define MMAP_SHIFT TARGET_PAGE_BITS
 198
 199 #define cpu_init cpu_cris_init
 200 #define cpu_exec cpu_cris_exec
 201 #define cpu_gen_code cpu_cris_gen_code
 202 #define cpu_signal_handler cpu_cris_signal_handler
 203
 204 #define CPU_SAVE_VERSION 1
 205
 206 /* MMU modes definitions */
 207 #define MMU_MODE0_SUFFIX _kernel
 208 #define MMU_MODE1_SUFFIX _user
 209 #define MMU_USER_IDX 1
 210 static inline int cpu_mmu_index (CPUState *env)
 211 {
 212         return !!(env->pregs[PR_CCS] & U_FLAG);
 213 }
 214
 215 int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 216                               int mmu_idx, int is_softmmu);
 217
 218 #if defined(CONFIG_USER_ONLY)
 219 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 220 {
 221     if (newsp)
 222         env->regs[14] = newsp;
 223     env->regs[10] = 0;
 224 }
 225 #endif
 226
 227 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
 228 {
 229         env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
 230 }
 231
 232 /* Support function regs.  */
 233 #define SFR_RW_GC_CFG      0][0
 234 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 235 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 236 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 237 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 238 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 239 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 240 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 241
 242 #include "cpu-all.h"
 243 #include "exec-all.h"
 244
 245 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 246 {
 247     env->pc = tb->pc;
 248 }
 249
 250 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 251                                         target_ulong *cs_base, int *flags)
 252 {
 253     *pc = env->pc;
 254     *cs_base = 0;
 255     *flags = env->dslot |
 256             (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG));
 257 }
 258
 259 #endif