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Compile pflash_cfi02 only once
[qemu/aliguori-queue.git] / hw / sun4m.c
blob90e661d5c269355d1344003f28cbf628093269c1
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "qdev-addr.h"
40 #include "loader.h"
41 #include "elf.h"
42
43 //#define DEBUG_IRQ
44
45 /*
46 * Sun4m architecture was used in the following machines:
47 *
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
56 * SPARCstation 4
57 *
58 * Sun4d architecture was used in the following machines:
59 *
60 * SPARCcenter 2000
61 * SPARCserver 1000
62 *
63 * Sun4c architecture was used in the following machines:
64 * SPARCstation 1/1+, SPARCserver 1/1+
65 * SPARCstation SLC
66 * SPARCstation IPC
67 * SPARCstation ELC
68 * SPARCstation IPX
69 *
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
71 */
72
73 #ifdef DEBUG_IRQ
74 #define DPRINTF(fmt, ...) \
75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
76 #else
77 #define DPRINTF(fmt, ...)
78 #endif
79
80 #define KERNEL_LOAD_ADDR 0x00004000
81 #define CMDLINE_ADDR 0x007ff000
82 #define INITRD_LOAD_ADDR 0x00800000
83 #define PROM_SIZE_MAX (1024 * 1024)
84 #define PROM_VADDR 0xffd00000
85 #define PROM_FILENAME "openbios-sparc32"
86 #define CFG_ADDR 0xd00000510ULL
87 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
88
89 #define MAX_CPUS 16
90 #define MAX_PILS 16
91
92 #define ESCC_CLOCK 4915200
93
94 struct sun4m_hwdef {
95 target_phys_addr_t iommu_base, slavio_base;
96 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
97 target_phys_addr_t serial_base, fd_base;
98 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
99 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
100 target_phys_addr_t ecc_base;
101 uint32_t ecc_version;
102 uint8_t nvram_machine_id;
103 uint16_t machine_id;
104 uint32_t iommu_version;
105 uint64_t max_mem;
106 const char * const default_cpu_model;
107 };
108
109 #define MAX_IOUNITS 5
110
111 struct sun4d_hwdef {
112 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
113 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
114 target_phys_addr_t serial_base;
115 target_phys_addr_t espdma_base, esp_base;
116 target_phys_addr_t ledma_base, le_base;
117 target_phys_addr_t tcx_base;
118 target_phys_addr_t sbi_base;
119 uint8_t nvram_machine_id;
120 uint16_t machine_id;
121 uint32_t iounit_version;
122 uint64_t max_mem;
123 const char * const default_cpu_model;
124 };
125
126 struct sun4c_hwdef {
127 target_phys_addr_t iommu_base, slavio_base;
128 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
129 target_phys_addr_t serial_base, fd_base;
130 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
131 target_phys_addr_t tcx_base, aux1_base;
132 uint8_t nvram_machine_id;
133 uint16_t machine_id;
134 uint32_t iommu_version;
135 uint64_t max_mem;
136 const char * const default_cpu_model;
137 };
138
139 int DMA_get_channel_mode (int nchan)
140 {
141 return 0;
142 }
143 int DMA_read_memory (int nchan, void *buf, int pos, int size)
144 {
145 return 0;
146 }
147 int DMA_write_memory (int nchan, void *buf, int pos, int size)
148 {
149 return 0;
150 }
151 void DMA_hold_DREQ (int nchan) {}
152 void DMA_release_DREQ (int nchan) {}
153 void DMA_schedule(int nchan) {}
154 void DMA_init (int high_page_enable) {}
155 void DMA_register_channel (int nchan,
156 DMA_transfer_handler transfer_handler,
157 void *opaque)
158 {
159 }
160
161 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
162 {
163 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
164 return 0;
165 }
166
167 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
168 const char *cmdline, const char *boot_devices,
169 ram_addr_t RAM_size, uint32_t kernel_size,
170 int width, int height, int depth,
171 int nvram_machine_id, const char *arch)
172 {
173 unsigned int i;
174 uint32_t start, end;
175 uint8_t image[0x1ff0];
176 struct OpenBIOS_nvpart_v1 *part_header;
177
178 memset(image, '\0', sizeof(image));
179
180 start = 0;
181
182 // OpenBIOS nvram variables
183 // Variable partition
184 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
185 part_header->signature = OPENBIOS_PART_SYSTEM;
186 pstrcpy(part_header->name, sizeof(part_header->name), "system");
187
188 end = start + sizeof(struct OpenBIOS_nvpart_v1);
189 for (i = 0; i < nb_prom_envs; i++)
190 end = OpenBIOS_set_var(image, end, prom_envs[i]);
191
192 // End marker
193 image[end++] = '\0';
194
195 end = start + ((end - start + 15) & ~15);
196 OpenBIOS_finish_partition(part_header, end - start);
197
198 // free partition
199 start = end;
200 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
201 part_header->signature = OPENBIOS_PART_FREE;
202 pstrcpy(part_header->name, sizeof(part_header->name), "free");
203
204 end = 0x1fd0;
205 OpenBIOS_finish_partition(part_header, end - start);
206
207 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
208 nvram_machine_id);
209
210 for (i = 0; i < sizeof(image); i++)
211 m48t59_write(nvram, i, image[i]);
212 }
213
214 static DeviceState *slavio_intctl;
215
216 void pic_info(Monitor *mon)
217 {
218 if (slavio_intctl)
219 slavio_pic_info(mon, slavio_intctl);
220 }
221
222 void irq_info(Monitor *mon)
223 {
224 if (slavio_intctl)
225 slavio_irq_info(mon, slavio_intctl);
226 }
227
228 void cpu_check_irqs(CPUState *env)
229 {
230 if (env->pil_in && (env->interrupt_index == 0 ||
231 (env->interrupt_index & ~15) == TT_EXTINT)) {
232 unsigned int i;
233
234 for (i = 15; i > 0; i--) {
235 if (env->pil_in & (1 << i)) {
236 int old_interrupt = env->interrupt_index;
237
238 env->interrupt_index = TT_EXTINT | i;
239 if (old_interrupt != env->interrupt_index) {
240 DPRINTF("Set CPU IRQ %d\n", i);
241 cpu_interrupt(env, CPU_INTERRUPT_HARD);
242 }
243 break;
244 }
245 }
246 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
247 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
248 env->interrupt_index = 0;
249 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
250 }
251 }
252
253 static void cpu_set_irq(void *opaque, int irq, int level)
254 {
255 CPUState *env = opaque;
256
257 if (level) {
258 DPRINTF("Raise CPU IRQ %d\n", irq);
259 env->halted = 0;
260 env->pil_in |= 1 << irq;
261 cpu_check_irqs(env);
262 } else {
263 DPRINTF("Lower CPU IRQ %d\n", irq);
264 env->pil_in &= ~(1 << irq);
265 cpu_check_irqs(env);
266 }
267 }
268
269 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
270 {
271 }
272
273 static void main_cpu_reset(void *opaque)
274 {
275 CPUState *env = opaque;
276
277 cpu_reset(env);
278 env->halted = 0;
279 }
280
281 static void secondary_cpu_reset(void *opaque)
282 {
283 CPUState *env = opaque;
284
285 cpu_reset(env);
286 env->halted = 1;
287 }
288
289 static void cpu_halt_signal(void *opaque, int irq, int level)
290 {
291 if (level && cpu_single_env)
292 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
293 }
294
295 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
296 {
297 return addr - 0xf0000000ULL;
298 }
299
300 static unsigned long sun4m_load_kernel(const char *kernel_filename,
301 const char *initrd_filename,
302 ram_addr_t RAM_size)
303 {
304 int linux_boot;
305 unsigned int i;
306 long initrd_size, kernel_size;
307 uint8_t *ptr;
308
309 linux_boot = (kernel_filename != NULL);
310
311 kernel_size = 0;
312 if (linux_boot) {
313 int bswap_needed;
314
315 #ifdef BSWAP_NEEDED
316 bswap_needed = 1;
317 #else
318 bswap_needed = 0;
319 #endif
320 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
321 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
322 if (kernel_size < 0)
323 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
324 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
325 TARGET_PAGE_SIZE);
326 if (kernel_size < 0)
327 kernel_size = load_image_targphys(kernel_filename,
328 KERNEL_LOAD_ADDR,
329 RAM_size - KERNEL_LOAD_ADDR);
330 if (kernel_size < 0) {
331 fprintf(stderr, "qemu: could not load kernel '%s'\n",
332 kernel_filename);
333 exit(1);
334 }
335
336 /* load initrd */
337 initrd_size = 0;
338 if (initrd_filename) {
339 initrd_size = load_image_targphys(initrd_filename,
340 INITRD_LOAD_ADDR,
341 RAM_size - INITRD_LOAD_ADDR);
342 if (initrd_size < 0) {
343 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
344 initrd_filename);
345 exit(1);
346 }
347 }
348 if (initrd_size > 0) {
349 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
350 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
351 if (ldl_p(ptr) == 0x48647253) { // HdrS
352 stl_p(ptr + 16, INITRD_LOAD_ADDR);
353 stl_p(ptr + 20, initrd_size);
354 break;
355 }
356 }
357 }
358 }
359 return kernel_size;
360 }
361
362 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
363 {
364 DeviceState *dev;
365 SysBusDevice *s;
366
367 dev = qdev_create(NULL, "iommu");
368 qdev_prop_set_uint32(dev, "version", version);
369 qdev_init_nofail(dev);
370 s = sysbus_from_qdev(dev);
371 sysbus_connect_irq(s, 0, irq);
372 sysbus_mmio_map(s, 0, addr);
373
374 return s;
375 }
376
377 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
378 void *iommu, qemu_irq *dev_irq)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382
383 dev = qdev_create(NULL, "sparc32_dma");
384 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
385 qdev_init_nofail(dev);
386 s = sysbus_from_qdev(dev);
387 sysbus_connect_irq(s, 0, parent_irq);
388 *dev_irq = qdev_get_gpio_in(dev, 0);
389 sysbus_mmio_map(s, 0, daddr);
390
391 return s;
392 }
393
394 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
395 void *dma_opaque, qemu_irq irq)
396 {
397 DeviceState *dev;
398 SysBusDevice *s;
399 qemu_irq reset;
400
401 qemu_check_nic_model(&nd_table[0], "lance");
402
403 dev = qdev_create(NULL, "lance");
404 qdev_set_nic_properties(dev, nd);
405 qdev_prop_set_ptr(dev, "dma", dma_opaque);
406 qdev_init_nofail(dev);
407 s = sysbus_from_qdev(dev);
408 sysbus_mmio_map(s, 0, leaddr);
409 sysbus_connect_irq(s, 0, irq);
410 reset = qdev_get_gpio_in(dev, 0);
411 qdev_connect_gpio_out(dma_opaque, 0, reset);
412 }
413
414 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
415 target_phys_addr_t addrg,
416 qemu_irq **parent_irq)
417 {
418 DeviceState *dev;
419 SysBusDevice *s;
420 unsigned int i, j;
421
422 dev = qdev_create(NULL, "slavio_intctl");
423 qdev_init_nofail(dev);
424
425 s = sysbus_from_qdev(dev);
426
427 for (i = 0; i < MAX_CPUS; i++) {
428 for (j = 0; j < MAX_PILS; j++) {
429 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
430 }
431 }
432 sysbus_mmio_map(s, 0, addrg);
433 for (i = 0; i < MAX_CPUS; i++) {
434 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
435 }
436
437 return dev;
438 }
439
440 #define SYS_TIMER_OFFSET 0x10000ULL
441 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
442
443 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
444 qemu_irq *cpu_irqs, unsigned int num_cpus)
445 {
446 DeviceState *dev;
447 SysBusDevice *s;
448 unsigned int i;
449
450 dev = qdev_create(NULL, "slavio_timer");
451 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
452 qdev_init_nofail(dev);
453 s = sysbus_from_qdev(dev);
454 sysbus_connect_irq(s, 0, master_irq);
455 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
456
457 for (i = 0; i < MAX_CPUS; i++) {
458 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
459 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
460 }
461 }
462
463 #define MISC_LEDS 0x01600000
464 #define MISC_CFG 0x01800000
465 #define MISC_DIAG 0x01a00000
466 #define MISC_MDM 0x01b00000
467 #define MISC_SYS 0x01f00000
468
469 static void slavio_misc_init(target_phys_addr_t base,
470 target_phys_addr_t aux1_base,
471 target_phys_addr_t aux2_base, qemu_irq irq,
472 qemu_irq fdc_tc)
473 {
474 DeviceState *dev;
475 SysBusDevice *s;
476
477 dev = qdev_create(NULL, "slavio_misc");
478 qdev_init_nofail(dev);
479 s = sysbus_from_qdev(dev);
480 if (base) {
481 /* 8 bit registers */
482 /* Slavio control */
483 sysbus_mmio_map(s, 0, base + MISC_CFG);
484 /* Diagnostics */
485 sysbus_mmio_map(s, 1, base + MISC_DIAG);
486 /* Modem control */
487 sysbus_mmio_map(s, 2, base + MISC_MDM);
488 /* 16 bit registers */
489 /* ss600mp diag LEDs */
490 sysbus_mmio_map(s, 3, base + MISC_LEDS);
491 /* 32 bit registers */
492 /* System control */
493 sysbus_mmio_map(s, 4, base + MISC_SYS);
494 }
495 if (aux1_base) {
496 /* AUX 1 (Misc System Functions) */
497 sysbus_mmio_map(s, 5, aux1_base);
498 }
499 if (aux2_base) {
500 /* AUX 2 (Software Powerdown Control) */
501 sysbus_mmio_map(s, 6, aux2_base);
502 }
503 sysbus_connect_irq(s, 0, irq);
504 sysbus_connect_irq(s, 1, fdc_tc);
505 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
506 }
507
508 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
509 {
510 DeviceState *dev;
511 SysBusDevice *s;
512
513 dev = qdev_create(NULL, "eccmemctl");
514 qdev_prop_set_uint32(dev, "version", version);
515 qdev_init_nofail(dev);
516 s = sysbus_from_qdev(dev);
517 sysbus_connect_irq(s, 0, irq);
518 sysbus_mmio_map(s, 0, base);
519 if (version == 0) { // SS-600MP only
520 sysbus_mmio_map(s, 1, base + 0x1000);
521 }
522 }
523
524 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
525 {
526 DeviceState *dev;
527 SysBusDevice *s;
528
529 dev = qdev_create(NULL, "apc");
530 qdev_init_nofail(dev);
531 s = sysbus_from_qdev(dev);
532 /* Power management (APC) XXX: not a Slavio device */
533 sysbus_mmio_map(s, 0, power_base);
534 sysbus_connect_irq(s, 0, cpu_halt);
535 }
536
537 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
538 int height, int depth)
539 {
540 DeviceState *dev;
541 SysBusDevice *s;
542
543 dev = qdev_create(NULL, "SUNW,tcx");
544 qdev_prop_set_taddr(dev, "addr", addr);
545 qdev_prop_set_uint32(dev, "vram_size", vram_size);
546 qdev_prop_set_uint16(dev, "width", width);
547 qdev_prop_set_uint16(dev, "height", height);
548 qdev_prop_set_uint16(dev, "depth", depth);
549 qdev_init_nofail(dev);
550 s = sysbus_from_qdev(dev);
551 /* 8-bit plane */
552 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
553 /* DAC */
554 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
555 /* TEC (dummy) */
556 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
557 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
558 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
559 if (depth == 24) {
560 /* 24-bit plane */
561 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
562 /* Control plane */
563 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
564 } else {
565 /* THC 8 bit (dummy) */
566 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
567 }
568 }
569
570 /* NCR89C100/MACIO Internal ID register */
571 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
572
573 static void idreg_init(target_phys_addr_t addr)
574 {
575 DeviceState *dev;
576 SysBusDevice *s;
577
578 dev = qdev_create(NULL, "macio_idreg");
579 qdev_init_nofail(dev);
580 s = sysbus_from_qdev(dev);
581
582 sysbus_mmio_map(s, 0, addr);
583 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
584 }
585
586 static int idreg_init1(SysBusDevice *dev)
587 {
588 ram_addr_t idreg_offset;
589
590 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
591 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
592 return 0;
593 }
594
595 static SysBusDeviceInfo idreg_info = {
596 .init = idreg_init1,
597 .qdev.name = "macio_idreg",
598 .qdev.size = sizeof(SysBusDevice),
599 };
600
601 static void idreg_register_devices(void)
602 {
603 sysbus_register_withprop(&idreg_info);
604 }
605
606 device_init(idreg_register_devices);
607
608 /* SS-5 TCX AFX register */
609 static void afx_init(target_phys_addr_t addr)
610 {
611 DeviceState *dev;
612 SysBusDevice *s;
613
614 dev = qdev_create(NULL, "tcx_afx");
615 qdev_init_nofail(dev);
616 s = sysbus_from_qdev(dev);
617
618 sysbus_mmio_map(s, 0, addr);
619 }
620
621 static int afx_init1(SysBusDevice *dev)
622 {
623 ram_addr_t afx_offset;
624
625 afx_offset = qemu_ram_alloc(4);
626 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
627 return 0;
628 }
629
630 static SysBusDeviceInfo afx_info = {
631 .init = afx_init1,
632 .qdev.name = "tcx_afx",
633 .qdev.size = sizeof(SysBusDevice),
634 };
635
636 static void afx_register_devices(void)
637 {
638 sysbus_register_withprop(&afx_info);
639 }
640
641 device_init(afx_register_devices);
642
643 /* Boot PROM (OpenBIOS) */
644 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
645 {
646 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
647 return addr + *base_addr - PROM_VADDR;
648 }
649
650 static void prom_init(target_phys_addr_t addr, const char *bios_name)
651 {
652 DeviceState *dev;
653 SysBusDevice *s;
654 char *filename;
655 int ret;
656
657 dev = qdev_create(NULL, "openprom");
658 qdev_init_nofail(dev);
659 s = sysbus_from_qdev(dev);
660
661 sysbus_mmio_map(s, 0, addr);
662
663 /* load boot prom */
664 if (bios_name == NULL) {
665 bios_name = PROM_FILENAME;
666 }
667 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
668 if (filename) {
669 ret = load_elf(filename, translate_prom_address, &addr, NULL,
670 NULL, NULL, 1, ELF_MACHINE, 0);
671 if (ret < 0 || ret > PROM_SIZE_MAX) {
672 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
673 }
674 qemu_free(filename);
675 } else {
676 ret = -1;
677 }
678 if (ret < 0 || ret > PROM_SIZE_MAX) {
679 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
680 exit(1);
681 }
682 }
683
684 static int prom_init1(SysBusDevice *dev)
685 {
686 ram_addr_t prom_offset;
687
688 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
689 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
690 return 0;
691 }
692
693 static SysBusDeviceInfo prom_info = {
694 .init = prom_init1,
695 .qdev.name = "openprom",
696 .qdev.size = sizeof(SysBusDevice),
697 .qdev.props = (Property[]) {
698 {/* end of property list */}
699 }
700 };
701
702 static void prom_register_devices(void)
703 {
704 sysbus_register_withprop(&prom_info);
705 }
706
707 device_init(prom_register_devices);
708
709 typedef struct RamDevice
710 {
711 SysBusDevice busdev;
712 uint64_t size;
713 } RamDevice;
714
715 /* System RAM */
716 static int ram_init1(SysBusDevice *dev)
717 {
718 ram_addr_t RAM_size, ram_offset;
719 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
720
721 RAM_size = d->size;
722
723 ram_offset = qemu_ram_alloc(RAM_size);
724 sysbus_init_mmio(dev, RAM_size, ram_offset);
725 return 0;
726 }
727
728 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
729 uint64_t max_mem)
730 {
731 DeviceState *dev;
732 SysBusDevice *s;
733 RamDevice *d;
734
735 /* allocate RAM */
736 if ((uint64_t)RAM_size > max_mem) {
737 fprintf(stderr,
738 "qemu: Too much memory for this machine: %d, maximum %d\n",
739 (unsigned int)(RAM_size / (1024 * 1024)),
740 (unsigned int)(max_mem / (1024 * 1024)));
741 exit(1);
742 }
743 dev = qdev_create(NULL, "memory");
744 s = sysbus_from_qdev(dev);
745
746 d = FROM_SYSBUS(RamDevice, s);
747 d->size = RAM_size;
748 qdev_init_nofail(dev);
749
750 sysbus_mmio_map(s, 0, addr);
751 }
752
753 static SysBusDeviceInfo ram_info = {
754 .init = ram_init1,
755 .qdev.name = "memory",
756 .qdev.size = sizeof(RamDevice),
757 .qdev.props = (Property[]) {
758 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
759 DEFINE_PROP_END_OF_LIST(),
760 }
761 };
762
763 static void ram_register_devices(void)
764 {
765 sysbus_register_withprop(&ram_info);
766 }
767
768 device_init(ram_register_devices);
769
770 static void cpu_devinit(const char *cpu_model, unsigned int id,
771 uint64_t prom_addr, qemu_irq **cpu_irqs)
772 {
773 CPUState *env;
774
775 env = cpu_init(cpu_model);
776 if (!env) {
777 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
778 exit(1);
779 }
780
781 cpu_sparc_set_id(env, id);
782 if (id == 0) {
783 qemu_register_reset(main_cpu_reset, env);
784 } else {
785 qemu_register_reset(secondary_cpu_reset, env);
786 env->halted = 1;
787 }
788 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
789 env->prom_addr = prom_addr;
790 }
791
792 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
793 const char *boot_device,
794 const char *kernel_filename,
795 const char *kernel_cmdline,
796 const char *initrd_filename, const char *cpu_model)
797 {
798 unsigned int i;
799 void *iommu, *espdma, *ledma, *nvram;
800 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
801 espdma_irq, ledma_irq;
802 qemu_irq esp_reset;
803 qemu_irq fdc_tc;
804 qemu_irq *cpu_halt;
805 unsigned long kernel_size;
806 DriveInfo *fd[MAX_FD];
807 void *fw_cfg;
808
809 /* init CPUs */
810 if (!cpu_model)
811 cpu_model = hwdef->default_cpu_model;
812
813 for(i = 0; i < smp_cpus; i++) {
814 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
815 }
816
817 for (i = smp_cpus; i < MAX_CPUS; i++)
818 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
819
820
821 /* set up devices */
822 ram_init(0, RAM_size, hwdef->max_mem);
823
824 prom_init(hwdef->slavio_base, bios_name);
825
826 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
827 hwdef->intctl_base + 0x10000ULL,
828 cpu_irqs);
829
830 for (i = 0; i < 32; i++) {
831 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
832 }
833 for (i = 0; i < MAX_CPUS; i++) {
834 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
835 }
836
837 if (hwdef->idreg_base) {
838 idreg_init(hwdef->idreg_base);
839 }
840
841 if (hwdef->afx_base) {
842 afx_init(hwdef->afx_base);
843 }
844
845 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
846 slavio_irq[30]);
847
848 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
849 iommu, &espdma_irq);
850
851 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
852 slavio_irq[16], iommu, &ledma_irq);
853
854 if (graphic_depth != 8 && graphic_depth != 24) {
855 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
856 exit (1);
857 }
858 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
859 graphic_depth);
860
861 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
862
863 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
864
865 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
866
867 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
868 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
869 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
870 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
871 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
872 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
873
874 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
875 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
876 slavio_irq[30], fdc_tc);
877
878 if (hwdef->apc_base) {
879 apc_init(hwdef->apc_base, cpu_halt[0]);
880 }
881
882 if (hwdef->fd_base) {
883 /* there is zero or one floppy drive */
884 memset(fd, 0, sizeof(fd));
885 fd[0] = drive_get(IF_FLOPPY, 0, 0);
886 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
887 &fdc_tc);
888 }
889
890 if (drive_get_max_bus(IF_SCSI) > 0) {
891 fprintf(stderr, "qemu: too many SCSI bus\n");
892 exit(1);
893 }
894
895 esp_reset = qdev_get_gpio_in(espdma, 0);
896 esp_init(hwdef->esp_base, 2,
897 espdma_memory_read, espdma_memory_write,
898 espdma, espdma_irq, &esp_reset);
899
900
901 if (hwdef->cs_base) {
902 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
903 slavio_irq[5]);
904 }
905
906 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
907 RAM_size);
908
909 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
910 boot_device, RAM_size, kernel_size, graphic_width,
911 graphic_height, graphic_depth, hwdef->nvram_machine_id,
912 "Sun4m");
913
914 if (hwdef->ecc_base)
915 ecc_init(hwdef->ecc_base, slavio_irq[28],
916 hwdef->ecc_version);
917
918 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
919 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
920 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
921 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
922 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
923 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
924 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
925 if (kernel_cmdline) {
926 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
927 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
928 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
929 (uint8_t*)strdup(kernel_cmdline),
930 strlen(kernel_cmdline) + 1);
931 } else {
932 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
933 }
934 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
935 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
936 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
937 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
938 }
939
940 enum {
941 ss2_id = 0,
942 ss5_id = 32,
943 vger_id,
944 lx_id,
945 ss4_id,
946 scls_id,
947 sbook_id,
948 ss10_id = 64,
949 ss20_id,
950 ss600mp_id,
951 ss1000_id = 96,
952 ss2000_id,
953 };
954
955 static const struct sun4m_hwdef sun4m_hwdefs[] = {
956 /* SS-5 */
957 {
958 .iommu_base = 0x10000000,
959 .tcx_base = 0x50000000,
960 .cs_base = 0x6c000000,
961 .slavio_base = 0x70000000,
962 .ms_kb_base = 0x71000000,
963 .serial_base = 0x71100000,
964 .nvram_base = 0x71200000,
965 .fd_base = 0x71400000,
966 .counter_base = 0x71d00000,
967 .intctl_base = 0x71e00000,
968 .idreg_base = 0x78000000,
969 .dma_base = 0x78400000,
970 .esp_base = 0x78800000,
971 .le_base = 0x78c00000,
972 .apc_base = 0x6a000000,
973 .afx_base = 0x6e000000,
974 .aux1_base = 0x71900000,
975 .aux2_base = 0x71910000,
976 .nvram_machine_id = 0x80,
977 .machine_id = ss5_id,
978 .iommu_version = 0x05000000,
979 .max_mem = 0x10000000,
980 .default_cpu_model = "Fujitsu MB86904",
981 },
982 /* SS-10 */
983 {
984 .iommu_base = 0xfe0000000ULL,
985 .tcx_base = 0xe20000000ULL,
986 .slavio_base = 0xff0000000ULL,
987 .ms_kb_base = 0xff1000000ULL,
988 .serial_base = 0xff1100000ULL,
989 .nvram_base = 0xff1200000ULL,
990 .fd_base = 0xff1700000ULL,
991 .counter_base = 0xff1300000ULL,
992 .intctl_base = 0xff1400000ULL,
993 .idreg_base = 0xef0000000ULL,
994 .dma_base = 0xef0400000ULL,
995 .esp_base = 0xef0800000ULL,
996 .le_base = 0xef0c00000ULL,
997 .apc_base = 0xefa000000ULL, // XXX should not exist
998 .aux1_base = 0xff1800000ULL,
999 .aux2_base = 0xff1a01000ULL,
1000 .ecc_base = 0xf00000000ULL,
1001 .ecc_version = 0x10000000, // version 0, implementation 1
1002 .nvram_machine_id = 0x72,
1003 .machine_id = ss10_id,
1004 .iommu_version = 0x03000000,
1005 .max_mem = 0xf00000000ULL,
1006 .default_cpu_model = "TI SuperSparc II",
1007 },
1008 /* SS-600MP */
1009 {
1010 .iommu_base = 0xfe0000000ULL,
1011 .tcx_base = 0xe20000000ULL,
1012 .slavio_base = 0xff0000000ULL,
1013 .ms_kb_base = 0xff1000000ULL,
1014 .serial_base = 0xff1100000ULL,
1015 .nvram_base = 0xff1200000ULL,
1016 .counter_base = 0xff1300000ULL,
1017 .intctl_base = 0xff1400000ULL,
1018 .dma_base = 0xef0081000ULL,
1019 .esp_base = 0xef0080000ULL,
1020 .le_base = 0xef0060000ULL,
1021 .apc_base = 0xefa000000ULL, // XXX should not exist
1022 .aux1_base = 0xff1800000ULL,
1023 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1024 .ecc_base = 0xf00000000ULL,
1025 .ecc_version = 0x00000000, // version 0, implementation 0
1026 .nvram_machine_id = 0x71,
1027 .machine_id = ss600mp_id,
1028 .iommu_version = 0x01000000,
1029 .max_mem = 0xf00000000ULL,
1030 .default_cpu_model = "TI SuperSparc II",
1031 },
1032 /* SS-20 */
1033 {
1034 .iommu_base = 0xfe0000000ULL,
1035 .tcx_base = 0xe20000000ULL,
1036 .slavio_base = 0xff0000000ULL,
1037 .ms_kb_base = 0xff1000000ULL,
1038 .serial_base = 0xff1100000ULL,
1039 .nvram_base = 0xff1200000ULL,
1040 .fd_base = 0xff1700000ULL,
1041 .counter_base = 0xff1300000ULL,
1042 .intctl_base = 0xff1400000ULL,
1043 .idreg_base = 0xef0000000ULL,
1044 .dma_base = 0xef0400000ULL,
1045 .esp_base = 0xef0800000ULL,
1046 .le_base = 0xef0c00000ULL,
1047 .apc_base = 0xefa000000ULL, // XXX should not exist
1048 .aux1_base = 0xff1800000ULL,
1049 .aux2_base = 0xff1a01000ULL,
1050 .ecc_base = 0xf00000000ULL,
1051 .ecc_version = 0x20000000, // version 0, implementation 2
1052 .nvram_machine_id = 0x72,
1053 .machine_id = ss20_id,
1054 .iommu_version = 0x13000000,
1055 .max_mem = 0xf00000000ULL,
1056 .default_cpu_model = "TI SuperSparc II",
1057 },
1058 /* Voyager */
1059 {
1060 .iommu_base = 0x10000000,
1061 .tcx_base = 0x50000000,
1062 .slavio_base = 0x70000000,
1063 .ms_kb_base = 0x71000000,
1064 .serial_base = 0x71100000,
1065 .nvram_base = 0x71200000,
1066 .fd_base = 0x71400000,
1067 .counter_base = 0x71d00000,
1068 .intctl_base = 0x71e00000,
1069 .idreg_base = 0x78000000,
1070 .dma_base = 0x78400000,
1071 .esp_base = 0x78800000,
1072 .le_base = 0x78c00000,
1073 .apc_base = 0x71300000, // pmc
1074 .aux1_base = 0x71900000,
1075 .aux2_base = 0x71910000,
1076 .nvram_machine_id = 0x80,
1077 .machine_id = vger_id,
1078 .iommu_version = 0x05000000,
1079 .max_mem = 0x10000000,
1080 .default_cpu_model = "Fujitsu MB86904",
1081 },
1082 /* LX */
1083 {
1084 .iommu_base = 0x10000000,
1085 .tcx_base = 0x50000000,
1086 .slavio_base = 0x70000000,
1087 .ms_kb_base = 0x71000000,
1088 .serial_base = 0x71100000,
1089 .nvram_base = 0x71200000,
1090 .fd_base = 0x71400000,
1091 .counter_base = 0x71d00000,
1092 .intctl_base = 0x71e00000,
1093 .idreg_base = 0x78000000,
1094 .dma_base = 0x78400000,
1095 .esp_base = 0x78800000,
1096 .le_base = 0x78c00000,
1097 .aux1_base = 0x71900000,
1098 .aux2_base = 0x71910000,
1099 .nvram_machine_id = 0x80,
1100 .machine_id = lx_id,
1101 .iommu_version = 0x04000000,
1102 .max_mem = 0x10000000,
1103 .default_cpu_model = "TI MicroSparc I",
1104 },
1105 /* SS-4 */
1106 {
1107 .iommu_base = 0x10000000,
1108 .tcx_base = 0x50000000,
1109 .cs_base = 0x6c000000,
1110 .slavio_base = 0x70000000,
1111 .ms_kb_base = 0x71000000,
1112 .serial_base = 0x71100000,
1113 .nvram_base = 0x71200000,
1114 .fd_base = 0x71400000,
1115 .counter_base = 0x71d00000,
1116 .intctl_base = 0x71e00000,
1117 .idreg_base = 0x78000000,
1118 .dma_base = 0x78400000,
1119 .esp_base = 0x78800000,
1120 .le_base = 0x78c00000,
1121 .apc_base = 0x6a000000,
1122 .aux1_base = 0x71900000,
1123 .aux2_base = 0x71910000,
1124 .nvram_machine_id = 0x80,
1125 .machine_id = ss4_id,
1126 .iommu_version = 0x05000000,
1127 .max_mem = 0x10000000,
1128 .default_cpu_model = "Fujitsu MB86904",
1129 },
1130 /* SPARCClassic */
1131 {
1132 .iommu_base = 0x10000000,
1133 .tcx_base = 0x50000000,
1134 .slavio_base = 0x70000000,
1135 .ms_kb_base = 0x71000000,
1136 .serial_base = 0x71100000,
1137 .nvram_base = 0x71200000,
1138 .fd_base = 0x71400000,
1139 .counter_base = 0x71d00000,
1140 .intctl_base = 0x71e00000,
1141 .idreg_base = 0x78000000,
1142 .dma_base = 0x78400000,
1143 .esp_base = 0x78800000,
1144 .le_base = 0x78c00000,
1145 .apc_base = 0x6a000000,
1146 .aux1_base = 0x71900000,
1147 .aux2_base = 0x71910000,
1148 .nvram_machine_id = 0x80,
1149 .machine_id = scls_id,
1150 .iommu_version = 0x05000000,
1151 .max_mem = 0x10000000,
1152 .default_cpu_model = "TI MicroSparc I",
1153 },
1154 /* SPARCbook */
1155 {
1156 .iommu_base = 0x10000000,
1157 .tcx_base = 0x50000000, // XXX
1158 .slavio_base = 0x70000000,
1159 .ms_kb_base = 0x71000000,
1160 .serial_base = 0x71100000,
1161 .nvram_base = 0x71200000,
1162 .fd_base = 0x71400000,
1163 .counter_base = 0x71d00000,
1164 .intctl_base = 0x71e00000,
1165 .idreg_base = 0x78000000,
1166 .dma_base = 0x78400000,
1167 .esp_base = 0x78800000,
1168 .le_base = 0x78c00000,
1169 .apc_base = 0x6a000000,
1170 .aux1_base = 0x71900000,
1171 .aux2_base = 0x71910000,
1172 .nvram_machine_id = 0x80,
1173 .machine_id = sbook_id,
1174 .iommu_version = 0x05000000,
1175 .max_mem = 0x10000000,
1176 .default_cpu_model = "TI MicroSparc I",
1177 },
1178 };
1179
1180 /* SPARCstation 5 hardware initialisation */
1181 static void ss5_init(ram_addr_t RAM_size,
1182 const char *boot_device,
1183 const char *kernel_filename, const char *kernel_cmdline,
1184 const char *initrd_filename, const char *cpu_model)
1185 {
1186 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1187 kernel_cmdline, initrd_filename, cpu_model);
1188 }
1189
1190 /* SPARCstation 10 hardware initialisation */
1191 static void ss10_init(ram_addr_t RAM_size,
1192 const char *boot_device,
1193 const char *kernel_filename, const char *kernel_cmdline,
1194 const char *initrd_filename, const char *cpu_model)
1195 {
1196 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1197 kernel_cmdline, initrd_filename, cpu_model);
1198 }
1199
1200 /* SPARCserver 600MP hardware initialisation */
1201 static void ss600mp_init(ram_addr_t RAM_size,
1202 const char *boot_device,
1203 const char *kernel_filename,
1204 const char *kernel_cmdline,
1205 const char *initrd_filename, const char *cpu_model)
1206 {
1207 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1208 kernel_cmdline, initrd_filename, cpu_model);
1209 }
1210
1211 /* SPARCstation 20 hardware initialisation */
1212 static void ss20_init(ram_addr_t RAM_size,
1213 const char *boot_device,
1214 const char *kernel_filename, const char *kernel_cmdline,
1215 const char *initrd_filename, const char *cpu_model)
1216 {
1217 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1218 kernel_cmdline, initrd_filename, cpu_model);
1219 }
1220
1221 /* SPARCstation Voyager hardware initialisation */
1222 static void vger_init(ram_addr_t RAM_size,
1223 const char *boot_device,
1224 const char *kernel_filename, const char *kernel_cmdline,
1225 const char *initrd_filename, const char *cpu_model)
1226 {
1227 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1228 kernel_cmdline, initrd_filename, cpu_model);
1229 }
1230
1231 /* SPARCstation LX hardware initialisation */
1232 static void ss_lx_init(ram_addr_t RAM_size,
1233 const char *boot_device,
1234 const char *kernel_filename, const char *kernel_cmdline,
1235 const char *initrd_filename, const char *cpu_model)
1236 {
1237 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1238 kernel_cmdline, initrd_filename, cpu_model);
1239 }
1240
1241 /* SPARCstation 4 hardware initialisation */
1242 static void ss4_init(ram_addr_t RAM_size,
1243 const char *boot_device,
1244 const char *kernel_filename, const char *kernel_cmdline,
1245 const char *initrd_filename, const char *cpu_model)
1246 {
1247 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1248 kernel_cmdline, initrd_filename, cpu_model);
1249 }
1250
1251 /* SPARCClassic hardware initialisation */
1252 static void scls_init(ram_addr_t RAM_size,
1253 const char *boot_device,
1254 const char *kernel_filename, const char *kernel_cmdline,
1255 const char *initrd_filename, const char *cpu_model)
1256 {
1257 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1258 kernel_cmdline, initrd_filename, cpu_model);
1259 }
1260
1261 /* SPARCbook hardware initialisation */
1262 static void sbook_init(ram_addr_t RAM_size,
1263 const char *boot_device,
1264 const char *kernel_filename, const char *kernel_cmdline,
1265 const char *initrd_filename, const char *cpu_model)
1266 {
1267 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1268 kernel_cmdline, initrd_filename, cpu_model);
1269 }
1270
1271 static QEMUMachine ss5_machine = {
1272 .name = "SS-5",
1273 .desc = "Sun4m platform, SPARCstation 5",
1274 .init = ss5_init,
1275 .use_scsi = 1,
1276 .is_default = 1,
1277 };
1278
1279 static QEMUMachine ss10_machine = {
1280 .name = "SS-10",
1281 .desc = "Sun4m platform, SPARCstation 10",
1282 .init = ss10_init,
1283 .use_scsi = 1,
1284 .max_cpus = 4,
1285 };
1286
1287 static QEMUMachine ss600mp_machine = {
1288 .name = "SS-600MP",
1289 .desc = "Sun4m platform, SPARCserver 600MP",
1290 .init = ss600mp_init,
1291 .use_scsi = 1,
1292 .max_cpus = 4,
1293 };
1294
1295 static QEMUMachine ss20_machine = {
1296 .name = "SS-20",
1297 .desc = "Sun4m platform, SPARCstation 20",
1298 .init = ss20_init,
1299 .use_scsi = 1,
1300 .max_cpus = 4,
1301 };
1302
1303 static QEMUMachine voyager_machine = {
1304 .name = "Voyager",
1305 .desc = "Sun4m platform, SPARCstation Voyager",
1306 .init = vger_init,
1307 .use_scsi = 1,
1308 };
1309
1310 static QEMUMachine ss_lx_machine = {
1311 .name = "LX",
1312 .desc = "Sun4m platform, SPARCstation LX",
1313 .init = ss_lx_init,
1314 .use_scsi = 1,
1315 };
1316
1317 static QEMUMachine ss4_machine = {
1318 .name = "SS-4",
1319 .desc = "Sun4m platform, SPARCstation 4",
1320 .init = ss4_init,
1321 .use_scsi = 1,
1322 };
1323
1324 static QEMUMachine scls_machine = {
1325 .name = "SPARCClassic",
1326 .desc = "Sun4m platform, SPARCClassic",
1327 .init = scls_init,
1328 .use_scsi = 1,
1329 };
1330
1331 static QEMUMachine sbook_machine = {
1332 .name = "SPARCbook",
1333 .desc = "Sun4m platform, SPARCbook",
1334 .init = sbook_init,
1335 .use_scsi = 1,
1336 };
1337
1338 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1339 /* SS-1000 */
1340 {
1341 .iounit_bases = {
1342 0xfe0200000ULL,
1343 0xfe1200000ULL,
1344 0xfe2200000ULL,
1345 0xfe3200000ULL,
1346 -1,
1347 },
1348 .tcx_base = 0x820000000ULL,
1349 .slavio_base = 0xf00000000ULL,
1350 .ms_kb_base = 0xf00240000ULL,
1351 .serial_base = 0xf00200000ULL,
1352 .nvram_base = 0xf00280000ULL,
1353 .counter_base = 0xf00300000ULL,
1354 .espdma_base = 0x800081000ULL,
1355 .esp_base = 0x800080000ULL,
1356 .ledma_base = 0x800040000ULL,
1357 .le_base = 0x800060000ULL,
1358 .sbi_base = 0xf02800000ULL,
1359 .nvram_machine_id = 0x80,
1360 .machine_id = ss1000_id,
1361 .iounit_version = 0x03000000,
1362 .max_mem = 0xf00000000ULL,
1363 .default_cpu_model = "TI SuperSparc II",
1364 },
1365 /* SS-2000 */
1366 {
1367 .iounit_bases = {
1368 0xfe0200000ULL,
1369 0xfe1200000ULL,
1370 0xfe2200000ULL,
1371 0xfe3200000ULL,
1372 0xfe4200000ULL,
1373 },
1374 .tcx_base = 0x820000000ULL,
1375 .slavio_base = 0xf00000000ULL,
1376 .ms_kb_base = 0xf00240000ULL,
1377 .serial_base = 0xf00200000ULL,
1378 .nvram_base = 0xf00280000ULL,
1379 .counter_base = 0xf00300000ULL,
1380 .espdma_base = 0x800081000ULL,
1381 .esp_base = 0x800080000ULL,
1382 .ledma_base = 0x800040000ULL,
1383 .le_base = 0x800060000ULL,
1384 .sbi_base = 0xf02800000ULL,
1385 .nvram_machine_id = 0x80,
1386 .machine_id = ss2000_id,
1387 .iounit_version = 0x03000000,
1388 .max_mem = 0xf00000000ULL,
1389 .default_cpu_model = "TI SuperSparc II",
1390 },
1391 };
1392
1393 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1394 {
1395 DeviceState *dev;
1396 SysBusDevice *s;
1397 unsigned int i;
1398
1399 dev = qdev_create(NULL, "sbi");
1400 qdev_init_nofail(dev);
1401
1402 s = sysbus_from_qdev(dev);
1403
1404 for (i = 0; i < MAX_CPUS; i++) {
1405 sysbus_connect_irq(s, i, *parent_irq[i]);
1406 }
1407
1408 sysbus_mmio_map(s, 0, addr);
1409
1410 return dev;
1411 }
1412
1413 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1414 const char *boot_device,
1415 const char *kernel_filename,
1416 const char *kernel_cmdline,
1417 const char *initrd_filename, const char *cpu_model)
1418 {
1419 unsigned int i;
1420 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1421 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1422 espdma_irq, ledma_irq;
1423 qemu_irq esp_reset;
1424 unsigned long kernel_size;
1425 void *fw_cfg;
1426 DeviceState *dev;
1427
1428 /* init CPUs */
1429 if (!cpu_model)
1430 cpu_model = hwdef->default_cpu_model;
1431
1432 for(i = 0; i < smp_cpus; i++) {
1433 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1434 }
1435
1436 for (i = smp_cpus; i < MAX_CPUS; i++)
1437 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1438
1439 /* set up devices */
1440 ram_init(0, RAM_size, hwdef->max_mem);
1441
1442 prom_init(hwdef->slavio_base, bios_name);
1443
1444 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1445
1446 for (i = 0; i < 32; i++) {
1447 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1448 }
1449 for (i = 0; i < MAX_CPUS; i++) {
1450 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1451 }
1452
1453 for (i = 0; i < MAX_IOUNITS; i++)
1454 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1455 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1456 hwdef->iounit_version,
1457 sbi_irq[0]);
1458
1459 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1460 iounits[0], &espdma_irq);
1461
1462 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1463 iounits[0], &ledma_irq);
1464
1465 if (graphic_depth != 8 && graphic_depth != 24) {
1466 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1467 exit (1);
1468 }
1469 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1470 graphic_depth);
1471
1472 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1473
1474 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1475
1476 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1477
1478 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1479 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1480 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1481 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1482 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1483 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1484
1485 if (drive_get_max_bus(IF_SCSI) > 0) {
1486 fprintf(stderr, "qemu: too many SCSI bus\n");
1487 exit(1);
1488 }
1489
1490 esp_reset = qdev_get_gpio_in(espdma, 0);
1491 esp_init(hwdef->esp_base, 2,
1492 espdma_memory_read, espdma_memory_write,
1493 espdma, espdma_irq, &esp_reset);
1494
1495 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1496 RAM_size);
1497
1498 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1499 boot_device, RAM_size, kernel_size, graphic_width,
1500 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1501 "Sun4d");
1502
1503 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1504 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1505 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1506 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1507 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1508 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1509 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1510 if (kernel_cmdline) {
1511 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1512 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1513 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1514 (uint8_t*)strdup(kernel_cmdline),
1515 strlen(kernel_cmdline) + 1);
1516 } else {
1517 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1518 }
1519 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1520 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1521 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1522 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1523 }
1524
1525 /* SPARCserver 1000 hardware initialisation */
1526 static void ss1000_init(ram_addr_t RAM_size,
1527 const char *boot_device,
1528 const char *kernel_filename, const char *kernel_cmdline,
1529 const char *initrd_filename, const char *cpu_model)
1530 {
1531 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1532 kernel_cmdline, initrd_filename, cpu_model);
1533 }
1534
1535 /* SPARCcenter 2000 hardware initialisation */
1536 static void ss2000_init(ram_addr_t RAM_size,
1537 const char *boot_device,
1538 const char *kernel_filename, const char *kernel_cmdline,
1539 const char *initrd_filename, const char *cpu_model)
1540 {
1541 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1542 kernel_cmdline, initrd_filename, cpu_model);
1543 }
1544
1545 static QEMUMachine ss1000_machine = {
1546 .name = "SS-1000",
1547 .desc = "Sun4d platform, SPARCserver 1000",
1548 .init = ss1000_init,
1549 .use_scsi = 1,
1550 .max_cpus = 8,
1551 };
1552
1553 static QEMUMachine ss2000_machine = {
1554 .name = "SS-2000",
1555 .desc = "Sun4d platform, SPARCcenter 2000",
1556 .init = ss2000_init,
1557 .use_scsi = 1,
1558 .max_cpus = 20,
1559 };
1560
1561 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1562 /* SS-2 */
1563 {
1564 .iommu_base = 0xf8000000,
1565 .tcx_base = 0xfe000000,
1566 .slavio_base = 0xf6000000,
1567 .intctl_base = 0xf5000000,
1568 .counter_base = 0xf3000000,
1569 .ms_kb_base = 0xf0000000,
1570 .serial_base = 0xf1000000,
1571 .nvram_base = 0xf2000000,
1572 .fd_base = 0xf7200000,
1573 .dma_base = 0xf8400000,
1574 .esp_base = 0xf8800000,
1575 .le_base = 0xf8c00000,
1576 .aux1_base = 0xf7400003,
1577 .nvram_machine_id = 0x55,
1578 .machine_id = ss2_id,
1579 .max_mem = 0x10000000,
1580 .default_cpu_model = "Cypress CY7C601",
1581 },
1582 };
1583
1584 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1585 qemu_irq *parent_irq)
1586 {
1587 DeviceState *dev;
1588 SysBusDevice *s;
1589 unsigned int i;
1590
1591 dev = qdev_create(NULL, "sun4c_intctl");
1592 qdev_init_nofail(dev);
1593
1594 s = sysbus_from_qdev(dev);
1595
1596 for (i = 0; i < MAX_PILS; i++) {
1597 sysbus_connect_irq(s, i, parent_irq[i]);
1598 }
1599 sysbus_mmio_map(s, 0, addr);
1600
1601 return dev;
1602 }
1603
1604 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1605 const char *boot_device,
1606 const char *kernel_filename,
1607 const char *kernel_cmdline,
1608 const char *initrd_filename, const char *cpu_model)
1609 {
1610 void *iommu, *espdma, *ledma, *nvram;
1611 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1612 qemu_irq esp_reset;
1613 qemu_irq fdc_tc;
1614 unsigned long kernel_size;
1615 DriveInfo *fd[MAX_FD];
1616 void *fw_cfg;
1617 DeviceState *dev;
1618 unsigned int i;
1619
1620 /* init CPU */
1621 if (!cpu_model)
1622 cpu_model = hwdef->default_cpu_model;
1623
1624 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1625
1626 /* set up devices */
1627 ram_init(0, RAM_size, hwdef->max_mem);
1628
1629 prom_init(hwdef->slavio_base, bios_name);
1630
1631 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1632
1633 for (i = 0; i < 8; i++) {
1634 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1635 }
1636
1637 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1638 slavio_irq[1]);
1639
1640 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1641 iommu, &espdma_irq);
1642
1643 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1644 slavio_irq[3], iommu, &ledma_irq);
1645
1646 if (graphic_depth != 8 && graphic_depth != 24) {
1647 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1648 exit (1);
1649 }
1650 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1651 graphic_depth);
1652
1653 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1654
1655 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1656
1657 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1658 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1659 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1660 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1661 escc_init(hwdef->serial_base, slavio_irq[1],
1662 slavio_irq[1], serial_hds[0], serial_hds[1],
1663 ESCC_CLOCK, 1);
1664
1665 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1666
1667 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1668 /* there is zero or one floppy drive */
1669 memset(fd, 0, sizeof(fd));
1670 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1671 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1672 &fdc_tc);
1673 }
1674
1675 if (drive_get_max_bus(IF_SCSI) > 0) {
1676 fprintf(stderr, "qemu: too many SCSI bus\n");
1677 exit(1);
1678 }
1679
1680 esp_reset = qdev_get_gpio_in(espdma, 0);
1681 esp_init(hwdef->esp_base, 2,
1682 espdma_memory_read, espdma_memory_write,
1683 espdma, espdma_irq, &esp_reset);
1684
1685 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1686 RAM_size);
1687
1688 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1689 boot_device, RAM_size, kernel_size, graphic_width,
1690 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1691 "Sun4c");
1692
1693 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1694 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1695 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1696 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1697 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1698 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1699 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1700 if (kernel_cmdline) {
1701 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1702 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1703 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1704 (uint8_t*)strdup(kernel_cmdline),
1705 strlen(kernel_cmdline) + 1);
1706 } else {
1707 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1708 }
1709 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1710 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1711 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1712 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1713 }
1714
1715 /* SPARCstation 2 hardware initialisation */
1716 static void ss2_init(ram_addr_t RAM_size,
1717 const char *boot_device,
1718 const char *kernel_filename, const char *kernel_cmdline,
1719 const char *initrd_filename, const char *cpu_model)
1720 {
1721 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1722 kernel_cmdline, initrd_filename, cpu_model);
1723 }
1724
1725 static QEMUMachine ss2_machine = {
1726 .name = "SS-2",
1727 .desc = "Sun4c platform, SPARCstation 2",
1728 .init = ss2_init,
1729 .use_scsi = 1,
1730 };
1731
1732 static void ss2_machine_init(void)
1733 {
1734 qemu_register_machine(&ss5_machine);
1735 qemu_register_machine(&ss10_machine);
1736 qemu_register_machine(&ss600mp_machine);
1737 qemu_register_machine(&ss20_machine);
1738 qemu_register_machine(&voyager_machine);
1739 qemu_register_machine(&ss_lx_machine);
1740 qemu_register_machine(&ss4_machine);
1741 qemu_register_machine(&scls_machine);
1742 qemu_register_machine(&sbook_machine);
1743 qemu_register_machine(&ss1000_machine);
1744 qemu_register_machine(&ss2000_machine);
1745 qemu_register_machine(&ss2_machine);
1746 }
1747
1748 machine_init(ss2_machine_init);
Anthony Liguori's QEMU queue