hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "usb-uhci.h"
  31 #include "usb-ohci.h"
  32 #include "prep_pci.h"
  33 #include "apb_pci.h"
  34 #include "block.h"
  35 #include "sysemu.h"
  36 #include "audio/audio.h"
  37 #include "net.h"
  38 #include "smbus.h"
  39 #include "boards.h"
  40 #include "monitor.h"
  41 #include "fw_cfg.h"
  42 #include "hpet_emul.h"
  43 #include "watchdog.h"
  44 #include "smbios.h"
  45 #include "ide.h"
  46 #include "loader.h"
  47 #include "elf.h"
  48 #include "multiboot.h"
  49 #include "kvm.h"
  50
  51 /* output Bochs bios info messages */
  52 //#define DEBUG_BIOS
  53
  54 #define BIOS_FILENAME "bios.bin"
  55
  56 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  57
  58 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  59 #define ACPI_DATA_SIZE       0x10000
  60 #define BIOS_CFG_IOPORT 0x510
  61 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  62 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  63 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  64 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  65
  66 #define MAX_IDE_BUS 2
  67
  68 static FDCtrl *floppy_controller;
  69 static RTCState *rtc_state;
  70
  71 #define E820_NR_ENTRIES         16
  72
  73 struct e820_entry {
  74     uint64_t address;
  75     uint64_t length;
  76     uint32_t type;
  77 };
  78
  79 struct e820_table {
  80     uint32_t count;
  81     struct e820_entry entry[E820_NR_ENTRIES];
  82 };
  83
  84 static struct e820_table e820_table;
  85
  86 typedef struct isa_irq_state {
  87     qemu_irq *i8259;
  88     qemu_irq *ioapic;
  89 } IsaIrqState;
  90
  91 static void isa_irq_handler(void *opaque, int n, int level)
  92 {
  93     IsaIrqState *isa = (IsaIrqState *)opaque;
  94
  95     if (n < 16) {
  96         qemu_set_irq(isa->i8259[n], level);
  97     }
  98     if (isa->ioapic)
  99         qemu_set_irq(isa->ioapic[n], level);
 100 };
 101
 102 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 103 {
 104 }
 105
 106 /* MSDOS compatibility mode FPU exception support */
 107 static qemu_irq ferr_irq;
 108 /* XXX: add IGNNE support */
 109 void cpu_set_ferr(CPUX86State *s)
 110 {
 111     qemu_irq_raise(ferr_irq);
 112 }
 113
 114 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 115 {
 116     qemu_irq_lower(ferr_irq);
 117 }
 118
 119 /* TSC handling */
 120 uint64_t cpu_get_tsc(CPUX86State *env)
 121 {
 122     return cpu_get_ticks();
 123 }
 124
 125 /* SMM support */
 126
 127 static cpu_set_smm_t smm_set;
 128 static void *smm_arg;
 129
 130 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 131 {
 132     assert(smm_set == NULL);
 133     assert(smm_arg == NULL);
 134     smm_set = callback;
 135     smm_arg = arg;
 136 }
 137
 138 void cpu_smm_update(CPUState *env)
 139 {
 140     if (smm_set && smm_arg && env == first_cpu)
 141         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 142 }
 143
 144
 145 /* IRQ handling */
 146 int cpu_get_pic_interrupt(CPUState *env)
 147 {
 148     int intno;
 149
 150     intno = apic_get_interrupt(env);
 151     if (intno >= 0) {
 152         /* set irq request if a PIC irq is still pending */
 153         /* XXX: improve that */
 154         pic_update_irq(isa_pic);
 155         return intno;
 156     }
 157     /* read the irq from the PIC */
 158     if (!apic_accept_pic_intr(env))
 159         return -1;
 160
 161     intno = pic_read_irq(isa_pic);
 162     return intno;
 163 }
 164
 165 static void pic_irq_request(void *opaque, int irq, int level)
 166 {
 167     CPUState *env = first_cpu;
 168
 169     if (env->apic_state) {
 170         while (env) {
 171             if (apic_accept_pic_intr(env))
 172                 apic_deliver_pic_intr(env, level);
 173             env = env->next_cpu;
 174         }
 175     } else {
 176         if (level)
 177             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 178         else
 179             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 180     }
 181 }
 182
 183 /* PC cmos mappings */
 184
 185 #define REG_EQUIPMENT_BYTE          0x14
 186
 187 static int cmos_get_fd_drive_type(int fd0)
 188 {
 189     int val;
 190
 191     switch (fd0) {
 192     case 0:
 193         /* 1.44 Mb 3"5 drive */
 194         val = 4;
 195         break;
 196     case 1:
 197         /* 2.88 Mb 3"5 drive */
 198         val = 5;
 199         break;
 200     case 2:
 201         /* 1.2 Mb 5"5 drive */
 202         val = 2;
 203         break;
 204     default:
 205         val = 0;
 206         break;
 207     }
 208     return val;
 209 }
 210
 211 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 212 {
 213     RTCState *s = rtc_state;
 214     int cylinders, heads, sectors;
 215     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 216     rtc_set_memory(s, type_ofs, 47);
 217     rtc_set_memory(s, info_ofs, cylinders);
 218     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 219     rtc_set_memory(s, info_ofs + 2, heads);
 220     rtc_set_memory(s, info_ofs + 3, 0xff);
 221     rtc_set_memory(s, info_ofs + 4, 0xff);
 222     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 223     rtc_set_memory(s, info_ofs + 6, cylinders);
 224     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 225     rtc_set_memory(s, info_ofs + 8, sectors);
 226 }
 227
 228 /* convert boot_device letter to something recognizable by the bios */
 229 static int boot_device2nibble(char boot_device)
 230 {
 231     switch(boot_device) {
 232     case 'a':
 233     case 'b':
 234         return 0x01; /* floppy boot */
 235     case 'c':
 236         return 0x02; /* hard drive boot */
 237     case 'd':
 238         return 0x03; /* CD-ROM boot */
 239     case 'n':
 240         return 0x04; /* Network boot */
 241     }
 242     return 0;
 243 }
 244
 245 static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk)
 246 {
 247 #define PC_MAX_BOOT_DEVICES 3
 248     int nbds, bds[3] = { 0, };
 249     int i;
 250
 251     nbds = strlen(boot_device);
 252     if (nbds > PC_MAX_BOOT_DEVICES) {
 253         error_report("Too many boot devices for PC");
 254         return(1);
 255     }
 256     for (i = 0; i < nbds; i++) {
 257         bds[i] = boot_device2nibble(boot_device[i]);
 258         if (bds[i] == 0) {
 259             error_report("Invalid boot device for PC: '%c'",
 260                          boot_device[i]);
 261             return(1);
 262         }
 263     }
 264     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 265     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 266     return(0);
 267 }
 268
 269 static int pc_boot_set(void *opaque, const char *boot_device)
 270 {
 271     return set_boot_dev(opaque, boot_device, 0);
 272 }
 273
 274 /* hd_table must contain 4 block drivers */
 275 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 276                       const char *boot_device, DriveInfo **hd_table)
 277 {
 278     RTCState *s = rtc_state;
 279     int val;
 280     int fd0, fd1, nb;
 281     int i;
 282
 283     /* various important CMOS locations needed by PC/Bochs bios */
 284
 285     /* memory size */
 286     val = 640; /* base memory in K */
 287     rtc_set_memory(s, 0x15, val);
 288     rtc_set_memory(s, 0x16, val >> 8);
 289
 290     val = (ram_size / 1024) - 1024;
 291     if (val > 65535)
 292         val = 65535;
 293     rtc_set_memory(s, 0x17, val);
 294     rtc_set_memory(s, 0x18, val >> 8);
 295     rtc_set_memory(s, 0x30, val);
 296     rtc_set_memory(s, 0x31, val >> 8);
 297
 298     if (above_4g_mem_size) {
 299         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 300         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 301         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 302     }
 303
 304     if (ram_size > (16 * 1024 * 1024))
 305         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 306     else
 307         val = 0;
 308     if (val > 65535)
 309         val = 65535;
 310     rtc_set_memory(s, 0x34, val);
 311     rtc_set_memory(s, 0x35, val >> 8);
 312
 313     /* set the number of CPU */
 314     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 315
 316     /* set boot devices, and disable floppy signature check if requested */
 317     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 318         exit(1);
 319     }
 320
 321     /* floppy type */
 322
 323     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 324     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 325
 326     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 327     rtc_set_memory(s, 0x10, val);
 328
 329     val = 0;
 330     nb = 0;
 331     if (fd0 < 3)
 332         nb++;
 333     if (fd1 < 3)
 334         nb++;
 335     switch (nb) {
 336     case 0:
 337         break;
 338     case 1:
 339         val |= 0x01; /* 1 drive, ready for boot */
 340         break;
 341     case 2:
 342         val |= 0x41; /* 2 drives, ready for boot */
 343         break;
 344     }
 345     val |= 0x02; /* FPU is there */
 346     val |= 0x04; /* PS/2 mouse installed */
 347     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 348
 349     /* hard drives */
 350
 351     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 352     if (hd_table[0])
 353         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
 354     if (hd_table[1])
 355         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
 356
 357     val = 0;
 358     for (i = 0; i < 4; i++) {
 359         if (hd_table[i]) {
 360             int cylinders, heads, sectors, translation;
 361             /* NOTE: bdrv_get_geometry_hint() returns the physical
 362                 geometry.  It is always such that: 1 <= sects <= 63, 1
 363                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 364                 geometry can be different if a translation is done. */
 365             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 366             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 367                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 368                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 369                     /* No translation. */
 370                     translation = 0;
 371                 } else {
 372                     /* LBA translation. */
 373                     translation = 1;
 374                 }
 375             } else {
 376                 translation--;
 377             }
 378             val |= translation << (i * 2);
 379         }
 380     }
 381     rtc_set_memory(s, 0x39, val);
 382 }
 383
 384 void ioport_set_a20(int enable)
 385 {
 386     /* XXX: send to all CPUs ? */
 387     cpu_x86_set_a20(first_cpu, enable);
 388 }
 389
 390 int ioport_get_a20(void)
 391 {
 392     return ((first_cpu->a20_mask >> 20) & 1);
 393 }
 394
 395 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 396 {
 397     ioport_set_a20((val >> 1) & 1);
 398     /* XXX: bit 0 is fast reset */
 399 }
 400
 401 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 402 {
 403     return ioport_get_a20() << 1;
 404 }
 405
 406 /***********************************************************/
 407 /* Bochs BIOS debug ports */
 408
 409 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 410 {
 411     static const char shutdown_str[8] = "Shutdown";
 412     static int shutdown_index = 0;
 413
 414     switch(addr) {
 415         /* Bochs BIOS messages */
 416     case 0x400:
 417     case 0x401:
 418         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 419         exit(1);
 420     case 0x402:
 421     case 0x403:
 422 #ifdef DEBUG_BIOS
 423         fprintf(stderr, "%c", val);
 424 #endif
 425         break;
 426     case 0x8900:
 427         /* same as Bochs power off */
 428         if (val == shutdown_str[shutdown_index]) {
 429             shutdown_index++;
 430             if (shutdown_index == 8) {
 431                 shutdown_index = 0;
 432                 qemu_system_shutdown_request();
 433             }
 434         } else {
 435             shutdown_index = 0;
 436         }
 437         break;
 438
 439         /* LGPL'ed VGA BIOS messages */
 440     case 0x501:
 441     case 0x502:
 442         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 443         exit(1);
 444     case 0x500:
 445     case 0x503:
 446 #ifdef DEBUG_BIOS
 447         fprintf(stderr, "%c", val);
 448 #endif
 449         break;
 450     }
 451 }
 452
 453 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 454 {
 455     int index = e820_table.count;
 456     struct e820_entry *entry;
 457
 458     if (index >= E820_NR_ENTRIES)
 459         return -EBUSY;
 460     entry = &e820_table.entry[index];
 461
 462     entry->address = address;
 463     entry->length = length;
 464     entry->type = type;
 465
 466     e820_table.count++;
 467     return e820_table.count;
 468 }
 469
 470 static void *bochs_bios_init(void)
 471 {
 472     void *fw_cfg;
 473     uint8_t *smbios_table;
 474     size_t smbios_len;
 475     uint64_t *numa_fw_cfg;
 476     int i, j;
 477
 478     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 479     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 480     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 481     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 482     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 483
 484     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 485     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 486     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 487     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 488
 489     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 490
 491     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 492     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 493     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 494                      acpi_tables_len);
 495     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 496
 497     smbios_table = smbios_get_table(&smbios_len);
 498     if (smbios_table)
 499         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 500                          smbios_table, smbios_len);
 501     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 502                      sizeof(struct e820_table));
 503
 504     /* allocate memory for the NUMA channel: one (64bit) word for the number
 505      * of nodes, one word for each VCPU->node and one word for each node to
 506      * hold the amount of memory.
 507      */
 508     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 509     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 510     for (i = 0; i < smp_cpus; i++) {
 511         for (j = 0; j < nb_numa_nodes; j++) {
 512             if (node_cpumask[j] & (1 << i)) {
 513                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 514                 break;
 515             }
 516         }
 517     }
 518     for (i = 0; i < nb_numa_nodes; i++) {
 519         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 520     }
 521     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 522                      (1 + smp_cpus + nb_numa_nodes) * 8);
 523
 524     return fw_cfg;
 525 }
 526
 527 static long get_file_size(FILE *f)
 528 {
 529     long where, size;
 530
 531     /* XXX: on Unix systems, using fstat() probably makes more sense */
 532
 533     where = ftell(f);
 534     fseek(f, 0, SEEK_END);
 535     size = ftell(f);
 536     fseek(f, where, SEEK_SET);
 537
 538     return size;
 539 }
 540
 541 static void load_linux(void *fw_cfg,
 542                        const char *kernel_filename,
 543                        const char *initrd_filename,
 544                        const char *kernel_cmdline,
 545                        target_phys_addr_t max_ram_size)
 546 {
 547     uint16_t protocol;
 548     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 549     uint32_t initrd_max;
 550     uint8_t header[8192], *setup, *kernel, *initrd_data;
 551     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 552     FILE *f;
 553     char *vmode;
 554
 555     /* Align to 16 bytes as a paranoia measure */
 556     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 557
 558     /* load the kernel header */
 559     f = fopen(kernel_filename, "rb");
 560     if (!f || !(kernel_size = get_file_size(f)) ||
 561         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 562         MIN(ARRAY_SIZE(header), kernel_size)) {
 563         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 564                 kernel_filename, strerror(errno));
 565         exit(1);
 566     }
 567
 568     /* kernel protocol version */
 569 #if 0
 570     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 571 #endif
 572     if (ldl_p(header+0x202) == 0x53726448)
 573         protocol = lduw_p(header+0x206);
 574     else {
 575         /* This looks like a multiboot kernel. If it is, let's stop
 576            treating it like a Linux kernel. */
 577         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 578                            kernel_cmdline, kernel_size, header))
 579             return;
 580         protocol = 0;
 581     }
 582
 583     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 584         /* Low kernel */
 585         real_addr    = 0x90000;
 586         cmdline_addr = 0x9a000 - cmdline_size;
 587         prot_addr    = 0x10000;
 588     } else if (protocol < 0x202) {
 589         /* High but ancient kernel */
 590         real_addr    = 0x90000;
 591         cmdline_addr = 0x9a000 - cmdline_size;
 592         prot_addr    = 0x100000;
 593     } else {
 594         /* High and recent kernel */
 595         real_addr    = 0x10000;
 596         cmdline_addr = 0x20000;
 597         prot_addr    = 0x100000;
 598     }
 599
 600 #if 0
 601     fprintf(stderr,
 602             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 603             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 604             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 605             real_addr,
 606             cmdline_addr,
 607             prot_addr);
 608 #endif
 609
 610     /* highest address for loading the initrd */
 611     if (protocol >= 0x203)
 612         initrd_max = ldl_p(header+0x22c);
 613     else
 614         initrd_max = 0x37ffffff;
 615
 616     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 617         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 618
 619     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 620     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 621     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 622                      (uint8_t*)strdup(kernel_cmdline),
 623                      strlen(kernel_cmdline)+1);
 624
 625     if (protocol >= 0x202) {
 626         stl_p(header+0x228, cmdline_addr);
 627     } else {
 628         stw_p(header+0x20, 0xA33F);
 629         stw_p(header+0x22, cmdline_addr-real_addr);
 630     }
 631
 632     /* handle vga= parameter */
 633     vmode = strstr(kernel_cmdline, "vga=");
 634     if (vmode) {
 635         unsigned int video_mode;
 636         /* skip "vga=" */
 637         vmode += 4;
 638         if (!strncmp(vmode, "normal", 6)) {
 639             video_mode = 0xffff;
 640         } else if (!strncmp(vmode, "ext", 3)) {
 641             video_mode = 0xfffe;
 642         } else if (!strncmp(vmode, "ask", 3)) {
 643             video_mode = 0xfffd;
 644         } else {
 645             video_mode = strtol(vmode, NULL, 0);
 646         }
 647         stw_p(header+0x1fa, video_mode);
 648     }
 649
 650     /* loader type */
 651     /* High nybble = B reserved for Qemu; low nybble is revision number.
 652        If this code is substantially changed, you may want to consider
 653        incrementing the revision. */
 654     if (protocol >= 0x200)
 655         header[0x210] = 0xB0;
 656
 657     /* heap */
 658     if (protocol >= 0x201) {
 659         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 660         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 661     }
 662
 663     /* load initrd */
 664     if (initrd_filename) {
 665         if (protocol < 0x200) {
 666             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 667             exit(1);
 668         }
 669
 670         initrd_size = get_image_size(initrd_filename);
 671         if (initrd_size < 0) {
 672             fprintf(stderr, "qemu: error reading initrd %s\n",
 673                     initrd_filename);
 674             exit(1);
 675         }
 676
 677         initrd_addr = (initrd_max-initrd_size) & ~4095;
 678
 679         initrd_data = qemu_malloc(initrd_size);
 680         load_image(initrd_filename, initrd_data);
 681
 682         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 683         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 684         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 685
 686         stl_p(header+0x218, initrd_addr);
 687         stl_p(header+0x21c, initrd_size);
 688     }
 689
 690     /* load kernel and setup */
 691     setup_size = header[0x1f1];
 692     if (setup_size == 0)
 693         setup_size = 4;
 694     setup_size = (setup_size+1)*512;
 695     kernel_size -= setup_size;
 696
 697     setup  = qemu_malloc(setup_size);
 698     kernel = qemu_malloc(kernel_size);
 699     fseek(f, 0, SEEK_SET);
 700     if (fread(setup, 1, setup_size, f) != setup_size) {
 701         fprintf(stderr, "fread() failed\n");
 702         exit(1);
 703     }
 704     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 705         fprintf(stderr, "fread() failed\n");
 706         exit(1);
 707     }
 708     fclose(f);
 709     memcpy(setup, header, MIN(sizeof(header), setup_size));
 710
 711     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 712     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 713     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 714
 715     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 716     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 717     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 718
 719     option_rom[nb_option_roms] = "linuxboot.bin";
 720     nb_option_roms++;
 721 }
 722
 723 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 724 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 725 static const int ide_irq[2] = { 14, 15 };
 726
 727 #define NE2000_NB_MAX 6
 728
 729 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 730                                               0x280, 0x380 };
 731 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 732
 733 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 734 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 735
 736 #ifdef HAS_AUDIO
 737 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 738 {
 739     struct soundhw *c;
 740
 741     for (c = soundhw; c->name; ++c) {
 742         if (c->enabled) {
 743             if (c->isa) {
 744                 c->init.init_isa(pic);
 745             } else {
 746                 if (pci_bus) {
 747                     c->init.init_pci(pci_bus);
 748                 }
 749             }
 750         }
 751     }
 752 }
 753 #endif
 754
 755 static void pc_init_ne2k_isa(NICInfo *nd)
 756 {
 757     static int nb_ne2k = 0;
 758
 759     if (nb_ne2k == NE2000_NB_MAX)
 760         return;
 761     isa_ne2000_init(ne2000_io[nb_ne2k],
 762                     ne2000_irq[nb_ne2k], nd);
 763     nb_ne2k++;
 764 }
 765
 766 int cpu_is_bsp(CPUState *env)
 767 {
 768     /* We hard-wire the BSP to the first CPU. */
 769     return env->cpu_index == 0;
 770 }
 771
 772 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 773    BIOS will read it and start S3 resume at POST Entry */
 774 static void cmos_set_s3_resume(void *opaque, int irq, int level)
 775 {
 776     RTCState *s = opaque;
 777
 778     if (level) {
 779         rtc_set_memory(s, 0xF, 0xFE);
 780     }
 781 }
 782
 783 static void acpi_smi_interrupt(void *opaque, int irq, int level)
 784 {
 785     CPUState *s = opaque;
 786
 787     if (level) {
 788         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 789     }
 790 }
 791
 792 static CPUState *pc_new_cpu(const char *cpu_model)
 793 {
 794     CPUState *env;
 795
 796     env = cpu_init(cpu_model);
 797     if (!env) {
 798         fprintf(stderr, "Unable to find x86 CPU definition\n");
 799         exit(1);
 800     }
 801     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 802         env->cpuid_apic_id = env->cpu_index;
 803         /* APIC reset callback resets cpu */
 804         apic_init(env);
 805     } else {
 806         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 807     }
 808     return env;
 809 }
 810
 811 /* PC hardware initialisation */
 812 static void pc_init1(ram_addr_t ram_size,
 813                      const char *boot_device,
 814                      const char *kernel_filename,
 815                      const char *kernel_cmdline,
 816                      const char *initrd_filename,
 817                      const char *cpu_model,
 818                      int pci_enabled)
 819 {
 820     char *filename;
 821     int ret, linux_boot, i;
 822     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 823     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 824     int bios_size, isa_bios_size;
 825     PCIBus *pci_bus;
 826     PCII440FXState *i440fx_state;
 827     int piix3_devfn = -1;
 828     qemu_irq *cpu_irq;
 829     qemu_irq *isa_irq;
 830     qemu_irq *i8259;
 831     qemu_irq *cmos_s3;
 832     qemu_irq *smi_irq;
 833     IsaIrqState *isa_irq_state;
 834     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 835     DriveInfo *fd[MAX_FD];
 836     void *fw_cfg;
 837     PITState *pit;
 838
 839     if (ram_size >= 0xe0000000 ) {
 840         above_4g_mem_size = ram_size - 0xe0000000;
 841         below_4g_mem_size = 0xe0000000;
 842     } else {
 843         below_4g_mem_size = ram_size;
 844     }
 845
 846     linux_boot = (kernel_filename != NULL);
 847
 848     /* init CPUs */
 849     if (cpu_model == NULL) {
 850 #ifdef TARGET_X86_64
 851         cpu_model = "qemu64";
 852 #else
 853         cpu_model = "qemu32";
 854 #endif
 855     }
 856
 857     for (i = 0; i < smp_cpus; i++) {
 858         pc_new_cpu(cpu_model);
 859     }
 860
 861     vmport_init();
 862
 863     /* allocate RAM */
 864     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 865     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 866     cpu_register_physical_memory(0x100000,
 867                  below_4g_mem_size - 0x100000,
 868                  ram_addr + 0x100000);
 869
 870     /* above 4giga memory allocation */
 871     if (above_4g_mem_size > 0) {
 872 #if TARGET_PHYS_ADDR_BITS == 32
 873         hw_error("To much RAM for 32-bit physical address");
 874 #else
 875         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 876         cpu_register_physical_memory(0x100000000ULL,
 877                                      above_4g_mem_size,
 878                                      ram_addr);
 879 #endif
 880     }
 881
 882
 883     /* BIOS load */
 884     if (bios_name == NULL)
 885         bios_name = BIOS_FILENAME;
 886     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 887     if (filename) {
 888         bios_size = get_image_size(filename);
 889     } else {
 890         bios_size = -1;
 891     }
 892     if (bios_size <= 0 ||
 893         (bios_size % 65536) != 0) {
 894         goto bios_error;
 895     }
 896     bios_offset = qemu_ram_alloc(bios_size);
 897     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 898     if (ret != 0) {
 899     bios_error:
 900         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 901         exit(1);
 902     }
 903     if (filename) {
 904         qemu_free(filename);
 905     }
 906     /* map the last 128KB of the BIOS in ISA space */
 907     isa_bios_size = bios_size;
 908     if (isa_bios_size > (128 * 1024))
 909         isa_bios_size = 128 * 1024;
 910     cpu_register_physical_memory(0x100000 - isa_bios_size,
 911                                  isa_bios_size,
 912                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 913
 914     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 915     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 916
 917     /* map all the bios at the top of memory */
 918     cpu_register_physical_memory((uint32_t)(-bios_size),
 919                                  bios_size, bios_offset | IO_MEM_ROM);
 920
 921     fw_cfg = bochs_bios_init();
 922     rom_set_fw(fw_cfg);
 923
 924     if (linux_boot) {
 925         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 926     }
 927
 928     for (i = 0; i < nb_option_roms; i++) {
 929         rom_add_option(option_rom[i]);
 930     }
 931
 932     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 933     i8259 = i8259_init(cpu_irq[0]);
 934     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
 935     isa_irq_state->i8259 = i8259;
 936     if (pci_enabled) {
 937         isa_irq_state->ioapic = ioapic_init();
 938     }
 939     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 940
 941     if (pci_enabled) {
 942         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size);
 943     } else {
 944         pci_bus = NULL;
 945         isa_bus_new(NULL);
 946     }
 947     isa_bus_irqs(isa_irq);
 948
 949     ferr_irq = isa_reserve_irq(13);
 950
 951     /* init basic PC hardware */
 952     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 953
 954     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 955
 956     if (cirrus_vga_enabled) {
 957         if (pci_enabled) {
 958             pci_cirrus_vga_init(pci_bus);
 959         } else {
 960             isa_cirrus_vga_init();
 961         }
 962     } else if (vmsvga_enabled) {
 963         if (pci_enabled)
 964             pci_vmsvga_init(pci_bus);
 965         else
 966             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 967     } else if (std_vga_enabled) {
 968         if (pci_enabled) {
 969             pci_vga_init(pci_bus, 0, 0);
 970         } else {
 971             isa_vga_init();
 972         }
 973     }
 974
 975     rtc_state = rtc_init(2000);
 976
 977     qemu_register_boot_set(pc_boot_set, rtc_state);
 978
 979     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
 980     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
 981
 982     pit = pit_init(0x40, isa_reserve_irq(0));
 983     pcspk_init(pit);
 984     if (!no_hpet) {
 985         hpet_init(isa_irq);
 986     }
 987
 988     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 989         if (serial_hds[i]) {
 990             serial_isa_init(i, serial_hds[i]);
 991         }
 992     }
 993
 994     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 995         if (parallel_hds[i]) {
 996             parallel_init(i, parallel_hds[i]);
 997         }
 998     }
 999
1000     for(i = 0; i < nb_nics; i++) {
1001         NICInfo *nd = &nd_table[i];
1002
1003         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1004             pc_init_ne2k_isa(nd);
1005         else
1006             pci_nic_init_nofail(nd, "e1000", NULL);
1007     }
1008
1009     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1010         fprintf(stderr, "qemu: too many IDE bus\n");
1011         exit(1);
1012     }
1013
1014     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1015         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1016     }
1017
1018     if (pci_enabled) {
1019         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
1020     } else {
1021         for(i = 0; i < MAX_IDE_BUS; i++) {
1022             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
1023                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1024         }
1025     }
1026
1027     isa_create_simple("i8042");
1028     DMA_init(0);
1029 #ifdef HAS_AUDIO
1030     audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1031 #endif
1032
1033     for(i = 0; i < MAX_FD; i++) {
1034         fd[i] = drive_get(IF_FLOPPY, 0, i);
1035     }
1036     floppy_controller = fdctrl_init_isa(fd);
1037
1038     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1039
1040     if (pci_enabled && usb_enabled) {
1041         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1042     }
1043
1044     if (pci_enabled && acpi_enabled) {
1045         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1046         i2c_bus *smbus;
1047
1048         cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1);
1049         smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1);
1050         /* TODO: Populate SPD eeprom data.  */
1051         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1052                               isa_reserve_irq(9), *cmos_s3, *smi_irq,
1053                               kvm_enabled());
1054         for (i = 0; i < 8; i++) {
1055             DeviceState *eeprom;
1056             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1057             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1058             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1059             qdev_init_nofail(eeprom);
1060         }
1061         piix4_acpi_system_hot_add_init(pci_bus);
1062     }
1063
1064     if (i440fx_state) {
1065         i440fx_init_memory_mappings(i440fx_state);
1066     }
1067
1068     if (pci_enabled) {
1069         int max_bus;
1070         int bus;
1071
1072         max_bus = drive_get_max_bus(IF_SCSI);
1073         for (bus = 0; bus <= max_bus; bus++) {
1074             pci_create_simple(pci_bus, -1, "lsi53c895a");
1075         }
1076     }
1077 }
1078
1079 static void pc_init_pci(ram_addr_t ram_size,
1080                         const char *boot_device,
1081                         const char *kernel_filename,
1082                         const char *kernel_cmdline,
1083                         const char *initrd_filename,
1084                         const char *cpu_model)
1085 {
1086     pc_init1(ram_size, boot_device,
1087              kernel_filename, kernel_cmdline,
1088              initrd_filename, cpu_model, 1);
1089 }
1090
1091 static void pc_init_isa(ram_addr_t ram_size,
1092                         const char *boot_device,
1093                         const char *kernel_filename,
1094                         const char *kernel_cmdline,
1095                         const char *initrd_filename,
1096                         const char *cpu_model)
1097 {
1098     if (cpu_model == NULL)
1099         cpu_model = "486";
1100     pc_init1(ram_size, boot_device,
1101              kernel_filename, kernel_cmdline,
1102              initrd_filename, cpu_model, 0);
1103 }
1104
1105 static QEMUMachine pc_machine = {
1106     .name = "pc-0.13",
1107     .alias = "pc",
1108     .desc = "Standard PC",
1109     .init = pc_init_pci,
1110     .max_cpus = 255,
1111     .is_default = 1,
1112 };
1113
1114 static QEMUMachine pc_machine_v0_12 = {
1115     .name = "pc-0.12",
1116     .desc = "Standard PC",
1117     .init = pc_init_pci,
1118     .max_cpus = 255,
1119     .compat_props = (GlobalProperty[]) {
1120         {
1121             .driver   = "virtio-serial-pci",
1122             .property = "max_nr_ports",
1123             .value    = stringify(1),
1124         },{
1125             .driver   = "virtio-serial-pci",
1126             .property = "vectors",
1127             .value    = stringify(0),
1128         },
1129         { /* end of list */ }
1130     }
1131 };
1132
1133 static QEMUMachine pc_machine_v0_11 = {
1134     .name = "pc-0.11",
1135     .desc = "Standard PC, qemu 0.11",
1136     .init = pc_init_pci,
1137     .max_cpus = 255,
1138     .compat_props = (GlobalProperty[]) {
1139         {
1140             .driver   = "virtio-blk-pci",
1141             .property = "vectors",
1142             .value    = stringify(0),
1143         },{
1144             .driver   = "virtio-serial-pci",
1145             .property = "max_nr_ports",
1146             .value    = stringify(1),
1147         },{
1148             .driver   = "virtio-serial-pci",
1149             .property = "vectors",
1150             .value    = stringify(0),
1151         },{
1152             .driver   = "ide-drive",
1153             .property = "ver",
1154             .value    = "0.11",
1155         },{
1156             .driver   = "scsi-disk",
1157             .property = "ver",
1158             .value    = "0.11",
1159         },{
1160             .driver   = "PCI",
1161             .property = "rombar",
1162             .value    = stringify(0),
1163         },
1164         { /* end of list */ }
1165     }
1166 };
1167
1168 static QEMUMachine pc_machine_v0_10 = {
1169     .name = "pc-0.10",
1170     .desc = "Standard PC, qemu 0.10",
1171     .init = pc_init_pci,
1172     .max_cpus = 255,
1173     .compat_props = (GlobalProperty[]) {
1174         {
1175             .driver   = "virtio-blk-pci",
1176             .property = "class",
1177             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1178         },{
1179             .driver   = "virtio-serial-pci",
1180             .property = "class",
1181             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1182         },{
1183             .driver   = "virtio-serial-pci",
1184             .property = "max_nr_ports",
1185             .value    = stringify(1),
1186         },{
1187             .driver   = "virtio-serial-pci",
1188             .property = "vectors",
1189             .value    = stringify(0),
1190         },{
1191             .driver   = "virtio-net-pci",
1192             .property = "vectors",
1193             .value    = stringify(0),
1194         },{
1195             .driver   = "virtio-blk-pci",
1196             .property = "vectors",
1197             .value    = stringify(0),
1198         },{
1199             .driver   = "ide-drive",
1200             .property = "ver",
1201             .value    = "0.10",
1202         },{
1203             .driver   = "scsi-disk",
1204             .property = "ver",
1205             .value    = "0.10",
1206         },{
1207             .driver   = "PCI",
1208             .property = "rombar",
1209             .value    = stringify(0),
1210         },
1211         { /* end of list */ }
1212     },
1213 };
1214
1215 static QEMUMachine isapc_machine = {
1216     .name = "isapc",
1217     .desc = "ISA-only PC",
1218     .init = pc_init_isa,
1219     .max_cpus = 1,
1220 };
1221
1222 static void pc_machine_init(void)
1223 {
1224     qemu_register_machine(&pc_machine);
1225     qemu_register_machine(&pc_machine_v0_12);
1226     qemu_register_machine(&pc_machine_v0_11);
1227     qemu_register_machine(&pc_machine_v0_10);
1228     qemu_register_machine(&isapc_machine);
1229 }
1230
1231 machine_init(pc_machine_init);