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tcg/x86_64: Special-case all 32-bit AND operands.
[qemu/aliguori-queue.git] / tcg / x86_64 / tcg-target.c
blob8c7e738180d5814f98eedba2a7b49f005b0f4c87
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef NDEBUG
26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27 "%rax",
28 "%rcx",
29 "%rdx",
30 "%rbx",
31 "%rsp",
32 "%rbp",
33 "%rsi",
34 "%rdi",
35 "%r8",
36 "%r9",
37 "%r10",
38 "%r11",
39 "%r12",
40 "%r13",
41 "%r14",
42 "%r15",
43 };
44 #endif
45
46 static const int tcg_target_reg_alloc_order[] = {
47 TCG_REG_RBP,
48 TCG_REG_RBX,
49 TCG_REG_R12,
50 TCG_REG_R13,
51 TCG_REG_R14,
52 TCG_REG_R15,
53 TCG_REG_R10,
54 TCG_REG_R11,
55 TCG_REG_R9,
56 TCG_REG_R8,
57 TCG_REG_RCX,
58 TCG_REG_RDX,
59 TCG_REG_RSI,
60 TCG_REG_RDI,
61 TCG_REG_RAX,
62 };
63
64 static const int tcg_target_call_iarg_regs[6] = {
65 TCG_REG_RDI,
66 TCG_REG_RSI,
67 TCG_REG_RDX,
68 TCG_REG_RCX,
69 TCG_REG_R8,
70 TCG_REG_R9,
71 };
72
73 static const int tcg_target_call_oarg_regs[2] = {
74 TCG_REG_RAX,
75 TCG_REG_RDX
76 };
77
78 static uint8_t *tb_ret_addr;
79
80 static void patch_reloc(uint8_t *code_ptr, int type,
81 tcg_target_long value, tcg_target_long addend)
82 {
83 value += addend;
84 switch(type) {
85 case R_X86_64_32:
86 if (value != (uint32_t)value)
87 tcg_abort();
88 *(uint32_t *)code_ptr = value;
89 break;
90 case R_X86_64_32S:
91 if (value != (int32_t)value)
92 tcg_abort();
93 *(uint32_t *)code_ptr = value;
94 break;
95 case R_386_PC32:
96 value -= (long)code_ptr;
97 if (value != (int32_t)value)
98 tcg_abort();
99 *(uint32_t *)code_ptr = value;
100 break;
101 default:
102 tcg_abort();
103 }
104 }
105
106 /* maximum number of register used for input function arguments */
107 static inline int tcg_target_get_call_iarg_regs_count(int flags)
108 {
109 return 6;
110 }
111
112 /* parse target specific constraints */
113 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
114 {
115 const char *ct_str;
116
117 ct_str = *pct_str;
118 switch(ct_str[0]) {
119 case 'a':
120 ct->ct |= TCG_CT_REG;
121 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
122 break;
123 case 'b':
124 ct->ct |= TCG_CT_REG;
125 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
126 break;
127 case 'c':
128 ct->ct |= TCG_CT_REG;
129 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
130 break;
131 case 'd':
132 ct->ct |= TCG_CT_REG;
133 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
134 break;
135 case 'S':
136 ct->ct |= TCG_CT_REG;
137 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
138 break;
139 case 'D':
140 ct->ct |= TCG_CT_REG;
141 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
142 break;
143 case 'q':
144 ct->ct |= TCG_CT_REG;
145 tcg_regset_set32(ct->u.regs, 0, 0xf);
146 break;
147 case 'r':
148 ct->ct |= TCG_CT_REG;
149 tcg_regset_set32(ct->u.regs, 0, 0xffff);
150 break;
151 case 'L': /* qemu_ld/st constraint */
152 ct->ct |= TCG_CT_REG;
153 tcg_regset_set32(ct->u.regs, 0, 0xffff);
154 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
156 break;
157 case 'e':
158 ct->ct |= TCG_CT_CONST_S32;
159 break;
160 case 'Z':
161 ct->ct |= TCG_CT_CONST_U32;
162 break;
163 default:
164 return -1;
165 }
166 ct_str++;
167 *pct_str = ct_str;
168 return 0;
169 }
170
171 /* test if a constant matches the constraint */
172 static inline int tcg_target_const_match(tcg_target_long val,
173 const TCGArgConstraint *arg_ct)
174 {
175 int ct;
176 ct = arg_ct->ct;
177 if (ct & TCG_CT_CONST)
178 return 1;
179 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
180 return 1;
181 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
182 return 1;
183 else
184 return 0;
185 }
186
187 #define ARITH_ADD 0
188 #define ARITH_OR 1
189 #define ARITH_ADC 2
190 #define ARITH_SBB 3
191 #define ARITH_AND 4
192 #define ARITH_SUB 5
193 #define ARITH_XOR 6
194 #define ARITH_CMP 7
195
196 #define SHIFT_ROL 0
197 #define SHIFT_ROR 1
198 #define SHIFT_SHL 4
199 #define SHIFT_SHR 5
200 #define SHIFT_SAR 7
201
202 #define JCC_JMP (-1)
203 #define JCC_JO 0x0
204 #define JCC_JNO 0x1
205 #define JCC_JB 0x2
206 #define JCC_JAE 0x3
207 #define JCC_JE 0x4
208 #define JCC_JNE 0x5
209 #define JCC_JBE 0x6
210 #define JCC_JA 0x7
211 #define JCC_JS 0x8
212 #define JCC_JNS 0x9
213 #define JCC_JP 0xa
214 #define JCC_JNP 0xb
215 #define JCC_JL 0xc
216 #define JCC_JGE 0xd
217 #define JCC_JLE 0xe
218 #define JCC_JG 0xf
219
220 #define P_EXT 0x100 /* 0x0f opcode prefix */
221 #define P_REXW 0x200 /* set rex.w = 1 */
222 #define P_REXB 0x400 /* force rex use for byte registers */
223
224 static const uint8_t tcg_cond_to_jcc[10] = {
225 [TCG_COND_EQ] = JCC_JE,
226 [TCG_COND_NE] = JCC_JNE,
227 [TCG_COND_LT] = JCC_JL,
228 [TCG_COND_GE] = JCC_JGE,
229 [TCG_COND_LE] = JCC_JLE,
230 [TCG_COND_GT] = JCC_JG,
231 [TCG_COND_LTU] = JCC_JB,
232 [TCG_COND_GEU] = JCC_JAE,
233 [TCG_COND_LEU] = JCC_JBE,
234 [TCG_COND_GTU] = JCC_JA,
235 };
236
237 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
238 {
239 int rex;
240 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
241 ((x >> 2) & 2) | ((rm >> 3) & 1);
242 if (rex || (opc & P_REXB)) {
243 tcg_out8(s, rex | 0x40);
244 }
245 if (opc & P_EXT)
246 tcg_out8(s, 0x0f);
247 tcg_out8(s, opc & 0xff);
248 }
249
250 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
251 {
252 tcg_out_opc(s, opc, r, rm, 0);
253 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
254 }
255
256 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
257 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
258 tcg_target_long offset)
259 {
260 if (rm < 0) {
261 tcg_target_long val;
262 tcg_out_opc(s, opc, r, 0, 0);
263 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
264 if (val == (int32_t)val) {
265 /* eip relative */
266 tcg_out8(s, 0x05 | ((r & 7) << 3));
267 tcg_out32(s, val);
268 } else if (offset == (int32_t)offset) {
269 tcg_out8(s, 0x04 | ((r & 7) << 3));
270 tcg_out8(s, 0x25); /* sib */
271 tcg_out32(s, offset);
272 } else {
273 tcg_abort();
274 }
275 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
276 tcg_out_opc(s, opc, r, rm, 0);
277 if ((rm & 7) == TCG_REG_RSP) {
278 tcg_out8(s, 0x04 | ((r & 7) << 3));
279 tcg_out8(s, 0x24);
280 } else {
281 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
282 }
283 } else if ((int8_t)offset == offset) {
284 tcg_out_opc(s, opc, r, rm, 0);
285 if ((rm & 7) == TCG_REG_RSP) {
286 tcg_out8(s, 0x44 | ((r & 7) << 3));
287 tcg_out8(s, 0x24);
288 } else {
289 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
290 }
291 tcg_out8(s, offset);
292 } else {
293 tcg_out_opc(s, opc, r, rm, 0);
294 if ((rm & 7) == TCG_REG_RSP) {
295 tcg_out8(s, 0x84 | ((r & 7) << 3));
296 tcg_out8(s, 0x24);
297 } else {
298 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
299 }
300 tcg_out32(s, offset);
301 }
302 }
303
304 #if defined(CONFIG_SOFTMMU)
305 /* XXX: incomplete. index must be different from ESP */
306 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
307 int index, int shift,
308 tcg_target_long offset)
309 {
310 int mod;
311 if (rm == -1)
312 tcg_abort();
313 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
314 mod = 0;
315 } else if (offset == (int8_t)offset) {
316 mod = 0x40;
317 } else if (offset == (int32_t)offset) {
318 mod = 0x80;
319 } else {
320 tcg_abort();
321 }
322 if (index == -1) {
323 tcg_out_opc(s, opc, r, rm, 0);
324 if ((rm & 7) == TCG_REG_RSP) {
325 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
326 tcg_out8(s, 0x04 | (rm & 7));
327 } else {
328 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
329 }
330 } else {
331 tcg_out_opc(s, opc, r, rm, index);
332 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
333 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
334 }
335 if (mod == 0x40) {
336 tcg_out8(s, offset);
337 } else if (mod == 0x80) {
338 tcg_out32(s, offset);
339 }
340 }
341 #endif
342
343 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
344 {
345 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
346 }
347
348 static inline void tcg_out_movi(TCGContext *s, TCGType type,
349 int ret, tcg_target_long arg)
350 {
351 if (arg == 0) {
352 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
353 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
354 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
355 tcg_out32(s, arg);
356 } else if (arg == (int32_t)arg) {
357 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
358 tcg_out32(s, arg);
359 } else {
360 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
361 tcg_out32(s, arg);
362 tcg_out32(s, arg >> 32);
363 }
364 }
365
366 static void tcg_out_goto(TCGContext *s, int call, uint8_t *target)
367 {
368 int32_t disp;
369
370 disp = target - s->code_ptr - 5;
371 if (disp == (target - s->code_ptr - 5)) {
372 tcg_out8(s, call ? 0xe8 : 0xe9);
373 tcg_out32(s, disp);
374 } else {
375 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target);
376 tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10);
377 }
378 }
379
380 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
381 int arg1, tcg_target_long arg2)
382 {
383 if (type == TCG_TYPE_I32)
384 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
385 else
386 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
387 }
388
389 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
390 int arg1, tcg_target_long arg2)
391 {
392 if (type == TCG_TYPE_I32)
393 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
394 else
395 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
396 }
397
398 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
399 {
400 if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
401 /* inc */
402 tcg_out_modrm(s, 0xff, 0, r0);
403 } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
404 /* dec */
405 tcg_out_modrm(s, 0xff, 1, r0);
406 } else if (val == (int8_t)val) {
407 tcg_out_modrm(s, 0x83, c, r0);
408 tcg_out8(s, val);
409 } else if (c == ARITH_AND && val == 0xffu) {
410 /* movzbl */
411 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
412 } else if (c == ARITH_AND && val == 0xffffu) {
413 /* movzwl */
414 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
415 } else {
416 tcg_out_modrm(s, 0x81, c, r0);
417 tcg_out32(s, val);
418 }
419 }
420
421 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
422 {
423 if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
424 /* inc */
425 tcg_out_modrm(s, 0xff | P_REXW, 0, r0);
426 } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
427 /* dec */
428 tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
429 } else if (c == ARITH_AND && val == 0xffffffffu) {
430 /* 32-bit mov zero extends */
431 tcg_out_modrm(s, 0x8b, r0, r0);
432 } else if (c == ARITH_AND && val == (uint32_t)val) {
433 /* AND with no high bits set can use a 32-bit operation. */
434 tgen_arithi32(s, c, r0, (uint32_t)val);
435 } else if (val == (int8_t)val) {
436 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
437 tcg_out8(s, val);
438 } else if (val == (int32_t)val) {
439 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
440 tcg_out32(s, val);
441 } else {
442 tcg_abort();
443 }
444 }
445
446 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
447 {
448 if (val != 0)
449 tgen_arithi64(s, ARITH_ADD, reg, val);
450 }
451
452 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
453 {
454 int32_t val, val1;
455 TCGLabel *l = &s->labels[label_index];
456
457 if (l->has_value) {
458 val = l->u.value - (tcg_target_long)s->code_ptr;
459 val1 = val - 2;
460 if ((int8_t)val1 == val1) {
461 if (opc == -1)
462 tcg_out8(s, 0xeb);
463 else
464 tcg_out8(s, 0x70 + opc);
465 tcg_out8(s, val1);
466 } else {
467 if (opc == -1) {
468 tcg_out8(s, 0xe9);
469 tcg_out32(s, val - 5);
470 } else {
471 tcg_out8(s, 0x0f);
472 tcg_out8(s, 0x80 + opc);
473 tcg_out32(s, val - 6);
474 }
475 }
476 } else {
477 if (opc == -1) {
478 tcg_out8(s, 0xe9);
479 } else {
480 tcg_out8(s, 0x0f);
481 tcg_out8(s, 0x80 + opc);
482 }
483 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
484 s->code_ptr += 4;
485 }
486 }
487
488 static void tcg_out_brcond(TCGContext *s, int cond,
489 TCGArg arg1, TCGArg arg2, int const_arg2,
490 int label_index, int rexw)
491 {
492 if (const_arg2) {
493 if (arg2 == 0) {
494 /* test r, r */
495 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
496 } else {
497 if (rexw)
498 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
499 else
500 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
501 }
502 } else {
503 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
504 }
505 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
506 }
507
508 #if defined(CONFIG_SOFTMMU)
509
510 #include "../../softmmu_defs.h"
511
512 static void *qemu_ld_helpers[4] = {
513 __ldb_mmu,
514 __ldw_mmu,
515 __ldl_mmu,
516 __ldq_mmu,
517 };
518
519 static void *qemu_st_helpers[4] = {
520 __stb_mmu,
521 __stw_mmu,
522 __stl_mmu,
523 __stq_mmu,
524 };
525 #endif
526
527 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
528 int opc)
529 {
530 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
531 int32_t offset;
532 #if defined(CONFIG_SOFTMMU)
533 uint8_t *label1_ptr, *label2_ptr;
534 #endif
535
536 data_reg = *args++;
537 addr_reg = *args++;
538 mem_index = *args;
539 s_bits = opc & 3;
540
541 r0 = TCG_REG_RDI;
542 r1 = TCG_REG_RSI;
543
544 #if TARGET_LONG_BITS == 32
545 rexw = 0;
546 #else
547 rexw = P_REXW;
548 #endif
549 #if defined(CONFIG_SOFTMMU)
550 /* mov */
551 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
552
553 /* mov */
554 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
555
556 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
557 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
558
559 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
560 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
561
562 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
563 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
564
565 /* lea offset(r1, env), r1 */
566 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
567 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
568
569 /* cmp 0(r1), r0 */
570 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
571
572 /* mov */
573 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
574
575 /* je label1 */
576 tcg_out8(s, 0x70 + JCC_JE);
577 label1_ptr = s->code_ptr;
578 s->code_ptr++;
579
580 /* XXX: move that code at the end of the TB */
581 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
582 tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
583
584 switch(opc) {
585 case 0 | 4:
586 /* movsbq */
587 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
588 break;
589 case 1 | 4:
590 /* movswq */
591 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
592 break;
593 case 2 | 4:
594 /* movslq */
595 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
596 break;
597 case 0:
598 /* movzbq */
599 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
600 break;
601 case 1:
602 /* movzwq */
603 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
604 break;
605 case 2:
606 default:
607 /* movl */
608 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
609 break;
610 case 3:
611 tcg_out_mov(s, data_reg, TCG_REG_RAX);
612 break;
613 }
614
615 /* jmp label2 */
616 tcg_out8(s, 0xeb);
617 label2_ptr = s->code_ptr;
618 s->code_ptr++;
619
620 /* label1: */
621 *label1_ptr = s->code_ptr - label1_ptr - 1;
622
623 /* add x(r1), r0 */
624 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
625 offsetof(CPUTLBEntry, addr_read));
626 offset = 0;
627 #else
628 if (GUEST_BASE == (int32_t)GUEST_BASE) {
629 r0 = addr_reg;
630 offset = GUEST_BASE;
631 } else {
632 offset = 0;
633 /* movq $GUEST_BASE, r0 */
634 tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
635 tcg_out32(s, GUEST_BASE);
636 tcg_out32(s, GUEST_BASE >> 32);
637 /* addq addr_reg, r0 */
638 tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
639 }
640 #endif
641
642 #ifdef TARGET_WORDS_BIGENDIAN
643 bswap = 1;
644 #else
645 bswap = 0;
646 #endif
647 switch(opc) {
648 case 0:
649 /* movzbl */
650 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
651 break;
652 case 0 | 4:
653 /* movsbX */
654 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
655 break;
656 case 1:
657 /* movzwl */
658 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
659 if (bswap) {
660 /* rolw $8, data_reg */
661 tcg_out8(s, 0x66);
662 tcg_out_modrm(s, 0xc1, 0, data_reg);
663 tcg_out8(s, 8);
664 }
665 break;
666 case 1 | 4:
667 if (bswap) {
668 /* movzwl */
669 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
670 /* rolw $8, data_reg */
671 tcg_out8(s, 0x66);
672 tcg_out_modrm(s, 0xc1, 0, data_reg);
673 tcg_out8(s, 8);
674
675 /* movswX data_reg, data_reg */
676 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
677 } else {
678 /* movswX */
679 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
680 }
681 break;
682 case 2:
683 /* movl (r0), data_reg */
684 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
685 if (bswap) {
686 /* bswap */
687 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
688 }
689 break;
690 case 2 | 4:
691 if (bswap) {
692 /* movl (r0), data_reg */
693 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
694 /* bswap */
695 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
696 /* movslq */
697 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
698 } else {
699 /* movslq */
700 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
701 }
702 break;
703 case 3:
704 /* movq (r0), data_reg */
705 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
706 if (bswap) {
707 /* bswap */
708 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
709 }
710 break;
711 default:
712 tcg_abort();
713 }
714
715 #if defined(CONFIG_SOFTMMU)
716 /* label2: */
717 *label2_ptr = s->code_ptr - label2_ptr - 1;
718 #endif
719 }
720
721 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
722 int opc)
723 {
724 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
725 int32_t offset;
726 #if defined(CONFIG_SOFTMMU)
727 uint8_t *label1_ptr, *label2_ptr;
728 #endif
729
730 data_reg = *args++;
731 addr_reg = *args++;
732 mem_index = *args;
733
734 s_bits = opc;
735
736 r0 = TCG_REG_RDI;
737 r1 = TCG_REG_RSI;
738
739 #if TARGET_LONG_BITS == 32
740 rexw = 0;
741 #else
742 rexw = P_REXW;
743 #endif
744 #if defined(CONFIG_SOFTMMU)
745 /* mov */
746 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
747
748 /* mov */
749 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
750
751 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
752 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
753
754 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
755 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
756
757 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
758 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
759
760 /* lea offset(r1, env), r1 */
761 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
762 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
763
764 /* cmp 0(r1), r0 */
765 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
766
767 /* mov */
768 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
769
770 /* je label1 */
771 tcg_out8(s, 0x70 + JCC_JE);
772 label1_ptr = s->code_ptr;
773 s->code_ptr++;
774
775 /* XXX: move that code at the end of the TB */
776 switch(opc) {
777 case 0:
778 /* movzbl */
779 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
780 break;
781 case 1:
782 /* movzwl */
783 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
784 break;
785 case 2:
786 /* movl */
787 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
788 break;
789 default:
790 case 3:
791 tcg_out_mov(s, TCG_REG_RSI, data_reg);
792 break;
793 }
794 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
795 tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
796
797 /* jmp label2 */
798 tcg_out8(s, 0xeb);
799 label2_ptr = s->code_ptr;
800 s->code_ptr++;
801
802 /* label1: */
803 *label1_ptr = s->code_ptr - label1_ptr - 1;
804
805 /* add x(r1), r0 */
806 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
807 offsetof(CPUTLBEntry, addr_write));
808 offset = 0;
809 #else
810 if (GUEST_BASE == (int32_t)GUEST_BASE) {
811 r0 = addr_reg;
812 offset = GUEST_BASE;
813 } else {
814 offset = 0;
815 /* movq $GUEST_BASE, r0 */
816 tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
817 tcg_out32(s, GUEST_BASE);
818 tcg_out32(s, GUEST_BASE >> 32);
819 /* addq addr_reg, r0 */
820 tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
821 }
822 #endif
823
824 #ifdef TARGET_WORDS_BIGENDIAN
825 bswap = 1;
826 #else
827 bswap = 0;
828 #endif
829 switch(opc) {
830 case 0:
831 /* movb */
832 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, offset);
833 break;
834 case 1:
835 if (bswap) {
836 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
837 tcg_out8(s, 0x66); /* rolw $8, %ecx */
838 tcg_out_modrm(s, 0xc1, 0, r1);
839 tcg_out8(s, 8);
840 data_reg = r1;
841 }
842 /* movw */
843 tcg_out8(s, 0x66);
844 tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
845 break;
846 case 2:
847 if (bswap) {
848 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
849 /* bswap data_reg */
850 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
851 data_reg = r1;
852 }
853 /* movl */
854 tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
855 break;
856 case 3:
857 if (bswap) {
858 tcg_out_mov(s, r1, data_reg);
859 /* bswap data_reg */
860 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
861 data_reg = r1;
862 }
863 /* movq */
864 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
865 break;
866 default:
867 tcg_abort();
868 }
869
870 #if defined(CONFIG_SOFTMMU)
871 /* label2: */
872 *label2_ptr = s->code_ptr - label2_ptr - 1;
873 #endif
874 }
875
876 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
877 const int *const_args)
878 {
879 int c;
880
881 switch(opc) {
882 case INDEX_op_exit_tb:
883 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
884 tcg_out_goto(s, 0, tb_ret_addr);
885 break;
886 case INDEX_op_goto_tb:
887 if (s->tb_jmp_offset) {
888 /* direct jump method */
889 tcg_out8(s, 0xe9); /* jmp im */
890 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
891 tcg_out32(s, 0);
892 } else {
893 /* indirect jump method */
894 /* jmp Ev */
895 tcg_out_modrm_offset(s, 0xff, 4, -1,
896 (tcg_target_long)(s->tb_next +
897 args[0]));
898 }
899 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
900 break;
901 case INDEX_op_call:
902 if (const_args[0]) {
903 tcg_out_goto(s, 1, (void *) args[0]);
904 } else {
905 tcg_out_modrm(s, 0xff, 2, args[0]);
906 }
907 break;
908 case INDEX_op_jmp:
909 if (const_args[0]) {
910 tcg_out_goto(s, 0, (void *) args[0]);
911 } else {
912 tcg_out_modrm(s, 0xff, 4, args[0]);
913 }
914 break;
915 case INDEX_op_br:
916 tcg_out_jxx(s, JCC_JMP, args[0]);
917 break;
918 case INDEX_op_movi_i32:
919 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
920 break;
921 case INDEX_op_movi_i64:
922 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
923 break;
924 case INDEX_op_ld8u_i32:
925 case INDEX_op_ld8u_i64:
926 /* movzbl */
927 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
928 break;
929 case INDEX_op_ld8s_i32:
930 /* movsbl */
931 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
932 break;
933 case INDEX_op_ld8s_i64:
934 /* movsbq */
935 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
936 break;
937 case INDEX_op_ld16u_i32:
938 case INDEX_op_ld16u_i64:
939 /* movzwl */
940 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
941 break;
942 case INDEX_op_ld16s_i32:
943 /* movswl */
944 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
945 break;
946 case INDEX_op_ld16s_i64:
947 /* movswq */
948 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
949 break;
950 case INDEX_op_ld_i32:
951 case INDEX_op_ld32u_i64:
952 /* movl */
953 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
954 break;
955 case INDEX_op_ld32s_i64:
956 /* movslq */
957 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
958 break;
959 case INDEX_op_ld_i64:
960 /* movq */
961 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
962 break;
963
964 case INDEX_op_st8_i32:
965 case INDEX_op_st8_i64:
966 /* movb */
967 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
968 break;
969 case INDEX_op_st16_i32:
970 case INDEX_op_st16_i64:
971 /* movw */
972 tcg_out8(s, 0x66);
973 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
974 break;
975 case INDEX_op_st_i32:
976 case INDEX_op_st32_i64:
977 /* movl */
978 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
979 break;
980 case INDEX_op_st_i64:
981 /* movq */
982 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
983 break;
984
985 case INDEX_op_sub_i32:
986 c = ARITH_SUB;
987 goto gen_arith32;
988 case INDEX_op_and_i32:
989 c = ARITH_AND;
990 goto gen_arith32;
991 case INDEX_op_or_i32:
992 c = ARITH_OR;
993 goto gen_arith32;
994 case INDEX_op_xor_i32:
995 c = ARITH_XOR;
996 goto gen_arith32;
997 case INDEX_op_add_i32:
998 c = ARITH_ADD;
999 gen_arith32:
1000 if (const_args[2]) {
1001 tgen_arithi32(s, c, args[0], args[2]);
1002 } else {
1003 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
1004 }
1005 break;
1006
1007 case INDEX_op_sub_i64:
1008 c = ARITH_SUB;
1009 goto gen_arith64;
1010 case INDEX_op_and_i64:
1011 c = ARITH_AND;
1012 goto gen_arith64;
1013 case INDEX_op_or_i64:
1014 c = ARITH_OR;
1015 goto gen_arith64;
1016 case INDEX_op_xor_i64:
1017 c = ARITH_XOR;
1018 goto gen_arith64;
1019 case INDEX_op_add_i64:
1020 c = ARITH_ADD;
1021 gen_arith64:
1022 if (const_args[2]) {
1023 tgen_arithi64(s, c, args[0], args[2]);
1024 } else {
1025 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
1026 }
1027 break;
1028
1029 case INDEX_op_mul_i32:
1030 if (const_args[2]) {
1031 int32_t val;
1032 val = args[2];
1033 if (val == (int8_t)val) {
1034 tcg_out_modrm(s, 0x6b, args[0], args[0]);
1035 tcg_out8(s, val);
1036 } else {
1037 tcg_out_modrm(s, 0x69, args[0], args[0]);
1038 tcg_out32(s, val);
1039 }
1040 } else {
1041 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1042 }
1043 break;
1044 case INDEX_op_mul_i64:
1045 if (const_args[2]) {
1046 int32_t val;
1047 val = args[2];
1048 if (val == (int8_t)val) {
1049 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1050 tcg_out8(s, val);
1051 } else {
1052 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1053 tcg_out32(s, val);
1054 }
1055 } else {
1056 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1057 }
1058 break;
1059 case INDEX_op_div2_i32:
1060 tcg_out_modrm(s, 0xf7, 7, args[4]);
1061 break;
1062 case INDEX_op_divu2_i32:
1063 tcg_out_modrm(s, 0xf7, 6, args[4]);
1064 break;
1065 case INDEX_op_div2_i64:
1066 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1067 break;
1068 case INDEX_op_divu2_i64:
1069 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1070 break;
1071
1072 case INDEX_op_shl_i32:
1073 c = SHIFT_SHL;
1074 gen_shift32:
1075 if (const_args[2]) {
1076 if (args[2] == 1) {
1077 tcg_out_modrm(s, 0xd1, c, args[0]);
1078 } else {
1079 tcg_out_modrm(s, 0xc1, c, args[0]);
1080 tcg_out8(s, args[2]);
1081 }
1082 } else {
1083 tcg_out_modrm(s, 0xd3, c, args[0]);
1084 }
1085 break;
1086 case INDEX_op_shr_i32:
1087 c = SHIFT_SHR;
1088 goto gen_shift32;
1089 case INDEX_op_sar_i32:
1090 c = SHIFT_SAR;
1091 goto gen_shift32;
1092 case INDEX_op_rotl_i32:
1093 c = SHIFT_ROL;
1094 goto gen_shift32;
1095 case INDEX_op_rotr_i32:
1096 c = SHIFT_ROR;
1097 goto gen_shift32;
1098
1099 case INDEX_op_shl_i64:
1100 c = SHIFT_SHL;
1101 gen_shift64:
1102 if (const_args[2]) {
1103 if (args[2] == 1) {
1104 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1105 } else {
1106 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1107 tcg_out8(s, args[2]);
1108 }
1109 } else {
1110 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1111 }
1112 break;
1113 case INDEX_op_shr_i64:
1114 c = SHIFT_SHR;
1115 goto gen_shift64;
1116 case INDEX_op_sar_i64:
1117 c = SHIFT_SAR;
1118 goto gen_shift64;
1119 case INDEX_op_rotl_i64:
1120 c = SHIFT_ROL;
1121 goto gen_shift64;
1122 case INDEX_op_rotr_i64:
1123 c = SHIFT_ROR;
1124 goto gen_shift64;
1125
1126 case INDEX_op_brcond_i32:
1127 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1128 args[3], 0);
1129 break;
1130 case INDEX_op_brcond_i64:
1131 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1132 args[3], P_REXW);
1133 break;
1134
1135 case INDEX_op_bswap16_i32:
1136 case INDEX_op_bswap16_i64:
1137 tcg_out8(s, 0x66);
1138 tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1139 tcg_out8(s, 8);
1140 break;
1141 case INDEX_op_bswap32_i32:
1142 case INDEX_op_bswap32_i64:
1143 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1144 break;
1145 case INDEX_op_bswap64_i64:
1146 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1147 break;
1148
1149 case INDEX_op_neg_i32:
1150 tcg_out_modrm(s, 0xf7, 3, args[0]);
1151 break;
1152 case INDEX_op_neg_i64:
1153 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1154 break;
1155
1156 case INDEX_op_not_i32:
1157 tcg_out_modrm(s, 0xf7, 2, args[0]);
1158 break;
1159 case INDEX_op_not_i64:
1160 tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
1161 break;
1162
1163 case INDEX_op_ext8s_i32:
1164 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1165 break;
1166 case INDEX_op_ext16s_i32:
1167 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1168 break;
1169 case INDEX_op_ext8s_i64:
1170 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1171 break;
1172 case INDEX_op_ext16s_i64:
1173 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1174 break;
1175 case INDEX_op_ext32s_i64:
1176 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1177 break;
1178 case INDEX_op_ext8u_i32:
1179 case INDEX_op_ext8u_i64:
1180 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, args[0], args[1]);
1181 break;
1182 case INDEX_op_ext16u_i32:
1183 case INDEX_op_ext16u_i64:
1184 tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
1185 break;
1186 case INDEX_op_ext32u_i64:
1187 tcg_out_modrm(s, 0x8b, args[0], args[1]);
1188 break;
1189
1190 case INDEX_op_qemu_ld8u:
1191 tcg_out_qemu_ld(s, args, 0);
1192 break;
1193 case INDEX_op_qemu_ld8s:
1194 tcg_out_qemu_ld(s, args, 0 | 4);
1195 break;
1196 case INDEX_op_qemu_ld16u:
1197 tcg_out_qemu_ld(s, args, 1);
1198 break;
1199 case INDEX_op_qemu_ld16s:
1200 tcg_out_qemu_ld(s, args, 1 | 4);
1201 break;
1202 case INDEX_op_qemu_ld32u:
1203 tcg_out_qemu_ld(s, args, 2);
1204 break;
1205 case INDEX_op_qemu_ld32s:
1206 tcg_out_qemu_ld(s, args, 2 | 4);
1207 break;
1208 case INDEX_op_qemu_ld64:
1209 tcg_out_qemu_ld(s, args, 3);
1210 break;
1211
1212 case INDEX_op_qemu_st8:
1213 tcg_out_qemu_st(s, args, 0);
1214 break;
1215 case INDEX_op_qemu_st16:
1216 tcg_out_qemu_st(s, args, 1);
1217 break;
1218 case INDEX_op_qemu_st32:
1219 tcg_out_qemu_st(s, args, 2);
1220 break;
1221 case INDEX_op_qemu_st64:
1222 tcg_out_qemu_st(s, args, 3);
1223 break;
1224
1225 default:
1226 tcg_abort();
1227 }
1228 }
1229
1230 static int tcg_target_callee_save_regs[] = {
1231 TCG_REG_RBP,
1232 TCG_REG_RBX,
1233 TCG_REG_R12,
1234 TCG_REG_R13,
1235 /* TCG_REG_R14, */ /* currently used for the global env, so no
1236 need to save */
1237 TCG_REG_R15,
1238 };
1239
1240 static inline void tcg_out_push(TCGContext *s, int reg)
1241 {
1242 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1243 }
1244
1245 static inline void tcg_out_pop(TCGContext *s, int reg)
1246 {
1247 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1248 }
1249
1250 /* Generate global QEMU prologue and epilogue code */
1251 void tcg_target_qemu_prologue(TCGContext *s)
1252 {
1253 int i, frame_size, push_size, stack_addend;
1254
1255 /* TB prologue */
1256 /* save all callee saved registers */
1257 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1258 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1259
1260 }
1261 /* reserve some stack space */
1262 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1263 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1264 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1265 ~(TCG_TARGET_STACK_ALIGN - 1);
1266 stack_addend = frame_size - push_size;
1267 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1268
1269 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1270
1271 /* TB epilogue */
1272 tb_ret_addr = s->code_ptr;
1273 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1274 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1275 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1276 }
1277 tcg_out8(s, 0xc3); /* ret */
1278 }
1279
1280 static const TCGTargetOpDef x86_64_op_defs[] = {
1281 { INDEX_op_exit_tb, { } },
1282 { INDEX_op_goto_tb, { } },
1283 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1284 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1285 { INDEX_op_br, { } },
1286
1287 { INDEX_op_mov_i32, { "r", "r" } },
1288 { INDEX_op_movi_i32, { "r" } },
1289 { INDEX_op_ld8u_i32, { "r", "r" } },
1290 { INDEX_op_ld8s_i32, { "r", "r" } },
1291 { INDEX_op_ld16u_i32, { "r", "r" } },
1292 { INDEX_op_ld16s_i32, { "r", "r" } },
1293 { INDEX_op_ld_i32, { "r", "r" } },
1294 { INDEX_op_st8_i32, { "r", "r" } },
1295 { INDEX_op_st16_i32, { "r", "r" } },
1296 { INDEX_op_st_i32, { "r", "r" } },
1297
1298 { INDEX_op_add_i32, { "r", "0", "ri" } },
1299 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1300 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1301 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1302 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1303 { INDEX_op_and_i32, { "r", "0", "ri" } },
1304 { INDEX_op_or_i32, { "r", "0", "ri" } },
1305 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1306
1307 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1308 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1309 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1310 { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1311 { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1312
1313 { INDEX_op_brcond_i32, { "r", "ri" } },
1314
1315 { INDEX_op_mov_i64, { "r", "r" } },
1316 { INDEX_op_movi_i64, { "r" } },
1317 { INDEX_op_ld8u_i64, { "r", "r" } },
1318 { INDEX_op_ld8s_i64, { "r", "r" } },
1319 { INDEX_op_ld16u_i64, { "r", "r" } },
1320 { INDEX_op_ld16s_i64, { "r", "r" } },
1321 { INDEX_op_ld32u_i64, { "r", "r" } },
1322 { INDEX_op_ld32s_i64, { "r", "r" } },
1323 { INDEX_op_ld_i64, { "r", "r" } },
1324 { INDEX_op_st8_i64, { "r", "r" } },
1325 { INDEX_op_st16_i64, { "r", "r" } },
1326 { INDEX_op_st32_i64, { "r", "r" } },
1327 { INDEX_op_st_i64, { "r", "r" } },
1328
1329 { INDEX_op_add_i64, { "r", "0", "re" } },
1330 { INDEX_op_mul_i64, { "r", "0", "re" } },
1331 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1332 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1333 { INDEX_op_sub_i64, { "r", "0", "re" } },
1334 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1335 { INDEX_op_or_i64, { "r", "0", "re" } },
1336 { INDEX_op_xor_i64, { "r", "0", "re" } },
1337
1338 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1339 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1340 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1341 { INDEX_op_rotl_i64, { "r", "0", "ci" } },
1342 { INDEX_op_rotr_i64, { "r", "0", "ci" } },
1343
1344 { INDEX_op_brcond_i64, { "r", "re" } },
1345
1346 { INDEX_op_bswap16_i32, { "r", "0" } },
1347 { INDEX_op_bswap16_i64, { "r", "0" } },
1348 { INDEX_op_bswap32_i32, { "r", "0" } },
1349 { INDEX_op_bswap32_i64, { "r", "0" } },
1350 { INDEX_op_bswap64_i64, { "r", "0" } },
1351
1352 { INDEX_op_neg_i32, { "r", "0" } },
1353 { INDEX_op_neg_i64, { "r", "0" } },
1354
1355 { INDEX_op_not_i32, { "r", "0" } },
1356 { INDEX_op_not_i64, { "r", "0" } },
1357
1358 { INDEX_op_ext8s_i32, { "r", "r"} },
1359 { INDEX_op_ext16s_i32, { "r", "r"} },
1360 { INDEX_op_ext8s_i64, { "r", "r"} },
1361 { INDEX_op_ext16s_i64, { "r", "r"} },
1362 { INDEX_op_ext32s_i64, { "r", "r"} },
1363 { INDEX_op_ext8u_i32, { "r", "r"} },
1364 { INDEX_op_ext16u_i32, { "r", "r"} },
1365 { INDEX_op_ext8u_i64, { "r", "r"} },
1366 { INDEX_op_ext16u_i64, { "r", "r"} },
1367 { INDEX_op_ext32u_i64, { "r", "r"} },
1368
1369 { INDEX_op_qemu_ld8u, { "r", "L" } },
1370 { INDEX_op_qemu_ld8s, { "r", "L" } },
1371 { INDEX_op_qemu_ld16u, { "r", "L" } },
1372 { INDEX_op_qemu_ld16s, { "r", "L" } },
1373 { INDEX_op_qemu_ld32u, { "r", "L" } },
1374 { INDEX_op_qemu_ld32s, { "r", "L" } },
1375 { INDEX_op_qemu_ld64, { "r", "L" } },
1376
1377 { INDEX_op_qemu_st8, { "L", "L" } },
1378 { INDEX_op_qemu_st16, { "L", "L" } },
1379 { INDEX_op_qemu_st32, { "L", "L" } },
1380 { INDEX_op_qemu_st64, { "L", "L" } },
1381
1382 { -1 },
1383 };
1384
1385 void tcg_target_init(TCGContext *s)
1386 {
1387 /* fail safe */
1388 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1389 tcg_abort();
1390
1391 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1392 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1393 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1394 (1 << TCG_REG_RDI) |
1395 (1 << TCG_REG_RSI) |
1396 (1 << TCG_REG_RDX) |
1397 (1 << TCG_REG_RCX) |
1398 (1 << TCG_REG_R8) |
1399 (1 << TCG_REG_R9) |
1400 (1 << TCG_REG_RAX) |
1401 (1 << TCG_REG_R10) |
1402 (1 << TCG_REG_R11));
1403
1404 tcg_regset_clear(s->reserved_regs);
1405 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1406
1407 tcg_add_target_add_op_defs(x86_64_op_defs);
1408 }
Anthony Liguori's QEMU queue