hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "msix.h"
  30
  31 //#define DEBUG_PCI
  32 #ifdef DEBUG_PCI
  33 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  34 #else
  35 # define PCI_DPRINTF(format, ...)       do { } while (0)
  36 #endif
  37
  38 struct PCIBus {
  39     BusState qbus;
  40     int bus_num;
  41     int devfn_min;
  42     pci_set_irq_fn set_irq;
  43     pci_map_irq_fn map_irq;
  44     pci_hotplug_fn hotplug;
  45     uint32_t config_reg; /* XXX: suppress */
  46     void *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     PCIBus *next;
  50     /* The bus IRQ state is the logical OR of the connected devices.
  51        Keep a count of the number of devices with raised IRQs.  */
  52     int nirq;
  53     int *irq_count;
  54 };
  55
  56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  57
  58 static struct BusInfo pci_bus_info = {
  59     .name       = "PCI",
  60     .size       = sizeof(PCIBus),
  61     .print_dev  = pcibus_dev_print,
  62     .props      = (Property[]) {
  63         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  64         DEFINE_PROP_END_OF_LIST()
  65     }
  66 };
  67
  68 static void pci_update_mappings(PCIDevice *d);
  69 static void pci_set_irq(void *opaque, int irq_num, int level);
  70
  71 target_phys_addr_t pci_mem_base;
  72 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  73 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  74 static PCIBus *first_bus;
  75
  76 static const VMStateDescription vmstate_pcibus = {
  77     .name = "PCIBUS",
  78     .version_id = 1,
  79     .minimum_version_id = 1,
  80     .minimum_version_id_old = 1,
  81     .fields      = (VMStateField []) {
  82         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  83         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  84         VMSTATE_END_OF_LIST()
  85     }
  86 };
  87
  88 static inline int pci_bar(int reg)
  89 {
  90     return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4;
  91 }
  92
  93 static void pci_device_reset(PCIDevice *dev)
  94 {
  95     memset(dev->irq_state, 0, sizeof dev->irq_state);
  96 }
  97
  98 static void pci_bus_reset(void *opaque)
  99 {
 100     PCIBus *bus = opaque;
 101     int i;
 102
 103     for (i = 0; i < bus->nirq; i++) {
 104         bus->irq_count[i] = 0;
 105     }
 106     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 107         if (bus->devices[i]) {
 108             pci_device_reset(bus->devices[i]);
 109         }
 110     }
 111 }
 112
 113 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 114                          const char *name, int devfn_min)
 115 {
 116     static int nbus = 0;
 117
 118     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 119     bus->devfn_min = devfn_min;
 120     bus->next = first_bus;
 121     first_bus = bus;
 122     vmstate_register(nbus++, &vmstate_pcibus, bus);
 123     qemu_register_reset(pci_bus_reset, bus);
 124 }
 125
 126 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 127 {
 128     PCIBus *bus;
 129
 130     bus = qemu_mallocz(sizeof(*bus));
 131     bus->qbus.qdev_allocated = 1;
 132     pci_bus_new_inplace(bus, parent, name, devfn_min);
 133     return bus;
 134 }
 135
 136 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 137                   void *irq_opaque, int nirq)
 138 {
 139     bus->set_irq = set_irq;
 140     bus->map_irq = map_irq;
 141     bus->irq_opaque = irq_opaque;
 142     bus->nirq = nirq;
 143     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 144 }
 145
 146 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 147 {
 148     bus->qbus.allow_hotplug = 1;
 149     bus->hotplug = hotplug;
 150 }
 151
 152 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 153                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 154                          void *irq_opaque, int devfn_min, int nirq)
 155 {
 156     PCIBus *bus;
 157
 158     bus = pci_bus_new(parent, name, devfn_min);
 159     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 160     return bus;
 161 }
 162
 163 static void pci_register_secondary_bus(PCIBus *bus,
 164                                        PCIDevice *dev,
 165                                        pci_map_irq_fn map_irq,
 166                                        const char *name)
 167 {
 168     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 169     bus->map_irq = map_irq;
 170     bus->parent_dev = dev;
 171     bus->next = dev->bus->next;
 172     dev->bus->next = bus;
 173 }
 174
 175 int pci_bus_num(PCIBus *s)
 176 {
 177     return s->bus_num;
 178 }
 179
 180 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 181 {
 182     PCIDevice *s = container_of(pv, PCIDevice, config);
 183     uint8_t config[size];
 184     int i;
 185
 186     qemu_get_buffer(f, config, size);
 187     for (i = 0; i < size; ++i)
 188         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 189             return -EINVAL;
 190     memcpy(s->config, config, size);
 191
 192     pci_update_mappings(s);
 193
 194     return 0;
 195 }
 196
 197 /* just put buffer */
 198 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 199 {
 200     const uint8_t *v = pv;
 201     qemu_put_buffer(f, v, size);
 202 }
 203
 204 static VMStateInfo vmstate_info_pci_config = {
 205     .name = "pci config",
 206     .get  = get_pci_config_device,
 207     .put  = put_pci_config_device,
 208 };
 209
 210 const VMStateDescription vmstate_pci_device = {
 211     .name = "PCIDevice",
 212     .version_id = 2,
 213     .minimum_version_id = 1,
 214     .minimum_version_id_old = 1,
 215     .fields      = (VMStateField []) {
 216         VMSTATE_INT32_LE(version_id, PCIDevice),
 217         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 218                        typeof_field(PCIDevice,config)),
 219         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 220         VMSTATE_END_OF_LIST()
 221     }
 222 };
 223
 224 void pci_device_save(PCIDevice *s, QEMUFile *f)
 225 {
 226     vmstate_save_state(f, &vmstate_pci_device, s);
 227 }
 228
 229 int pci_device_load(PCIDevice *s, QEMUFile *f)
 230 {
 231     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 232 }
 233
 234 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 235 {
 236     uint16_t *id;
 237
 238     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 239     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 240     id[1] = cpu_to_le16(pci_default_sub_device_id);
 241     return 0;
 242 }
 243
 244 /*
 245  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 246  */
 247 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 248 {
 249     const char *p;
 250     char *e;
 251     unsigned long val;
 252     unsigned long dom = 0, bus = 0;
 253     unsigned slot = 0;
 254
 255     p = addr;
 256     val = strtoul(p, &e, 16);
 257     if (e == p)
 258         return -1;
 259     if (*e == ':') {
 260         bus = val;
 261         p = e + 1;
 262         val = strtoul(p, &e, 16);
 263         if (e == p)
 264             return -1;
 265         if (*e == ':') {
 266             dom = bus;
 267             bus = val;
 268             p = e + 1;
 269             val = strtoul(p, &e, 16);
 270             if (e == p)
 271                 return -1;
 272         }
 273     }
 274
 275     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 276         return -1;
 277
 278     slot = val;
 279
 280     if (*e)
 281         return -1;
 282
 283     /* Note: QEMU doesn't implement domains other than 0 */
 284     if (dom != 0 || pci_find_bus(bus) == NULL)
 285         return -1;
 286
 287     *domp = dom;
 288     *busp = bus;
 289     *slotp = slot;
 290     return 0;
 291 }
 292
 293 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 294                      unsigned *slotp)
 295 {
 296     /* strip legacy tag */
 297     if (!strncmp(addr, "pci_addr=", 9)) {
 298         addr += 9;
 299     }
 300     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 301         monitor_printf(mon, "Invalid pci address\n");
 302         return -1;
 303     }
 304     return 0;
 305 }
 306
 307 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 308 {
 309     int dom, bus;
 310     unsigned slot;
 311
 312     if (!devaddr) {
 313         *devfnp = -1;
 314         return pci_find_bus(0);
 315     }
 316
 317     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 318         return NULL;
 319     }
 320
 321     *devfnp = slot << 3;
 322     return pci_find_bus(bus);
 323 }
 324
 325 static void pci_init_cmask(PCIDevice *dev)
 326 {
 327     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 328     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 329     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 330     dev->cmask[PCI_REVISION_ID] = 0xff;
 331     dev->cmask[PCI_CLASS_PROG] = 0xff;
 332     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 333     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 334     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 335 }
 336
 337 static void pci_init_wmask(PCIDevice *dev)
 338 {
 339     int i;
 340     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 341     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 342     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 343                               | PCI_COMMAND_MASTER;
 344     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 345         dev->wmask[i] = 0xff;
 346 }
 347
 348 /* -1 for devfn means auto assign */
 349 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 350                                          const char *name, int devfn,
 351                                          PCIConfigReadFunc *config_read,
 352                                          PCIConfigWriteFunc *config_write)
 353 {
 354     if (devfn < 0) {
 355         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 356             if (!bus->devices[devfn])
 357                 goto found;
 358         }
 359         return NULL;
 360     found: ;
 361     } else if (bus->devices[devfn]) {
 362         return NULL;
 363     }
 364     pci_dev->bus = bus;
 365     pci_dev->devfn = devfn;
 366     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 367     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 368     pci_set_default_subsystem_id(pci_dev);
 369     pci_init_cmask(pci_dev);
 370     pci_init_wmask(pci_dev);
 371
 372     if (!config_read)
 373         config_read = pci_default_read_config;
 374     if (!config_write)
 375         config_write = pci_default_write_config;
 376     pci_dev->config_read = config_read;
 377     pci_dev->config_write = config_write;
 378     bus->devices[devfn] = pci_dev;
 379     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 380     pci_dev->version_id = 2; /* Current pci device vmstate version */
 381     return pci_dev;
 382 }
 383
 384 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 385                                int instance_size, int devfn,
 386                                PCIConfigReadFunc *config_read,
 387                                PCIConfigWriteFunc *config_write)
 388 {
 389     PCIDevice *pci_dev;
 390
 391     pci_dev = qemu_mallocz(instance_size);
 392     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 393                                      config_read, config_write);
 394     return pci_dev;
 395 }
 396 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 397 {
 398     return addr + pci_mem_base;
 399 }
 400
 401 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 402 {
 403     PCIIORegion *r;
 404     int i;
 405
 406     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 407         r = &pci_dev->io_regions[i];
 408         if (!r->size || r->addr == -1)
 409             continue;
 410         if (r->type == PCI_ADDRESS_SPACE_IO) {
 411             isa_unassign_ioport(r->addr, r->size);
 412         } else {
 413             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 414                                                      r->size,
 415                                                      IO_MEM_UNASSIGNED);
 416         }
 417     }
 418 }
 419
 420 static int pci_unregister_device(DeviceState *dev)
 421 {
 422     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 423     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 424     int ret = 0;
 425
 426     if (info->exit)
 427         ret = info->exit(pci_dev);
 428     if (ret)
 429         return ret;
 430
 431     msix_uninit(pci_dev);
 432     pci_unregister_io_regions(pci_dev);
 433
 434     qemu_free_irqs(pci_dev->irq);
 435     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 436     return 0;
 437 }
 438
 439 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 440                             uint32_t size, int type,
 441                             PCIMapIORegionFunc *map_func)
 442 {
 443     PCIIORegion *r;
 444     uint32_t addr;
 445     uint32_t wmask;
 446
 447     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 448         return;
 449
 450     if (size & (size-1)) {
 451         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 452                     "type=0x%x, size=0x%x\n", type, size);
 453         exit(1);
 454     }
 455
 456     r = &pci_dev->io_regions[region_num];
 457     r->addr = -1;
 458     r->size = size;
 459     r->type = type;
 460     r->map_func = map_func;
 461
 462     wmask = ~(size - 1);
 463     addr = pci_bar(region_num);
 464     if (region_num == PCI_ROM_SLOT) {
 465         /* ROM enable bit is writeable */
 466         wmask |= PCI_ROM_ADDRESS_ENABLE;
 467     }
 468     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 469     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 470     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 471 }
 472
 473 static void pci_update_mappings(PCIDevice *d)
 474 {
 475     PCIIORegion *r;
 476     int cmd, i;
 477     uint32_t last_addr, new_addr;
 478
 479     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 480     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 481         r = &d->io_regions[i];
 482         if (r->size != 0) {
 483             if (r->type & PCI_ADDRESS_SPACE_IO) {
 484                 if (cmd & PCI_COMMAND_IO) {
 485                     new_addr = pci_get_long(d->config + pci_bar(i));
 486                     new_addr = new_addr & ~(r->size - 1);
 487                     last_addr = new_addr + r->size - 1;
 488                     /* NOTE: we have only 64K ioports on PC */
 489                     if (last_addr <= new_addr || new_addr == 0 ||
 490                         last_addr >= 0x10000) {
 491                         new_addr = -1;
 492                     }
 493                 } else {
 494                     new_addr = -1;
 495                 }
 496             } else {
 497                 if (cmd & PCI_COMMAND_MEMORY) {
 498                     new_addr = pci_get_long(d->config + pci_bar(i));
 499                     /* the ROM slot has a specific enable bit */
 500                     if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 501                         goto no_mem_map;
 502                     new_addr = new_addr & ~(r->size - 1);
 503                     last_addr = new_addr + r->size - 1;
 504                     /* NOTE: we do not support wrapping */
 505                     /* XXX: as we cannot support really dynamic
 506                        mappings, we handle specific values as invalid
 507                        mappings. */
 508                     if (last_addr <= new_addr || new_addr == 0 ||
 509                         last_addr == -1) {
 510                         new_addr = -1;
 511                     }
 512                 } else {
 513                 no_mem_map:
 514                     new_addr = -1;
 515                 }
 516             }
 517             /* now do the real mapping */
 518             if (new_addr != r->addr) {
 519                 if (r->addr != -1) {
 520                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 521                         int class;
 522                         /* NOTE: specific hack for IDE in PC case:
 523                            only one byte must be mapped. */
 524                         class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 525                         if (class == 0x0101 && r->size == 4) {
 526                             isa_unassign_ioport(r->addr + 2, 1);
 527                         } else {
 528                             isa_unassign_ioport(r->addr, r->size);
 529                         }
 530                     } else {
 531                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 532                                                      r->size,
 533                                                      IO_MEM_UNASSIGNED);
 534                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 535                     }
 536                 }
 537                 r->addr = new_addr;
 538                 if (r->addr != -1) {
 539                     r->map_func(d, i, r->addr, r->size, r->type);
 540                 }
 541             }
 542         }
 543     }
 544 }
 545
 546 uint32_t pci_default_read_config(PCIDevice *d,
 547                                  uint32_t address, int len)
 548 {
 549     uint32_t val;
 550
 551     switch(len) {
 552     default:
 553     case 4:
 554         if (address <= 0xfc) {
 555             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 556             break;
 557         }
 558         /* fall through */
 559     case 2:
 560         if (address <= 0xfe) {
 561             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 562             break;
 563         }
 564         /* fall through */
 565     case 1:
 566         val = d->config[address];
 567         break;
 568     }
 569     return val;
 570 }
 571
 572 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 573 {
 574     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 575     int i;
 576
 577     /* not efficient, but simple */
 578     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 579     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 580         uint8_t wmask = d->wmask[addr];
 581         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 582     }
 583     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 584         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 585             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 586         pci_update_mappings(d);
 587 }
 588
 589 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 590 {
 591     PCIBus *s = opaque;
 592     PCIDevice *pci_dev;
 593     int config_addr, bus_num;
 594
 595 #if 0
 596     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 597                 addr, val, len);
 598 #endif
 599     bus_num = (addr >> 16) & 0xff;
 600     while (s && s->bus_num != bus_num)
 601         s = s->next;
 602     if (!s)
 603         return;
 604     pci_dev = s->devices[(addr >> 8) & 0xff];
 605     if (!pci_dev)
 606         return;
 607     config_addr = addr & 0xff;
 608     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 609                 pci_dev->name, config_addr, val, len);
 610     pci_dev->config_write(pci_dev, config_addr, val, len);
 611 }
 612
 613 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 614 {
 615     PCIBus *s = opaque;
 616     PCIDevice *pci_dev;
 617     int config_addr, bus_num;
 618     uint32_t val;
 619
 620     bus_num = (addr >> 16) & 0xff;
 621     while (s && s->bus_num != bus_num)
 622         s= s->next;
 623     if (!s)
 624         goto fail;
 625     pci_dev = s->devices[(addr >> 8) & 0xff];
 626     if (!pci_dev) {
 627     fail:
 628         switch(len) {
 629         case 1:
 630             val = 0xff;
 631             break;
 632         case 2:
 633             val = 0xffff;
 634             break;
 635         default:
 636         case 4:
 637             val = 0xffffffff;
 638             break;
 639         }
 640         goto the_end;
 641     }
 642     config_addr = addr & 0xff;
 643     val = pci_dev->config_read(pci_dev, config_addr, len);
 644     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 645                 pci_dev->name, config_addr, val, len);
 646  the_end:
 647 #if 0
 648     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 649                 addr, val, len);
 650 #endif
 651     return val;
 652 }
 653
 654 /***********************************************************/
 655 /* generic PCI irq support */
 656
 657 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 658 static void pci_set_irq(void *opaque, int irq_num, int level)
 659 {
 660     PCIDevice *pci_dev = opaque;
 661     PCIBus *bus;
 662     int change;
 663
 664     change = level - pci_dev->irq_state[irq_num];
 665     if (!change)
 666         return;
 667
 668     pci_dev->irq_state[irq_num] = level;
 669     for (;;) {
 670         bus = pci_dev->bus;
 671         irq_num = bus->map_irq(pci_dev, irq_num);
 672         if (bus->set_irq)
 673             break;
 674         pci_dev = bus->parent_dev;
 675     }
 676     bus->irq_count[irq_num] += change;
 677     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 678 }
 679
 680 /***********************************************************/
 681 /* monitor info on PCI */
 682
 683 typedef struct {
 684     uint16_t class;
 685     const char *desc;
 686 } pci_class_desc;
 687
 688 static const pci_class_desc pci_class_descriptions[] =
 689 {
 690     { 0x0100, "SCSI controller"},
 691     { 0x0101, "IDE controller"},
 692     { 0x0102, "Floppy controller"},
 693     { 0x0103, "IPI controller"},
 694     { 0x0104, "RAID controller"},
 695     { 0x0106, "SATA controller"},
 696     { 0x0107, "SAS controller"},
 697     { 0x0180, "Storage controller"},
 698     { 0x0200, "Ethernet controller"},
 699     { 0x0201, "Token Ring controller"},
 700     { 0x0202, "FDDI controller"},
 701     { 0x0203, "ATM controller"},
 702     { 0x0280, "Network controller"},
 703     { 0x0300, "VGA controller"},
 704     { 0x0301, "XGA controller"},
 705     { 0x0302, "3D controller"},
 706     { 0x0380, "Display controller"},
 707     { 0x0400, "Video controller"},
 708     { 0x0401, "Audio controller"},
 709     { 0x0402, "Phone"},
 710     { 0x0480, "Multimedia controller"},
 711     { 0x0500, "RAM controller"},
 712     { 0x0501, "Flash controller"},
 713     { 0x0580, "Memory controller"},
 714     { 0x0600, "Host bridge"},
 715     { 0x0601, "ISA bridge"},
 716     { 0x0602, "EISA bridge"},
 717     { 0x0603, "MC bridge"},
 718     { 0x0604, "PCI bridge"},
 719     { 0x0605, "PCMCIA bridge"},
 720     { 0x0606, "NUBUS bridge"},
 721     { 0x0607, "CARDBUS bridge"},
 722     { 0x0608, "RACEWAY bridge"},
 723     { 0x0680, "Bridge"},
 724     { 0x0c03, "USB controller"},
 725     { 0, NULL}
 726 };
 727
 728 static void pci_info_device(PCIDevice *d)
 729 {
 730     Monitor *mon = cur_mon;
 731     int i, class;
 732     PCIIORegion *r;
 733     const pci_class_desc *desc;
 734
 735     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 736                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 737     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 738     monitor_printf(mon, "    ");
 739     desc = pci_class_descriptions;
 740     while (desc->desc && class != desc->class)
 741         desc++;
 742     if (desc->desc) {
 743         monitor_printf(mon, "%s", desc->desc);
 744     } else {
 745         monitor_printf(mon, "Class %04x", class);
 746     }
 747     monitor_printf(mon, ": PCI device %04x:%04x\n",
 748            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 749            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 750
 751     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 752         monitor_printf(mon, "      IRQ %d.\n",
 753                        d->config[PCI_INTERRUPT_LINE]);
 754     }
 755     if (class == 0x0604) {
 756         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 757     }
 758     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 759         r = &d->io_regions[i];
 760         if (r->size != 0) {
 761             monitor_printf(mon, "      BAR%d: ", i);
 762             if (r->type & PCI_ADDRESS_SPACE_IO) {
 763                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 764                                r->addr, r->addr + r->size - 1);
 765             } else {
 766                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 767                                r->addr, r->addr + r->size - 1);
 768             }
 769         }
 770     }
 771     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 772     if (class == 0x0604 && d->config[0x19] != 0) {
 773         pci_for_each_device(d->config[0x19], pci_info_device);
 774     }
 775 }
 776
 777 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 778 {
 779     PCIBus *bus = first_bus;
 780     PCIDevice *d;
 781     int devfn;
 782
 783     while (bus && bus->bus_num != bus_num)
 784         bus = bus->next;
 785     if (bus) {
 786         for(devfn = 0; devfn < 256; devfn++) {
 787             d = bus->devices[devfn];
 788             if (d)
 789                 fn(d);
 790         }
 791     }
 792 }
 793
 794 void pci_info(Monitor *mon)
 795 {
 796     pci_for_each_device(0, pci_info_device);
 797 }
 798
 799 PCIDevice *pci_create(const char *name, const char *devaddr)
 800 {
 801     PCIBus *bus;
 802     int devfn;
 803     DeviceState *dev;
 804
 805     bus = pci_get_bus_devfn(&devfn, devaddr);
 806     if (!bus) {
 807         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 808                 devaddr, name);
 809         exit(1);
 810     }
 811
 812     dev = qdev_create(&bus->qbus, name);
 813     qdev_prop_set_uint32(dev, "addr", devfn);
 814     return (PCIDevice *)dev;
 815 }
 816
 817 static const char * const pci_nic_models[] = {
 818     "ne2k_pci",
 819     "i82551",
 820     "i82557b",
 821     "i82559er",
 822     "rtl8139",
 823     "e1000",
 824     "pcnet",
 825     "virtio",
 826     NULL
 827 };
 828
 829 static const char * const pci_nic_names[] = {
 830     "ne2k_pci",
 831     "i82551",
 832     "i82557b",
 833     "i82559er",
 834     "rtl8139",
 835     "e1000",
 836     "pcnet",
 837     "virtio-net-pci",
 838     NULL
 839 };
 840
 841 int pci_nic_supported(const char *model)
 842 {
 843     int i;
 844
 845     for (i = 0; pci_nic_names[i]; i++)
 846         if (strcmp(model, pci_nic_names[i]) == 0)
 847             return 1;
 848
 849     return 0;
 850 }
 851
 852 /* Initialize a PCI NIC.  */
 853 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 854                         const char *default_devaddr)
 855 {
 856     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 857     PCIDevice *pci_dev;
 858     DeviceState *dev;
 859     int i;
 860
 861     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 862
 863     for (i = 0; pci_nic_models[i]; i++) {
 864         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 865             pci_dev = pci_create(pci_nic_names[i], devaddr);
 866             dev = &pci_dev->qdev;
 867             if (nd->id)
 868                 dev->id = qemu_strdup(nd->id);
 869             dev->nd = nd;
 870             qdev_init(dev);
 871             nd->private = dev;
 872             return pci_dev;
 873         }
 874     }
 875
 876     return NULL;
 877 }
 878
 879 typedef struct {
 880     PCIDevice dev;
 881     PCIBus bus;
 882     uint32_t vid;
 883     uint32_t did;
 884 } PCIBridge;
 885
 886 static void pci_bridge_write_config(PCIDevice *d,
 887                              uint32_t address, uint32_t val, int len)
 888 {
 889     PCIBridge *s = (PCIBridge *)d;
 890
 891     pci_default_write_config(d, address, val, len);
 892     s->bus.bus_num = d->config[PCI_SECONDARY_BUS];
 893 }
 894
 895 PCIBus *pci_find_bus(int bus_num)
 896 {
 897     PCIBus *bus = first_bus;
 898
 899     while (bus && bus->bus_num != bus_num)
 900         bus = bus->next;
 901
 902     return bus;
 903 }
 904
 905 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 906 {
 907     PCIBus *bus = pci_find_bus(bus_num);
 908
 909     if (!bus)
 910         return NULL;
 911
 912     return bus->devices[PCI_DEVFN(slot, function)];
 913 }
 914
 915 static int pci_bridge_initfn(PCIDevice *dev)
 916 {
 917     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
 918
 919     pci_config_set_vendor_id(s->dev.config, s->vid);
 920     pci_config_set_device_id(s->dev.config, s->did);
 921
 922     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 923     s->dev.config[0x05] = 0x00;
 924     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 925     s->dev.config[0x07] = 0x00; // status = fast devsel
 926     s->dev.config[0x08] = 0x00; // revision
 927     s->dev.config[0x09] = 0x00; // programming i/f
 928     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 929     s->dev.config[0x0D] = 0x10; // latency_timer
 930     s->dev.config[PCI_HEADER_TYPE] =
 931         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 932     s->dev.config[0x1E] = 0xa0; // secondary status
 933     return 0;
 934 }
 935
 936 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 937                         pci_map_irq_fn map_irq, const char *name)
 938 {
 939     PCIDevice *dev;
 940     PCIBridge *s;
 941
 942     dev = pci_create_noinit(bus, devfn, "pci-bridge");
 943     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
 944     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
 945     qdev_init(&dev->qdev);
 946
 947     s = DO_UPCAST(PCIBridge, dev, dev);
 948     pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name);
 949     return &s->bus;
 950 }
 951
 952 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 953 {
 954     PCIDevice *pci_dev = (PCIDevice *)qdev;
 955     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 956     PCIBus *bus;
 957     int devfn, rc;
 958
 959     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 960     devfn = pci_dev->devfn;
 961     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 962                                      info->config_read, info->config_write);
 963     assert(pci_dev);
 964     rc = info->init(pci_dev);
 965     if (rc != 0)
 966         return rc;
 967     if (qdev->hotplugged)
 968         bus->hotplug(pci_dev, 1);
 969     return 0;
 970 }
 971
 972 static int pci_unplug_device(DeviceState *qdev)
 973 {
 974     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
 975
 976     dev->bus->hotplug(dev, 0);
 977     return 0;
 978 }
 979
 980 void pci_qdev_register(PCIDeviceInfo *info)
 981 {
 982     info->qdev.init = pci_qdev_init;
 983     info->qdev.unplug = pci_unplug_device;
 984     info->qdev.exit = pci_unregister_device;
 985     info->qdev.bus_info = &pci_bus_info;
 986     qdev_register(&info->qdev);
 987 }
 988
 989 void pci_qdev_register_many(PCIDeviceInfo *info)
 990 {
 991     while (info->qdev.name) {
 992         pci_qdev_register(info);
 993         info++;
 994     }
 995 }
 996
 997 PCIDevice *pci_create_noinit(PCIBus *bus, int devfn, const char *name)
 998 {
 999     DeviceState *dev;
1000
1001     dev = qdev_create(&bus->qbus, name);
1002     qdev_prop_set_uint32(dev, "addr", devfn);
1003     return DO_UPCAST(PCIDevice, qdev, dev);
1004 }
1005
1006 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1007 {
1008     PCIDevice *dev = pci_create_noinit(bus, devfn, name);
1009     qdev_init(&dev->qdev);
1010     return dev;
1011 }
1012
1013 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1014 {
1015     int offset = PCI_CONFIG_HEADER_SIZE;
1016     int i;
1017     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
1018         if (pdev->used[i])
1019             offset = i + 1;
1020         else if (i - offset + 1 == size)
1021             return offset;
1022     return 0;
1023 }
1024
1025 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1026                                         uint8_t *prev_p)
1027 {
1028     uint8_t next, prev;
1029
1030     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1031         return 0;
1032
1033     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1034          prev = next + PCI_CAP_LIST_NEXT)
1035         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1036             break;
1037
1038     if (prev_p)
1039         *prev_p = prev;
1040     return next;
1041 }
1042
1043 /* Reserve space and add capability to the linked list in pci config space */
1044 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1045 {
1046     uint8_t offset = pci_find_space(pdev, size);
1047     uint8_t *config = pdev->config + offset;
1048     if (!offset)
1049         return -ENOSPC;
1050     config[PCI_CAP_LIST_ID] = cap_id;
1051     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1052     pdev->config[PCI_CAPABILITY_LIST] = offset;
1053     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1054     memset(pdev->used + offset, 0xFF, size);
1055     /* Make capability read-only by default */
1056     memset(pdev->wmask + offset, 0, size);
1057     /* Check capability by default */
1058     memset(pdev->cmask + offset, 0xFF, size);
1059     return offset;
1060 }
1061
1062 /* Unlink capability from the pci config space. */
1063 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1064 {
1065     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1066     if (!offset)
1067         return;
1068     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1069     /* Make capability writeable again */
1070     memset(pdev->wmask + offset, 0xff, size);
1071     /* Clear cmask as device-specific registers can't be checked */
1072     memset(pdev->cmask + offset, 0, size);
1073     memset(pdev->used + offset, 0, size);
1074
1075     if (!pdev->config[PCI_CAPABILITY_LIST])
1076         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1077 }
1078
1079 /* Reserve space for capability at a known offset (to call after load). */
1080 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1081 {
1082     memset(pdev->used + offset, 0xff, size);
1083 }
1084
1085 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1086 {
1087     return pci_find_capability_list(pdev, cap_id, NULL);
1088 }
1089
1090 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1091 {
1092     PCIDevice *d = (PCIDevice *)dev;
1093     const pci_class_desc *desc;
1094     char ctxt[64];
1095     PCIIORegion *r;
1096     int i, class;
1097
1098     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1099     desc = pci_class_descriptions;
1100     while (desc->desc && class != desc->class)
1101         desc++;
1102     if (desc->desc) {
1103         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1104     } else {
1105         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1106     }
1107
1108     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1109                    "pci id %04x:%04x (sub %04x:%04x)\n",
1110                    indent, "", ctxt,
1111                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1112                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1113                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1114                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1115                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1116     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1117         r = &d->io_regions[i];
1118         if (!r->size)
1119             continue;
1120         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1121                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1122                        r->addr, r->addr + r->size - 1);
1123     }
1124 }
1125
1126 static PCIDeviceInfo bridge_info = {
1127     .qdev.name    = "pci-bridge",
1128     .qdev.size    = sizeof(PCIBridge),
1129     .init         = pci_bridge_initfn,
1130     .config_write = pci_bridge_write_config,
1131     .qdev.props   = (Property[]) {
1132         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1133         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1134         DEFINE_PROP_END_OF_LIST(),
1135     }
1136 };
1137
1138 static void pci_register_devices(void)
1139 {
1140     pci_qdev_register(&bridge_info);
1141 }
1142
1143 device_init(pci_register_devices)