sparc64: trap handling corrections
[qemu/aliguori-queue.git] / hw / axis_dev88.c
blob79a4d7106e04241e36088418a2a92bb92a39fdfe
1 /*
2 * QEMU model for the AXIS devboard 88.
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "sysbus.h"
26 #include "net.h"
27 #include "flash.h"
28 #include "boards.h"
29 #include "sysemu.h"
30 #include "etraxfs.h"
32 #define D(x)
33 #define DNAND(x)
35 struct nand_state_t
37 NANDFlashState *nand;
38 unsigned int rdy:1;
39 unsigned int ale:1;
40 unsigned int cle:1;
41 unsigned int ce:1;
44 static struct nand_state_t nand_state;
45 static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
47 struct nand_state_t *s = opaque;
48 uint32_t r;
49 int rdy;
51 r = nand_getio(s->nand);
52 nand_getpins(s->nand, &rdy);
53 s->rdy = rdy;
55 DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
56 return r;
59 static void
60 nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
62 struct nand_state_t *s = opaque;
63 int rdy;
65 DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
66 nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
67 nand_setio(s->nand, value);
68 nand_getpins(s->nand, &rdy);
69 s->rdy = rdy;
72 static CPUReadMemoryFunc *nand_read[] = {
73 &nand_readl,
74 &nand_readl,
75 &nand_readl,
78 static CPUWriteMemoryFunc *nand_write[] = {
79 &nand_writel,
80 &nand_writel,
81 &nand_writel,
85 struct tempsensor_t
87 unsigned int shiftreg;
88 unsigned int count;
89 enum {
90 ST_OUT, ST_IN, ST_Z
91 } state;
93 uint16_t regs[3];
96 static void tempsensor_clkedge(struct tempsensor_t *s,
97 unsigned int clk, unsigned int data_in)
99 D(printf("%s clk=%d state=%d sr=%x\n", __func__,
100 clk, s->state, s->shiftreg));
101 if (s->count == 0) {
102 s->count = 16;
103 s->state = ST_OUT;
105 switch (s->state) {
106 case ST_OUT:
107 /* Output reg is clocked at negedge. */
108 if (!clk) {
109 s->count--;
110 s->shiftreg <<= 1;
111 if (s->count == 0) {
112 s->shiftreg = 0;
113 s->state = ST_IN;
114 s->count = 16;
117 break;
118 case ST_Z:
119 if (clk) {
120 s->count--;
121 if (s->count == 0) {
122 s->shiftreg = 0;
123 s->state = ST_OUT;
124 s->count = 16;
127 break;
128 case ST_IN:
129 /* Indata is sampled at posedge. */
130 if (clk) {
131 s->count--;
132 s->shiftreg <<= 1;
133 s->shiftreg |= data_in & 1;
134 if (s->count == 0) {
135 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
136 s->regs[0] = s->shiftreg;
137 s->state = ST_OUT;
138 s->count = 16;
140 if ((s->regs[0] & 0xff) == 0) {
141 /* 25 degrees celcius. */
142 s->shiftreg = 0x0b9f;
143 } else if ((s->regs[0] & 0xff) == 0xff) {
144 /* Sensor ID, 0x8100 LM70. */
145 s->shiftreg = 0x8100;
146 } else
147 printf("Invalid tempsens state %x\n", s->regs[0]);
150 break;
155 #define RW_PA_DOUT 0x00
156 #define R_PA_DIN 0x01
157 #define RW_PA_OE 0x02
158 #define RW_PD_DOUT 0x10
159 #define R_PD_DIN 0x11
160 #define RW_PD_OE 0x12
162 static struct gpio_state_t
164 struct nand_state_t *nand;
165 struct tempsensor_t tempsensor;
166 uint32_t regs[0x5c / 4];
167 } gpio_state;
169 static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
171 struct gpio_state_t *s = opaque;
172 uint32_t r = 0;
174 addr >>= 2;
175 switch (addr)
177 case R_PA_DIN:
178 r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
180 /* Encode pins from the nand. */
181 r |= s->nand->rdy << 7;
182 break;
183 case R_PD_DIN:
184 r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
186 /* Encode temp sensor pins. */
187 r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
188 break;
190 default:
191 r = s->regs[addr];
192 break;
194 return r;
195 D(printf("%s %x=%x\n", __func__, addr, r));
198 static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
200 struct gpio_state_t *s = opaque;
201 D(printf("%s %x=%x\n", __func__, addr, value));
203 addr >>= 2;
204 switch (addr)
206 case RW_PA_DOUT:
207 /* Decode nand pins. */
208 s->nand->ale = !!(value & (1 << 6));
209 s->nand->cle = !!(value & (1 << 5));
210 s->nand->ce = !!(value & (1 << 4));
212 s->regs[addr] = value;
213 break;
215 case RW_PD_DOUT:
216 /* Temp sensor clk. */
217 if ((s->regs[addr] ^ value) & 2)
218 tempsensor_clkedge(&s->tempsensor, !!(value & 2),
219 !!(value & 16));
220 s->regs[addr] = value;
221 break;
223 default:
224 s->regs[addr] = value;
225 break;
229 static CPUReadMemoryFunc *gpio_read[] = {
230 NULL, NULL,
231 &gpio_readl,
234 static CPUWriteMemoryFunc *gpio_write[] = {
235 NULL, NULL,
236 &gpio_writel,
239 #define INTMEM_SIZE (128 * 1024)
241 static uint32_t bootstrap_pc;
242 static void main_cpu_reset(void *opaque)
244 CPUState *env = opaque;
245 cpu_reset(env);
247 env->pc = bootstrap_pc;
250 static
251 void axisdev88_init (ram_addr_t ram_size,
252 const char *boot_device,
253 const char *kernel_filename, const char *kernel_cmdline,
254 const char *initrd_filename, const char *cpu_model)
256 CPUState *env;
257 DeviceState *dev;
258 SysBusDevice *s;
259 qemu_irq irq[30], nmi[2], *cpu_irq;
260 void *etraxfs_dmac;
261 struct etraxfs_dma_client *eth[2] = {NULL, NULL};
262 int kernel_size;
263 int i;
264 int nand_regs;
265 int gpio_regs;
266 ram_addr_t phys_ram;
267 ram_addr_t phys_intmem;
269 /* init CPUs */
270 if (cpu_model == NULL) {
271 cpu_model = "crisv32";
273 env = cpu_init(cpu_model);
274 qemu_register_reset(main_cpu_reset, env);
276 /* allocate RAM */
277 phys_ram = qemu_ram_alloc(ram_size);
278 cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
280 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
281 internal memory. */
282 phys_intmem = qemu_ram_alloc(INTMEM_SIZE);
283 cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
284 phys_intmem | IO_MEM_RAM);
287 /* Attach a NAND flash to CS1. */
288 nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
289 nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state);
290 cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
292 gpio_state.nand = &nand_state;
293 gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state);
294 cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
297 cpu_irq = cris_pic_init_cpu(env);
298 dev = qdev_create(NULL, "etraxfs,pic");
299 /* FIXME: Is there a proper way to signal vectors to the CPU core? */
300 qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
301 qdev_init(dev);
302 s = sysbus_from_qdev(dev);
303 sysbus_mmio_map(s, 0, 0x3001c000);
304 sysbus_connect_irq(s, 0, cpu_irq[0]);
305 sysbus_connect_irq(s, 1, cpu_irq[1]);
306 for (i = 0; i < 30; i++) {
307 irq[i] = qdev_get_gpio_in(dev, i);
309 nmi[0] = qdev_get_gpio_in(dev, 30);
310 nmi[1] = qdev_get_gpio_in(dev, 31);
312 etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
313 for (i = 0; i < 10; i++) {
314 /* On ETRAX, odd numbered channels are inputs. */
315 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
318 /* Add the two ethernet blocks. */
319 eth[0] = etraxfs_eth_init(&nd_table[0], 0x30034000, 1);
320 if (nb_nics > 1)
321 eth[1] = etraxfs_eth_init(&nd_table[1], 0x30036000, 2);
323 /* The DMA Connector block is missing, hardwire things for now. */
324 etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
325 etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
326 if (eth[1]) {
327 etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
328 etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
331 /* 2 timers. */
332 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
333 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
335 for (i = 0; i < 4; i++) {
336 sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
337 irq[0x14 + i]);
340 if (kernel_filename) {
341 uint64_t entry, high;
342 int kcmdline_len;
344 /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
345 devboard SDK. */
346 kernel_size = load_elf(kernel_filename, -0x80000000LL,
347 &entry, NULL, &high);
348 bootstrap_pc = entry;
349 if (kernel_size < 0) {
350 /* Takes a kimage from the axis devboard SDK. */
351 kernel_size = load_image_targphys(kernel_filename, 0x40004000,
352 ram_size);
353 bootstrap_pc = 0x40004000;
354 env->regs[9] = 0x40004000 + kernel_size;
356 env->regs[8] = 0x56902387; /* RAM init magic. */
358 if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
359 if (kcmdline_len > 256) {
360 fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n");
361 exit(1);
363 /* Let the kernel know we are modifying the cmdline. */
364 env->regs[10] = 0x87109563;
365 env->regs[11] = 0x40000000;
366 pstrcpy_targphys(env->regs[11], 256, kernel_cmdline);
369 env->pc = bootstrap_pc;
371 printf ("pc =%x\n", env->pc);
372 printf ("ram size =%ld\n", ram_size);
375 static QEMUMachine axisdev88_machine = {
376 .name = "axis-dev88",
377 .desc = "AXIS devboard 88",
378 .init = axisdev88_init,
381 static void axisdev88_machine_init(void)
383 qemu_register_machine(&axisdev88_machine);
386 machine_init(axisdev88_machine_init);