eepro100: symbolic names for pci registers
[qemu/aliguori-queue.git] / tcg / tcg-op.h
blobfaf2e8b609ad8996a2c1053779f30793787c9c85
1 /*
2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "tcg.h"
26 int gen_new_label(void);
28 static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
30 *gen_opc_ptr++ = opc;
31 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
34 static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
36 *gen_opc_ptr++ = opc;
37 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
40 static inline void tcg_gen_op1i(int opc, TCGArg arg1)
42 *gen_opc_ptr++ = opc;
43 *gen_opparam_ptr++ = arg1;
46 static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
48 *gen_opc_ptr++ = opc;
49 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
50 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
53 static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
55 *gen_opc_ptr++ = opc;
56 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
57 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
60 static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
62 *gen_opc_ptr++ = opc;
63 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
64 *gen_opparam_ptr++ = arg2;
67 static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
69 *gen_opc_ptr++ = opc;
70 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
71 *gen_opparam_ptr++ = arg2;
74 static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
76 *gen_opc_ptr++ = opc;
77 *gen_opparam_ptr++ = arg1;
78 *gen_opparam_ptr++ = arg2;
81 static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
82 TCGv_i32 arg3)
84 *gen_opc_ptr++ = opc;
85 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
86 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
87 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
90 static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
91 TCGv_i64 arg3)
93 *gen_opc_ptr++ = opc;
94 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
95 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
96 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
99 static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
100 TCGArg arg3)
102 *gen_opc_ptr++ = opc;
103 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
104 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
105 *gen_opparam_ptr++ = arg3;
108 static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
109 TCGArg arg3)
111 *gen_opc_ptr++ = opc;
112 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
113 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
114 *gen_opparam_ptr++ = arg3;
117 static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
118 TCGArg offset)
120 *gen_opc_ptr++ = opc;
121 *gen_opparam_ptr++ = GET_TCGV_I32(val);
122 *gen_opparam_ptr++ = GET_TCGV_PTR(base);
123 *gen_opparam_ptr++ = offset;
126 static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
127 TCGArg offset)
129 *gen_opc_ptr++ = opc;
130 *gen_opparam_ptr++ = GET_TCGV_I64(val);
131 *gen_opparam_ptr++ = GET_TCGV_PTR(base);
132 *gen_opparam_ptr++ = offset;
135 static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
136 TCGArg mem_index)
138 *gen_opc_ptr++ = opc;
139 *gen_opparam_ptr++ = GET_TCGV_I64(val);
140 *gen_opparam_ptr++ = GET_TCGV_I32(addr);
141 *gen_opparam_ptr++ = mem_index;
144 static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
145 TCGArg mem_index)
147 *gen_opc_ptr++ = opc;
148 *gen_opparam_ptr++ = GET_TCGV_I64(val);
149 *gen_opparam_ptr++ = GET_TCGV_I64(addr);
150 *gen_opparam_ptr++ = mem_index;
153 static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
154 TCGv_i32 arg3, TCGv_i32 arg4)
156 *gen_opc_ptr++ = opc;
157 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
158 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
159 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
160 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
163 static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
164 TCGv_i64 arg3, TCGv_i64 arg4)
166 *gen_opc_ptr++ = opc;
167 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
168 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
169 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
170 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
173 static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
174 TCGv_i32 arg3, TCGArg arg4)
176 *gen_opc_ptr++ = opc;
177 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
178 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
179 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
180 *gen_opparam_ptr++ = arg4;
183 static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
184 TCGv_i64 arg3, TCGArg arg4)
186 *gen_opc_ptr++ = opc;
187 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
188 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
189 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
190 *gen_opparam_ptr++ = arg4;
193 static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
194 TCGArg arg3, TCGArg arg4)
196 *gen_opc_ptr++ = opc;
197 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
198 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
199 *gen_opparam_ptr++ = arg3;
200 *gen_opparam_ptr++ = arg4;
203 static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
204 TCGArg arg3, TCGArg arg4)
206 *gen_opc_ptr++ = opc;
207 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
208 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
209 *gen_opparam_ptr++ = arg3;
210 *gen_opparam_ptr++ = arg4;
213 static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
214 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
216 *gen_opc_ptr++ = opc;
217 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
218 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
219 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
220 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
221 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
224 static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
225 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
227 *gen_opc_ptr++ = opc;
228 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
229 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
230 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
231 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
232 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
235 static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
236 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
238 *gen_opc_ptr++ = opc;
239 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
240 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
241 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
242 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
243 *gen_opparam_ptr++ = arg5;
246 static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
247 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
249 *gen_opc_ptr++ = opc;
250 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
251 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
252 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
253 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
254 *gen_opparam_ptr++ = arg5;
257 static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
258 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
259 TCGv_i32 arg6)
261 *gen_opc_ptr++ = opc;
262 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
263 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
264 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
265 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
266 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
267 *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
270 static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
271 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
272 TCGv_i64 arg6)
274 *gen_opc_ptr++ = opc;
275 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
276 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
277 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
278 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
279 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
280 *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
283 static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
284 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
285 TCGArg arg6)
287 *gen_opc_ptr++ = opc;
288 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
289 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
290 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
291 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
292 *gen_opparam_ptr++ = arg5;
293 *gen_opparam_ptr++ = arg6;
296 static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
297 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
298 TCGArg arg6)
300 *gen_opc_ptr++ = opc;
301 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
302 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
303 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
304 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
305 *gen_opparam_ptr++ = arg5;
306 *gen_opparam_ptr++ = arg6;
309 static inline void gen_set_label(int n)
311 tcg_gen_op1i(INDEX_op_set_label, n);
314 static inline void tcg_gen_br(int label)
316 tcg_gen_op1i(INDEX_op_br, label);
319 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
321 if (!TCGV_EQUAL_I32(ret, arg))
322 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
325 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
327 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
330 /* helper calls */
331 static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
332 TCGArg ret, int nargs, TCGArg *args)
334 TCGv_ptr fn;
335 fn = tcg_const_ptr((tcg_target_long)func);
336 tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
337 nargs, args);
338 tcg_temp_free_ptr(fn);
341 /* FIXME: Should this be pure? */
342 static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
343 TCGv_i64 a, TCGv_i64 b)
345 TCGv_ptr fn;
346 TCGArg args[2];
347 fn = tcg_const_ptr((tcg_target_long)func);
348 args[0] = GET_TCGV_I64(a);
349 args[1] = GET_TCGV_I64(b);
350 tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
351 tcg_temp_free_ptr(fn);
354 /* 32 bit ops */
356 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
358 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
361 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
363 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
366 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
368 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
371 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
373 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
376 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
378 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
381 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
383 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
386 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
388 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
391 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
393 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
396 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
398 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
401 static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
403 /* some cases can be optimized here */
404 if (arg2 == 0) {
405 tcg_gen_mov_i32(ret, arg1);
406 } else {
407 TCGv_i32 t0 = tcg_const_i32(arg2);
408 tcg_gen_add_i32(ret, arg1, t0);
409 tcg_temp_free_i32(t0);
413 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
415 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
418 static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
420 TCGv_i32 t0 = tcg_const_i32(arg1);
421 tcg_gen_sub_i32(ret, t0, arg2);
422 tcg_temp_free_i32(t0);
425 static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
427 /* some cases can be optimized here */
428 if (arg2 == 0) {
429 tcg_gen_mov_i32(ret, arg1);
430 } else {
431 TCGv_i32 t0 = tcg_const_i32(arg2);
432 tcg_gen_sub_i32(ret, arg1, t0);
433 tcg_temp_free_i32(t0);
437 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
439 if (TCGV_EQUAL_I32(arg1, arg2)) {
440 tcg_gen_mov_i32(ret, arg1);
441 } else {
442 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
446 static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
448 /* some cases can be optimized here */
449 if (arg2 == 0) {
450 tcg_gen_movi_i32(ret, 0);
451 } else if (arg2 == 0xffffffff) {
452 tcg_gen_mov_i32(ret, arg1);
453 } else {
454 TCGv_i32 t0 = tcg_const_i32(arg2);
455 tcg_gen_and_i32(ret, arg1, t0);
456 tcg_temp_free_i32(t0);
460 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
462 if (TCGV_EQUAL_I32(arg1, arg2)) {
463 tcg_gen_mov_i32(ret, arg1);
464 } else {
465 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
469 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
471 /* some cases can be optimized here */
472 if (arg2 == 0xffffffff) {
473 tcg_gen_movi_i32(ret, 0xffffffff);
474 } else if (arg2 == 0) {
475 tcg_gen_mov_i32(ret, arg1);
476 } else {
477 TCGv_i32 t0 = tcg_const_i32(arg2);
478 tcg_gen_or_i32(ret, arg1, t0);
479 tcg_temp_free_i32(t0);
483 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
485 if (TCGV_EQUAL_I32(arg1, arg2)) {
486 tcg_gen_movi_i32(ret, 0);
487 } else {
488 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
492 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
494 /* some cases can be optimized here */
495 if (arg2 == 0) {
496 tcg_gen_mov_i32(ret, arg1);
497 } else {
498 TCGv_i32 t0 = tcg_const_i32(arg2);
499 tcg_gen_xor_i32(ret, arg1, t0);
500 tcg_temp_free_i32(t0);
504 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
506 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
509 static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
511 if (arg2 == 0) {
512 tcg_gen_mov_i32(ret, arg1);
513 } else {
514 TCGv_i32 t0 = tcg_const_i32(arg2);
515 tcg_gen_shl_i32(ret, arg1, t0);
516 tcg_temp_free_i32(t0);
520 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
522 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
525 static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
527 if (arg2 == 0) {
528 tcg_gen_mov_i32(ret, arg1);
529 } else {
530 TCGv_i32 t0 = tcg_const_i32(arg2);
531 tcg_gen_shr_i32(ret, arg1, t0);
532 tcg_temp_free_i32(t0);
536 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
538 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
541 static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
543 if (arg2 == 0) {
544 tcg_gen_mov_i32(ret, arg1);
545 } else {
546 TCGv_i32 t0 = tcg_const_i32(arg2);
547 tcg_gen_sar_i32(ret, arg1, t0);
548 tcg_temp_free_i32(t0);
552 static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
553 int label_index)
555 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
558 static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
559 int label_index)
561 TCGv_i32 t0 = tcg_const_i32(arg2);
562 tcg_gen_brcond_i32(cond, arg1, t0, label_index);
563 tcg_temp_free_i32(t0);
566 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
568 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
571 static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
573 TCGv_i32 t0 = tcg_const_i32(arg2);
574 tcg_gen_mul_i32(ret, arg1, t0);
575 tcg_temp_free_i32(t0);
578 #ifdef TCG_TARGET_HAS_div_i32
579 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
581 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
584 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
586 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
589 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
591 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
594 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
596 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
598 #else
599 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
601 TCGv_i32 t0;
602 t0 = tcg_temp_new_i32();
603 tcg_gen_sari_i32(t0, arg1, 31);
604 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
605 tcg_temp_free_i32(t0);
608 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
610 TCGv_i32 t0;
611 t0 = tcg_temp_new_i32();
612 tcg_gen_sari_i32(t0, arg1, 31);
613 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
614 tcg_temp_free_i32(t0);
617 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
619 TCGv_i32 t0;
620 t0 = tcg_temp_new_i32();
621 tcg_gen_movi_i32(t0, 0);
622 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
623 tcg_temp_free_i32(t0);
626 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
628 TCGv_i32 t0;
629 t0 = tcg_temp_new_i32();
630 tcg_gen_movi_i32(t0, 0);
631 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
632 tcg_temp_free_i32(t0);
634 #endif
636 #if TCG_TARGET_REG_BITS == 32
638 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
640 if (!TCGV_EQUAL_I64(ret, arg)) {
641 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
642 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
646 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
648 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
649 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
652 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
653 tcg_target_long offset)
655 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
656 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
659 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
660 tcg_target_long offset)
662 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
663 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
666 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
667 tcg_target_long offset)
669 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
670 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
673 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
674 tcg_target_long offset)
676 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
677 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
680 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
681 tcg_target_long offset)
683 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
684 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
687 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
688 tcg_target_long offset)
690 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
691 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
694 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
695 tcg_target_long offset)
697 /* since arg2 and ret have different types, they cannot be the
698 same temporary */
699 #ifdef TCG_TARGET_WORDS_BIGENDIAN
700 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
701 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
702 #else
703 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
704 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
705 #endif
708 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
709 tcg_target_long offset)
711 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
714 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
715 tcg_target_long offset)
717 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
720 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
721 tcg_target_long offset)
723 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
726 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
727 tcg_target_long offset)
729 #ifdef TCG_TARGET_WORDS_BIGENDIAN
730 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
731 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
732 #else
733 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
734 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
735 #endif
738 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
740 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
741 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
742 TCGV_HIGH(arg2));
745 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
747 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
748 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
749 TCGV_HIGH(arg2));
752 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
754 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
755 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
758 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
760 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
761 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
764 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
766 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
767 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
770 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
772 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
773 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
776 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
778 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
779 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
782 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
784 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
785 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
788 /* XXX: use generic code when basic block handling is OK or CPU
789 specific code (x86) */
790 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
792 tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
795 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
797 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
800 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
802 tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
805 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
807 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
810 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
812 tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
815 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
817 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
820 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
821 int label_index)
823 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
824 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
825 TCGV_HIGH(arg2), cond, label_index);
828 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
830 TCGv_i64 t0;
831 TCGv_i32 t1;
833 t0 = tcg_temp_new_i64();
834 t1 = tcg_temp_new_i32();
836 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
837 TCGV_LOW(arg1), TCGV_LOW(arg2));
839 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
840 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
841 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
842 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
844 tcg_gen_mov_i64(ret, t0);
845 tcg_temp_free_i64(t0);
846 tcg_temp_free_i32(t1);
849 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
851 tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
854 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
856 tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
859 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
861 tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
864 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
866 tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
869 #else
871 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
873 if (!TCGV_EQUAL_I64(ret, arg))
874 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
877 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
879 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
882 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
883 tcg_target_long offset)
885 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
888 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
889 tcg_target_long offset)
891 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
894 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
895 tcg_target_long offset)
897 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
900 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
901 tcg_target_long offset)
903 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
906 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
907 tcg_target_long offset)
909 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
912 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
913 tcg_target_long offset)
915 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
918 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
920 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
923 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
924 tcg_target_long offset)
926 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
929 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
930 tcg_target_long offset)
932 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
935 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
936 tcg_target_long offset)
938 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
941 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
943 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
946 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
948 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
951 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
953 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
956 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
958 if (TCGV_EQUAL_I64(arg1, arg2)) {
959 tcg_gen_mov_i64(ret, arg1);
960 } else {
961 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
965 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
967 TCGv_i64 t0 = tcg_const_i64(arg2);
968 tcg_gen_and_i64(ret, arg1, t0);
969 tcg_temp_free_i64(t0);
972 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
974 if (TCGV_EQUAL_I64(arg1, arg2)) {
975 tcg_gen_mov_i64(ret, arg1);
976 } else {
977 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
981 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
983 TCGv_i64 t0 = tcg_const_i64(arg2);
984 tcg_gen_or_i64(ret, arg1, t0);
985 tcg_temp_free_i64(t0);
988 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
990 if (TCGV_EQUAL_I64(arg1, arg2)) {
991 tcg_gen_movi_i64(ret, 0);
992 } else {
993 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
997 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
999 TCGv_i64 t0 = tcg_const_i64(arg2);
1000 tcg_gen_xor_i64(ret, arg1, t0);
1001 tcg_temp_free_i64(t0);
1004 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1006 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1009 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1011 if (arg2 == 0) {
1012 tcg_gen_mov_i64(ret, arg1);
1013 } else {
1014 TCGv_i64 t0 = tcg_const_i64(arg2);
1015 tcg_gen_shl_i64(ret, arg1, t0);
1016 tcg_temp_free_i64(t0);
1020 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1022 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1025 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1027 if (arg2 == 0) {
1028 tcg_gen_mov_i64(ret, arg1);
1029 } else {
1030 TCGv_i64 t0 = tcg_const_i64(arg2);
1031 tcg_gen_shr_i64(ret, arg1, t0);
1032 tcg_temp_free_i64(t0);
1036 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1038 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1041 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1043 if (arg2 == 0) {
1044 tcg_gen_mov_i64(ret, arg1);
1045 } else {
1046 TCGv_i64 t0 = tcg_const_i64(arg2);
1047 tcg_gen_sar_i64(ret, arg1, t0);
1048 tcg_temp_free_i64(t0);
1052 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1053 int label_index)
1055 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1058 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1060 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1063 #ifdef TCG_TARGET_HAS_div_i64
1064 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1066 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1069 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1071 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1074 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1076 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1079 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1081 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1083 #else
1084 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1086 TCGv_i64 t0;
1087 t0 = tcg_temp_new_i64();
1088 tcg_gen_sari_i64(t0, arg1, 63);
1089 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1090 tcg_temp_free_i64(t0);
1093 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1095 TCGv_i64 t0;
1096 t0 = tcg_temp_new_i64();
1097 tcg_gen_sari_i64(t0, arg1, 63);
1098 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1099 tcg_temp_free_i64(t0);
1102 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1104 TCGv_i64 t0;
1105 t0 = tcg_temp_new_i64();
1106 tcg_gen_movi_i64(t0, 0);
1107 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1108 tcg_temp_free_i64(t0);
1111 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1113 TCGv_i64 t0;
1114 t0 = tcg_temp_new_i64();
1115 tcg_gen_movi_i64(t0, 0);
1116 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1117 tcg_temp_free_i64(t0);
1119 #endif
1121 #endif
1123 static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1125 /* some cases can be optimized here */
1126 if (arg2 == 0) {
1127 tcg_gen_mov_i64(ret, arg1);
1128 } else {
1129 TCGv_i64 t0 = tcg_const_i64(arg2);
1130 tcg_gen_add_i64(ret, arg1, t0);
1131 tcg_temp_free_i64(t0);
1135 static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1137 TCGv_i64 t0 = tcg_const_i64(arg1);
1138 tcg_gen_sub_i64(ret, t0, arg2);
1139 tcg_temp_free_i64(t0);
1142 static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1144 /* some cases can be optimized here */
1145 if (arg2 == 0) {
1146 tcg_gen_mov_i64(ret, arg1);
1147 } else {
1148 TCGv_i64 t0 = tcg_const_i64(arg2);
1149 tcg_gen_sub_i64(ret, arg1, t0);
1150 tcg_temp_free_i64(t0);
1153 static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1154 int label_index)
1156 TCGv_i64 t0 = tcg_const_i64(arg2);
1157 tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1158 tcg_temp_free_i64(t0);
1161 static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1163 TCGv_i64 t0 = tcg_const_i64(arg2);
1164 tcg_gen_mul_i64(ret, arg1, t0);
1165 tcg_temp_free_i64(t0);
1169 /***************************************/
1170 /* optional operations */
1172 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1174 #ifdef TCG_TARGET_HAS_ext8s_i32
1175 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1176 #else
1177 tcg_gen_shli_i32(ret, arg, 24);
1178 tcg_gen_sari_i32(ret, ret, 24);
1179 #endif
1182 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1184 #ifdef TCG_TARGET_HAS_ext16s_i32
1185 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1186 #else
1187 tcg_gen_shli_i32(ret, arg, 16);
1188 tcg_gen_sari_i32(ret, ret, 16);
1189 #endif
1192 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1194 #ifdef TCG_TARGET_HAS_ext8u_i32
1195 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1196 #else
1197 tcg_gen_andi_i32(ret, arg, 0xffu);
1198 #endif
1201 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1203 #ifdef TCG_TARGET_HAS_ext16u_i32
1204 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1205 #else
1206 tcg_gen_andi_i32(ret, arg, 0xffffu);
1207 #endif
1210 /* Note: we assume the two high bytes are set to zero */
1211 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1213 #ifdef TCG_TARGET_HAS_bswap16_i32
1214 tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1215 #else
1216 TCGv_i32 t0 = tcg_temp_new_i32();
1218 tcg_gen_ext8u_i32(t0, arg);
1219 tcg_gen_shli_i32(t0, t0, 8);
1220 tcg_gen_shri_i32(ret, arg, 8);
1221 tcg_gen_or_i32(ret, ret, t0);
1222 tcg_temp_free_i32(t0);
1223 #endif
1226 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1228 #ifdef TCG_TARGET_HAS_bswap32_i32
1229 tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1230 #else
1231 TCGv_i32 t0, t1;
1232 t0 = tcg_temp_new_i32();
1233 t1 = tcg_temp_new_i32();
1235 tcg_gen_shli_i32(t0, arg, 24);
1237 tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1238 tcg_gen_shli_i32(t1, t1, 8);
1239 tcg_gen_or_i32(t0, t0, t1);
1241 tcg_gen_shri_i32(t1, arg, 8);
1242 tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1243 tcg_gen_or_i32(t0, t0, t1);
1245 tcg_gen_shri_i32(t1, arg, 24);
1246 tcg_gen_or_i32(ret, t0, t1);
1247 tcg_temp_free_i32(t0);
1248 tcg_temp_free_i32(t1);
1249 #endif
1252 #if TCG_TARGET_REG_BITS == 32
1253 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1255 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1256 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1259 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1261 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1262 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1265 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1267 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1268 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1271 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1273 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1274 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1277 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1279 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1280 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1283 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1285 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1286 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1289 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1291 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1294 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1296 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1297 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1300 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1302 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1303 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1306 /* Note: we assume the six high bytes are set to zero */
1307 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1309 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1310 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1313 /* Note: we assume the four high bytes are set to zero */
1314 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1316 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1317 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1320 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1322 TCGv_i32 t0, t1;
1323 t0 = tcg_temp_new_i32();
1324 t1 = tcg_temp_new_i32();
1326 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1327 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1328 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1329 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1330 tcg_temp_free_i32(t0);
1331 tcg_temp_free_i32(t1);
1333 #else
1335 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1337 #ifdef TCG_TARGET_HAS_ext8s_i64
1338 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1339 #else
1340 tcg_gen_shli_i64(ret, arg, 56);
1341 tcg_gen_sari_i64(ret, ret, 56);
1342 #endif
1345 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1347 #ifdef TCG_TARGET_HAS_ext16s_i64
1348 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1349 #else
1350 tcg_gen_shli_i64(ret, arg, 48);
1351 tcg_gen_sari_i64(ret, ret, 48);
1352 #endif
1355 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1357 #ifdef TCG_TARGET_HAS_ext32s_i64
1358 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1359 #else
1360 tcg_gen_shli_i64(ret, arg, 32);
1361 tcg_gen_sari_i64(ret, ret, 32);
1362 #endif
1365 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1367 #ifdef TCG_TARGET_HAS_ext8u_i64
1368 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1369 #else
1370 tcg_gen_andi_i64(ret, arg, 0xffu);
1371 #endif
1374 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1376 #ifdef TCG_TARGET_HAS_ext16u_i64
1377 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1378 #else
1379 tcg_gen_andi_i64(ret, arg, 0xffffu);
1380 #endif
1383 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1385 #ifdef TCG_TARGET_HAS_ext32u_i64
1386 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1387 #else
1388 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1389 #endif
1392 /* Note: we assume the target supports move between 32 and 64 bit
1393 registers. This will probably break MIPS64 targets. */
1394 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1396 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1399 /* Note: we assume the target supports move between 32 and 64 bit
1400 registers */
1401 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1403 tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1406 /* Note: we assume the target supports move between 32 and 64 bit
1407 registers */
1408 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1410 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1413 /* Note: we assume the six high bytes are set to zero */
1414 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1416 #ifdef TCG_TARGET_HAS_bswap16_i64
1417 tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1418 #else
1419 TCGv_i64 t0 = tcg_temp_new_i64();
1421 tcg_gen_ext8u_i64(t0, arg);
1422 tcg_gen_shli_i64(t0, t0, 8);
1423 tcg_gen_shri_i64(ret, arg, 8);
1424 tcg_gen_or_i64(ret, ret, t0);
1425 tcg_temp_free_i64(t0);
1426 #endif
1429 /* Note: we assume the four high bytes are set to zero */
1430 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1432 #ifdef TCG_TARGET_HAS_bswap32_i64
1433 tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1434 #else
1435 TCGv_i64 t0, t1;
1436 t0 = tcg_temp_new_i64();
1437 t1 = tcg_temp_new_i64();
1439 tcg_gen_shli_i64(t0, arg, 24);
1440 tcg_gen_ext32u_i64(t0, t0);
1442 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1443 tcg_gen_shli_i64(t1, t1, 8);
1444 tcg_gen_or_i64(t0, t0, t1);
1446 tcg_gen_shri_i64(t1, arg, 8);
1447 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1448 tcg_gen_or_i64(t0, t0, t1);
1450 tcg_gen_shri_i64(t1, arg, 24);
1451 tcg_gen_or_i64(ret, t0, t1);
1452 tcg_temp_free_i64(t0);
1453 tcg_temp_free_i64(t1);
1454 #endif
1457 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1459 #ifdef TCG_TARGET_HAS_bswap64_i64
1460 tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1461 #else
1462 TCGv_i64 t0 = tcg_temp_new_i64();
1463 TCGv_i64 t1 = tcg_temp_new_i64();
1465 tcg_gen_shli_i64(t0, arg, 56);
1467 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1468 tcg_gen_shli_i64(t1, t1, 40);
1469 tcg_gen_or_i64(t0, t0, t1);
1471 tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1472 tcg_gen_shli_i64(t1, t1, 24);
1473 tcg_gen_or_i64(t0, t0, t1);
1475 tcg_gen_andi_i64(t1, arg, 0xff000000);
1476 tcg_gen_shli_i64(t1, t1, 8);
1477 tcg_gen_or_i64(t0, t0, t1);
1479 tcg_gen_shri_i64(t1, arg, 8);
1480 tcg_gen_andi_i64(t1, t1, 0xff000000);
1481 tcg_gen_or_i64(t0, t0, t1);
1483 tcg_gen_shri_i64(t1, arg, 24);
1484 tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1485 tcg_gen_or_i64(t0, t0, t1);
1487 tcg_gen_shri_i64(t1, arg, 40);
1488 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1489 tcg_gen_or_i64(t0, t0, t1);
1491 tcg_gen_shri_i64(t1, arg, 56);
1492 tcg_gen_or_i64(ret, t0, t1);
1493 tcg_temp_free_i64(t0);
1494 tcg_temp_free_i64(t1);
1495 #endif
1498 #endif
1500 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1502 #ifdef TCG_TARGET_HAS_neg_i32
1503 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1504 #else
1505 TCGv_i32 t0 = tcg_const_i32(0);
1506 tcg_gen_sub_i32(ret, t0, arg);
1507 tcg_temp_free_i32(t0);
1508 #endif
1511 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1513 #ifdef TCG_TARGET_HAS_neg_i64
1514 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1515 #else
1516 TCGv_i64 t0 = tcg_const_i64(0);
1517 tcg_gen_sub_i64(ret, t0, arg);
1518 tcg_temp_free_i64(t0);
1519 #endif
1522 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1524 #ifdef TCG_TARGET_HAS_not_i32
1525 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1526 #else
1527 tcg_gen_xori_i32(ret, arg, -1);
1528 #endif
1531 static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1533 #ifdef TCG_TARGET_HAS_not_i64
1534 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1535 #else
1536 tcg_gen_xori_i64(ret, arg, -1);
1537 #endif
1540 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1542 tcg_gen_op1_i32(INDEX_op_discard, arg);
1545 #if TCG_TARGET_REG_BITS == 32
1546 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1548 tcg_gen_discard_i32(TCGV_LOW(arg));
1549 tcg_gen_discard_i32(TCGV_HIGH(arg));
1551 #else
1552 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1554 tcg_gen_op1_i64(INDEX_op_discard, arg);
1556 #endif
1558 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1560 #if TCG_TARGET_REG_BITS == 32
1561 tcg_gen_mov_i32(TCGV_LOW(dest), low);
1562 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1563 #else
1564 TCGv_i64 tmp = tcg_temp_new_i64();
1565 /* This extension is only needed for type correctness.
1566 We may be able to do better given target specific information. */
1567 tcg_gen_extu_i32_i64(tmp, high);
1568 tcg_gen_shli_i64(tmp, tmp, 32);
1569 tcg_gen_extu_i32_i64(dest, low);
1570 tcg_gen_or_i64(dest, dest, tmp);
1571 tcg_temp_free_i64(tmp);
1572 #endif
1575 static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1577 #if TCG_TARGET_REG_BITS == 32
1578 tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1579 #else
1580 TCGv_i64 tmp = tcg_temp_new_i64();
1581 tcg_gen_ext32u_i64(dest, low);
1582 tcg_gen_shli_i64(tmp, high, 32);
1583 tcg_gen_or_i64(dest, dest, tmp);
1584 tcg_temp_free_i64(tmp);
1585 #endif
1588 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1590 TCGv_i32 t0;
1591 t0 = tcg_temp_new_i32();
1592 tcg_gen_not_i32(t0, arg2);
1593 tcg_gen_and_i32(ret, arg1, t0);
1594 tcg_temp_free_i32(t0);
1597 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1599 TCGv_i64 t0;
1600 t0 = tcg_temp_new_i64();
1601 tcg_gen_not_i64(t0, arg2);
1602 tcg_gen_and_i64(ret, arg1, t0);
1603 tcg_temp_free_i64(t0);
1606 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1608 tcg_gen_xor_i32(ret, arg1, arg2);
1609 tcg_gen_not_i32(ret, ret);
1612 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1614 tcg_gen_xor_i64(ret, arg1, arg2);
1615 tcg_gen_not_i64(ret, ret);
1618 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1620 tcg_gen_and_i32(ret, arg1, arg2);
1621 tcg_gen_not_i32(ret, ret);
1624 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1626 tcg_gen_and_i64(ret, arg1, arg2);
1627 tcg_gen_not_i64(ret, ret);
1630 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1632 tcg_gen_or_i32(ret, arg1, arg2);
1633 tcg_gen_not_i32(ret, ret);
1636 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1638 tcg_gen_or_i64(ret, arg1, arg2);
1639 tcg_gen_not_i64(ret, ret);
1642 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1644 TCGv_i32 t0;
1645 t0 = tcg_temp_new_i32();
1646 tcg_gen_not_i32(t0, arg2);
1647 tcg_gen_or_i32(ret, arg1, t0);
1648 tcg_temp_free_i32(t0);
1651 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1653 TCGv_i64 t0;
1654 t0 = tcg_temp_new_i64();
1655 tcg_gen_not_i64(t0, arg2);
1656 tcg_gen_or_i64(ret, arg1, t0);
1657 tcg_temp_free_i64(t0);
1660 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1662 #ifdef TCG_TARGET_HAS_rot_i32
1663 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1664 #else
1665 TCGv_i32 t0, t1;
1667 t0 = tcg_temp_new_i32();
1668 t1 = tcg_temp_new_i32();
1669 tcg_gen_shl_i32(t0, arg1, arg2);
1670 tcg_gen_subfi_i32(t1, 32, arg2);
1671 tcg_gen_shr_i32(t1, arg1, t1);
1672 tcg_gen_or_i32(ret, t0, t1);
1673 tcg_temp_free_i32(t0);
1674 tcg_temp_free_i32(t1);
1675 #endif
1678 static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1680 #ifdef TCG_TARGET_HAS_rot_i64
1681 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1682 #else
1683 TCGv_i64 t0, t1;
1685 t0 = tcg_temp_new_i64();
1686 t1 = tcg_temp_new_i64();
1687 tcg_gen_shl_i64(t0, arg1, arg2);
1688 tcg_gen_subfi_i64(t1, 64, arg2);
1689 tcg_gen_shr_i64(t1, arg1, t1);
1690 tcg_gen_or_i64(ret, t0, t1);
1691 tcg_temp_free_i64(t0);
1692 tcg_temp_free_i64(t1);
1693 #endif
1696 static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1698 /* some cases can be optimized here */
1699 if (arg2 == 0) {
1700 tcg_gen_mov_i32(ret, arg1);
1701 } else {
1702 #ifdef TCG_TARGET_HAS_rot_i32
1703 TCGv_i32 t0 = tcg_const_i32(arg2);
1704 tcg_gen_rotl_i32(ret, arg1, t0);
1705 tcg_temp_free_i32(t0);
1706 #else
1707 TCGv_i32 t0, t1;
1708 t0 = tcg_temp_new_i32();
1709 t1 = tcg_temp_new_i32();
1710 tcg_gen_shli_i32(t0, arg1, arg2);
1711 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1712 tcg_gen_or_i32(ret, t0, t1);
1713 tcg_temp_free_i32(t0);
1714 tcg_temp_free_i32(t1);
1715 #endif
1719 static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1721 /* some cases can be optimized here */
1722 if (arg2 == 0) {
1723 tcg_gen_mov_i64(ret, arg1);
1724 } else {
1725 #ifdef TCG_TARGET_HAS_rot_i64
1726 TCGv_i64 t0 = tcg_const_i64(arg2);
1727 tcg_gen_rotl_i64(ret, arg1, t0);
1728 tcg_temp_free_i64(t0);
1729 #else
1730 TCGv_i64 t0, t1;
1731 t0 = tcg_temp_new_i64();
1732 t1 = tcg_temp_new_i64();
1733 tcg_gen_shli_i64(t0, arg1, arg2);
1734 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1735 tcg_gen_or_i64(ret, t0, t1);
1736 tcg_temp_free_i64(t0);
1737 tcg_temp_free_i64(t1);
1738 #endif
1742 static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1744 #ifdef TCG_TARGET_HAS_rot_i32
1745 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1746 #else
1747 TCGv_i32 t0, t1;
1749 t0 = tcg_temp_new_i32();
1750 t1 = tcg_temp_new_i32();
1751 tcg_gen_shr_i32(t0, arg1, arg2);
1752 tcg_gen_subfi_i32(t1, 32, arg2);
1753 tcg_gen_shl_i32(t1, arg1, t1);
1754 tcg_gen_or_i32(ret, t0, t1);
1755 tcg_temp_free_i32(t0);
1756 tcg_temp_free_i32(t1);
1757 #endif
1760 static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1762 #ifdef TCG_TARGET_HAS_rot_i64
1763 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
1764 #else
1765 TCGv_i64 t0, t1;
1767 t0 = tcg_temp_new_i64();
1768 t1 = tcg_temp_new_i64();
1769 tcg_gen_shr_i64(t0, arg1, arg2);
1770 tcg_gen_subfi_i64(t1, 64, arg2);
1771 tcg_gen_shl_i64(t1, arg1, t1);
1772 tcg_gen_or_i64(ret, t0, t1);
1773 tcg_temp_free_i64(t0);
1774 tcg_temp_free_i64(t1);
1775 #endif
1778 static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1780 /* some cases can be optimized here */
1781 if (arg2 == 0) {
1782 tcg_gen_mov_i32(ret, arg1);
1783 } else {
1784 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1788 static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1790 /* some cases can be optimized here */
1791 if (arg2 == 0) {
1792 tcg_gen_mov_i64(ret, arg1);
1793 } else {
1794 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1798 /***************************************/
1799 /* QEMU specific operations. Their type depend on the QEMU CPU
1800 type. */
1801 #ifndef TARGET_LONG_BITS
1802 #error must include QEMU headers
1803 #endif
1805 #if TARGET_LONG_BITS == 32
1806 #define TCGv TCGv_i32
1807 #define tcg_temp_new() tcg_temp_new_i32()
1808 #define tcg_global_reg_new tcg_global_reg_new_i32
1809 #define tcg_global_mem_new tcg_global_mem_new_i32
1810 #define tcg_temp_local_new() tcg_temp_local_new_i32()
1811 #define tcg_temp_free tcg_temp_free_i32
1812 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1813 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1814 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1815 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1816 #else
1817 #define TCGv TCGv_i64
1818 #define tcg_temp_new() tcg_temp_new_i64()
1819 #define tcg_global_reg_new tcg_global_reg_new_i64
1820 #define tcg_global_mem_new tcg_global_mem_new_i64
1821 #define tcg_temp_local_new() tcg_temp_local_new_i64()
1822 #define tcg_temp_free tcg_temp_free_i64
1823 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1824 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1825 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1826 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1827 #endif
1829 /* debug info: write the PC of the corresponding QEMU CPU instruction */
1830 static inline void tcg_gen_debug_insn_start(uint64_t pc)
1832 /* XXX: must really use a 32 bit size for TCGArg in all cases */
1833 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1834 tcg_gen_op2ii(INDEX_op_debug_insn_start,
1835 (uint32_t)(pc), (uint32_t)(pc >> 32));
1836 #else
1837 tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1838 #endif
1841 static inline void tcg_gen_exit_tb(tcg_target_long val)
1843 tcg_gen_op1i(INDEX_op_exit_tb, val);
1846 static inline void tcg_gen_goto_tb(int idx)
1848 tcg_gen_op1i(INDEX_op_goto_tb, idx);
1851 #if TCG_TARGET_REG_BITS == 32
1852 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1854 #if TARGET_LONG_BITS == 32
1855 tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1856 #else
1857 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1858 TCGV_HIGH(addr), mem_index);
1859 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1860 #endif
1863 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1865 #if TARGET_LONG_BITS == 32
1866 tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1867 #else
1868 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1869 TCGV_HIGH(addr), mem_index);
1870 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1871 #endif
1874 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1876 #if TARGET_LONG_BITS == 32
1877 tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1878 #else
1879 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1880 TCGV_HIGH(addr), mem_index);
1881 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1882 #endif
1885 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1887 #if TARGET_LONG_BITS == 32
1888 tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1889 #else
1890 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1891 TCGV_HIGH(addr), mem_index);
1892 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1893 #endif
1896 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1898 #if TARGET_LONG_BITS == 32
1899 tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1900 #else
1901 tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1902 TCGV_HIGH(addr), mem_index);
1903 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1904 #endif
1907 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1909 #if TARGET_LONG_BITS == 32
1910 tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1911 #else
1912 tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1913 TCGV_HIGH(addr), mem_index);
1914 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1915 #endif
1918 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1920 #if TARGET_LONG_BITS == 32
1921 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1922 #else
1923 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1924 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1925 #endif
1928 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1930 #if TARGET_LONG_BITS == 32
1931 tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1932 #else
1933 tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1934 TCGV_HIGH(addr), mem_index);
1935 #endif
1938 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1940 #if TARGET_LONG_BITS == 32
1941 tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
1942 #else
1943 tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
1944 TCGV_HIGH(addr), mem_index);
1945 #endif
1948 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1950 #if TARGET_LONG_BITS == 32
1951 tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
1952 #else
1953 tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
1954 TCGV_HIGH(addr), mem_index);
1955 #endif
1958 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1960 #if TARGET_LONG_BITS == 32
1961 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
1962 mem_index);
1963 #else
1964 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
1965 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1966 #endif
1969 #define tcg_gen_ld_ptr tcg_gen_ld_i32
1970 #define tcg_gen_discard_ptr tcg_gen_discard_i32
1972 #else /* TCG_TARGET_REG_BITS == 32 */
1974 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1976 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1979 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1981 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1984 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1986 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1989 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1991 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1994 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1996 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1999 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2001 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2004 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2006 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2009 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2011 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2014 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2016 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2019 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2021 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2024 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2026 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2029 #define tcg_gen_ld_ptr tcg_gen_ld_i64
2030 #define tcg_gen_discard_ptr tcg_gen_discard_i64
2032 #endif /* TCG_TARGET_REG_BITS != 32 */
2034 #if TARGET_LONG_BITS == 64
2035 #define TCG_TYPE_TL TCG_TYPE_I64
2036 #define tcg_gen_movi_tl tcg_gen_movi_i64
2037 #define tcg_gen_mov_tl tcg_gen_mov_i64
2038 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2039 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2040 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2041 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2042 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2043 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2044 #define tcg_gen_ld_tl tcg_gen_ld_i64
2045 #define tcg_gen_st8_tl tcg_gen_st8_i64
2046 #define tcg_gen_st16_tl tcg_gen_st16_i64
2047 #define tcg_gen_st32_tl tcg_gen_st32_i64
2048 #define tcg_gen_st_tl tcg_gen_st_i64
2049 #define tcg_gen_add_tl tcg_gen_add_i64
2050 #define tcg_gen_addi_tl tcg_gen_addi_i64
2051 #define tcg_gen_sub_tl tcg_gen_sub_i64
2052 #define tcg_gen_neg_tl tcg_gen_neg_i64
2053 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2054 #define tcg_gen_subi_tl tcg_gen_subi_i64
2055 #define tcg_gen_and_tl tcg_gen_and_i64
2056 #define tcg_gen_andi_tl tcg_gen_andi_i64
2057 #define tcg_gen_or_tl tcg_gen_or_i64
2058 #define tcg_gen_ori_tl tcg_gen_ori_i64
2059 #define tcg_gen_xor_tl tcg_gen_xor_i64
2060 #define tcg_gen_xori_tl tcg_gen_xori_i64
2061 #define tcg_gen_not_tl tcg_gen_not_i64
2062 #define tcg_gen_shl_tl tcg_gen_shl_i64
2063 #define tcg_gen_shli_tl tcg_gen_shli_i64
2064 #define tcg_gen_shr_tl tcg_gen_shr_i64
2065 #define tcg_gen_shri_tl tcg_gen_shri_i64
2066 #define tcg_gen_sar_tl tcg_gen_sar_i64
2067 #define tcg_gen_sari_tl tcg_gen_sari_i64
2068 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2069 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2070 #define tcg_gen_mul_tl tcg_gen_mul_i64
2071 #define tcg_gen_muli_tl tcg_gen_muli_i64
2072 #define tcg_gen_div_tl tcg_gen_div_i64
2073 #define tcg_gen_rem_tl tcg_gen_rem_i64
2074 #define tcg_gen_divu_tl tcg_gen_divu_i64
2075 #define tcg_gen_remu_tl tcg_gen_remu_i64
2076 #define tcg_gen_discard_tl tcg_gen_discard_i64
2077 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2078 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2079 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2080 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2081 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2082 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2083 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2084 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2085 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2086 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2087 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2088 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2089 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2090 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2091 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2092 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2093 #define tcg_gen_andc_tl tcg_gen_andc_i64
2094 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2095 #define tcg_gen_nand_tl tcg_gen_nand_i64
2096 #define tcg_gen_nor_tl tcg_gen_nor_i64
2097 #define tcg_gen_orc_tl tcg_gen_orc_i64
2098 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2099 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2100 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2101 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2102 #define tcg_const_tl tcg_const_i64
2103 #define tcg_const_local_tl tcg_const_local_i64
2104 #else
2105 #define TCG_TYPE_TL TCG_TYPE_I32
2106 #define tcg_gen_movi_tl tcg_gen_movi_i32
2107 #define tcg_gen_mov_tl tcg_gen_mov_i32
2108 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2109 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2110 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2111 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2112 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2113 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2114 #define tcg_gen_ld_tl tcg_gen_ld_i32
2115 #define tcg_gen_st8_tl tcg_gen_st8_i32
2116 #define tcg_gen_st16_tl tcg_gen_st16_i32
2117 #define tcg_gen_st32_tl tcg_gen_st_i32
2118 #define tcg_gen_st_tl tcg_gen_st_i32
2119 #define tcg_gen_add_tl tcg_gen_add_i32
2120 #define tcg_gen_addi_tl tcg_gen_addi_i32
2121 #define tcg_gen_sub_tl tcg_gen_sub_i32
2122 #define tcg_gen_neg_tl tcg_gen_neg_i32
2123 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2124 #define tcg_gen_subi_tl tcg_gen_subi_i32
2125 #define tcg_gen_and_tl tcg_gen_and_i32
2126 #define tcg_gen_andi_tl tcg_gen_andi_i32
2127 #define tcg_gen_or_tl tcg_gen_or_i32
2128 #define tcg_gen_ori_tl tcg_gen_ori_i32
2129 #define tcg_gen_xor_tl tcg_gen_xor_i32
2130 #define tcg_gen_xori_tl tcg_gen_xori_i32
2131 #define tcg_gen_not_tl tcg_gen_not_i32
2132 #define tcg_gen_shl_tl tcg_gen_shl_i32
2133 #define tcg_gen_shli_tl tcg_gen_shli_i32
2134 #define tcg_gen_shr_tl tcg_gen_shr_i32
2135 #define tcg_gen_shri_tl tcg_gen_shri_i32
2136 #define tcg_gen_sar_tl tcg_gen_sar_i32
2137 #define tcg_gen_sari_tl tcg_gen_sari_i32
2138 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2139 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2140 #define tcg_gen_mul_tl tcg_gen_mul_i32
2141 #define tcg_gen_muli_tl tcg_gen_muli_i32
2142 #define tcg_gen_div_tl tcg_gen_div_i32
2143 #define tcg_gen_rem_tl tcg_gen_rem_i32
2144 #define tcg_gen_divu_tl tcg_gen_divu_i32
2145 #define tcg_gen_remu_tl tcg_gen_remu_i32
2146 #define tcg_gen_discard_tl tcg_gen_discard_i32
2147 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2148 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2149 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2150 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2151 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2152 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2153 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2154 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2155 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2156 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2157 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2158 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2159 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2160 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2161 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2162 #define tcg_gen_andc_tl tcg_gen_andc_i32
2163 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2164 #define tcg_gen_nand_tl tcg_gen_nand_i32
2165 #define tcg_gen_nor_tl tcg_gen_nor_i32
2166 #define tcg_gen_orc_tl tcg_gen_orc_i32
2167 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2168 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2169 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2170 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2171 #define tcg_const_tl tcg_const_i32
2172 #define tcg_const_local_tl tcg_const_local_i32
2173 #endif
2175 #if TCG_TARGET_REG_BITS == 32
2176 #define tcg_gen_add_ptr tcg_gen_add_i32
2177 #define tcg_gen_addi_ptr tcg_gen_addi_i32
2178 #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2179 #else /* TCG_TARGET_REG_BITS == 32 */
2180 #define tcg_gen_add_ptr tcg_gen_add_i64
2181 #define tcg_gen_addi_ptr tcg_gen_addi_i64
2182 #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2183 #endif /* TCG_TARGET_REG_BITS != 32 */