hw/sbi.c

   1 /*
   2  * QEMU Sparc SBI interrupt controller emulation
   3  *
   4  * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "sun4m.h"
  27 #include "console.h"
  28 #include "sysbus.h"
  29
  30 //#define DEBUG_IRQ
  31
  32 #ifdef DEBUG_IRQ
  33 #define DPRINTF(fmt, ...)                                       \
  34     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 #define MAX_CPUS 16
  40
  41 #define SBI_NREGS 16
  42
  43 typedef struct SBIState {
  44     SysBusDevice busdev;
  45     uint32_t regs[SBI_NREGS];
  46     uint32_t intreg_pending[MAX_CPUS];
  47     qemu_irq cpu_irqs[MAX_CPUS];
  48     uint32_t pil_out[MAX_CPUS];
  49 } SBIState;
  50
  51 #define SBI_SIZE (SBI_NREGS * 4)
  52
  53 static void sbi_set_irq(void *opaque, int irq, int level)
  54 {
  55 }
  56
  57 static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
  58 {
  59     SBIState *s = opaque;
  60     uint32_t saddr, ret;
  61
  62     saddr = addr >> 2;
  63     switch (saddr) {
  64     default:
  65         ret = s->regs[saddr];
  66         break;
  67     }
  68     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  69
  70     return ret;
  71 }
  72
  73 static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  74 {
  75     SBIState *s = opaque;
  76     uint32_t saddr;
  77
  78     saddr = addr >> 2;
  79     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  80     switch (saddr) {
  81     default:
  82         s->regs[saddr] = val;
  83         break;
  84     }
  85 }
  86
  87 static CPUReadMemoryFunc *sbi_mem_read[3] = {
  88     NULL,
  89     NULL,
  90     sbi_mem_readl,
  91 };
  92
  93 static CPUWriteMemoryFunc *sbi_mem_write[3] = {
  94     NULL,
  95     NULL,
  96     sbi_mem_writel,
  97 };
  98
  99 static void sbi_save(QEMUFile *f, void *opaque)
 100 {
 101     SBIState *s = opaque;
 102     unsigned int i;
 103
 104     for (i = 0; i < MAX_CPUS; i++) {
 105         qemu_put_be32s(f, &s->intreg_pending[i]);
 106     }
 107 }
 108
 109 static int sbi_load(QEMUFile *f, void *opaque, int version_id)
 110 {
 111     SBIState *s = opaque;
 112     unsigned int i;
 113
 114     if (version_id != 1)
 115         return -EINVAL;
 116
 117     for (i = 0; i < MAX_CPUS; i++) {
 118         qemu_get_be32s(f, &s->intreg_pending[i]);
 119     }
 120
 121     return 0;
 122 }
 123
 124 static void sbi_reset(void *opaque)
 125 {
 126     SBIState *s = opaque;
 127     unsigned int i;
 128
 129     for (i = 0; i < MAX_CPUS; i++) {
 130         s->intreg_pending[i] = 0;
 131     }
 132 }
 133
 134 DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
 135 {
 136     DeviceState *dev;
 137     SysBusDevice *s;
 138     unsigned int i;
 139
 140     dev = qdev_create(NULL, "sbi");
 141     qdev_init(dev);
 142
 143     s = sysbus_from_qdev(dev);
 144
 145     for (i = 0; i < MAX_CPUS; i++) {
 146         sysbus_connect_irq(s, i, *parent_irq[i]);
 147     }
 148
 149     sysbus_mmio_map(s, 0, addr);
 150
 151     return dev;
 152 }
 153
 154 static void sbi_init1(SysBusDevice *dev)
 155 {
 156     SBIState *s = FROM_SYSBUS(SBIState, dev);
 157     int sbi_io_memory;
 158     unsigned int i;
 159
 160     qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
 161     for (i = 0; i < MAX_CPUS; i++) {
 162         sysbus_init_irq(dev, &s->cpu_irqs[i]);
 163     }
 164
 165     sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
 166     sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory);
 167
 168     register_savevm("sbi", -1, 1, sbi_save, sbi_load, s);
 169     qemu_register_reset(sbi_reset, s);
 170     sbi_reset(s);
 171 }
 172
 173 static SysBusDeviceInfo sbi_info = {
 174     .init = sbi_init1,
 175     .qdev.name  = "sbi",
 176     .qdev.size  = sizeof(SBIState),
 177 };
 178
 179 static void sbi_register_devices(void)
 180 {
 181     sysbus_register_withprop(&sbi_info);
 182 }
 183
 184 device_init(sbi_register_devices)