target-ppc/translate_init.c

   1 /*
   2  *  PowerPC CPU initialization for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20
  21 /* A lot of PowerPC definition have been included here.
  22  * Most of them are not usable for now but have been kept
  23  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
  24  */
  25
  26 #include "dis-asm.h"
  27 #include "gdbstub.h"
  28
  29 //#define PPC_DUMP_CPU
  30 //#define PPC_DEBUG_SPR
  31 //#define PPC_DUMP_SPR_ACCESSES
  32 #if defined(CONFIG_USER_ONLY)
  33 #define TODO_USER_ONLY 1
  34 #endif
  35
  36 struct ppc_def_t {
  37     const char *name;
  38     uint32_t pvr;
  39     uint32_t svr;
  40     uint64_t insns_flags;
  41     uint64_t msr_mask;
  42     powerpc_mmu_t   mmu_model;
  43     powerpc_excp_t  excp_model;
  44     powerpc_input_t bus_model;
  45     uint32_t flags;
  46     int bfd_mach;
  47     void (*init_proc)(CPUPPCState *env);
  48     int  (*check_pow)(CPUPPCState *env);
  49 };
  50
  51 /* For user-mode emulation, we don't emulate any IRQ controller */
  52 #if defined(CONFIG_USER_ONLY)
  53 #define PPC_IRQ_INIT_FN(name)                                                 \
  54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  55 {                                                                             \
  56 }
  57 #else
  58 #define PPC_IRQ_INIT_FN(name)                                                 \
  59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  60 #endif
  61
  62 PPC_IRQ_INIT_FN(40x);
  63 PPC_IRQ_INIT_FN(6xx);
  64 PPC_IRQ_INIT_FN(970);
  65 PPC_IRQ_INIT_FN(e500);
  66
  67 /* Generic callbacks:
  68  * do nothing but store/retrieve spr value
  69  */
  70 static void spr_read_generic (void *opaque, int gprn, int sprn)
  71 {
  72     gen_load_spr(cpu_gpr[gprn], sprn);
  73 #ifdef PPC_DUMP_SPR_ACCESSES
  74     {
  75         TCGv t0 = tcg_const_i32(sprn);
  76         gen_helper_load_dump_spr(t0);
  77         tcg_temp_free_i32(t0);
  78     }
  79 #endif
  80 }
  81
  82 static void spr_write_generic (void *opaque, int sprn, int gprn)
  83 {
  84     gen_store_spr(sprn, cpu_gpr[gprn]);
  85 #ifdef PPC_DUMP_SPR_ACCESSES
  86     {
  87         TCGv t0 = tcg_const_i32(sprn);
  88         gen_helper_store_dump_spr(t0);
  89         tcg_temp_free_i32(t0);
  90     }
  91 #endif
  92 }
  93
  94 #if !defined(CONFIG_USER_ONLY)
  95 static void spr_write_clear (void *opaque, int sprn, int gprn)
  96 {
  97     TCGv t0 = tcg_temp_new();
  98     TCGv t1 = tcg_temp_new();
  99     gen_load_spr(t0, sprn);
 100     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 101     tcg_gen_and_tl(t0, t0, t1);
 102     gen_store_spr(sprn, t0);
 103     tcg_temp_free(t0);
 104     tcg_temp_free(t1);
 105 }
 106 #endif
 107
 108 /* SPR common to all PowerPC */
 109 /* XER */
 110 static void spr_read_xer (void *opaque, int gprn, int sprn)
 111 {
 112     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
 113 }
 114
 115 static void spr_write_xer (void *opaque, int sprn, int gprn)
 116 {
 117     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
 118 }
 119
 120 /* LR */
 121 static void spr_read_lr (void *opaque, int gprn, int sprn)
 122 {
 123     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 124 }
 125
 126 static void spr_write_lr (void *opaque, int sprn, int gprn)
 127 {
 128     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 129 }
 130
 131 /* CTR */
 132 static void spr_read_ctr (void *opaque, int gprn, int sprn)
 133 {
 134     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 135 }
 136
 137 static void spr_write_ctr (void *opaque, int sprn, int gprn)
 138 {
 139     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 140 }
 141
 142 /* User read access to SPR */
 143 /* USPRx */
 144 /* UMMCRx */
 145 /* UPMCx */
 146 /* USIA */
 147 /* UDECR */
 148 static void spr_read_ureg (void *opaque, int gprn, int sprn)
 149 {
 150     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 151 }
 152
 153 /* SPR common to all non-embedded PowerPC */
 154 /* DECR */
 155 #if !defined(CONFIG_USER_ONLY)
 156 static void spr_read_decr (void *opaque, int gprn, int sprn)
 157 {
 158     gen_helper_load_decr(cpu_gpr[gprn]);
 159 }
 160
 161 static void spr_write_decr (void *opaque, int sprn, int gprn)
 162 {
 163     gen_helper_store_decr(cpu_gpr[gprn]);
 164 }
 165 #endif
 166
 167 /* SPR common to all non-embedded PowerPC, except 601 */
 168 /* Time base */
 169 static void spr_read_tbl (void *opaque, int gprn, int sprn)
 170 {
 171     gen_helper_load_tbl(cpu_gpr[gprn]);
 172 }
 173
 174 static void spr_read_tbu (void *opaque, int gprn, int sprn)
 175 {
 176     gen_helper_load_tbu(cpu_gpr[gprn]);
 177 }
 178
 179 __attribute__ (( unused ))
 180 static void spr_read_atbl (void *opaque, int gprn, int sprn)
 181 {
 182     gen_helper_load_atbl(cpu_gpr[gprn]);
 183 }
 184
 185 __attribute__ (( unused ))
 186 static void spr_read_atbu (void *opaque, int gprn, int sprn)
 187 {
 188     gen_helper_load_atbu(cpu_gpr[gprn]);
 189 }
 190
 191 #if !defined(CONFIG_USER_ONLY)
 192 static void spr_write_tbl (void *opaque, int sprn, int gprn)
 193 {
 194     gen_helper_store_tbl(cpu_gpr[gprn]);
 195 }
 196
 197 static void spr_write_tbu (void *opaque, int sprn, int gprn)
 198 {
 199     gen_helper_store_tbu(cpu_gpr[gprn]);
 200 }
 201
 202 __attribute__ (( unused ))
 203 static void spr_write_atbl (void *opaque, int sprn, int gprn)
 204 {
 205     gen_helper_store_atbl(cpu_gpr[gprn]);
 206 }
 207
 208 __attribute__ (( unused ))
 209 static void spr_write_atbu (void *opaque, int sprn, int gprn)
 210 {
 211     gen_helper_store_atbu(cpu_gpr[gprn]);
 212 }
 213 #endif
 214
 215 #if !defined(CONFIG_USER_ONLY)
 216 /* IBAT0U...IBAT0U */
 217 /* IBAT0L...IBAT7L */
 218 static void spr_read_ibat (void *opaque, int gprn, int sprn)
 219 {
 220     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 221 }
 222
 223 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
 224 {
 225     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
 226 }
 227
 228 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
 229 {
 230     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 231     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 232     tcg_temp_free_i32(t0);
 233 }
 234
 235 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
 236 {
 237     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
 238     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 239     tcg_temp_free_i32(t0);
 240 }
 241
 242 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
 243 {
 244     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 245     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 246     tcg_temp_free_i32(t0);
 247 }
 248
 249 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
 250 {
 251     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
 252     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 253     tcg_temp_free_i32(t0);
 254 }
 255
 256 /* DBAT0U...DBAT7U */
 257 /* DBAT0L...DBAT7L */
 258 static void spr_read_dbat (void *opaque, int gprn, int sprn)
 259 {
 260     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 261 }
 262
 263 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
 264 {
 265     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 266 }
 267
 268 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
 269 {
 270     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 271     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 272     tcg_temp_free_i32(t0);
 273 }
 274
 275 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
 276 {
 277     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 278     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 279     tcg_temp_free_i32(t0);
 280 }
 281
 282 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
 283 {
 284     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 285     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 286     tcg_temp_free_i32(t0);
 287 }
 288
 289 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
 290 {
 291     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 292     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 293     tcg_temp_free_i32(t0);
 294 }
 295
 296 /* SDR1 */
 297 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
 298 {
 299     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
 300 }
 301
 302 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
 303 {
 304     gen_helper_store_sdr1(cpu_gpr[gprn]);
 305 }
 306
 307 /* 64 bits PowerPC specific SPRs */
 308 /* ASR */
 309 #if defined(TARGET_PPC64)
 310 static void spr_read_hior (void *opaque, int gprn, int sprn)
 311 {
 312     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
 313 }
 314
 315 static void spr_write_hior (void *opaque, int sprn, int gprn)
 316 {
 317     TCGv t0 = tcg_temp_new();
 318     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 319     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 320     tcg_temp_free(t0);
 321 }
 322
 323 static void spr_read_asr (void *opaque, int gprn, int sprn)
 324 {
 325     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
 326 }
 327
 328 static void spr_write_asr (void *opaque, int sprn, int gprn)
 329 {
 330     gen_helper_store_asr(cpu_gpr[gprn]);
 331 }
 332 #endif
 333 #endif
 334
 335 /* PowerPC 601 specific registers */
 336 /* RTC */
 337 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
 338 {
 339     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
 340 }
 341
 342 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
 343 {
 344     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
 345 }
 346
 347 #if !defined(CONFIG_USER_ONLY)
 348 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
 349 {
 350     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
 351 }
 352
 353 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
 354 {
 355     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
 356 }
 357
 358 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
 359 {
 360     DisasContext *ctx = opaque;
 361
 362     gen_helper_store_hid0_601(cpu_gpr[gprn]);
 363     /* Must stop the translation as endianness may have changed */
 364     gen_stop_exception(ctx);
 365 }
 366 #endif
 367
 368 /* Unified bats */
 369 #if !defined(CONFIG_USER_ONLY)
 370 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
 371 {
 372     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 373 }
 374
 375 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
 376 {
 377     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 378     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
 379     tcg_temp_free_i32(t0);
 380 }
 381
 382 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
 383 {
 384     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 385     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
 386     tcg_temp_free_i32(t0);
 387 }
 388 #endif
 389
 390 /* PowerPC 40x specific registers */
 391 #if !defined(CONFIG_USER_ONLY)
 392 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
 393 {
 394     gen_helper_load_40x_pit(cpu_gpr[gprn]);
 395 }
 396
 397 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
 398 {
 399     gen_helper_store_40x_pit(cpu_gpr[gprn]);
 400 }
 401
 402 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
 403 {
 404     DisasContext *ctx = opaque;
 405
 406     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
 407     /* We must stop translation as we may have rebooted */
 408     gen_stop_exception(ctx);
 409 }
 410
 411 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
 412 {
 413     gen_helper_store_40x_sler(cpu_gpr[gprn]);
 414 }
 415
 416 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
 417 {
 418     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
 419 }
 420
 421 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
 422 {
 423     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
 424 }
 425 #endif
 426
 427 /* PowerPC 403 specific registers */
 428 /* PBL1 / PBU1 / PBL2 / PBU2 */
 429 #if !defined(CONFIG_USER_ONLY)
 430 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
 431 {
 432     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
 433 }
 434
 435 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
 436 {
 437     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 438     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
 439     tcg_temp_free_i32(t0);
 440 }
 441
 442 static void spr_write_pir (void *opaque, int sprn, int gprn)
 443 {
 444     TCGv t0 = tcg_temp_new();
 445     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 446     gen_store_spr(SPR_PIR, t0);
 447     tcg_temp_free(t0);
 448 }
 449 #endif
 450
 451 /* SPE specific registers */
 452 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
 453 {
 454     TCGv_i32 t0 = tcg_temp_new_i32();
 455     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 456     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 457     tcg_temp_free_i32(t0);
 458 }
 459
 460 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
 461 {
 462     TCGv_i32 t0 = tcg_temp_new_i32();
 463     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 464     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 465     tcg_temp_free_i32(t0);
 466 }
 467
 468 #if !defined(CONFIG_USER_ONLY)
 469 /* Callback used to write the exception vector base */
 470 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
 471 {
 472     TCGv t0 = tcg_temp_new();
 473     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
 474     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 475     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 476     gen_store_spr(sprn, t0);
 477     tcg_temp_free(t0);
 478 }
 479
 480 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
 481 {
 482     DisasContext *ctx = opaque;
 483
 484     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 485         TCGv t0 = tcg_temp_new();
 486         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 487         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 488         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
 489         gen_store_spr(sprn, t0);
 490         tcg_temp_free(t0);
 491     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 492         TCGv t0 = tcg_temp_new();
 493         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 494         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 495         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
 496         gen_store_spr(sprn, t0);
 497         tcg_temp_free(t0);
 498     } else {
 499         printf("Trying to write an unknown exception vector %d %03x\n",
 500                sprn, sprn);
 501         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 502     }
 503 }
 504 #endif
 505
 506 static inline void vscr_init (CPUPPCState *env, uint32_t val)
 507 {
 508     env->vscr = val;
 509     /* Altivec always uses round-to-nearest */
 510     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 511     set_flush_to_zero(vscr_nj, &env->vec_status);
 512 }
 513
 514 #if defined(CONFIG_USER_ONLY)
 515 #define spr_register(env, num, name, uea_read, uea_write,                     \
 516                      oea_read, oea_write, initial_value)                      \
 517 do {                                                                          \
 518      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
 519 } while (0)
 520 static inline void _spr_register (CPUPPCState *env, int num,
 521                                   const char *name,
 522                                   void (*uea_read)(void *opaque, int gprn, int sprn),
 523                                   void (*uea_write)(void *opaque, int sprn, int gprn),
 524                                   target_ulong initial_value)
 525 #else
 526 static inline void spr_register (CPUPPCState *env, int num,
 527                                  const char *name,
 528                                  void (*uea_read)(void *opaque, int gprn, int sprn),
 529                                  void (*uea_write)(void *opaque, int sprn, int gprn),
 530                                  void (*oea_read)(void *opaque, int gprn, int sprn),
 531                                  void (*oea_write)(void *opaque, int sprn, int gprn),
 532                                  target_ulong initial_value)
 533 #endif
 534 {
 535     ppc_spr_t *spr;
 536
 537     spr = &env->spr_cb[num];
 538     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 539 #if !defined(CONFIG_USER_ONLY)
 540         spr->oea_read != NULL || spr->oea_write != NULL ||
 541 #endif
 542         spr->uea_read != NULL || spr->uea_write != NULL) {
 543         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 544         exit(1);
 545     }
 546 #if defined(PPC_DEBUG_SPR)
 547     printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
 548            initial_value);
 549 #endif
 550     spr->name = name;
 551     spr->uea_read = uea_read;
 552     spr->uea_write = uea_write;
 553 #if !defined(CONFIG_USER_ONLY)
 554     spr->oea_read = oea_read;
 555     spr->oea_write = oea_write;
 556 #endif
 557     env->spr[num] = initial_value;
 558 }
 559
 560 /* Generic PowerPC SPRs */
 561 static void gen_spr_generic (CPUPPCState *env)
 562 {
 563     /* Integer processing */
 564     spr_register(env, SPR_XER, "XER",
 565                  &spr_read_xer, &spr_write_xer,
 566                  &spr_read_xer, &spr_write_xer,
 567                  0x00000000);
 568     /* Branch contol */
 569     spr_register(env, SPR_LR, "LR",
 570                  &spr_read_lr, &spr_write_lr,
 571                  &spr_read_lr, &spr_write_lr,
 572                  0x00000000);
 573     spr_register(env, SPR_CTR, "CTR",
 574                  &spr_read_ctr, &spr_write_ctr,
 575                  &spr_read_ctr, &spr_write_ctr,
 576                  0x00000000);
 577     /* Interrupt processing */
 578     spr_register(env, SPR_SRR0, "SRR0",
 579                  SPR_NOACCESS, SPR_NOACCESS,
 580                  &spr_read_generic, &spr_write_generic,
 581                  0x00000000);
 582     spr_register(env, SPR_SRR1, "SRR1",
 583                  SPR_NOACCESS, SPR_NOACCESS,
 584                  &spr_read_generic, &spr_write_generic,
 585                  0x00000000);
 586     /* Processor control */
 587     spr_register(env, SPR_SPRG0, "SPRG0",
 588                  SPR_NOACCESS, SPR_NOACCESS,
 589                  &spr_read_generic, &spr_write_generic,
 590                  0x00000000);
 591     spr_register(env, SPR_SPRG1, "SPRG1",
 592                  SPR_NOACCESS, SPR_NOACCESS,
 593                  &spr_read_generic, &spr_write_generic,
 594                  0x00000000);
 595     spr_register(env, SPR_SPRG2, "SPRG2",
 596                  SPR_NOACCESS, SPR_NOACCESS,
 597                  &spr_read_generic, &spr_write_generic,
 598                  0x00000000);
 599     spr_register(env, SPR_SPRG3, "SPRG3",
 600                  SPR_NOACCESS, SPR_NOACCESS,
 601                  &spr_read_generic, &spr_write_generic,
 602                  0x00000000);
 603 }
 604
 605 /* SPR common to all non-embedded PowerPC, including 601 */
 606 static void gen_spr_ne_601 (CPUPPCState *env)
 607 {
 608     /* Exception processing */
 609     spr_register(env, SPR_DSISR, "DSISR",
 610                  SPR_NOACCESS, SPR_NOACCESS,
 611                  &spr_read_generic, &spr_write_generic,
 612                  0x00000000);
 613     spr_register(env, SPR_DAR, "DAR",
 614                  SPR_NOACCESS, SPR_NOACCESS,
 615                  &spr_read_generic, &spr_write_generic,
 616                  0x00000000);
 617     /* Timer */
 618     spr_register(env, SPR_DECR, "DECR",
 619                  SPR_NOACCESS, SPR_NOACCESS,
 620                  &spr_read_decr, &spr_write_decr,
 621                  0x00000000);
 622     /* Memory management */
 623     spr_register(env, SPR_SDR1, "SDR1",
 624                  SPR_NOACCESS, SPR_NOACCESS,
 625                  &spr_read_sdr1, &spr_write_sdr1,
 626                  0x00000000);
 627 }
 628
 629 /* BATs 0-3 */
 630 static void gen_low_BATs (CPUPPCState *env)
 631 {
 632 #if !defined(CONFIG_USER_ONLY)
 633     spr_register(env, SPR_IBAT0U, "IBAT0U",
 634                  SPR_NOACCESS, SPR_NOACCESS,
 635                  &spr_read_ibat, &spr_write_ibatu,
 636                  0x00000000);
 637     spr_register(env, SPR_IBAT0L, "IBAT0L",
 638                  SPR_NOACCESS, SPR_NOACCESS,
 639                  &spr_read_ibat, &spr_write_ibatl,
 640                  0x00000000);
 641     spr_register(env, SPR_IBAT1U, "IBAT1U",
 642                  SPR_NOACCESS, SPR_NOACCESS,
 643                  &spr_read_ibat, &spr_write_ibatu,
 644                  0x00000000);
 645     spr_register(env, SPR_IBAT1L, "IBAT1L",
 646                  SPR_NOACCESS, SPR_NOACCESS,
 647                  &spr_read_ibat, &spr_write_ibatl,
 648                  0x00000000);
 649     spr_register(env, SPR_IBAT2U, "IBAT2U",
 650                  SPR_NOACCESS, SPR_NOACCESS,
 651                  &spr_read_ibat, &spr_write_ibatu,
 652                  0x00000000);
 653     spr_register(env, SPR_IBAT2L, "IBAT2L",
 654                  SPR_NOACCESS, SPR_NOACCESS,
 655                  &spr_read_ibat, &spr_write_ibatl,
 656                  0x00000000);
 657     spr_register(env, SPR_IBAT3U, "IBAT3U",
 658                  SPR_NOACCESS, SPR_NOACCESS,
 659                  &spr_read_ibat, &spr_write_ibatu,
 660                  0x00000000);
 661     spr_register(env, SPR_IBAT3L, "IBAT3L",
 662                  SPR_NOACCESS, SPR_NOACCESS,
 663                  &spr_read_ibat, &spr_write_ibatl,
 664                  0x00000000);
 665     spr_register(env, SPR_DBAT0U, "DBAT0U",
 666                  SPR_NOACCESS, SPR_NOACCESS,
 667                  &spr_read_dbat, &spr_write_dbatu,
 668                  0x00000000);
 669     spr_register(env, SPR_DBAT0L, "DBAT0L",
 670                  SPR_NOACCESS, SPR_NOACCESS,
 671                  &spr_read_dbat, &spr_write_dbatl,
 672                  0x00000000);
 673     spr_register(env, SPR_DBAT1U, "DBAT1U",
 674                  SPR_NOACCESS, SPR_NOACCESS,
 675                  &spr_read_dbat, &spr_write_dbatu,
 676                  0x00000000);
 677     spr_register(env, SPR_DBAT1L, "DBAT1L",
 678                  SPR_NOACCESS, SPR_NOACCESS,
 679                  &spr_read_dbat, &spr_write_dbatl,
 680                  0x00000000);
 681     spr_register(env, SPR_DBAT2U, "DBAT2U",
 682                  SPR_NOACCESS, SPR_NOACCESS,
 683                  &spr_read_dbat, &spr_write_dbatu,
 684                  0x00000000);
 685     spr_register(env, SPR_DBAT2L, "DBAT2L",
 686                  SPR_NOACCESS, SPR_NOACCESS,
 687                  &spr_read_dbat, &spr_write_dbatl,
 688                  0x00000000);
 689     spr_register(env, SPR_DBAT3U, "DBAT3U",
 690                  SPR_NOACCESS, SPR_NOACCESS,
 691                  &spr_read_dbat, &spr_write_dbatu,
 692                  0x00000000);
 693     spr_register(env, SPR_DBAT3L, "DBAT3L",
 694                  SPR_NOACCESS, SPR_NOACCESS,
 695                  &spr_read_dbat, &spr_write_dbatl,
 696                  0x00000000);
 697     env->nb_BATs += 4;
 698 #endif
 699 }
 700
 701 /* BATs 4-7 */
 702 static void gen_high_BATs (CPUPPCState *env)
 703 {
 704 #if !defined(CONFIG_USER_ONLY)
 705     spr_register(env, SPR_IBAT4U, "IBAT4U",
 706                  SPR_NOACCESS, SPR_NOACCESS,
 707                  &spr_read_ibat_h, &spr_write_ibatu_h,
 708                  0x00000000);
 709     spr_register(env, SPR_IBAT4L, "IBAT4L",
 710                  SPR_NOACCESS, SPR_NOACCESS,
 711                  &spr_read_ibat_h, &spr_write_ibatl_h,
 712                  0x00000000);
 713     spr_register(env, SPR_IBAT5U, "IBAT5U",
 714                  SPR_NOACCESS, SPR_NOACCESS,
 715                  &spr_read_ibat_h, &spr_write_ibatu_h,
 716                  0x00000000);
 717     spr_register(env, SPR_IBAT5L, "IBAT5L",
 718                  SPR_NOACCESS, SPR_NOACCESS,
 719                  &spr_read_ibat_h, &spr_write_ibatl_h,
 720                  0x00000000);
 721     spr_register(env, SPR_IBAT6U, "IBAT6U",
 722                  SPR_NOACCESS, SPR_NOACCESS,
 723                  &spr_read_ibat_h, &spr_write_ibatu_h,
 724                  0x00000000);
 725     spr_register(env, SPR_IBAT6L, "IBAT6L",
 726                  SPR_NOACCESS, SPR_NOACCESS,
 727                  &spr_read_ibat_h, &spr_write_ibatl_h,
 728                  0x00000000);
 729     spr_register(env, SPR_IBAT7U, "IBAT7U",
 730                  SPR_NOACCESS, SPR_NOACCESS,
 731                  &spr_read_ibat_h, &spr_write_ibatu_h,
 732                  0x00000000);
 733     spr_register(env, SPR_IBAT7L, "IBAT7L",
 734                  SPR_NOACCESS, SPR_NOACCESS,
 735                  &spr_read_ibat_h, &spr_write_ibatl_h,
 736                  0x00000000);
 737     spr_register(env, SPR_DBAT4U, "DBAT4U",
 738                  SPR_NOACCESS, SPR_NOACCESS,
 739                  &spr_read_dbat_h, &spr_write_dbatu_h,
 740                  0x00000000);
 741     spr_register(env, SPR_DBAT4L, "DBAT4L",
 742                  SPR_NOACCESS, SPR_NOACCESS,
 743                  &spr_read_dbat_h, &spr_write_dbatl_h,
 744                  0x00000000);
 745     spr_register(env, SPR_DBAT5U, "DBAT5U",
 746                  SPR_NOACCESS, SPR_NOACCESS,
 747                  &spr_read_dbat_h, &spr_write_dbatu_h,
 748                  0x00000000);
 749     spr_register(env, SPR_DBAT5L, "DBAT5L",
 750                  SPR_NOACCESS, SPR_NOACCESS,
 751                  &spr_read_dbat_h, &spr_write_dbatl_h,
 752                  0x00000000);
 753     spr_register(env, SPR_DBAT6U, "DBAT6U",
 754                  SPR_NOACCESS, SPR_NOACCESS,
 755                  &spr_read_dbat_h, &spr_write_dbatu_h,
 756                  0x00000000);
 757     spr_register(env, SPR_DBAT6L, "DBAT6L",
 758                  SPR_NOACCESS, SPR_NOACCESS,
 759                  &spr_read_dbat_h, &spr_write_dbatl_h,
 760                  0x00000000);
 761     spr_register(env, SPR_DBAT7U, "DBAT7U",
 762                  SPR_NOACCESS, SPR_NOACCESS,
 763                  &spr_read_dbat_h, &spr_write_dbatu_h,
 764                  0x00000000);
 765     spr_register(env, SPR_DBAT7L, "DBAT7L",
 766                  SPR_NOACCESS, SPR_NOACCESS,
 767                  &spr_read_dbat_h, &spr_write_dbatl_h,
 768                  0x00000000);
 769     env->nb_BATs += 4;
 770 #endif
 771 }
 772
 773 /* Generic PowerPC time base */
 774 static void gen_tbl (CPUPPCState *env)
 775 {
 776     spr_register(env, SPR_VTBL,  "TBL",
 777                  &spr_read_tbl, SPR_NOACCESS,
 778                  &spr_read_tbl, SPR_NOACCESS,
 779                  0x00000000);
 780     spr_register(env, SPR_TBL,   "TBL",
 781                  SPR_NOACCESS, SPR_NOACCESS,
 782                  SPR_NOACCESS, &spr_write_tbl,
 783                  0x00000000);
 784     spr_register(env, SPR_VTBU,  "TBU",
 785                  &spr_read_tbu, SPR_NOACCESS,
 786                  &spr_read_tbu, SPR_NOACCESS,
 787                  0x00000000);
 788     spr_register(env, SPR_TBU,   "TBU",
 789                  SPR_NOACCESS, SPR_NOACCESS,
 790                  SPR_NOACCESS, &spr_write_tbu,
 791                  0x00000000);
 792 }
 793
 794 /* Softare table search registers */
 795 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 796 {
 797 #if !defined(CONFIG_USER_ONLY)
 798     env->nb_tlb = nb_tlbs;
 799     env->nb_ways = nb_ways;
 800     env->id_tlbs = 1;
 801     spr_register(env, SPR_DMISS, "DMISS",
 802                  SPR_NOACCESS, SPR_NOACCESS,
 803                  &spr_read_generic, SPR_NOACCESS,
 804                  0x00000000);
 805     spr_register(env, SPR_DCMP, "DCMP",
 806                  SPR_NOACCESS, SPR_NOACCESS,
 807                  &spr_read_generic, SPR_NOACCESS,
 808                  0x00000000);
 809     spr_register(env, SPR_HASH1, "HASH1",
 810                  SPR_NOACCESS, SPR_NOACCESS,
 811                  &spr_read_generic, SPR_NOACCESS,
 812                  0x00000000);
 813     spr_register(env, SPR_HASH2, "HASH2",
 814                  SPR_NOACCESS, SPR_NOACCESS,
 815                  &spr_read_generic, SPR_NOACCESS,
 816                  0x00000000);
 817     spr_register(env, SPR_IMISS, "IMISS",
 818                  SPR_NOACCESS, SPR_NOACCESS,
 819                  &spr_read_generic, SPR_NOACCESS,
 820                  0x00000000);
 821     spr_register(env, SPR_ICMP, "ICMP",
 822                  SPR_NOACCESS, SPR_NOACCESS,
 823                  &spr_read_generic, SPR_NOACCESS,
 824                  0x00000000);
 825     spr_register(env, SPR_RPA, "RPA",
 826                  SPR_NOACCESS, SPR_NOACCESS,
 827                  &spr_read_generic, &spr_write_generic,
 828                  0x00000000);
 829 #endif
 830 }
 831
 832 /* SPR common to MPC755 and G2 */
 833 static void gen_spr_G2_755 (CPUPPCState *env)
 834 {
 835     /* SGPRs */
 836     spr_register(env, SPR_SPRG4, "SPRG4",
 837                  SPR_NOACCESS, SPR_NOACCESS,
 838                  &spr_read_generic, &spr_write_generic,
 839                  0x00000000);
 840     spr_register(env, SPR_SPRG5, "SPRG5",
 841                  SPR_NOACCESS, SPR_NOACCESS,
 842                  &spr_read_generic, &spr_write_generic,
 843                  0x00000000);
 844     spr_register(env, SPR_SPRG6, "SPRG6",
 845                  SPR_NOACCESS, SPR_NOACCESS,
 846                  &spr_read_generic, &spr_write_generic,
 847                  0x00000000);
 848     spr_register(env, SPR_SPRG7, "SPRG7",
 849                  SPR_NOACCESS, SPR_NOACCESS,
 850                  &spr_read_generic, &spr_write_generic,
 851                  0x00000000);
 852 }
 853
 854 /* SPR common to all 7xx PowerPC implementations */
 855 static void gen_spr_7xx (CPUPPCState *env)
 856 {
 857     /* Breakpoints */
 858     /* XXX : not implemented */
 859     spr_register(env, SPR_DABR, "DABR",
 860                  SPR_NOACCESS, SPR_NOACCESS,
 861                  &spr_read_generic, &spr_write_generic,
 862                  0x00000000);
 863     /* XXX : not implemented */
 864     spr_register(env, SPR_IABR, "IABR",
 865                  SPR_NOACCESS, SPR_NOACCESS,
 866                  &spr_read_generic, &spr_write_generic,
 867                  0x00000000);
 868     /* Cache management */
 869     /* XXX : not implemented */
 870     spr_register(env, SPR_ICTC, "ICTC",
 871                  SPR_NOACCESS, SPR_NOACCESS,
 872                  &spr_read_generic, &spr_write_generic,
 873                  0x00000000);
 874     /* Performance monitors */
 875     /* XXX : not implemented */
 876     spr_register(env, SPR_MMCR0, "MMCR0",
 877                  SPR_NOACCESS, SPR_NOACCESS,
 878                  &spr_read_generic, &spr_write_generic,
 879                  0x00000000);
 880     /* XXX : not implemented */
 881     spr_register(env, SPR_MMCR1, "MMCR1",
 882                  SPR_NOACCESS, SPR_NOACCESS,
 883                  &spr_read_generic, &spr_write_generic,
 884                  0x00000000);
 885     /* XXX : not implemented */
 886     spr_register(env, SPR_PMC1, "PMC1",
 887                  SPR_NOACCESS, SPR_NOACCESS,
 888                  &spr_read_generic, &spr_write_generic,
 889                  0x00000000);
 890     /* XXX : not implemented */
 891     spr_register(env, SPR_PMC2, "PMC2",
 892                  SPR_NOACCESS, SPR_NOACCESS,
 893                  &spr_read_generic, &spr_write_generic,
 894                  0x00000000);
 895     /* XXX : not implemented */
 896     spr_register(env, SPR_PMC3, "PMC3",
 897                  SPR_NOACCESS, SPR_NOACCESS,
 898                  &spr_read_generic, &spr_write_generic,
 899                  0x00000000);
 900     /* XXX : not implemented */
 901     spr_register(env, SPR_PMC4, "PMC4",
 902                  SPR_NOACCESS, SPR_NOACCESS,
 903                  &spr_read_generic, &spr_write_generic,
 904                  0x00000000);
 905     /* XXX : not implemented */
 906     spr_register(env, SPR_SIAR, "SIAR",
 907                  SPR_NOACCESS, SPR_NOACCESS,
 908                  &spr_read_generic, SPR_NOACCESS,
 909                  0x00000000);
 910     /* XXX : not implemented */
 911     spr_register(env, SPR_UMMCR0, "UMMCR0",
 912                  &spr_read_ureg, SPR_NOACCESS,
 913                  &spr_read_ureg, SPR_NOACCESS,
 914                  0x00000000);
 915     /* XXX : not implemented */
 916     spr_register(env, SPR_UMMCR1, "UMMCR1",
 917                  &spr_read_ureg, SPR_NOACCESS,
 918                  &spr_read_ureg, SPR_NOACCESS,
 919                  0x00000000);
 920     /* XXX : not implemented */
 921     spr_register(env, SPR_UPMC1, "UPMC1",
 922                  &spr_read_ureg, SPR_NOACCESS,
 923                  &spr_read_ureg, SPR_NOACCESS,
 924                  0x00000000);
 925     /* XXX : not implemented */
 926     spr_register(env, SPR_UPMC2, "UPMC2",
 927                  &spr_read_ureg, SPR_NOACCESS,
 928                  &spr_read_ureg, SPR_NOACCESS,
 929                  0x00000000);
 930     /* XXX : not implemented */
 931     spr_register(env, SPR_UPMC3, "UPMC3",
 932                  &spr_read_ureg, SPR_NOACCESS,
 933                  &spr_read_ureg, SPR_NOACCESS,
 934                  0x00000000);
 935     /* XXX : not implemented */
 936     spr_register(env, SPR_UPMC4, "UPMC4",
 937                  &spr_read_ureg, SPR_NOACCESS,
 938                  &spr_read_ureg, SPR_NOACCESS,
 939                  0x00000000);
 940     /* XXX : not implemented */
 941     spr_register(env, SPR_USIAR, "USIAR",
 942                  &spr_read_ureg, SPR_NOACCESS,
 943                  &spr_read_ureg, SPR_NOACCESS,
 944                  0x00000000);
 945     /* External access control */
 946     /* XXX : not implemented */
 947     spr_register(env, SPR_EAR, "EAR",
 948                  SPR_NOACCESS, SPR_NOACCESS,
 949                  &spr_read_generic, &spr_write_generic,
 950                  0x00000000);
 951 }
 952
 953 static void gen_spr_thrm (CPUPPCState *env)
 954 {
 955     /* Thermal management */
 956     /* XXX : not implemented */
 957     spr_register(env, SPR_THRM1, "THRM1",
 958                  SPR_NOACCESS, SPR_NOACCESS,
 959                  &spr_read_generic, &spr_write_generic,
 960                  0x00000000);
 961     /* XXX : not implemented */
 962     spr_register(env, SPR_THRM2, "THRM2",
 963                  SPR_NOACCESS, SPR_NOACCESS,
 964                  &spr_read_generic, &spr_write_generic,
 965                  0x00000000);
 966     /* XXX : not implemented */
 967     spr_register(env, SPR_THRM3, "THRM3",
 968                  SPR_NOACCESS, SPR_NOACCESS,
 969                  &spr_read_generic, &spr_write_generic,
 970                  0x00000000);
 971 }
 972
 973 /* SPR specific to PowerPC 604 implementation */
 974 static void gen_spr_604 (CPUPPCState *env)
 975 {
 976     /* Processor identification */
 977     spr_register(env, SPR_PIR, "PIR",
 978                  SPR_NOACCESS, SPR_NOACCESS,
 979                  &spr_read_generic, &spr_write_pir,
 980                  0x00000000);
 981     /* Breakpoints */
 982     /* XXX : not implemented */
 983     spr_register(env, SPR_IABR, "IABR",
 984                  SPR_NOACCESS, SPR_NOACCESS,
 985                  &spr_read_generic, &spr_write_generic,
 986                  0x00000000);
 987     /* XXX : not implemented */
 988     spr_register(env, SPR_DABR, "DABR",
 989                  SPR_NOACCESS, SPR_NOACCESS,
 990                  &spr_read_generic, &spr_write_generic,
 991                  0x00000000);
 992     /* Performance counters */
 993     /* XXX : not implemented */
 994     spr_register(env, SPR_MMCR0, "MMCR0",
 995                  SPR_NOACCESS, SPR_NOACCESS,
 996                  &spr_read_generic, &spr_write_generic,
 997                  0x00000000);
 998     /* XXX : not implemented */
 999     spr_register(env, SPR_PMC1, "PMC1",
1000                  SPR_NOACCESS, SPR_NOACCESS,
1001                  &spr_read_generic, &spr_write_generic,
1002                  0x00000000);
1003     /* XXX : not implemented */
1004     spr_register(env, SPR_PMC2, "PMC2",
1005                  SPR_NOACCESS, SPR_NOACCESS,
1006                  &spr_read_generic, &spr_write_generic,
1007                  0x00000000);
1008     /* XXX : not implemented */
1009     spr_register(env, SPR_SIAR, "SIAR",
1010                  SPR_NOACCESS, SPR_NOACCESS,
1011                  &spr_read_generic, SPR_NOACCESS,
1012                  0x00000000);
1013     /* XXX : not implemented */
1014     spr_register(env, SPR_SDA, "SDA",
1015                  SPR_NOACCESS, SPR_NOACCESS,
1016                  &spr_read_generic, SPR_NOACCESS,
1017                  0x00000000);
1018     /* External access control */
1019     /* XXX : not implemented */
1020     spr_register(env, SPR_EAR, "EAR",
1021                  SPR_NOACCESS, SPR_NOACCESS,
1022                  &spr_read_generic, &spr_write_generic,
1023                  0x00000000);
1024 }
1025
1026 /* SPR specific to PowerPC 603 implementation */
1027 static void gen_spr_603 (CPUPPCState *env)
1028 {
1029     /* External access control */
1030     /* XXX : not implemented */
1031     spr_register(env, SPR_EAR, "EAR",
1032                  SPR_NOACCESS, SPR_NOACCESS,
1033                  &spr_read_generic, &spr_write_generic,
1034                  0x00000000);
1035 }
1036
1037 /* SPR specific to PowerPC G2 implementation */
1038 static void gen_spr_G2 (CPUPPCState *env)
1039 {
1040     /* Memory base address */
1041     /* MBAR */
1042     /* XXX : not implemented */
1043     spr_register(env, SPR_MBAR, "MBAR",
1044                  SPR_NOACCESS, SPR_NOACCESS,
1045                  &spr_read_generic, &spr_write_generic,
1046                  0x00000000);
1047     /* Exception processing */
1048     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1049                  SPR_NOACCESS, SPR_NOACCESS,
1050                  &spr_read_generic, &spr_write_generic,
1051                  0x00000000);
1052     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1053                  SPR_NOACCESS, SPR_NOACCESS,
1054                  &spr_read_generic, &spr_write_generic,
1055                  0x00000000);
1056     /* Breakpoints */
1057     /* XXX : not implemented */
1058     spr_register(env, SPR_DABR, "DABR",
1059                  SPR_NOACCESS, SPR_NOACCESS,
1060                  &spr_read_generic, &spr_write_generic,
1061                  0x00000000);
1062     /* XXX : not implemented */
1063     spr_register(env, SPR_DABR2, "DABR2",
1064                  SPR_NOACCESS, SPR_NOACCESS,
1065                  &spr_read_generic, &spr_write_generic,
1066                  0x00000000);
1067     /* XXX : not implemented */
1068     spr_register(env, SPR_IABR, "IABR",
1069                  SPR_NOACCESS, SPR_NOACCESS,
1070                  &spr_read_generic, &spr_write_generic,
1071                  0x00000000);
1072     /* XXX : not implemented */
1073     spr_register(env, SPR_IABR2, "IABR2",
1074                  SPR_NOACCESS, SPR_NOACCESS,
1075                  &spr_read_generic, &spr_write_generic,
1076                  0x00000000);
1077     /* XXX : not implemented */
1078     spr_register(env, SPR_IBCR, "IBCR",
1079                  SPR_NOACCESS, SPR_NOACCESS,
1080                  &spr_read_generic, &spr_write_generic,
1081                  0x00000000);
1082     /* XXX : not implemented */
1083     spr_register(env, SPR_DBCR, "DBCR",
1084                  SPR_NOACCESS, SPR_NOACCESS,
1085                  &spr_read_generic, &spr_write_generic,
1086                  0x00000000);
1087 }
1088
1089 /* SPR specific to PowerPC 602 implementation */
1090 static void gen_spr_602 (CPUPPCState *env)
1091 {
1092     /* ESA registers */
1093     /* XXX : not implemented */
1094     spr_register(env, SPR_SER, "SER",
1095                  SPR_NOACCESS, SPR_NOACCESS,
1096                  &spr_read_generic, &spr_write_generic,
1097                  0x00000000);
1098     /* XXX : not implemented */
1099     spr_register(env, SPR_SEBR, "SEBR",
1100                  SPR_NOACCESS, SPR_NOACCESS,
1101                  &spr_read_generic, &spr_write_generic,
1102                  0x00000000);
1103     /* XXX : not implemented */
1104     spr_register(env, SPR_ESASRR, "ESASRR",
1105                  SPR_NOACCESS, SPR_NOACCESS,
1106                  &spr_read_generic, &spr_write_generic,
1107                  0x00000000);
1108     /* Floating point status */
1109     /* XXX : not implemented */
1110     spr_register(env, SPR_SP, "SP",
1111                  SPR_NOACCESS, SPR_NOACCESS,
1112                  &spr_read_generic, &spr_write_generic,
1113                  0x00000000);
1114     /* XXX : not implemented */
1115     spr_register(env, SPR_LT, "LT",
1116                  SPR_NOACCESS, SPR_NOACCESS,
1117                  &spr_read_generic, &spr_write_generic,
1118                  0x00000000);
1119     /* Watchdog timer */
1120     /* XXX : not implemented */
1121     spr_register(env, SPR_TCR, "TCR",
1122                  SPR_NOACCESS, SPR_NOACCESS,
1123                  &spr_read_generic, &spr_write_generic,
1124                  0x00000000);
1125     /* Interrupt base */
1126     spr_register(env, SPR_IBR, "IBR",
1127                  SPR_NOACCESS, SPR_NOACCESS,
1128                  &spr_read_generic, &spr_write_generic,
1129                  0x00000000);
1130     /* XXX : not implemented */
1131     spr_register(env, SPR_IABR, "IABR",
1132                  SPR_NOACCESS, SPR_NOACCESS,
1133                  &spr_read_generic, &spr_write_generic,
1134                  0x00000000);
1135 }
1136
1137 /* SPR specific to PowerPC 601 implementation */
1138 static void gen_spr_601 (CPUPPCState *env)
1139 {
1140     /* Multiplication/division register */
1141     /* MQ */
1142     spr_register(env, SPR_MQ, "MQ",
1143                  &spr_read_generic, &spr_write_generic,
1144                  &spr_read_generic, &spr_write_generic,
1145                  0x00000000);
1146     /* RTC registers */
1147     spr_register(env, SPR_601_RTCU, "RTCU",
1148                  SPR_NOACCESS, SPR_NOACCESS,
1149                  SPR_NOACCESS, &spr_write_601_rtcu,
1150                  0x00000000);
1151     spr_register(env, SPR_601_VRTCU, "RTCU",
1152                  &spr_read_601_rtcu, SPR_NOACCESS,
1153                  &spr_read_601_rtcu, SPR_NOACCESS,
1154                  0x00000000);
1155     spr_register(env, SPR_601_RTCL, "RTCL",
1156                  SPR_NOACCESS, SPR_NOACCESS,
1157                  SPR_NOACCESS, &spr_write_601_rtcl,
1158                  0x00000000);
1159     spr_register(env, SPR_601_VRTCL, "RTCL",
1160                  &spr_read_601_rtcl, SPR_NOACCESS,
1161                  &spr_read_601_rtcl, SPR_NOACCESS,
1162                  0x00000000);
1163     /* Timer */
1164 #if 0 /* ? */
1165     spr_register(env, SPR_601_UDECR, "UDECR",
1166                  &spr_read_decr, SPR_NOACCESS,
1167                  &spr_read_decr, SPR_NOACCESS,
1168                  0x00000000);
1169 #endif
1170     /* External access control */
1171     /* XXX : not implemented */
1172     spr_register(env, SPR_EAR, "EAR",
1173                  SPR_NOACCESS, SPR_NOACCESS,
1174                  &spr_read_generic, &spr_write_generic,
1175                  0x00000000);
1176     /* Memory management */
1177 #if !defined(CONFIG_USER_ONLY)
1178     spr_register(env, SPR_IBAT0U, "IBAT0U",
1179                  SPR_NOACCESS, SPR_NOACCESS,
1180                  &spr_read_601_ubat, &spr_write_601_ubatu,
1181                  0x00000000);
1182     spr_register(env, SPR_IBAT0L, "IBAT0L",
1183                  SPR_NOACCESS, SPR_NOACCESS,
1184                  &spr_read_601_ubat, &spr_write_601_ubatl,
1185                  0x00000000);
1186     spr_register(env, SPR_IBAT1U, "IBAT1U",
1187                  SPR_NOACCESS, SPR_NOACCESS,
1188                  &spr_read_601_ubat, &spr_write_601_ubatu,
1189                  0x00000000);
1190     spr_register(env, SPR_IBAT1L, "IBAT1L",
1191                  SPR_NOACCESS, SPR_NOACCESS,
1192                  &spr_read_601_ubat, &spr_write_601_ubatl,
1193                  0x00000000);
1194     spr_register(env, SPR_IBAT2U, "IBAT2U",
1195                  SPR_NOACCESS, SPR_NOACCESS,
1196                  &spr_read_601_ubat, &spr_write_601_ubatu,
1197                  0x00000000);
1198     spr_register(env, SPR_IBAT2L, "IBAT2L",
1199                  SPR_NOACCESS, SPR_NOACCESS,
1200                  &spr_read_601_ubat, &spr_write_601_ubatl,
1201                  0x00000000);
1202     spr_register(env, SPR_IBAT3U, "IBAT3U",
1203                  SPR_NOACCESS, SPR_NOACCESS,
1204                  &spr_read_601_ubat, &spr_write_601_ubatu,
1205                  0x00000000);
1206     spr_register(env, SPR_IBAT3L, "IBAT3L",
1207                  SPR_NOACCESS, SPR_NOACCESS,
1208                  &spr_read_601_ubat, &spr_write_601_ubatl,
1209                  0x00000000);
1210     env->nb_BATs = 4;
1211 #endif
1212 }
1213
1214 static void gen_spr_74xx (CPUPPCState *env)
1215 {
1216     /* Processor identification */
1217     spr_register(env, SPR_PIR, "PIR",
1218                  SPR_NOACCESS, SPR_NOACCESS,
1219                  &spr_read_generic, &spr_write_pir,
1220                  0x00000000);
1221     /* XXX : not implemented */
1222     spr_register(env, SPR_MMCR2, "MMCR2",
1223                  SPR_NOACCESS, SPR_NOACCESS,
1224                  &spr_read_generic, &spr_write_generic,
1225                  0x00000000);
1226     /* XXX : not implemented */
1227     spr_register(env, SPR_UMMCR2, "UMMCR2",
1228                  &spr_read_ureg, SPR_NOACCESS,
1229                  &spr_read_ureg, SPR_NOACCESS,
1230                  0x00000000);
1231     /* XXX: not implemented */
1232     spr_register(env, SPR_BAMR, "BAMR",
1233                  SPR_NOACCESS, SPR_NOACCESS,
1234                  &spr_read_generic, &spr_write_generic,
1235                  0x00000000);
1236     /* XXX : not implemented */
1237     spr_register(env, SPR_MSSCR0, "MSSCR0",
1238                  SPR_NOACCESS, SPR_NOACCESS,
1239                  &spr_read_generic, &spr_write_generic,
1240                  0x00000000);
1241     /* Hardware implementation registers */
1242     /* XXX : not implemented */
1243     spr_register(env, SPR_HID0, "HID0",
1244                  SPR_NOACCESS, SPR_NOACCESS,
1245                  &spr_read_generic, &spr_write_generic,
1246                  0x00000000);
1247     /* XXX : not implemented */
1248     spr_register(env, SPR_HID1, "HID1",
1249                  SPR_NOACCESS, SPR_NOACCESS,
1250                  &spr_read_generic, &spr_write_generic,
1251                  0x00000000);
1252     /* Altivec */
1253     spr_register(env, SPR_VRSAVE, "VRSAVE",
1254                  &spr_read_generic, &spr_write_generic,
1255                  &spr_read_generic, &spr_write_generic,
1256                  0x00000000);
1257     /* XXX : not implemented */
1258     spr_register(env, SPR_L2CR, "L2CR",
1259                  SPR_NOACCESS, SPR_NOACCESS,
1260                  &spr_read_generic, &spr_write_generic,
1261                  0x00000000);
1262     /* Not strictly an SPR */
1263     vscr_init(env, 0x00010000);
1264 }
1265
1266 static void gen_l3_ctrl (CPUPPCState *env)
1267 {
1268     /* L3CR */
1269     /* XXX : not implemented */
1270     spr_register(env, SPR_L3CR, "L3CR",
1271                  SPR_NOACCESS, SPR_NOACCESS,
1272                  &spr_read_generic, &spr_write_generic,
1273                  0x00000000);
1274     /* L3ITCR0 */
1275     /* XXX : not implemented */
1276     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1277                  SPR_NOACCESS, SPR_NOACCESS,
1278                  &spr_read_generic, &spr_write_generic,
1279                  0x00000000);
1280     /* L3PM */
1281     /* XXX : not implemented */
1282     spr_register(env, SPR_L3PM, "L3PM",
1283                  SPR_NOACCESS, SPR_NOACCESS,
1284                  &spr_read_generic, &spr_write_generic,
1285                  0x00000000);
1286 }
1287
1288 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1289 {
1290 #if !defined(CONFIG_USER_ONLY)
1291     env->nb_tlb = nb_tlbs;
1292     env->nb_ways = nb_ways;
1293     env->id_tlbs = 1;
1294     /* XXX : not implemented */
1295     spr_register(env, SPR_PTEHI, "PTEHI",
1296                  SPR_NOACCESS, SPR_NOACCESS,
1297                  &spr_read_generic, &spr_write_generic,
1298                  0x00000000);
1299     /* XXX : not implemented */
1300     spr_register(env, SPR_PTELO, "PTELO",
1301                  SPR_NOACCESS, SPR_NOACCESS,
1302                  &spr_read_generic, &spr_write_generic,
1303                  0x00000000);
1304     /* XXX : not implemented */
1305     spr_register(env, SPR_TLBMISS, "TLBMISS",
1306                  SPR_NOACCESS, SPR_NOACCESS,
1307                  &spr_read_generic, &spr_write_generic,
1308                  0x00000000);
1309 #endif
1310 }
1311
1312 static void gen_spr_usprgh (CPUPPCState *env)
1313 {
1314     spr_register(env, SPR_USPRG4, "USPRG4",
1315                  &spr_read_ureg, SPR_NOACCESS,
1316                  &spr_read_ureg, SPR_NOACCESS,
1317                  0x00000000);
1318     spr_register(env, SPR_USPRG5, "USPRG5",
1319                  &spr_read_ureg, SPR_NOACCESS,
1320                  &spr_read_ureg, SPR_NOACCESS,
1321                  0x00000000);
1322     spr_register(env, SPR_USPRG6, "USPRG6",
1323                  &spr_read_ureg, SPR_NOACCESS,
1324                  &spr_read_ureg, SPR_NOACCESS,
1325                  0x00000000);
1326     spr_register(env, SPR_USPRG7, "USPRG7",
1327                  &spr_read_ureg, SPR_NOACCESS,
1328                  &spr_read_ureg, SPR_NOACCESS,
1329                  0x00000000);
1330 }
1331
1332 /* PowerPC BookE SPR */
1333 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1334 {
1335     const char *ivor_names[64] = {
1336         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1337         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1338         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1339         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1340         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1341         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1342         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1343         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1344         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1345         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1346         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1347         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1348         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1349         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1350         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1351         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1352     };
1353 #define SPR_BOOKE_IVORxx (-1)
1354     int ivor_sprn[64] = {
1355         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1356         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1357         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1358         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1359         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1360         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1361         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1362         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1363         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1364         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1365         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1366         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1367         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1368         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1369         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1370         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1371     };
1372     int i;
1373
1374     /* Interrupt processing */
1375     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1376                  SPR_NOACCESS, SPR_NOACCESS,
1377                  &spr_read_generic, &spr_write_generic,
1378                  0x00000000);
1379     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1380                  SPR_NOACCESS, SPR_NOACCESS,
1381                  &spr_read_generic, &spr_write_generic,
1382                  0x00000000);
1383     /* Debug */
1384     /* XXX : not implemented */
1385     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1386                  SPR_NOACCESS, SPR_NOACCESS,
1387                  &spr_read_generic, &spr_write_generic,
1388                  0x00000000);
1389     /* XXX : not implemented */
1390     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1391                  SPR_NOACCESS, SPR_NOACCESS,
1392                  &spr_read_generic, &spr_write_generic,
1393                  0x00000000);
1394     /* XXX : not implemented */
1395     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1396                  SPR_NOACCESS, SPR_NOACCESS,
1397                  &spr_read_generic, &spr_write_generic,
1398                  0x00000000);
1399     /* XXX : not implemented */
1400     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1401                  SPR_NOACCESS, SPR_NOACCESS,
1402                  &spr_read_generic, &spr_write_generic,
1403                  0x00000000);
1404     /* XXX : not implemented */
1405     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1406                  SPR_NOACCESS, SPR_NOACCESS,
1407                  &spr_read_generic, &spr_write_generic,
1408                  0x00000000);
1409     /* XXX : not implemented */
1410     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1411                  SPR_NOACCESS, SPR_NOACCESS,
1412                  &spr_read_generic, &spr_write_generic,
1413                  0x00000000);
1414     /* XXX : not implemented */
1415     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1416                  SPR_NOACCESS, SPR_NOACCESS,
1417                  &spr_read_generic, &spr_write_generic,
1418                  0x00000000);
1419     /* XXX : not implemented */
1420     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1421                  SPR_NOACCESS, SPR_NOACCESS,
1422                  &spr_read_generic, &spr_write_clear,
1423                  0x00000000);
1424     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1425                  SPR_NOACCESS, SPR_NOACCESS,
1426                  &spr_read_generic, &spr_write_generic,
1427                  0x00000000);
1428     spr_register(env, SPR_BOOKE_ESR, "ESR",
1429                  SPR_NOACCESS, SPR_NOACCESS,
1430                  &spr_read_generic, &spr_write_generic,
1431                  0x00000000);
1432     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1433                  SPR_NOACCESS, SPR_NOACCESS,
1434                  &spr_read_generic, &spr_write_excp_prefix,
1435                  0x00000000);
1436     /* Exception vectors */
1437     for (i = 0; i < 64; i++) {
1438         if (ivor_mask & (1ULL << i)) {
1439             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1440                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1441                 exit(1);
1442             }
1443             spr_register(env, ivor_sprn[i], ivor_names[i],
1444                          SPR_NOACCESS, SPR_NOACCESS,
1445                          &spr_read_generic, &spr_write_excp_vector,
1446                          0x00000000);
1447         }
1448     }
1449     spr_register(env, SPR_BOOKE_PID, "PID",
1450                  SPR_NOACCESS, SPR_NOACCESS,
1451                  &spr_read_generic, &spr_write_generic,
1452                  0x00000000);
1453     spr_register(env, SPR_BOOKE_TCR, "TCR",
1454                  SPR_NOACCESS, SPR_NOACCESS,
1455                  &spr_read_generic, &spr_write_booke_tcr,
1456                  0x00000000);
1457     spr_register(env, SPR_BOOKE_TSR, "TSR",
1458                  SPR_NOACCESS, SPR_NOACCESS,
1459                  &spr_read_generic, &spr_write_booke_tsr,
1460                  0x00000000);
1461     /* Timer */
1462     spr_register(env, SPR_DECR, "DECR",
1463                  SPR_NOACCESS, SPR_NOACCESS,
1464                  &spr_read_decr, &spr_write_decr,
1465                  0x00000000);
1466     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1467                  SPR_NOACCESS, SPR_NOACCESS,
1468                  SPR_NOACCESS, &spr_write_generic,
1469                  0x00000000);
1470     /* SPRGs */
1471     spr_register(env, SPR_USPRG0, "USPRG0",
1472                  &spr_read_generic, &spr_write_generic,
1473                  &spr_read_generic, &spr_write_generic,
1474                  0x00000000);
1475     spr_register(env, SPR_SPRG4, "SPRG4",
1476                  SPR_NOACCESS, SPR_NOACCESS,
1477                  &spr_read_generic, &spr_write_generic,
1478                  0x00000000);
1479     spr_register(env, SPR_SPRG5, "SPRG5",
1480                  SPR_NOACCESS, SPR_NOACCESS,
1481                  &spr_read_generic, &spr_write_generic,
1482                  0x00000000);
1483     spr_register(env, SPR_SPRG6, "SPRG6",
1484                  SPR_NOACCESS, SPR_NOACCESS,
1485                  &spr_read_generic, &spr_write_generic,
1486                  0x00000000);
1487     spr_register(env, SPR_SPRG7, "SPRG7",
1488                  SPR_NOACCESS, SPR_NOACCESS,
1489                  &spr_read_generic, &spr_write_generic,
1490                  0x00000000);
1491 }
1492
1493 /* FSL storage control registers */
1494 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1495 {
1496 #if !defined(CONFIG_USER_ONLY)
1497     const char *mas_names[8] = {
1498         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1499     };
1500     int mas_sprn[8] = {
1501         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1502         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1503     };
1504     int i;
1505
1506     /* TLB assist registers */
1507     /* XXX : not implemented */
1508     for (i = 0; i < 8; i++) {
1509         if (mas_mask & (1 << i)) {
1510             spr_register(env, mas_sprn[i], mas_names[i],
1511                          SPR_NOACCESS, SPR_NOACCESS,
1512                          &spr_read_generic, &spr_write_generic,
1513                          0x00000000);
1514         }
1515     }
1516     if (env->nb_pids > 1) {
1517         /* XXX : not implemented */
1518         spr_register(env, SPR_BOOKE_PID1, "PID1",
1519                      SPR_NOACCESS, SPR_NOACCESS,
1520                      &spr_read_generic, &spr_write_generic,
1521                      0x00000000);
1522     }
1523     if (env->nb_pids > 2) {
1524         /* XXX : not implemented */
1525         spr_register(env, SPR_BOOKE_PID2, "PID2",
1526                      SPR_NOACCESS, SPR_NOACCESS,
1527                      &spr_read_generic, &spr_write_generic,
1528                      0x00000000);
1529     }
1530     /* XXX : not implemented */
1531     spr_register(env, SPR_MMUCFG, "MMUCFG",
1532                  SPR_NOACCESS, SPR_NOACCESS,
1533                  &spr_read_generic, SPR_NOACCESS,
1534                  0x00000000); /* TOFIX */
1535     /* XXX : not implemented */
1536     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1537                  SPR_NOACCESS, SPR_NOACCESS,
1538                  &spr_read_generic, &spr_write_generic,
1539                  0x00000000); /* TOFIX */
1540     switch (env->nb_ways) {
1541     case 4:
1542         /* XXX : not implemented */
1543         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1544                      SPR_NOACCESS, SPR_NOACCESS,
1545                      &spr_read_generic, SPR_NOACCESS,
1546                      0x00000000); /* TOFIX */
1547         /* Fallthru */
1548     case 3:
1549         /* XXX : not implemented */
1550         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1551                      SPR_NOACCESS, SPR_NOACCESS,
1552                      &spr_read_generic, SPR_NOACCESS,
1553                      0x00000000); /* TOFIX */
1554         /* Fallthru */
1555     case 2:
1556         /* XXX : not implemented */
1557         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1558                      SPR_NOACCESS, SPR_NOACCESS,
1559                      &spr_read_generic, SPR_NOACCESS,
1560                      0x00000000); /* TOFIX */
1561         /* Fallthru */
1562     case 1:
1563         /* XXX : not implemented */
1564         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1565                      SPR_NOACCESS, SPR_NOACCESS,
1566                      &spr_read_generic, SPR_NOACCESS,
1567                      0x00000000); /* TOFIX */
1568         /* Fallthru */
1569     case 0:
1570     default:
1571         break;
1572     }
1573 #endif
1574 }
1575
1576 /* SPR specific to PowerPC 440 implementation */
1577 static void gen_spr_440 (CPUPPCState *env)
1578 {
1579     /* Cache control */
1580     /* XXX : not implemented */
1581     spr_register(env, SPR_440_DNV0, "DNV0",
1582                  SPR_NOACCESS, SPR_NOACCESS,
1583                  &spr_read_generic, &spr_write_generic,
1584                  0x00000000);
1585     /* XXX : not implemented */
1586     spr_register(env, SPR_440_DNV1, "DNV1",
1587                  SPR_NOACCESS, SPR_NOACCESS,
1588                  &spr_read_generic, &spr_write_generic,
1589                  0x00000000);
1590     /* XXX : not implemented */
1591     spr_register(env, SPR_440_DNV2, "DNV2",
1592                  SPR_NOACCESS, SPR_NOACCESS,
1593                  &spr_read_generic, &spr_write_generic,
1594                  0x00000000);
1595     /* XXX : not implemented */
1596     spr_register(env, SPR_440_DNV3, "DNV3",
1597                  SPR_NOACCESS, SPR_NOACCESS,
1598                  &spr_read_generic, &spr_write_generic,
1599                  0x00000000);
1600     /* XXX : not implemented */
1601     spr_register(env, SPR_440_DTV0, "DTV0",
1602                  SPR_NOACCESS, SPR_NOACCESS,
1603                  &spr_read_generic, &spr_write_generic,
1604                  0x00000000);
1605     /* XXX : not implemented */
1606     spr_register(env, SPR_440_DTV1, "DTV1",
1607                  SPR_NOACCESS, SPR_NOACCESS,
1608                  &spr_read_generic, &spr_write_generic,
1609                  0x00000000);
1610     /* XXX : not implemented */
1611     spr_register(env, SPR_440_DTV2, "DTV2",
1612                  SPR_NOACCESS, SPR_NOACCESS,
1613                  &spr_read_generic, &spr_write_generic,
1614                  0x00000000);
1615     /* XXX : not implemented */
1616     spr_register(env, SPR_440_DTV3, "DTV3",
1617                  SPR_NOACCESS, SPR_NOACCESS,
1618                  &spr_read_generic, &spr_write_generic,
1619                  0x00000000);
1620     /* XXX : not implemented */
1621     spr_register(env, SPR_440_DVLIM, "DVLIM",
1622                  SPR_NOACCESS, SPR_NOACCESS,
1623                  &spr_read_generic, &spr_write_generic,
1624                  0x00000000);
1625     /* XXX : not implemented */
1626     spr_register(env, SPR_440_INV0, "INV0",
1627                  SPR_NOACCESS, SPR_NOACCESS,
1628                  &spr_read_generic, &spr_write_generic,
1629                  0x00000000);
1630     /* XXX : not implemented */
1631     spr_register(env, SPR_440_INV1, "INV1",
1632                  SPR_NOACCESS, SPR_NOACCESS,
1633                  &spr_read_generic, &spr_write_generic,
1634                  0x00000000);
1635     /* XXX : not implemented */
1636     spr_register(env, SPR_440_INV2, "INV2",
1637                  SPR_NOACCESS, SPR_NOACCESS,
1638                  &spr_read_generic, &spr_write_generic,
1639                  0x00000000);
1640     /* XXX : not implemented */
1641     spr_register(env, SPR_440_INV3, "INV3",
1642                  SPR_NOACCESS, SPR_NOACCESS,
1643                  &spr_read_generic, &spr_write_generic,
1644                  0x00000000);
1645     /* XXX : not implemented */
1646     spr_register(env, SPR_440_ITV0, "ITV0",
1647                  SPR_NOACCESS, SPR_NOACCESS,
1648                  &spr_read_generic, &spr_write_generic,
1649                  0x00000000);
1650     /* XXX : not implemented */
1651     spr_register(env, SPR_440_ITV1, "ITV1",
1652                  SPR_NOACCESS, SPR_NOACCESS,
1653                  &spr_read_generic, &spr_write_generic,
1654                  0x00000000);
1655     /* XXX : not implemented */
1656     spr_register(env, SPR_440_ITV2, "ITV2",
1657                  SPR_NOACCESS, SPR_NOACCESS,
1658                  &spr_read_generic, &spr_write_generic,
1659                  0x00000000);
1660     /* XXX : not implemented */
1661     spr_register(env, SPR_440_ITV3, "ITV3",
1662                  SPR_NOACCESS, SPR_NOACCESS,
1663                  &spr_read_generic, &spr_write_generic,
1664                  0x00000000);
1665     /* XXX : not implemented */
1666     spr_register(env, SPR_440_IVLIM, "IVLIM",
1667                  SPR_NOACCESS, SPR_NOACCESS,
1668                  &spr_read_generic, &spr_write_generic,
1669                  0x00000000);
1670     /* Cache debug */
1671     /* XXX : not implemented */
1672     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1673                  SPR_NOACCESS, SPR_NOACCESS,
1674                  &spr_read_generic, SPR_NOACCESS,
1675                  0x00000000);
1676     /* XXX : not implemented */
1677     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1678                  SPR_NOACCESS, SPR_NOACCESS,
1679                  &spr_read_generic, SPR_NOACCESS,
1680                  0x00000000);
1681     /* XXX : not implemented */
1682     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1683                  SPR_NOACCESS, SPR_NOACCESS,
1684                  &spr_read_generic, SPR_NOACCESS,
1685                  0x00000000);
1686     /* XXX : not implemented */
1687     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1688                  SPR_NOACCESS, SPR_NOACCESS,
1689                  &spr_read_generic, SPR_NOACCESS,
1690                  0x00000000);
1691     /* XXX : not implemented */
1692     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1693                  SPR_NOACCESS, SPR_NOACCESS,
1694                  &spr_read_generic, SPR_NOACCESS,
1695                  0x00000000);
1696     /* XXX : not implemented */
1697     spr_register(env, SPR_440_DBDR, "DBDR",
1698                  SPR_NOACCESS, SPR_NOACCESS,
1699                  &spr_read_generic, &spr_write_generic,
1700                  0x00000000);
1701     /* Processor control */
1702     spr_register(env, SPR_4xx_CCR0, "CCR0",
1703                  SPR_NOACCESS, SPR_NOACCESS,
1704                  &spr_read_generic, &spr_write_generic,
1705                  0x00000000);
1706     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1707                  SPR_NOACCESS, SPR_NOACCESS,
1708                  &spr_read_generic, SPR_NOACCESS,
1709                  0x00000000);
1710     /* Storage control */
1711     spr_register(env, SPR_440_MMUCR, "MMUCR",
1712                  SPR_NOACCESS, SPR_NOACCESS,
1713                  &spr_read_generic, &spr_write_generic,
1714                  0x00000000);
1715 }
1716
1717 /* SPR shared between PowerPC 40x implementations */
1718 static void gen_spr_40x (CPUPPCState *env)
1719 {
1720     /* Cache */
1721     /* not emulated, as Qemu do not emulate caches */
1722     spr_register(env, SPR_40x_DCCR, "DCCR",
1723                  SPR_NOACCESS, SPR_NOACCESS,
1724                  &spr_read_generic, &spr_write_generic,
1725                  0x00000000);
1726     /* not emulated, as Qemu do not emulate caches */
1727     spr_register(env, SPR_40x_ICCR, "ICCR",
1728                  SPR_NOACCESS, SPR_NOACCESS,
1729                  &spr_read_generic, &spr_write_generic,
1730                  0x00000000);
1731     /* not emulated, as Qemu do not emulate caches */
1732     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1733                  SPR_NOACCESS, SPR_NOACCESS,
1734                  &spr_read_generic, SPR_NOACCESS,
1735                  0x00000000);
1736     /* Exception */
1737     spr_register(env, SPR_40x_DEAR, "DEAR",
1738                  SPR_NOACCESS, SPR_NOACCESS,
1739                  &spr_read_generic, &spr_write_generic,
1740                  0x00000000);
1741     spr_register(env, SPR_40x_ESR, "ESR",
1742                  SPR_NOACCESS, SPR_NOACCESS,
1743                  &spr_read_generic, &spr_write_generic,
1744                  0x00000000);
1745     spr_register(env, SPR_40x_EVPR, "EVPR",
1746                  SPR_NOACCESS, SPR_NOACCESS,
1747                  &spr_read_generic, &spr_write_excp_prefix,
1748                  0x00000000);
1749     spr_register(env, SPR_40x_SRR2, "SRR2",
1750                  &spr_read_generic, &spr_write_generic,
1751                  &spr_read_generic, &spr_write_generic,
1752                  0x00000000);
1753     spr_register(env, SPR_40x_SRR3, "SRR3",
1754                  &spr_read_generic, &spr_write_generic,
1755                  &spr_read_generic, &spr_write_generic,
1756                  0x00000000);
1757     /* Timers */
1758     spr_register(env, SPR_40x_PIT, "PIT",
1759                  SPR_NOACCESS, SPR_NOACCESS,
1760                  &spr_read_40x_pit, &spr_write_40x_pit,
1761                  0x00000000);
1762     spr_register(env, SPR_40x_TCR, "TCR",
1763                  SPR_NOACCESS, SPR_NOACCESS,
1764                  &spr_read_generic, &spr_write_booke_tcr,
1765                  0x00000000);
1766     spr_register(env, SPR_40x_TSR, "TSR",
1767                  SPR_NOACCESS, SPR_NOACCESS,
1768                  &spr_read_generic, &spr_write_booke_tsr,
1769                  0x00000000);
1770 }
1771
1772 /* SPR specific to PowerPC 405 implementation */
1773 static void gen_spr_405 (CPUPPCState *env)
1774 {
1775     /* MMU */
1776     spr_register(env, SPR_40x_PID, "PID",
1777                  SPR_NOACCESS, SPR_NOACCESS,
1778                  &spr_read_generic, &spr_write_generic,
1779                  0x00000000);
1780     spr_register(env, SPR_4xx_CCR0, "CCR0",
1781                  SPR_NOACCESS, SPR_NOACCESS,
1782                  &spr_read_generic, &spr_write_generic,
1783                  0x00700000);
1784     /* Debug interface */
1785     /* XXX : not implemented */
1786     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1787                  SPR_NOACCESS, SPR_NOACCESS,
1788                  &spr_read_generic, &spr_write_40x_dbcr0,
1789                  0x00000000);
1790     /* XXX : not implemented */
1791     spr_register(env, SPR_405_DBCR1, "DBCR1",
1792                  SPR_NOACCESS, SPR_NOACCESS,
1793                  &spr_read_generic, &spr_write_generic,
1794                  0x00000000);
1795     /* XXX : not implemented */
1796     spr_register(env, SPR_40x_DBSR, "DBSR",
1797                  SPR_NOACCESS, SPR_NOACCESS,
1798                  &spr_read_generic, &spr_write_clear,
1799                  /* Last reset was system reset */
1800                  0x00000300);
1801     /* XXX : not implemented */
1802     spr_register(env, SPR_40x_DAC1, "DAC1",
1803                  SPR_NOACCESS, SPR_NOACCESS,
1804                  &spr_read_generic, &spr_write_generic,
1805                  0x00000000);
1806     spr_register(env, SPR_40x_DAC2, "DAC2",
1807                  SPR_NOACCESS, SPR_NOACCESS,
1808                  &spr_read_generic, &spr_write_generic,
1809                  0x00000000);
1810     /* XXX : not implemented */
1811     spr_register(env, SPR_405_DVC1, "DVC1",
1812                  SPR_NOACCESS, SPR_NOACCESS,
1813                  &spr_read_generic, &spr_write_generic,
1814                  0x00000000);
1815     /* XXX : not implemented */
1816     spr_register(env, SPR_405_DVC2, "DVC2",
1817                  SPR_NOACCESS, SPR_NOACCESS,
1818                  &spr_read_generic, &spr_write_generic,
1819                  0x00000000);
1820     /* XXX : not implemented */
1821     spr_register(env, SPR_40x_IAC1, "IAC1",
1822                  SPR_NOACCESS, SPR_NOACCESS,
1823                  &spr_read_generic, &spr_write_generic,
1824                  0x00000000);
1825     spr_register(env, SPR_40x_IAC2, "IAC2",
1826                  SPR_NOACCESS, SPR_NOACCESS,
1827                  &spr_read_generic, &spr_write_generic,
1828                  0x00000000);
1829     /* XXX : not implemented */
1830     spr_register(env, SPR_405_IAC3, "IAC3",
1831                  SPR_NOACCESS, SPR_NOACCESS,
1832                  &spr_read_generic, &spr_write_generic,
1833                  0x00000000);
1834     /* XXX : not implemented */
1835     spr_register(env, SPR_405_IAC4, "IAC4",
1836                  SPR_NOACCESS, SPR_NOACCESS,
1837                  &spr_read_generic, &spr_write_generic,
1838                  0x00000000);
1839     /* Storage control */
1840     /* XXX: TODO: not implemented */
1841     spr_register(env, SPR_405_SLER, "SLER",
1842                  SPR_NOACCESS, SPR_NOACCESS,
1843                  &spr_read_generic, &spr_write_40x_sler,
1844                  0x00000000);
1845     spr_register(env, SPR_40x_ZPR, "ZPR",
1846                  SPR_NOACCESS, SPR_NOACCESS,
1847                  &spr_read_generic, &spr_write_generic,
1848                  0x00000000);
1849     /* XXX : not implemented */
1850     spr_register(env, SPR_405_SU0R, "SU0R",
1851                  SPR_NOACCESS, SPR_NOACCESS,
1852                  &spr_read_generic, &spr_write_generic,
1853                  0x00000000);
1854     /* SPRG */
1855     spr_register(env, SPR_USPRG0, "USPRG0",
1856                  &spr_read_ureg, SPR_NOACCESS,
1857                  &spr_read_ureg, SPR_NOACCESS,
1858                  0x00000000);
1859     spr_register(env, SPR_SPRG4, "SPRG4",
1860                  SPR_NOACCESS, SPR_NOACCESS,
1861                  &spr_read_generic, &spr_write_generic,
1862                  0x00000000);
1863     spr_register(env, SPR_SPRG5, "SPRG5",
1864                  SPR_NOACCESS, SPR_NOACCESS,
1865                  spr_read_generic, &spr_write_generic,
1866                  0x00000000);
1867     spr_register(env, SPR_SPRG6, "SPRG6",
1868                  SPR_NOACCESS, SPR_NOACCESS,
1869                  spr_read_generic, &spr_write_generic,
1870                  0x00000000);
1871     spr_register(env, SPR_SPRG7, "SPRG7",
1872                  SPR_NOACCESS, SPR_NOACCESS,
1873                  spr_read_generic, &spr_write_generic,
1874                  0x00000000);
1875     gen_spr_usprgh(env);
1876 }
1877
1878 /* SPR shared between PowerPC 401 & 403 implementations */
1879 static void gen_spr_401_403 (CPUPPCState *env)
1880 {
1881     /* Time base */
1882     spr_register(env, SPR_403_VTBL,  "TBL",
1883                  &spr_read_tbl, SPR_NOACCESS,
1884                  &spr_read_tbl, SPR_NOACCESS,
1885                  0x00000000);
1886     spr_register(env, SPR_403_TBL,   "TBL",
1887                  SPR_NOACCESS, SPR_NOACCESS,
1888                  SPR_NOACCESS, &spr_write_tbl,
1889                  0x00000000);
1890     spr_register(env, SPR_403_VTBU,  "TBU",
1891                  &spr_read_tbu, SPR_NOACCESS,
1892                  &spr_read_tbu, SPR_NOACCESS,
1893                  0x00000000);
1894     spr_register(env, SPR_403_TBU,   "TBU",
1895                  SPR_NOACCESS, SPR_NOACCESS,
1896                  SPR_NOACCESS, &spr_write_tbu,
1897                  0x00000000);
1898     /* Debug */
1899     /* not emulated, as Qemu do not emulate caches */
1900     spr_register(env, SPR_403_CDBCR, "CDBCR",
1901                  SPR_NOACCESS, SPR_NOACCESS,
1902                  &spr_read_generic, &spr_write_generic,
1903                  0x00000000);
1904 }
1905
1906 /* SPR specific to PowerPC 401 implementation */
1907 static void gen_spr_401 (CPUPPCState *env)
1908 {
1909     /* Debug interface */
1910     /* XXX : not implemented */
1911     spr_register(env, SPR_40x_DBCR0, "DBCR",
1912                  SPR_NOACCESS, SPR_NOACCESS,
1913                  &spr_read_generic, &spr_write_40x_dbcr0,
1914                  0x00000000);
1915     /* XXX : not implemented */
1916     spr_register(env, SPR_40x_DBSR, "DBSR",
1917                  SPR_NOACCESS, SPR_NOACCESS,
1918                  &spr_read_generic, &spr_write_clear,
1919                  /* Last reset was system reset */
1920                  0x00000300);
1921     /* XXX : not implemented */
1922     spr_register(env, SPR_40x_DAC1, "DAC",
1923                  SPR_NOACCESS, SPR_NOACCESS,
1924                  &spr_read_generic, &spr_write_generic,
1925                  0x00000000);
1926     /* XXX : not implemented */
1927     spr_register(env, SPR_40x_IAC1, "IAC",
1928                  SPR_NOACCESS, SPR_NOACCESS,
1929                  &spr_read_generic, &spr_write_generic,
1930                  0x00000000);
1931     /* Storage control */
1932     /* XXX: TODO: not implemented */
1933     spr_register(env, SPR_405_SLER, "SLER",
1934                  SPR_NOACCESS, SPR_NOACCESS,
1935                  &spr_read_generic, &spr_write_40x_sler,
1936                  0x00000000);
1937     /* not emulated, as Qemu never does speculative access */
1938     spr_register(env, SPR_40x_SGR, "SGR",
1939                  SPR_NOACCESS, SPR_NOACCESS,
1940                  &spr_read_generic, &spr_write_generic,
1941                  0xFFFFFFFF);
1942     /* not emulated, as Qemu do not emulate caches */
1943     spr_register(env, SPR_40x_DCWR, "DCWR",
1944                  SPR_NOACCESS, SPR_NOACCESS,
1945                  &spr_read_generic, &spr_write_generic,
1946                  0x00000000);
1947 }
1948
1949 static void gen_spr_401x2 (CPUPPCState *env)
1950 {
1951     gen_spr_401(env);
1952     spr_register(env, SPR_40x_PID, "PID",
1953                  SPR_NOACCESS, SPR_NOACCESS,
1954                  &spr_read_generic, &spr_write_generic,
1955                  0x00000000);
1956     spr_register(env, SPR_40x_ZPR, "ZPR",
1957                  SPR_NOACCESS, SPR_NOACCESS,
1958                  &spr_read_generic, &spr_write_generic,
1959                  0x00000000);
1960 }
1961
1962 /* SPR specific to PowerPC 403 implementation */
1963 static void gen_spr_403 (CPUPPCState *env)
1964 {
1965     /* Debug interface */
1966     /* XXX : not implemented */
1967     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1968                  SPR_NOACCESS, SPR_NOACCESS,
1969                  &spr_read_generic, &spr_write_40x_dbcr0,
1970                  0x00000000);
1971     /* XXX : not implemented */
1972     spr_register(env, SPR_40x_DBSR, "DBSR",
1973                  SPR_NOACCESS, SPR_NOACCESS,
1974                  &spr_read_generic, &spr_write_clear,
1975                  /* Last reset was system reset */
1976                  0x00000300);
1977     /* XXX : not implemented */
1978     spr_register(env, SPR_40x_DAC1, "DAC1",
1979                  SPR_NOACCESS, SPR_NOACCESS,
1980                  &spr_read_generic, &spr_write_generic,
1981                  0x00000000);
1982     /* XXX : not implemented */
1983     spr_register(env, SPR_40x_DAC2, "DAC2",
1984                  SPR_NOACCESS, SPR_NOACCESS,
1985                  &spr_read_generic, &spr_write_generic,
1986                  0x00000000);
1987     /* XXX : not implemented */
1988     spr_register(env, SPR_40x_IAC1, "IAC1",
1989                  SPR_NOACCESS, SPR_NOACCESS,
1990                  &spr_read_generic, &spr_write_generic,
1991                  0x00000000);
1992     /* XXX : not implemented */
1993     spr_register(env, SPR_40x_IAC2, "IAC2",
1994                  SPR_NOACCESS, SPR_NOACCESS,
1995                  &spr_read_generic, &spr_write_generic,
1996                  0x00000000);
1997 }
1998
1999 static void gen_spr_403_real (CPUPPCState *env)
2000 {
2001     spr_register(env, SPR_403_PBL1,  "PBL1",
2002                  SPR_NOACCESS, SPR_NOACCESS,
2003                  &spr_read_403_pbr, &spr_write_403_pbr,
2004                  0x00000000);
2005     spr_register(env, SPR_403_PBU1,  "PBU1",
2006                  SPR_NOACCESS, SPR_NOACCESS,
2007                  &spr_read_403_pbr, &spr_write_403_pbr,
2008                  0x00000000);
2009     spr_register(env, SPR_403_PBL2,  "PBL2",
2010                  SPR_NOACCESS, SPR_NOACCESS,
2011                  &spr_read_403_pbr, &spr_write_403_pbr,
2012                  0x00000000);
2013     spr_register(env, SPR_403_PBU2,  "PBU2",
2014                  SPR_NOACCESS, SPR_NOACCESS,
2015                  &spr_read_403_pbr, &spr_write_403_pbr,
2016                  0x00000000);
2017 }
2018
2019 static void gen_spr_403_mmu (CPUPPCState *env)
2020 {
2021     /* MMU */
2022     spr_register(env, SPR_40x_PID, "PID",
2023                  SPR_NOACCESS, SPR_NOACCESS,
2024                  &spr_read_generic, &spr_write_generic,
2025                  0x00000000);
2026     spr_register(env, SPR_40x_ZPR, "ZPR",
2027                  SPR_NOACCESS, SPR_NOACCESS,
2028                  &spr_read_generic, &spr_write_generic,
2029                  0x00000000);
2030 }
2031
2032 /* SPR specific to PowerPC compression coprocessor extension */
2033 static void gen_spr_compress (CPUPPCState *env)
2034 {
2035     /* XXX : not implemented */
2036     spr_register(env, SPR_401_SKR, "SKR",
2037                  SPR_NOACCESS, SPR_NOACCESS,
2038                  &spr_read_generic, &spr_write_generic,
2039                  0x00000000);
2040 }
2041
2042 #if defined (TARGET_PPC64)
2043 /* SPR specific to PowerPC 620 */
2044 static void gen_spr_620 (CPUPPCState *env)
2045 {
2046     /* Processor identification */
2047     spr_register(env, SPR_PIR, "PIR",
2048                  SPR_NOACCESS, SPR_NOACCESS,
2049                  &spr_read_generic, &spr_write_pir,
2050                  0x00000000);
2051     spr_register(env, SPR_ASR, "ASR",
2052                  SPR_NOACCESS, SPR_NOACCESS,
2053                  &spr_read_asr, &spr_write_asr,
2054                  0x00000000);
2055     /* Breakpoints */
2056     /* XXX : not implemented */
2057     spr_register(env, SPR_IABR, "IABR",
2058                  SPR_NOACCESS, SPR_NOACCESS,
2059                  &spr_read_generic, &spr_write_generic,
2060                  0x00000000);
2061     /* XXX : not implemented */
2062     spr_register(env, SPR_DABR, "DABR",
2063                  SPR_NOACCESS, SPR_NOACCESS,
2064                  &spr_read_generic, &spr_write_generic,
2065                  0x00000000);
2066     /* XXX : not implemented */
2067     spr_register(env, SPR_SIAR, "SIAR",
2068                  SPR_NOACCESS, SPR_NOACCESS,
2069                  &spr_read_generic, SPR_NOACCESS,
2070                  0x00000000);
2071     /* XXX : not implemented */
2072     spr_register(env, SPR_SDA, "SDA",
2073                  SPR_NOACCESS, SPR_NOACCESS,
2074                  &spr_read_generic, SPR_NOACCESS,
2075                  0x00000000);
2076     /* XXX : not implemented */
2077     spr_register(env, SPR_620_PMC1R, "PMC1",
2078                  SPR_NOACCESS, SPR_NOACCESS,
2079                  &spr_read_generic, SPR_NOACCESS,
2080                  0x00000000);
2081     spr_register(env, SPR_620_PMC1W, "PMC1",
2082                  SPR_NOACCESS, SPR_NOACCESS,
2083                   SPR_NOACCESS, &spr_write_generic,
2084                  0x00000000);
2085     /* XXX : not implemented */
2086     spr_register(env, SPR_620_PMC2R, "PMC2",
2087                  SPR_NOACCESS, SPR_NOACCESS,
2088                  &spr_read_generic, SPR_NOACCESS,
2089                  0x00000000);
2090     spr_register(env, SPR_620_PMC2W, "PMC2",
2091                  SPR_NOACCESS, SPR_NOACCESS,
2092                   SPR_NOACCESS, &spr_write_generic,
2093                  0x00000000);
2094     /* XXX : not implemented */
2095     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2096                  SPR_NOACCESS, SPR_NOACCESS,
2097                  &spr_read_generic, SPR_NOACCESS,
2098                  0x00000000);
2099     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2100                  SPR_NOACCESS, SPR_NOACCESS,
2101                   SPR_NOACCESS, &spr_write_generic,
2102                  0x00000000);
2103     /* External access control */
2104     /* XXX : not implemented */
2105     spr_register(env, SPR_EAR, "EAR",
2106                  SPR_NOACCESS, SPR_NOACCESS,
2107                  &spr_read_generic, &spr_write_generic,
2108                  0x00000000);
2109 #if 0 // XXX: check this
2110     /* XXX : not implemented */
2111     spr_register(env, SPR_620_PMR0, "PMR0",
2112                  SPR_NOACCESS, SPR_NOACCESS,
2113                  &spr_read_generic, &spr_write_generic,
2114                  0x00000000);
2115     /* XXX : not implemented */
2116     spr_register(env, SPR_620_PMR1, "PMR1",
2117                  SPR_NOACCESS, SPR_NOACCESS,
2118                  &spr_read_generic, &spr_write_generic,
2119                  0x00000000);
2120     /* XXX : not implemented */
2121     spr_register(env, SPR_620_PMR2, "PMR2",
2122                  SPR_NOACCESS, SPR_NOACCESS,
2123                  &spr_read_generic, &spr_write_generic,
2124                  0x00000000);
2125     /* XXX : not implemented */
2126     spr_register(env, SPR_620_PMR3, "PMR3",
2127                  SPR_NOACCESS, SPR_NOACCESS,
2128                  &spr_read_generic, &spr_write_generic,
2129                  0x00000000);
2130     /* XXX : not implemented */
2131     spr_register(env, SPR_620_PMR4, "PMR4",
2132                  SPR_NOACCESS, SPR_NOACCESS,
2133                  &spr_read_generic, &spr_write_generic,
2134                  0x00000000);
2135     /* XXX : not implemented */
2136     spr_register(env, SPR_620_PMR5, "PMR5",
2137                  SPR_NOACCESS, SPR_NOACCESS,
2138                  &spr_read_generic, &spr_write_generic,
2139                  0x00000000);
2140     /* XXX : not implemented */
2141     spr_register(env, SPR_620_PMR6, "PMR6",
2142                  SPR_NOACCESS, SPR_NOACCESS,
2143                  &spr_read_generic, &spr_write_generic,
2144                  0x00000000);
2145     /* XXX : not implemented */
2146     spr_register(env, SPR_620_PMR7, "PMR7",
2147                  SPR_NOACCESS, SPR_NOACCESS,
2148                  &spr_read_generic, &spr_write_generic,
2149                  0x00000000);
2150     /* XXX : not implemented */
2151     spr_register(env, SPR_620_PMR8, "PMR8",
2152                  SPR_NOACCESS, SPR_NOACCESS,
2153                  &spr_read_generic, &spr_write_generic,
2154                  0x00000000);
2155     /* XXX : not implemented */
2156     spr_register(env, SPR_620_PMR9, "PMR9",
2157                  SPR_NOACCESS, SPR_NOACCESS,
2158                  &spr_read_generic, &spr_write_generic,
2159                  0x00000000);
2160     /* XXX : not implemented */
2161     spr_register(env, SPR_620_PMRA, "PMR10",
2162                  SPR_NOACCESS, SPR_NOACCESS,
2163                  &spr_read_generic, &spr_write_generic,
2164                  0x00000000);
2165     /* XXX : not implemented */
2166     spr_register(env, SPR_620_PMRB, "PMR11",
2167                  SPR_NOACCESS, SPR_NOACCESS,
2168                  &spr_read_generic, &spr_write_generic,
2169                  0x00000000);
2170     /* XXX : not implemented */
2171     spr_register(env, SPR_620_PMRC, "PMR12",
2172                  SPR_NOACCESS, SPR_NOACCESS,
2173                  &spr_read_generic, &spr_write_generic,
2174                  0x00000000);
2175     /* XXX : not implemented */
2176     spr_register(env, SPR_620_PMRD, "PMR13",
2177                  SPR_NOACCESS, SPR_NOACCESS,
2178                  &spr_read_generic, &spr_write_generic,
2179                  0x00000000);
2180     /* XXX : not implemented */
2181     spr_register(env, SPR_620_PMRE, "PMR14",
2182                  SPR_NOACCESS, SPR_NOACCESS,
2183                  &spr_read_generic, &spr_write_generic,
2184                  0x00000000);
2185     /* XXX : not implemented */
2186     spr_register(env, SPR_620_PMRF, "PMR15",
2187                  SPR_NOACCESS, SPR_NOACCESS,
2188                  &spr_read_generic, &spr_write_generic,
2189                  0x00000000);
2190 #endif
2191     /* XXX : not implemented */
2192     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2193                  SPR_NOACCESS, SPR_NOACCESS,
2194                  &spr_read_generic, &spr_write_generic,
2195                  0x00000000);
2196     /* XXX : not implemented */
2197     spr_register(env, SPR_620_L2CR, "L2CR",
2198                  SPR_NOACCESS, SPR_NOACCESS,
2199                  &spr_read_generic, &spr_write_generic,
2200                  0x00000000);
2201     /* XXX : not implemented */
2202     spr_register(env, SPR_620_L2SR, "L2SR",
2203                  SPR_NOACCESS, SPR_NOACCESS,
2204                  &spr_read_generic, &spr_write_generic,
2205                  0x00000000);
2206 }
2207 #endif /* defined (TARGET_PPC64) */
2208
2209 static void gen_spr_5xx_8xx (CPUPPCState *env)
2210 {
2211     /* Exception processing */
2212     spr_register(env, SPR_DSISR, "DSISR",
2213                  SPR_NOACCESS, SPR_NOACCESS,
2214                  &spr_read_generic, &spr_write_generic,
2215                  0x00000000);
2216     spr_register(env, SPR_DAR, "DAR",
2217                  SPR_NOACCESS, SPR_NOACCESS,
2218                  &spr_read_generic, &spr_write_generic,
2219                  0x00000000);
2220     /* Timer */
2221     spr_register(env, SPR_DECR, "DECR",
2222                  SPR_NOACCESS, SPR_NOACCESS,
2223                  &spr_read_decr, &spr_write_decr,
2224                  0x00000000);
2225     /* XXX : not implemented */
2226     spr_register(env, SPR_MPC_EIE, "EIE",
2227                  SPR_NOACCESS, SPR_NOACCESS,
2228                  &spr_read_generic, &spr_write_generic,
2229                  0x00000000);
2230     /* XXX : not implemented */
2231     spr_register(env, SPR_MPC_EID, "EID",
2232                  SPR_NOACCESS, SPR_NOACCESS,
2233                  &spr_read_generic, &spr_write_generic,
2234                  0x00000000);
2235     /* XXX : not implemented */
2236     spr_register(env, SPR_MPC_NRI, "NRI",
2237                  SPR_NOACCESS, SPR_NOACCESS,
2238                  &spr_read_generic, &spr_write_generic,
2239                  0x00000000);
2240     /* XXX : not implemented */
2241     spr_register(env, SPR_MPC_CMPA, "CMPA",
2242                  SPR_NOACCESS, SPR_NOACCESS,
2243                  &spr_read_generic, &spr_write_generic,
2244                  0x00000000);
2245     /* XXX : not implemented */
2246     spr_register(env, SPR_MPC_CMPB, "CMPB",
2247                  SPR_NOACCESS, SPR_NOACCESS,
2248                  &spr_read_generic, &spr_write_generic,
2249                  0x00000000);
2250     /* XXX : not implemented */
2251     spr_register(env, SPR_MPC_CMPC, "CMPC",
2252                  SPR_NOACCESS, SPR_NOACCESS,
2253                  &spr_read_generic, &spr_write_generic,
2254                  0x00000000);
2255     /* XXX : not implemented */
2256     spr_register(env, SPR_MPC_CMPD, "CMPD",
2257                  SPR_NOACCESS, SPR_NOACCESS,
2258                  &spr_read_generic, &spr_write_generic,
2259                  0x00000000);
2260     /* XXX : not implemented */
2261     spr_register(env, SPR_MPC_ECR, "ECR",
2262                  SPR_NOACCESS, SPR_NOACCESS,
2263                  &spr_read_generic, &spr_write_generic,
2264                  0x00000000);
2265     /* XXX : not implemented */
2266     spr_register(env, SPR_MPC_DER, "DER",
2267                  SPR_NOACCESS, SPR_NOACCESS,
2268                  &spr_read_generic, &spr_write_generic,
2269                  0x00000000);
2270     /* XXX : not implemented */
2271     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2272                  SPR_NOACCESS, SPR_NOACCESS,
2273                  &spr_read_generic, &spr_write_generic,
2274                  0x00000000);
2275     /* XXX : not implemented */
2276     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2277                  SPR_NOACCESS, SPR_NOACCESS,
2278                  &spr_read_generic, &spr_write_generic,
2279                  0x00000000);
2280     /* XXX : not implemented */
2281     spr_register(env, SPR_MPC_CMPE, "CMPE",
2282                  SPR_NOACCESS, SPR_NOACCESS,
2283                  &spr_read_generic, &spr_write_generic,
2284                  0x00000000);
2285     /* XXX : not implemented */
2286     spr_register(env, SPR_MPC_CMPF, "CMPF",
2287                  SPR_NOACCESS, SPR_NOACCESS,
2288                  &spr_read_generic, &spr_write_generic,
2289                  0x00000000);
2290     /* XXX : not implemented */
2291     spr_register(env, SPR_MPC_CMPG, "CMPG",
2292                  SPR_NOACCESS, SPR_NOACCESS,
2293                  &spr_read_generic, &spr_write_generic,
2294                  0x00000000);
2295     /* XXX : not implemented */
2296     spr_register(env, SPR_MPC_CMPH, "CMPH",
2297                  SPR_NOACCESS, SPR_NOACCESS,
2298                  &spr_read_generic, &spr_write_generic,
2299                  0x00000000);
2300     /* XXX : not implemented */
2301     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2302                  SPR_NOACCESS, SPR_NOACCESS,
2303                  &spr_read_generic, &spr_write_generic,
2304                  0x00000000);
2305     /* XXX : not implemented */
2306     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2307                  SPR_NOACCESS, SPR_NOACCESS,
2308                  &spr_read_generic, &spr_write_generic,
2309                  0x00000000);
2310     /* XXX : not implemented */
2311     spr_register(env, SPR_MPC_BAR, "BAR",
2312                  SPR_NOACCESS, SPR_NOACCESS,
2313                  &spr_read_generic, &spr_write_generic,
2314                  0x00000000);
2315     /* XXX : not implemented */
2316     spr_register(env, SPR_MPC_DPDR, "DPDR",
2317                  SPR_NOACCESS, SPR_NOACCESS,
2318                  &spr_read_generic, &spr_write_generic,
2319                  0x00000000);
2320     /* XXX : not implemented */
2321     spr_register(env, SPR_MPC_IMMR, "IMMR",
2322                  SPR_NOACCESS, SPR_NOACCESS,
2323                  &spr_read_generic, &spr_write_generic,
2324                  0x00000000);
2325 }
2326
2327 static void gen_spr_5xx (CPUPPCState *env)
2328 {
2329     /* XXX : not implemented */
2330     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2331                  SPR_NOACCESS, SPR_NOACCESS,
2332                  &spr_read_generic, &spr_write_generic,
2333                  0x00000000);
2334     /* XXX : not implemented */
2335     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2336                  SPR_NOACCESS, SPR_NOACCESS,
2337                  &spr_read_generic, &spr_write_generic,
2338                  0x00000000);
2339     /* XXX : not implemented */
2340     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2341                  SPR_NOACCESS, SPR_NOACCESS,
2342                  &spr_read_generic, &spr_write_generic,
2343                  0x00000000);
2344     /* XXX : not implemented */
2345     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2346                  SPR_NOACCESS, SPR_NOACCESS,
2347                  &spr_read_generic, &spr_write_generic,
2348                  0x00000000);
2349     /* XXX : not implemented */
2350     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2351                  SPR_NOACCESS, SPR_NOACCESS,
2352                  &spr_read_generic, &spr_write_generic,
2353                  0x00000000);
2354     /* XXX : not implemented */
2355     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2356                  SPR_NOACCESS, SPR_NOACCESS,
2357                  &spr_read_generic, &spr_write_generic,
2358                  0x00000000);
2359     /* XXX : not implemented */
2360     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2361                  SPR_NOACCESS, SPR_NOACCESS,
2362                  &spr_read_generic, &spr_write_generic,
2363                  0x00000000);
2364     /* XXX : not implemented */
2365     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2366                  SPR_NOACCESS, SPR_NOACCESS,
2367                  &spr_read_generic, &spr_write_generic,
2368                  0x00000000);
2369     /* XXX : not implemented */
2370     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2371                  SPR_NOACCESS, SPR_NOACCESS,
2372                  &spr_read_generic, &spr_write_generic,
2373                  0x00000000);
2374     /* XXX : not implemented */
2375     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2376                  SPR_NOACCESS, SPR_NOACCESS,
2377                  &spr_read_generic, &spr_write_generic,
2378                  0x00000000);
2379     /* XXX : not implemented */
2380     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2381                  SPR_NOACCESS, SPR_NOACCESS,
2382                  &spr_read_generic, &spr_write_generic,
2383                  0x00000000);
2384     /* XXX : not implemented */
2385     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2386                  SPR_NOACCESS, SPR_NOACCESS,
2387                  &spr_read_generic, &spr_write_generic,
2388                  0x00000000);
2389     /* XXX : not implemented */
2390     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2391                  SPR_NOACCESS, SPR_NOACCESS,
2392                  &spr_read_generic, &spr_write_generic,
2393                  0x00000000);
2394     /* XXX : not implemented */
2395     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2396                  SPR_NOACCESS, SPR_NOACCESS,
2397                  &spr_read_generic, &spr_write_generic,
2398                  0x00000000);
2399     /* XXX : not implemented */
2400     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2401                  SPR_NOACCESS, SPR_NOACCESS,
2402                  &spr_read_generic, &spr_write_generic,
2403                  0x00000000);
2404     /* XXX : not implemented */
2405     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2406                  SPR_NOACCESS, SPR_NOACCESS,
2407                  &spr_read_generic, &spr_write_generic,
2408                  0x00000000);
2409     /* XXX : not implemented */
2410     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2411                  SPR_NOACCESS, SPR_NOACCESS,
2412                  &spr_read_generic, &spr_write_generic,
2413                  0x00000000);
2414     /* XXX : not implemented */
2415     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2416                  SPR_NOACCESS, SPR_NOACCESS,
2417                  &spr_read_generic, &spr_write_generic,
2418                  0x00000000);
2419     /* XXX : not implemented */
2420     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2421                  SPR_NOACCESS, SPR_NOACCESS,
2422                  &spr_read_generic, &spr_write_generic,
2423                  0x00000000);
2424     /* XXX : not implemented */
2425     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2426                  SPR_NOACCESS, SPR_NOACCESS,
2427                  &spr_read_generic, &spr_write_generic,
2428                  0x00000000);
2429     /* XXX : not implemented */
2430     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2431                  SPR_NOACCESS, SPR_NOACCESS,
2432                  &spr_read_generic, &spr_write_generic,
2433                  0x00000000);
2434 }
2435
2436 static void gen_spr_8xx (CPUPPCState *env)
2437 {
2438     /* XXX : not implemented */
2439     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2440                  SPR_NOACCESS, SPR_NOACCESS,
2441                  &spr_read_generic, &spr_write_generic,
2442                  0x00000000);
2443     /* XXX : not implemented */
2444     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2445                  SPR_NOACCESS, SPR_NOACCESS,
2446                  &spr_read_generic, &spr_write_generic,
2447                  0x00000000);
2448     /* XXX : not implemented */
2449     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2450                  SPR_NOACCESS, SPR_NOACCESS,
2451                  &spr_read_generic, &spr_write_generic,
2452                  0x00000000);
2453     /* XXX : not implemented */
2454     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2455                  SPR_NOACCESS, SPR_NOACCESS,
2456                  &spr_read_generic, &spr_write_generic,
2457                  0x00000000);
2458     /* XXX : not implemented */
2459     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2460                  SPR_NOACCESS, SPR_NOACCESS,
2461                  &spr_read_generic, &spr_write_generic,
2462                  0x00000000);
2463     /* XXX : not implemented */
2464     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2465                  SPR_NOACCESS, SPR_NOACCESS,
2466                  &spr_read_generic, &spr_write_generic,
2467                  0x00000000);
2468     /* XXX : not implemented */
2469     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2470                  SPR_NOACCESS, SPR_NOACCESS,
2471                  &spr_read_generic, &spr_write_generic,
2472                  0x00000000);
2473     /* XXX : not implemented */
2474     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2475                  SPR_NOACCESS, SPR_NOACCESS,
2476                  &spr_read_generic, &spr_write_generic,
2477                  0x00000000);
2478     /* XXX : not implemented */
2479     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2480                  SPR_NOACCESS, SPR_NOACCESS,
2481                  &spr_read_generic, &spr_write_generic,
2482                  0x00000000);
2483     /* XXX : not implemented */
2484     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2485                  SPR_NOACCESS, SPR_NOACCESS,
2486                  &spr_read_generic, &spr_write_generic,
2487                  0x00000000);
2488     /* XXX : not implemented */
2489     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2490                  SPR_NOACCESS, SPR_NOACCESS,
2491                  &spr_read_generic, &spr_write_generic,
2492                  0x00000000);
2493     /* XXX : not implemented */
2494     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2495                  SPR_NOACCESS, SPR_NOACCESS,
2496                  &spr_read_generic, &spr_write_generic,
2497                  0x00000000);
2498     /* XXX : not implemented */
2499     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2500                  SPR_NOACCESS, SPR_NOACCESS,
2501                  &spr_read_generic, &spr_write_generic,
2502                  0x00000000);
2503     /* XXX : not implemented */
2504     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2505                  SPR_NOACCESS, SPR_NOACCESS,
2506                  &spr_read_generic, &spr_write_generic,
2507                  0x00000000);
2508     /* XXX : not implemented */
2509     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2510                  SPR_NOACCESS, SPR_NOACCESS,
2511                  &spr_read_generic, &spr_write_generic,
2512                  0x00000000);
2513     /* XXX : not implemented */
2514     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2515                  SPR_NOACCESS, SPR_NOACCESS,
2516                  &spr_read_generic, &spr_write_generic,
2517                  0x00000000);
2518     /* XXX : not implemented */
2519     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2520                  SPR_NOACCESS, SPR_NOACCESS,
2521                  &spr_read_generic, &spr_write_generic,
2522                  0x00000000);
2523     /* XXX : not implemented */
2524     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2525                  SPR_NOACCESS, SPR_NOACCESS,
2526                  &spr_read_generic, &spr_write_generic,
2527                  0x00000000);
2528     /* XXX : not implemented */
2529     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2530                  SPR_NOACCESS, SPR_NOACCESS,
2531                  &spr_read_generic, &spr_write_generic,
2532                  0x00000000);
2533     /* XXX : not implemented */
2534     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2535                  SPR_NOACCESS, SPR_NOACCESS,
2536                  &spr_read_generic, &spr_write_generic,
2537                  0x00000000);
2538     /* XXX : not implemented */
2539     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2540                  SPR_NOACCESS, SPR_NOACCESS,
2541                  &spr_read_generic, &spr_write_generic,
2542                  0x00000000);
2543     /* XXX : not implemented */
2544     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2545                  SPR_NOACCESS, SPR_NOACCESS,
2546                  &spr_read_generic, &spr_write_generic,
2547                  0x00000000);
2548     /* XXX : not implemented */
2549     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2550                  SPR_NOACCESS, SPR_NOACCESS,
2551                  &spr_read_generic, &spr_write_generic,
2552                  0x00000000);
2553     /* XXX : not implemented */
2554     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2555                  SPR_NOACCESS, SPR_NOACCESS,
2556                  &spr_read_generic, &spr_write_generic,
2557                  0x00000000);
2558     /* XXX : not implemented */
2559     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2560                  SPR_NOACCESS, SPR_NOACCESS,
2561                  &spr_read_generic, &spr_write_generic,
2562                  0x00000000);
2563 }
2564
2565 // XXX: TODO
2566 /*
2567  * AMR     => SPR 29 (Power 2.04)
2568  * CTRL    => SPR 136 (Power 2.04)
2569  * CTRL    => SPR 152 (Power 2.04)
2570  * SCOMC   => SPR 276 (64 bits ?)
2571  * SCOMD   => SPR 277 (64 bits ?)
2572  * TBU40   => SPR 286 (Power 2.04 hypv)
2573  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2574  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2575  * HDSISR  => SPR 306 (Power 2.04 hypv)
2576  * HDAR    => SPR 307 (Power 2.04 hypv)
2577  * PURR    => SPR 309 (Power 2.04 hypv)
2578  * HDEC    => SPR 310 (Power 2.04 hypv)
2579  * HIOR    => SPR 311 (hypv)
2580  * RMOR    => SPR 312 (970)
2581  * HRMOR   => SPR 313 (Power 2.04 hypv)
2582  * HSRR0   => SPR 314 (Power 2.04 hypv)
2583  * HSRR1   => SPR 315 (Power 2.04 hypv)
2584  * LPCR    => SPR 316 (970)
2585  * LPIDR   => SPR 317 (970)
2586  * EPR     => SPR 702 (Power 2.04 emb)
2587  * perf    => 768-783 (Power 2.04)
2588  * perf    => 784-799 (Power 2.04)
2589  * PPR     => SPR 896 (Power 2.04)
2590  * EPLC    => SPR 947 (Power 2.04 emb)
2591  * EPSC    => SPR 948 (Power 2.04 emb)
2592  * DABRX   => 1015    (Power 2.04 hypv)
2593  * FPECR   => SPR 1022 (?)
2594  * ... and more (thermal management, performance counters, ...)
2595  */
2596
2597 /*****************************************************************************/
2598 /* Exception vectors models                                                  */
2599 static void init_excp_4xx_real (CPUPPCState *env)
2600 {
2601 #if !defined(CONFIG_USER_ONLY)
2602     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2603     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2604     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2605     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2606     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2607     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2608     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2609     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2610     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2611     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2612     env->hreset_excp_prefix = 0x00000000UL;
2613     env->ivor_mask = 0x0000FFF0UL;
2614     env->ivpr_mask = 0xFFFF0000UL;
2615     /* Hardware reset vector */
2616     env->hreset_vector = 0xFFFFFFFCUL;
2617 #endif
2618 }
2619
2620 static void init_excp_4xx_softmmu (CPUPPCState *env)
2621 {
2622 #if !defined(CONFIG_USER_ONLY)
2623     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2624     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2625     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2626     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2627     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2628     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2629     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2630     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2631     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2632     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2633     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2634     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2635     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2636     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2637     env->hreset_excp_prefix = 0x00000000UL;
2638     env->ivor_mask = 0x0000FFF0UL;
2639     env->ivpr_mask = 0xFFFF0000UL;
2640     /* Hardware reset vector */
2641     env->hreset_vector = 0xFFFFFFFCUL;
2642 #endif
2643 }
2644
2645 static void init_excp_MPC5xx (CPUPPCState *env)
2646 {
2647 #if !defined(CONFIG_USER_ONLY)
2648     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2649     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2650     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2651     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2652     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2653     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2654     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2655     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2656     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2657     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2658     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2659     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2660     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2661     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2662     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2663     env->hreset_excp_prefix = 0x00000000UL;
2664     env->ivor_mask = 0x0000FFF0UL;
2665     env->ivpr_mask = 0xFFFF0000UL;
2666     /* Hardware reset vector */
2667     env->hreset_vector = 0xFFFFFFFCUL;
2668 #endif
2669 }
2670
2671 static void init_excp_MPC8xx (CPUPPCState *env)
2672 {
2673 #if !defined(CONFIG_USER_ONLY)
2674     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2675     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2676     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2677     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2678     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2679     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2680     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2681     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2682     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2683     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2684     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2685     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2686     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2687     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2688     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2689     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2690     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2691     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2692     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2693     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2694     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2695     env->hreset_excp_prefix = 0x00000000UL;
2696     env->ivor_mask = 0x0000FFF0UL;
2697     env->ivpr_mask = 0xFFFF0000UL;
2698     /* Hardware reset vector */
2699     env->hreset_vector = 0xFFFFFFFCUL;
2700 #endif
2701 }
2702
2703 static void init_excp_G2 (CPUPPCState *env)
2704 {
2705 #if !defined(CONFIG_USER_ONLY)
2706     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2707     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2708     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2709     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2710     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2711     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2712     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2713     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2714     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2715     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2716     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2717     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2718     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2719     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2720     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2721     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2722     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2723     env->hreset_excp_prefix = 0x00000000UL;
2724     /* Hardware reset vector */
2725     env->hreset_vector = 0xFFFFFFFCUL;
2726 #endif
2727 }
2728
2729 static void init_excp_e200 (CPUPPCState *env)
2730 {
2731 #if !defined(CONFIG_USER_ONLY)
2732     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2733     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2734     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2735     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2736     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2737     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2738     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2739     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2740     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2741     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2742     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2743     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2744     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2745     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2746     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2747     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2748     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2749     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2750     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2751     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2752     env->hreset_excp_prefix = 0x00000000UL;
2753     env->ivor_mask = 0x0000FFF7UL;
2754     env->ivpr_mask = 0xFFFF0000UL;
2755     /* Hardware reset vector */
2756     env->hreset_vector = 0xFFFFFFFCUL;
2757 #endif
2758 }
2759
2760 static void init_excp_BookE (CPUPPCState *env)
2761 {
2762 #if !defined(CONFIG_USER_ONLY)
2763     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2764     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2765     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2766     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2767     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2768     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2769     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2770     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2771     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2772     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2773     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2774     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2775     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2776     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2777     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2778     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2779     env->hreset_excp_prefix = 0x00000000UL;
2780     env->ivor_mask = 0x0000FFE0UL;
2781     env->ivpr_mask = 0xFFFF0000UL;
2782     /* Hardware reset vector */
2783     env->hreset_vector = 0xFFFFFFFCUL;
2784 #endif
2785 }
2786
2787 static void init_excp_601 (CPUPPCState *env)
2788 {
2789 #if !defined(CONFIG_USER_ONLY)
2790     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2791     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2792     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2793     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2794     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2795     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2796     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2797     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2798     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2799     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2800     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2801     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2802     env->hreset_excp_prefix = 0xFFF00000UL;
2803     /* Hardware reset vector */
2804     env->hreset_vector = 0x00000100UL;
2805 #endif
2806 }
2807
2808 static void init_excp_602 (CPUPPCState *env)
2809 {
2810 #if !defined(CONFIG_USER_ONLY)
2811     /* XXX: exception prefix has a special behavior on 602 */
2812     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2813     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2814     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2815     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2816     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2817     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2818     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2819     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2820     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2821     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2822     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2823     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2824     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2825     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2826     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2827     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2828     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2829     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2830     env->hreset_excp_prefix = 0xFFF00000UL;
2831     /* Hardware reset vector */
2832     env->hreset_vector = 0xFFFFFFFCUL;
2833 #endif
2834 }
2835
2836 static void init_excp_603 (CPUPPCState *env)
2837 {
2838 #if !defined(CONFIG_USER_ONLY)
2839     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2840     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2841     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2842     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2843     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2844     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2845     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2846     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2847     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2848     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2849     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2850     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2851     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2852     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2853     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2854     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2855     env->hreset_excp_prefix = 0x00000000UL;
2856     /* Hardware reset vector */
2857     env->hreset_vector = 0xFFFFFFFCUL;
2858 #endif
2859 }
2860
2861 static void init_excp_604 (CPUPPCState *env)
2862 {
2863 #if !defined(CONFIG_USER_ONLY)
2864     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2865     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2866     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2867     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2868     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2869     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2870     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2871     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2872     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2873     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2874     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2875     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2876     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2877     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2878     env->hreset_excp_prefix = 0xFFF00000UL;
2879     /* Hardware reset vector */
2880     env->hreset_vector = 0x00000100UL;
2881 #endif
2882 }
2883
2884 #if defined(TARGET_PPC64)
2885 static void init_excp_620 (CPUPPCState *env)
2886 {
2887 #if !defined(CONFIG_USER_ONLY)
2888     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2889     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2890     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2891     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2892     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2893     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2894     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2895     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2896     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2897     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2898     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2899     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2900     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2901     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2902     env->hreset_excp_prefix = 0xFFF00000UL;
2903     /* Hardware reset vector */
2904     env->hreset_vector = 0x0000000000000100ULL;
2905 #endif
2906 }
2907 #endif /* defined(TARGET_PPC64) */
2908
2909 static void init_excp_7x0 (CPUPPCState *env)
2910 {
2911 #if !defined(CONFIG_USER_ONLY)
2912     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2913     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2914     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2915     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2916     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2917     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2918     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2919     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2920     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2921     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2922     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2923     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2924     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2925     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2926     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2927     env->hreset_excp_prefix = 0x00000000UL;
2928     /* Hardware reset vector */
2929     env->hreset_vector = 0xFFFFFFFCUL;
2930 #endif
2931 }
2932
2933 static void init_excp_750cl (CPUPPCState *env)
2934 {
2935 #if !defined(CONFIG_USER_ONLY)
2936     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2937     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2938     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2939     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2940     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2941     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2942     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2943     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2944     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2945     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2946     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2947     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2948     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2949     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2950     env->hreset_excp_prefix = 0x00000000UL;
2951     /* Hardware reset vector */
2952     env->hreset_vector = 0xFFFFFFFCUL;
2953 #endif
2954 }
2955
2956 static void init_excp_750cx (CPUPPCState *env)
2957 {
2958 #if !defined(CONFIG_USER_ONLY)
2959     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2960     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2961     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2962     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2963     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2964     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2965     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2966     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2967     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2968     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2969     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2970     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2971     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2972     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2973     env->hreset_excp_prefix = 0x00000000UL;
2974     /* Hardware reset vector */
2975     env->hreset_vector = 0xFFFFFFFCUL;
2976 #endif
2977 }
2978
2979 /* XXX: Check if this is correct */
2980 static void init_excp_7x5 (CPUPPCState *env)
2981 {
2982 #if !defined(CONFIG_USER_ONLY)
2983     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2984     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2985     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2986     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2987     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2988     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2989     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2990     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2991     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2992     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2993     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2994     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2995     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2996     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2997     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2998     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2999     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3000     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3001     env->hreset_excp_prefix = 0x00000000UL;
3002     /* Hardware reset vector */
3003     env->hreset_vector = 0xFFFFFFFCUL;
3004 #endif
3005 }
3006
3007 static void init_excp_7400 (CPUPPCState *env)
3008 {
3009 #if !defined(CONFIG_USER_ONLY)
3010     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3011     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3012     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3013     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3014     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3015     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3016     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3017     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3018     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3019     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3020     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3021     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3022     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3023     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3024     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3025     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3026     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3027     env->hreset_excp_prefix = 0x00000000UL;
3028     /* Hardware reset vector */
3029     env->hreset_vector = 0xFFFFFFFCUL;
3030 #endif
3031 }
3032
3033 static void init_excp_7450 (CPUPPCState *env)
3034 {
3035 #if !defined(CONFIG_USER_ONLY)
3036     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3037     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3038     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3039     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3040     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3041     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3042     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3043     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3044     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3045     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3046     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3047     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3048     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3049     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3050     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3051     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3052     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3053     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3054     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3055     env->hreset_excp_prefix = 0x00000000UL;
3056     /* Hardware reset vector */
3057     env->hreset_vector = 0xFFFFFFFCUL;
3058 #endif
3059 }
3060
3061 #if defined (TARGET_PPC64)
3062 static void init_excp_970 (CPUPPCState *env)
3063 {
3064 #if !defined(CONFIG_USER_ONLY)
3065     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3066     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3067     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3068     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3069     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3070     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3071     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3072     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3073     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3074     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3075     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3076     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3077     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3078     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3079     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3080     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3081     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3082     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3083     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3084     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3085     env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3086     /* Hardware reset vector */
3087     env->hreset_vector = 0x0000000000000100ULL;
3088 #endif
3089 }
3090 #endif
3091
3092 /*****************************************************************************/
3093 /* Power management enable checks                                            */
3094 static int check_pow_none (CPUPPCState *env)
3095 {
3096     return 0;
3097 }
3098
3099 static int check_pow_nocheck (CPUPPCState *env)
3100 {
3101     return 1;
3102 }
3103
3104 static int check_pow_hid0 (CPUPPCState *env)
3105 {
3106     if (env->spr[SPR_HID0] & 0x00E00000)
3107         return 1;
3108
3109     return 0;
3110 }
3111
3112 static int check_pow_hid0_74xx (CPUPPCState *env)
3113 {
3114     if (env->spr[SPR_HID0] & 0x00600000)
3115         return 1;
3116
3117     return 0;
3118 }
3119
3120 /*****************************************************************************/
3121 /* PowerPC implementations definitions                                       */
3122
3123 /* PowerPC 401                                                               */
3124 #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3125                               PPC_WRTEE | PPC_DCR |                           \
3126                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3127                               PPC_CACHE_DCBZ |                                \
3128                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3129                               PPC_4xx_COMMON | PPC_40x_EXCP)
3130 #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3131 #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3132 #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3133 #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3134 #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3135 #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3136                               POWERPC_FLAG_BUS_CLK)
3137 #define check_pow_401        check_pow_nocheck
3138
3139 static void init_proc_401 (CPUPPCState *env)
3140 {
3141     gen_spr_40x(env);
3142     gen_spr_401_403(env);
3143     gen_spr_401(env);
3144     init_excp_4xx_real(env);
3145     env->dcache_line_size = 32;
3146     env->icache_line_size = 32;
3147     /* Allocate hardware IRQ controller */
3148     ppc40x_irq_init(env);
3149 }
3150
3151 /* PowerPC 401x2                                                             */
3152 #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3153                               PPC_DCR | PPC_WRTEE |                           \
3154                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3155                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3156                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3157                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3158                               PPC_4xx_COMMON | PPC_40x_EXCP)
3159 #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3160 #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3161 #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3162 #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3163 #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3164 #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3165                               POWERPC_FLAG_BUS_CLK)
3166 #define check_pow_401x2      check_pow_nocheck
3167
3168 static void init_proc_401x2 (CPUPPCState *env)
3169 {
3170     gen_spr_40x(env);
3171     gen_spr_401_403(env);
3172     gen_spr_401x2(env);
3173     gen_spr_compress(env);
3174     /* Memory management */
3175 #if !defined(CONFIG_USER_ONLY)
3176     env->nb_tlb = 64;
3177     env->nb_ways = 1;
3178     env->id_tlbs = 0;
3179 #endif
3180     init_excp_4xx_softmmu(env);
3181     env->dcache_line_size = 32;
3182     env->icache_line_size = 32;
3183     /* Allocate hardware IRQ controller */
3184     ppc40x_irq_init(env);
3185 }
3186
3187 /* PowerPC 401x3                                                             */
3188 #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3189                               PPC_DCR | PPC_WRTEE |                           \
3190                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3191                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3192                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3193                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3194                               PPC_4xx_COMMON | PPC_40x_EXCP)
3195 #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3196 #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3197 #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3198 #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3199 #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3200 #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3201                               POWERPC_FLAG_BUS_CLK)
3202 #define check_pow_401x3      check_pow_nocheck
3203
3204 __attribute__ (( unused ))
3205 static void init_proc_401x3 (CPUPPCState *env)
3206 {
3207     gen_spr_40x(env);
3208     gen_spr_401_403(env);
3209     gen_spr_401(env);
3210     gen_spr_401x2(env);
3211     gen_spr_compress(env);
3212     init_excp_4xx_softmmu(env);
3213     env->dcache_line_size = 32;
3214     env->icache_line_size = 32;
3215     /* Allocate hardware IRQ controller */
3216     ppc40x_irq_init(env);
3217 }
3218
3219 /* IOP480                                                                    */
3220 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3221                               PPC_DCR | PPC_WRTEE |                           \
3222                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3223                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3224                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3225                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3226                               PPC_4xx_COMMON | PPC_40x_EXCP)
3227 #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3228 #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3229 #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3230 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3231 #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3232 #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3233                               POWERPC_FLAG_BUS_CLK)
3234 #define check_pow_IOP480     check_pow_nocheck
3235
3236 static void init_proc_IOP480 (CPUPPCState *env)
3237 {
3238     gen_spr_40x(env);
3239     gen_spr_401_403(env);
3240     gen_spr_401x2(env);
3241     gen_spr_compress(env);
3242     /* Memory management */
3243 #if !defined(CONFIG_USER_ONLY)
3244     env->nb_tlb = 64;
3245     env->nb_ways = 1;
3246     env->id_tlbs = 0;
3247 #endif
3248     init_excp_4xx_softmmu(env);
3249     env->dcache_line_size = 32;
3250     env->icache_line_size = 32;
3251     /* Allocate hardware IRQ controller */
3252     ppc40x_irq_init(env);
3253 }
3254
3255 /* PowerPC 403                                                               */
3256 #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3257                               PPC_DCR | PPC_WRTEE |                           \
3258                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3259                               PPC_CACHE_DCBZ |                                \
3260                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3261                               PPC_4xx_COMMON | PPC_40x_EXCP)
3262 #define POWERPC_MSRM_403     (0x000000000007D00DULL)
3263 #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3264 #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3265 #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3266 #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3267 #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3268                               POWERPC_FLAG_BUS_CLK)
3269 #define check_pow_403        check_pow_nocheck
3270
3271 static void init_proc_403 (CPUPPCState *env)
3272 {
3273     gen_spr_40x(env);
3274     gen_spr_401_403(env);
3275     gen_spr_403(env);
3276     gen_spr_403_real(env);
3277     init_excp_4xx_real(env);
3278     env->dcache_line_size = 32;
3279     env->icache_line_size = 32;
3280     /* Allocate hardware IRQ controller */
3281     ppc40x_irq_init(env);
3282 }
3283
3284 /* PowerPC 403 GCX                                                           */
3285 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3286                               PPC_DCR | PPC_WRTEE |                           \
3287                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3288                               PPC_CACHE_DCBZ |                                \
3289                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3290                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3291                               PPC_4xx_COMMON | PPC_40x_EXCP)
3292 #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3293 #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3294 #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3295 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3296 #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3297 #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3298                               POWERPC_FLAG_BUS_CLK)
3299 #define check_pow_403GCX     check_pow_nocheck
3300
3301 static void init_proc_403GCX (CPUPPCState *env)
3302 {
3303     gen_spr_40x(env);
3304     gen_spr_401_403(env);
3305     gen_spr_403(env);
3306     gen_spr_403_real(env);
3307     gen_spr_403_mmu(env);
3308     /* Bus access control */
3309     /* not emulated, as Qemu never does speculative access */
3310     spr_register(env, SPR_40x_SGR, "SGR",
3311                  SPR_NOACCESS, SPR_NOACCESS,
3312                  &spr_read_generic, &spr_write_generic,
3313                  0xFFFFFFFF);
3314     /* not emulated, as Qemu do not emulate caches */
3315     spr_register(env, SPR_40x_DCWR, "DCWR",
3316                  SPR_NOACCESS, SPR_NOACCESS,
3317                  &spr_read_generic, &spr_write_generic,
3318                  0x00000000);
3319     /* Memory management */
3320 #if !defined(CONFIG_USER_ONLY)
3321     env->nb_tlb = 64;
3322     env->nb_ways = 1;
3323     env->id_tlbs = 0;
3324 #endif
3325     init_excp_4xx_softmmu(env);
3326     env->dcache_line_size = 32;
3327     env->icache_line_size = 32;
3328     /* Allocate hardware IRQ controller */
3329     ppc40x_irq_init(env);
3330 }
3331
3332 /* PowerPC 405                                                               */
3333 #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3334                               PPC_DCR | PPC_WRTEE |                           \
3335                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3336                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3337                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3338                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3339                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3340 #define POWERPC_MSRM_405     (0x000000000006E630ULL)
3341 #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3342 #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3343 #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3344 #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3345 #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3346                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3347 #define check_pow_405        check_pow_nocheck
3348
3349 static void init_proc_405 (CPUPPCState *env)
3350 {
3351     /* Time base */
3352     gen_tbl(env);
3353     gen_spr_40x(env);
3354     gen_spr_405(env);
3355     /* Bus access control */
3356     /* not emulated, as Qemu never does speculative access */
3357     spr_register(env, SPR_40x_SGR, "SGR",
3358                  SPR_NOACCESS, SPR_NOACCESS,
3359                  &spr_read_generic, &spr_write_generic,
3360                  0xFFFFFFFF);
3361     /* not emulated, as Qemu do not emulate caches */
3362     spr_register(env, SPR_40x_DCWR, "DCWR",
3363                  SPR_NOACCESS, SPR_NOACCESS,
3364                  &spr_read_generic, &spr_write_generic,
3365                  0x00000000);
3366     /* Memory management */
3367 #if !defined(CONFIG_USER_ONLY)
3368     env->nb_tlb = 64;
3369     env->nb_ways = 1;
3370     env->id_tlbs = 0;
3371 #endif
3372     init_excp_4xx_softmmu(env);
3373     env->dcache_line_size = 32;
3374     env->icache_line_size = 32;
3375     /* Allocate hardware IRQ controller */
3376     ppc40x_irq_init(env);
3377 }
3378
3379 /* PowerPC 440 EP                                                            */
3380 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3381                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3382                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3383                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3384                               PPC_MEM_TLBSYNC |                               \
3385                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3386                               PPC_440_SPEC)
3387 #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3388 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3389 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3390 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3391 #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3392 #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3393                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3394 #define check_pow_440EP      check_pow_nocheck
3395
3396 __attribute__ (( unused ))
3397 static void init_proc_440EP (CPUPPCState *env)
3398 {
3399     /* Time base */
3400     gen_tbl(env);
3401     gen_spr_BookE(env, 0x000000000000FFFFULL);
3402     gen_spr_440(env);
3403     gen_spr_usprgh(env);
3404     /* Processor identification */
3405     spr_register(env, SPR_BOOKE_PIR, "PIR",
3406                  SPR_NOACCESS, SPR_NOACCESS,
3407                  &spr_read_generic, &spr_write_pir,
3408                  0x00000000);
3409     /* XXX : not implemented */
3410     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3411                  SPR_NOACCESS, SPR_NOACCESS,
3412                  &spr_read_generic, &spr_write_generic,
3413                  0x00000000);
3414     /* XXX : not implemented */
3415     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3416                  SPR_NOACCESS, SPR_NOACCESS,
3417                  &spr_read_generic, &spr_write_generic,
3418                  0x00000000);
3419     /* XXX : not implemented */
3420     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3421                  SPR_NOACCESS, SPR_NOACCESS,
3422                  &spr_read_generic, &spr_write_generic,
3423                  0x00000000);
3424     /* XXX : not implemented */
3425     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3426                  SPR_NOACCESS, SPR_NOACCESS,
3427                  &spr_read_generic, &spr_write_generic,
3428                  0x00000000);
3429     /* XXX : not implemented */
3430     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3431                  SPR_NOACCESS, SPR_NOACCESS,
3432                  &spr_read_generic, &spr_write_generic,
3433                  0x00000000);
3434     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3435                  SPR_NOACCESS, SPR_NOACCESS,
3436                  &spr_read_generic, &spr_write_generic,
3437                  0x00000000);
3438     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3439                  SPR_NOACCESS, SPR_NOACCESS,
3440                  &spr_read_generic, &spr_write_generic,
3441                  0x00000000);
3442     /* XXX : not implemented */
3443     spr_register(env, SPR_440_CCR1, "CCR1",
3444                  SPR_NOACCESS, SPR_NOACCESS,
3445                  &spr_read_generic, &spr_write_generic,
3446                  0x00000000);
3447     /* Memory management */
3448 #if !defined(CONFIG_USER_ONLY)
3449     env->nb_tlb = 64;
3450     env->nb_ways = 1;
3451     env->id_tlbs = 0;
3452 #endif
3453     init_excp_BookE(env);
3454     env->dcache_line_size = 32;
3455     env->icache_line_size = 32;
3456     /* XXX: TODO: allocate internal IRQ controller */
3457 }
3458
3459 /* PowerPC 440 GP                                                            */
3460 #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3461                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3462                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3463                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3464                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3465                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3466                               PPC_440_SPEC)
3467 #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3468 #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3469 #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3470 #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3471 #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3472 #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3473                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3474 #define check_pow_440GP      check_pow_nocheck
3475
3476 __attribute__ (( unused ))
3477 static void init_proc_440GP (CPUPPCState *env)
3478 {
3479     /* Time base */
3480     gen_tbl(env);
3481     gen_spr_BookE(env, 0x000000000000FFFFULL);
3482     gen_spr_440(env);
3483     gen_spr_usprgh(env);
3484     /* Processor identification */
3485     spr_register(env, SPR_BOOKE_PIR, "PIR",
3486                  SPR_NOACCESS, SPR_NOACCESS,
3487                  &spr_read_generic, &spr_write_pir,
3488                  0x00000000);
3489     /* XXX : not implemented */
3490     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3491                  SPR_NOACCESS, SPR_NOACCESS,
3492                  &spr_read_generic, &spr_write_generic,
3493                  0x00000000);
3494     /* XXX : not implemented */
3495     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3496                  SPR_NOACCESS, SPR_NOACCESS,
3497                  &spr_read_generic, &spr_write_generic,
3498                  0x00000000);
3499     /* XXX : not implemented */
3500     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3501                  SPR_NOACCESS, SPR_NOACCESS,
3502                  &spr_read_generic, &spr_write_generic,
3503                  0x00000000);
3504     /* XXX : not implemented */
3505     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3506                  SPR_NOACCESS, SPR_NOACCESS,
3507                  &spr_read_generic, &spr_write_generic,
3508                  0x00000000);
3509     /* Memory management */
3510 #if !defined(CONFIG_USER_ONLY)
3511     env->nb_tlb = 64;
3512     env->nb_ways = 1;
3513     env->id_tlbs = 0;
3514 #endif
3515     init_excp_BookE(env);
3516     env->dcache_line_size = 32;
3517     env->icache_line_size = 32;
3518     /* XXX: TODO: allocate internal IRQ controller */
3519 }
3520
3521 /* PowerPC 440x4                                                             */
3522 #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3523                               PPC_DCR | PPC_WRTEE |                           \
3524                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3525                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3526                               PPC_MEM_TLBSYNC |                               \
3527                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3528                               PPC_440_SPEC)
3529 #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3530 #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3531 #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3532 #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3533 #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3534 #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3535                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3536 #define check_pow_440x4      check_pow_nocheck
3537
3538 __attribute__ (( unused ))
3539 static void init_proc_440x4 (CPUPPCState *env)
3540 {
3541     /* Time base */
3542     gen_tbl(env);
3543     gen_spr_BookE(env, 0x000000000000FFFFULL);
3544     gen_spr_440(env);
3545     gen_spr_usprgh(env);
3546     /* Processor identification */
3547     spr_register(env, SPR_BOOKE_PIR, "PIR",
3548                  SPR_NOACCESS, SPR_NOACCESS,
3549                  &spr_read_generic, &spr_write_pir,
3550                  0x00000000);
3551     /* XXX : not implemented */
3552     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3553                  SPR_NOACCESS, SPR_NOACCESS,
3554                  &spr_read_generic, &spr_write_generic,
3555                  0x00000000);
3556     /* XXX : not implemented */
3557     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3558                  SPR_NOACCESS, SPR_NOACCESS,
3559                  &spr_read_generic, &spr_write_generic,
3560                  0x00000000);
3561     /* XXX : not implemented */
3562     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3563                  SPR_NOACCESS, SPR_NOACCESS,
3564                  &spr_read_generic, &spr_write_generic,
3565                  0x00000000);
3566     /* XXX : not implemented */
3567     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3568                  SPR_NOACCESS, SPR_NOACCESS,
3569                  &spr_read_generic, &spr_write_generic,
3570                  0x00000000);
3571     /* Memory management */
3572 #if !defined(CONFIG_USER_ONLY)
3573     env->nb_tlb = 64;
3574     env->nb_ways = 1;
3575     env->id_tlbs = 0;
3576 #endif
3577     init_excp_BookE(env);
3578     env->dcache_line_size = 32;
3579     env->icache_line_size = 32;
3580     /* XXX: TODO: allocate internal IRQ controller */
3581 }
3582
3583 /* PowerPC 440x5                                                             */
3584 #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3585                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3586                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3587                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3588                               PPC_MEM_TLBSYNC |                               \
3589                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3590                               PPC_440_SPEC)
3591 #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3592 #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3593 #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3594 #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3595 #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3596 #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3597                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3598 #define check_pow_440x5      check_pow_nocheck
3599
3600 __attribute__ (( unused ))
3601 static void init_proc_440x5 (CPUPPCState *env)
3602 {
3603     /* Time base */
3604     gen_tbl(env);
3605     gen_spr_BookE(env, 0x000000000000FFFFULL);
3606     gen_spr_440(env);
3607     gen_spr_usprgh(env);
3608     /* Processor identification */
3609     spr_register(env, SPR_BOOKE_PIR, "PIR",
3610                  SPR_NOACCESS, SPR_NOACCESS,
3611                  &spr_read_generic, &spr_write_pir,
3612                  0x00000000);
3613     /* XXX : not implemented */
3614     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3615                  SPR_NOACCESS, SPR_NOACCESS,
3616                  &spr_read_generic, &spr_write_generic,
3617                  0x00000000);
3618     /* XXX : not implemented */
3619     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3620                  SPR_NOACCESS, SPR_NOACCESS,
3621                  &spr_read_generic, &spr_write_generic,
3622                  0x00000000);
3623     /* XXX : not implemented */
3624     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3625                  SPR_NOACCESS, SPR_NOACCESS,
3626                  &spr_read_generic, &spr_write_generic,
3627                  0x00000000);
3628     /* XXX : not implemented */
3629     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3630                  SPR_NOACCESS, SPR_NOACCESS,
3631                  &spr_read_generic, &spr_write_generic,
3632                  0x00000000);
3633     /* XXX : not implemented */
3634     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3635                  SPR_NOACCESS, SPR_NOACCESS,
3636                  &spr_read_generic, &spr_write_generic,
3637                  0x00000000);
3638     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3639                  SPR_NOACCESS, SPR_NOACCESS,
3640                  &spr_read_generic, &spr_write_generic,
3641                  0x00000000);
3642     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3643                  SPR_NOACCESS, SPR_NOACCESS,
3644                  &spr_read_generic, &spr_write_generic,
3645                  0x00000000);
3646     /* XXX : not implemented */
3647     spr_register(env, SPR_440_CCR1, "CCR1",
3648                  SPR_NOACCESS, SPR_NOACCESS,
3649                  &spr_read_generic, &spr_write_generic,
3650                  0x00000000);
3651     /* Memory management */
3652 #if !defined(CONFIG_USER_ONLY)
3653     env->nb_tlb = 64;
3654     env->nb_ways = 1;
3655     env->id_tlbs = 0;
3656 #endif
3657     init_excp_BookE(env);
3658     env->dcache_line_size = 32;
3659     env->icache_line_size = 32;
3660     /* XXX: TODO: allocate internal IRQ controller */
3661 }
3662
3663 /* PowerPC 460 (guessed)                                                     */
3664 #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3665                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3666                               PPC_WRTEE | PPC_MFAPIDI |                       \
3667                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3668                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3669                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3670                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3671                               PPC_440_SPEC)
3672 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3673 #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3674 #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3675 #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3676 #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3677 #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3678                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3679 #define check_pow_460        check_pow_nocheck
3680
3681 __attribute__ (( unused ))
3682 static void init_proc_460 (CPUPPCState *env)
3683 {
3684     /* Time base */
3685     gen_tbl(env);
3686     gen_spr_BookE(env, 0x000000000000FFFFULL);
3687     gen_spr_440(env);
3688     gen_spr_usprgh(env);
3689     /* Processor identification */
3690     spr_register(env, SPR_BOOKE_PIR, "PIR",
3691                  SPR_NOACCESS, SPR_NOACCESS,
3692                  &spr_read_generic, &spr_write_pir,
3693                  0x00000000);
3694     /* XXX : not implemented */
3695     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3696                  SPR_NOACCESS, SPR_NOACCESS,
3697                  &spr_read_generic, &spr_write_generic,
3698                  0x00000000);
3699     /* XXX : not implemented */
3700     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3701                  SPR_NOACCESS, SPR_NOACCESS,
3702                  &spr_read_generic, &spr_write_generic,
3703                  0x00000000);
3704     /* XXX : not implemented */
3705     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3706                  SPR_NOACCESS, SPR_NOACCESS,
3707                  &spr_read_generic, &spr_write_generic,
3708                  0x00000000);
3709     /* XXX : not implemented */
3710     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3711                  SPR_NOACCESS, SPR_NOACCESS,
3712                  &spr_read_generic, &spr_write_generic,
3713                  0x00000000);
3714     /* XXX : not implemented */
3715     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3716                  SPR_NOACCESS, SPR_NOACCESS,
3717                  &spr_read_generic, &spr_write_generic,
3718                  0x00000000);
3719     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3720                  SPR_NOACCESS, SPR_NOACCESS,
3721                  &spr_read_generic, &spr_write_generic,
3722                  0x00000000);
3723     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3724                  SPR_NOACCESS, SPR_NOACCESS,
3725                  &spr_read_generic, &spr_write_generic,
3726                  0x00000000);
3727     /* XXX : not implemented */
3728     spr_register(env, SPR_440_CCR1, "CCR1",
3729                  SPR_NOACCESS, SPR_NOACCESS,
3730                  &spr_read_generic, &spr_write_generic,
3731                  0x00000000);
3732     /* XXX : not implemented */
3733     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3734                  &spr_read_generic, &spr_write_generic,
3735                  &spr_read_generic, &spr_write_generic,
3736                  0x00000000);
3737     /* Memory management */
3738 #if !defined(CONFIG_USER_ONLY)
3739     env->nb_tlb = 64;
3740     env->nb_ways = 1;
3741     env->id_tlbs = 0;
3742 #endif
3743     init_excp_BookE(env);
3744     env->dcache_line_size = 32;
3745     env->icache_line_size = 32;
3746     /* XXX: TODO: allocate internal IRQ controller */
3747 }
3748
3749 /* PowerPC 460F (guessed)                                                    */
3750 #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3751                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3752                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3753                               PPC_FLOAT_STFIWX |                              \
3754                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3755                               PPC_WRTEE | PPC_MFAPIDI |                       \
3756                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3757                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3758                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3759                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3760                               PPC_440_SPEC)
3761 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3762 #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3763 #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3764 #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3765 #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3766 #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3767                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3768 #define check_pow_460F       check_pow_nocheck
3769
3770 __attribute__ (( unused ))
3771 static void init_proc_460F (CPUPPCState *env)
3772 {
3773     /* Time base */
3774     gen_tbl(env);
3775     gen_spr_BookE(env, 0x000000000000FFFFULL);
3776     gen_spr_440(env);
3777     gen_spr_usprgh(env);
3778     /* Processor identification */
3779     spr_register(env, SPR_BOOKE_PIR, "PIR",
3780                  SPR_NOACCESS, SPR_NOACCESS,
3781                  &spr_read_generic, &spr_write_pir,
3782                  0x00000000);
3783     /* XXX : not implemented */
3784     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3785                  SPR_NOACCESS, SPR_NOACCESS,
3786                  &spr_read_generic, &spr_write_generic,
3787                  0x00000000);
3788     /* XXX : not implemented */
3789     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3790                  SPR_NOACCESS, SPR_NOACCESS,
3791                  &spr_read_generic, &spr_write_generic,
3792                  0x00000000);
3793     /* XXX : not implemented */
3794     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3795                  SPR_NOACCESS, SPR_NOACCESS,
3796                  &spr_read_generic, &spr_write_generic,
3797                  0x00000000);
3798     /* XXX : not implemented */
3799     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3800                  SPR_NOACCESS, SPR_NOACCESS,
3801                  &spr_read_generic, &spr_write_generic,
3802                  0x00000000);
3803     /* XXX : not implemented */
3804     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3805                  SPR_NOACCESS, SPR_NOACCESS,
3806                  &spr_read_generic, &spr_write_generic,
3807                  0x00000000);
3808     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3809                  SPR_NOACCESS, SPR_NOACCESS,
3810                  &spr_read_generic, &spr_write_generic,
3811                  0x00000000);
3812     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3813                  SPR_NOACCESS, SPR_NOACCESS,
3814                  &spr_read_generic, &spr_write_generic,
3815                  0x00000000);
3816     /* XXX : not implemented */
3817     spr_register(env, SPR_440_CCR1, "CCR1",
3818                  SPR_NOACCESS, SPR_NOACCESS,
3819                  &spr_read_generic, &spr_write_generic,
3820                  0x00000000);
3821     /* XXX : not implemented */
3822     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3823                  &spr_read_generic, &spr_write_generic,
3824                  &spr_read_generic, &spr_write_generic,
3825                  0x00000000);
3826     /* Memory management */
3827 #if !defined(CONFIG_USER_ONLY)
3828     env->nb_tlb = 64;
3829     env->nb_ways = 1;
3830     env->id_tlbs = 0;
3831 #endif
3832     init_excp_BookE(env);
3833     env->dcache_line_size = 32;
3834     env->icache_line_size = 32;
3835     /* XXX: TODO: allocate internal IRQ controller */
3836 }
3837
3838 /* Freescale 5xx cores (aka RCPU) */
3839 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3840                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3841                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3842                               PPC_MFTB)
3843 #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3844 #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3845 #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3846 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3847 #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3848 #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3849                               POWERPC_FLAG_BUS_CLK)
3850 #define check_pow_MPC5xx     check_pow_none
3851
3852 __attribute__ (( unused ))
3853 static void init_proc_MPC5xx (CPUPPCState *env)
3854 {
3855     /* Time base */
3856     gen_tbl(env);
3857     gen_spr_5xx_8xx(env);
3858     gen_spr_5xx(env);
3859     init_excp_MPC5xx(env);
3860     env->dcache_line_size = 32;
3861     env->icache_line_size = 32;
3862     /* XXX: TODO: allocate internal IRQ controller */
3863 }
3864
3865 /* Freescale 8xx cores (aka PowerQUICC) */
3866 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3867                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3868                               PPC_CACHE_ICBI | PPC_MFTB)
3869 #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3870 #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3871 #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3872 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3873 #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3874 #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3875                               POWERPC_FLAG_BUS_CLK)
3876 #define check_pow_MPC8xx     check_pow_none
3877
3878 __attribute__ (( unused ))
3879 static void init_proc_MPC8xx (CPUPPCState *env)
3880 {
3881     /* Time base */
3882     gen_tbl(env);
3883     gen_spr_5xx_8xx(env);
3884     gen_spr_8xx(env);
3885     init_excp_MPC8xx(env);
3886     env->dcache_line_size = 32;
3887     env->icache_line_size = 32;
3888     /* XXX: TODO: allocate internal IRQ controller */
3889 }
3890
3891 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3892 /* PowerPC G2                                                                */
3893 #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3894                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3895                               PPC_FLOAT_STFIWX |                              \
3896                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3897                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3898                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3899                               PPC_SEGMENT | PPC_EXTERN)
3900 #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3901 #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3902 //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3903 #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3904 #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3905 #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3906                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3907 #define check_pow_G2         check_pow_hid0
3908
3909 static void init_proc_G2 (CPUPPCState *env)
3910 {
3911     gen_spr_ne_601(env);
3912     gen_spr_G2_755(env);
3913     gen_spr_G2(env);
3914     /* Time base */
3915     gen_tbl(env);
3916     /* External access control */
3917     /* XXX : not implemented */
3918     spr_register(env, SPR_EAR, "EAR",
3919                  SPR_NOACCESS, SPR_NOACCESS,
3920                  &spr_read_generic, &spr_write_generic,
3921                  0x00000000);
3922     /* Hardware implementation register */
3923     /* XXX : not implemented */
3924     spr_register(env, SPR_HID0, "HID0",
3925                  SPR_NOACCESS, SPR_NOACCESS,
3926                  &spr_read_generic, &spr_write_generic,
3927                  0x00000000);
3928     /* XXX : not implemented */
3929     spr_register(env, SPR_HID1, "HID1",
3930                  SPR_NOACCESS, SPR_NOACCESS,
3931                  &spr_read_generic, &spr_write_generic,
3932                  0x00000000);
3933     /* XXX : not implemented */
3934     spr_register(env, SPR_HID2, "HID2",
3935                  SPR_NOACCESS, SPR_NOACCESS,
3936                  &spr_read_generic, &spr_write_generic,
3937                  0x00000000);
3938     /* Memory management */
3939     gen_low_BATs(env);
3940     gen_high_BATs(env);
3941     gen_6xx_7xx_soft_tlb(env, 64, 2);
3942     init_excp_G2(env);
3943     env->dcache_line_size = 32;
3944     env->icache_line_size = 32;
3945     /* Allocate hardware IRQ controller */
3946     ppc6xx_irq_init(env);
3947 }
3948
3949 /* PowerPC G2LE                                                              */
3950 #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3951                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3952                               PPC_FLOAT_STFIWX |                              \
3953                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3954                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3955                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3956                               PPC_SEGMENT | PPC_EXTERN)
3957 #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3958 #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3959 #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3960 #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3961 #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3962 #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3963                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3964 #define check_pow_G2LE       check_pow_hid0
3965
3966 static void init_proc_G2LE (CPUPPCState *env)
3967 {
3968     gen_spr_ne_601(env);
3969     gen_spr_G2_755(env);
3970     gen_spr_G2(env);
3971     /* Time base */
3972     gen_tbl(env);
3973     /* External access control */
3974     /* XXX : not implemented */
3975     spr_register(env, SPR_EAR, "EAR",
3976                  SPR_NOACCESS, SPR_NOACCESS,
3977                  &spr_read_generic, &spr_write_generic,
3978                  0x00000000);
3979     /* Hardware implementation register */
3980     /* XXX : not implemented */
3981     spr_register(env, SPR_HID0, "HID0",
3982                  SPR_NOACCESS, SPR_NOACCESS,
3983                  &spr_read_generic, &spr_write_generic,
3984                  0x00000000);
3985     /* XXX : not implemented */
3986     spr_register(env, SPR_HID1, "HID1",
3987                  SPR_NOACCESS, SPR_NOACCESS,
3988                  &spr_read_generic, &spr_write_generic,
3989                  0x00000000);
3990     /* XXX : not implemented */
3991     spr_register(env, SPR_HID2, "HID2",
3992                  SPR_NOACCESS, SPR_NOACCESS,
3993                  &spr_read_generic, &spr_write_generic,
3994                  0x00000000);
3995     /* Memory management */
3996     gen_low_BATs(env);
3997     gen_high_BATs(env);
3998     gen_6xx_7xx_soft_tlb(env, 64, 2);
3999     init_excp_G2(env);
4000     env->dcache_line_size = 32;
4001     env->icache_line_size = 32;
4002     /* Allocate hardware IRQ controller */
4003     ppc6xx_irq_init(env);
4004 }
4005
4006 /* e200 core                                                                 */
4007 /* XXX: unimplemented instructions:
4008  * dcblc
4009  * dcbtlst
4010  * dcbtstls
4011  * icblc
4012  * icbtls
4013  * tlbivax
4014  * all SPE multiply-accumulate instructions
4015  */
4016 #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
4017                               PPC_SPE | PPC_SPE_SINGLE |                      \
4018                               PPC_WRTEE | PPC_RFDI |                          \
4019                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
4020                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
4021                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
4022                               PPC_BOOKE)
4023 #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
4024 #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
4025 #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
4026 #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
4027 #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
4028 #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4029                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4030                               POWERPC_FLAG_BUS_CLK)
4031 #define check_pow_e200       check_pow_hid0
4032
4033 __attribute__ (( unused ))
4034 static void init_proc_e200 (CPUPPCState *env)
4035 {
4036     /* Time base */
4037     gen_tbl(env);
4038     gen_spr_BookE(env, 0x000000070000FFFFULL);
4039     /* XXX : not implemented */
4040     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4041                  &spr_read_spefscr, &spr_write_spefscr,
4042                  &spr_read_spefscr, &spr_write_spefscr,
4043                  0x00000000);
4044     /* Memory management */
4045     gen_spr_BookE_FSL(env, 0x0000005D);
4046     /* XXX : not implemented */
4047     spr_register(env, SPR_HID0, "HID0",
4048                  SPR_NOACCESS, SPR_NOACCESS,
4049                  &spr_read_generic, &spr_write_generic,
4050                  0x00000000);
4051     /* XXX : not implemented */
4052     spr_register(env, SPR_HID1, "HID1",
4053                  SPR_NOACCESS, SPR_NOACCESS,
4054                  &spr_read_generic, &spr_write_generic,
4055                  0x00000000);
4056     /* XXX : not implemented */
4057     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4058                  SPR_NOACCESS, SPR_NOACCESS,
4059                  &spr_read_generic, &spr_write_generic,
4060                  0x00000000);
4061     /* XXX : not implemented */
4062     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4063                  SPR_NOACCESS, SPR_NOACCESS,
4064                  &spr_read_generic, &spr_write_generic,
4065                  0x00000000);
4066     /* XXX : not implemented */
4067     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4068                  SPR_NOACCESS, SPR_NOACCESS,
4069                  &spr_read_generic, &spr_write_generic,
4070                  0x00000000);
4071     /* XXX : not implemented */
4072     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4073                  SPR_NOACCESS, SPR_NOACCESS,
4074                  &spr_read_generic, &spr_write_generic,
4075                  0x00000000);
4076     /* XXX : not implemented */
4077     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4078                  SPR_NOACCESS, SPR_NOACCESS,
4079                  &spr_read_generic, &spr_write_generic,
4080                  0x00000000);
4081     /* XXX : not implemented */
4082     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4083                  SPR_NOACCESS, SPR_NOACCESS,
4084                  &spr_read_generic, &spr_write_generic,
4085                  0x00000000);
4086     /* XXX : not implemented */
4087     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4088                  SPR_NOACCESS, SPR_NOACCESS,
4089                  &spr_read_generic, &spr_write_generic,
4090                  0x00000000);
4091     /* XXX : not implemented */
4092     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4093                  SPR_NOACCESS, SPR_NOACCESS,
4094                  &spr_read_generic, &spr_write_generic,
4095                  0x00000000);
4096     /* XXX : not implemented */
4097     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4098                  SPR_NOACCESS, SPR_NOACCESS,
4099                  &spr_read_generic, &spr_write_generic,
4100                  0x00000000);
4101     /* XXX : not implemented */
4102     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4103                  SPR_NOACCESS, SPR_NOACCESS,
4104                  &spr_read_generic, &spr_write_generic,
4105                  0x00000000);
4106     /* XXX : not implemented */
4107     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4108                  SPR_NOACCESS, SPR_NOACCESS,
4109                  &spr_read_generic, &spr_write_generic,
4110                  0x00000000);
4111     /* XXX : not implemented */
4112     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4113                  SPR_NOACCESS, SPR_NOACCESS,
4114                  &spr_read_generic, &spr_write_generic,
4115                  0x00000000);
4116     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4117                  SPR_NOACCESS, SPR_NOACCESS,
4118                  &spr_read_generic, &spr_write_generic,
4119                  0x00000000);
4120     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4121                  SPR_NOACCESS, SPR_NOACCESS,
4122                  &spr_read_generic, &spr_write_generic,
4123                  0x00000000);
4124 #if !defined(CONFIG_USER_ONLY)
4125     env->nb_tlb = 64;
4126     env->nb_ways = 1;
4127     env->id_tlbs = 0;
4128 #endif
4129     init_excp_e200(env);
4130     env->dcache_line_size = 32;
4131     env->icache_line_size = 32;
4132     /* XXX: TODO: allocate internal IRQ controller */
4133 }
4134
4135 /* e300 core                                                                 */
4136 #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4137                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4138                               PPC_FLOAT_STFIWX |                              \
4139                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4140                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4141                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4142                               PPC_SEGMENT | PPC_EXTERN)
4143 #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4144 #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4145 #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4146 #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4147 #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4148 #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4149                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4150 #define check_pow_e300       check_pow_hid0
4151
4152 __attribute__ (( unused ))
4153 static void init_proc_e300 (CPUPPCState *env)
4154 {
4155     gen_spr_ne_601(env);
4156     gen_spr_603(env);
4157     /* Time base */
4158     gen_tbl(env);
4159     /* hardware implementation registers */
4160     /* XXX : not implemented */
4161     spr_register(env, SPR_HID0, "HID0",
4162                  SPR_NOACCESS, SPR_NOACCESS,
4163                  &spr_read_generic, &spr_write_generic,
4164                  0x00000000);
4165     /* XXX : not implemented */
4166     spr_register(env, SPR_HID1, "HID1",
4167                  SPR_NOACCESS, SPR_NOACCESS,
4168                  &spr_read_generic, &spr_write_generic,
4169                  0x00000000);
4170     /* Memory management */
4171     gen_low_BATs(env);
4172     gen_6xx_7xx_soft_tlb(env, 64, 2);
4173     init_excp_603(env);
4174     env->dcache_line_size = 32;
4175     env->icache_line_size = 32;
4176     /* Allocate hardware IRQ controller */
4177     ppc6xx_irq_init(env);
4178 }
4179
4180 /* e500v1 core                                                               */
4181 #define POWERPC_INSNS_e500v1   (PPC_INSNS_BASE | PPC_ISEL |             \
4182                                 PPC_SPE | PPC_SPE_SINGLE |              \
4183                                 PPC_WRTEE | PPC_RFDI |                  \
4184                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4185                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4186                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4187                                 PPC_BOOKE)
4188 #define POWERPC_MSRM_e500v1    (0x000000000606FF30ULL)
4189 #define POWERPC_MMU_e500v1     (POWERPC_MMU_BOOKE_FSL)
4190 #define POWERPC_EXCP_e500v1    (POWERPC_EXCP_BOOKE)
4191 #define POWERPC_INPUT_e500v1   (PPC_FLAGS_INPUT_BookE)
4192 #define POWERPC_BFDM_e500v1    (bfd_mach_ppc_860)
4193 #define POWERPC_FLAG_e500v1    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4194                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4195                                 POWERPC_FLAG_BUS_CLK)
4196 #define check_pow_e500v1       check_pow_hid0
4197 #define init_proc_e500v1       init_proc_e500
4198
4199 /* e500v2 core                                                               */
4200 #define POWERPC_INSNS_e500v2   (PPC_INSNS_BASE | PPC_ISEL |             \
4201                                 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
4202                                 PPC_WRTEE | PPC_RFDI |                  \
4203                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4204                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4205                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4206                                 PPC_BOOKE)
4207 #define POWERPC_MSRM_e500v2    (0x000000000606FF30ULL)
4208 #define POWERPC_MMU_e500v2     (POWERPC_MMU_BOOKE_FSL)
4209 #define POWERPC_EXCP_e500v2    (POWERPC_EXCP_BOOKE)
4210 #define POWERPC_INPUT_e500v2   (PPC_FLAGS_INPUT_BookE)
4211 #define POWERPC_BFDM_e500v2    (bfd_mach_ppc_860)
4212 #define POWERPC_FLAG_e500v2    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4213                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4214                                 POWERPC_FLAG_BUS_CLK)
4215 #define check_pow_e500v2       check_pow_hid0
4216 #define init_proc_e500v2       init_proc_e500
4217
4218 static void init_proc_e500 (CPUPPCState *env)
4219 {
4220     /* Time base */
4221     gen_tbl(env);
4222     gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4223     /* Processor identification */
4224     spr_register(env, SPR_BOOKE_PIR, "PIR",
4225                  SPR_NOACCESS, SPR_NOACCESS,
4226                  &spr_read_generic, &spr_write_pir,
4227                  0x00000000);
4228     /* XXX : not implemented */
4229     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4230                  &spr_read_spefscr, &spr_write_spefscr,
4231                  &spr_read_spefscr, &spr_write_spefscr,
4232                  0x00000000);
4233     /* Memory management */
4234 #if !defined(CONFIG_USER_ONLY)
4235     env->nb_pids = 3;
4236 #endif
4237     gen_spr_BookE_FSL(env, 0x0000005F);
4238     /* XXX : not implemented */
4239     spr_register(env, SPR_HID0, "HID0",
4240                  SPR_NOACCESS, SPR_NOACCESS,
4241                  &spr_read_generic, &spr_write_generic,
4242                  0x00000000);
4243     /* XXX : not implemented */
4244     spr_register(env, SPR_HID1, "HID1",
4245                  SPR_NOACCESS, SPR_NOACCESS,
4246                  &spr_read_generic, &spr_write_generic,
4247                  0x00000000);
4248     /* XXX : not implemented */
4249     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4250                  SPR_NOACCESS, SPR_NOACCESS,
4251                  &spr_read_generic, &spr_write_generic,
4252                  0x00000000);
4253     /* XXX : not implemented */
4254     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4255                  SPR_NOACCESS, SPR_NOACCESS,
4256                  &spr_read_generic, &spr_write_generic,
4257                  0x00000000);
4258     /* XXX : not implemented */
4259     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4260                  SPR_NOACCESS, SPR_NOACCESS,
4261                  &spr_read_generic, &spr_write_generic,
4262                  0x00000000);
4263     /* XXX : not implemented */
4264     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4265                  SPR_NOACCESS, SPR_NOACCESS,
4266                  &spr_read_generic, &spr_write_generic,
4267                  0x00000000);
4268     /* XXX : not implemented */
4269     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4270                  SPR_NOACCESS, SPR_NOACCESS,
4271                  &spr_read_generic, &spr_write_generic,
4272                  0x00000000);
4273     /* XXX : not implemented */
4274     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4275                  SPR_NOACCESS, SPR_NOACCESS,
4276                  &spr_read_generic, &spr_write_generic,
4277                  0x00000000);
4278     /* XXX : not implemented */
4279     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4280                  SPR_NOACCESS, SPR_NOACCESS,
4281                  &spr_read_generic, &spr_write_generic,
4282                  0x00000000);
4283     /* XXX : not implemented */
4284     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4285                  SPR_NOACCESS, SPR_NOACCESS,
4286                  &spr_read_generic, &spr_write_generic,
4287                  0x00000000);
4288     /* XXX : not implemented */
4289     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4290                  SPR_NOACCESS, SPR_NOACCESS,
4291                  &spr_read_generic, &spr_write_generic,
4292                  0x00000000);
4293     /* XXX : not implemented */
4294     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4295                  SPR_NOACCESS, SPR_NOACCESS,
4296                  &spr_read_generic, &spr_write_generic,
4297                  0x00000000);
4298     /* XXX : not implemented */
4299     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4300                  SPR_NOACCESS, SPR_NOACCESS,
4301                  &spr_read_generic, &spr_write_generic,
4302                  0x00000000);
4303     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4304                  SPR_NOACCESS, SPR_NOACCESS,
4305                  &spr_read_generic, &spr_write_generic,
4306                  0x00000000);
4307     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4308                  SPR_NOACCESS, SPR_NOACCESS,
4309                  &spr_read_generic, &spr_write_generic,
4310                  0x00000000);
4311 #if !defined(CONFIG_USER_ONLY)
4312     env->nb_tlb = 64;
4313     env->nb_ways = 1;
4314     env->id_tlbs = 0;
4315 #endif
4316     init_excp_e200(env);
4317     env->dcache_line_size = 32;
4318     env->icache_line_size = 32;
4319     /* Allocate hardware IRQ controller */
4320     ppce500_irq_init(env);
4321 }
4322
4323 /* Non-embedded PowerPC                                                      */
4324
4325 /* POWER : same as 601, without mfmsr, mfsr                                  */
4326 #if defined(TODO)
4327 #define POWERPC_INSNS_POWER  (XXX_TODO)
4328 /* POWER RSC (from RAD6000) */
4329 #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4330 #endif /* TODO */
4331
4332 /* PowerPC 601                                                               */
4333 #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4334                               PPC_FLOAT |                                     \
4335                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4336                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4337                               PPC_SEGMENT | PPC_EXTERN)
4338 #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4339 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4340 //#define POWERPC_MMU_601      (POWERPC_MMU_601)
4341 //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4342 #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4343 #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4344 #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4345 #define check_pow_601        check_pow_none
4346
4347 static void init_proc_601 (CPUPPCState *env)
4348 {
4349     gen_spr_ne_601(env);
4350     gen_spr_601(env);
4351     /* Hardware implementation registers */
4352     /* XXX : not implemented */
4353     spr_register(env, SPR_HID0, "HID0",
4354                  SPR_NOACCESS, SPR_NOACCESS,
4355                  &spr_read_generic, &spr_write_hid0_601,
4356                  0x80010080);
4357     /* XXX : not implemented */
4358     spr_register(env, SPR_HID1, "HID1",
4359                  SPR_NOACCESS, SPR_NOACCESS,
4360                  &spr_read_generic, &spr_write_generic,
4361                  0x00000000);
4362     /* XXX : not implemented */
4363     spr_register(env, SPR_601_HID2, "HID2",
4364                  SPR_NOACCESS, SPR_NOACCESS,
4365                  &spr_read_generic, &spr_write_generic,
4366                  0x00000000);
4367     /* XXX : not implemented */
4368     spr_register(env, SPR_601_HID5, "HID5",
4369                  SPR_NOACCESS, SPR_NOACCESS,
4370                  &spr_read_generic, &spr_write_generic,
4371                  0x00000000);
4372     /* Memory management */
4373     init_excp_601(env);
4374     /* XXX: beware that dcache line size is 64
4375      *      but dcbz uses 32 bytes "sectors"
4376      * XXX: this breaks clcs instruction !
4377      */
4378     env->dcache_line_size = 32;
4379     env->icache_line_size = 64;
4380     /* Allocate hardware IRQ controller */
4381     ppc6xx_irq_init(env);
4382 }
4383
4384 /* PowerPC 601v                                                              */
4385 #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4386                               PPC_FLOAT |                                     \
4387                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4388                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4389                               PPC_SEGMENT | PPC_EXTERN)
4390 #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4391 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4392 #define POWERPC_MMU_601v     (POWERPC_MMU_601)
4393 #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4394 #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4395 #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4396 #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4397 #define check_pow_601v       check_pow_none
4398
4399 static void init_proc_601v (CPUPPCState *env)
4400 {
4401     init_proc_601(env);
4402     /* XXX : not implemented */
4403     spr_register(env, SPR_601_HID15, "HID15",
4404                  SPR_NOACCESS, SPR_NOACCESS,
4405                  &spr_read_generic, &spr_write_generic,
4406                  0x00000000);
4407 }
4408
4409 /* PowerPC 602                                                               */
4410 #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4411                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4412                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4413                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4414                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4415                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4416                               PPC_SEGMENT | PPC_602_SPEC)
4417 #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4418 /* XXX: 602 MMU is quite specific. Should add a special case */
4419 #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4420 //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4421 #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4422 #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4423 #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4424                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4425 #define check_pow_602        check_pow_hid0
4426
4427 static void init_proc_602 (CPUPPCState *env)
4428 {
4429     gen_spr_ne_601(env);
4430     gen_spr_602(env);
4431     /* Time base */
4432     gen_tbl(env);
4433     /* hardware implementation registers */
4434     /* XXX : not implemented */
4435     spr_register(env, SPR_HID0, "HID0",
4436                  SPR_NOACCESS, SPR_NOACCESS,
4437                  &spr_read_generic, &spr_write_generic,
4438                  0x00000000);
4439     /* XXX : not implemented */
4440     spr_register(env, SPR_HID1, "HID1",
4441                  SPR_NOACCESS, SPR_NOACCESS,
4442                  &spr_read_generic, &spr_write_generic,
4443                  0x00000000);
4444     /* Memory management */
4445     gen_low_BATs(env);
4446     gen_6xx_7xx_soft_tlb(env, 64, 2);
4447     init_excp_602(env);
4448     env->dcache_line_size = 32;
4449     env->icache_line_size = 32;
4450     /* Allocate hardware IRQ controller */
4451     ppc6xx_irq_init(env);
4452 }
4453
4454 /* PowerPC 603                                                               */
4455 #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4456                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4457                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4458                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4459                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4460                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4461                               PPC_SEGMENT | PPC_EXTERN)
4462 #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4463 #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4464 //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4465 #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4466 #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4467 #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4468                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4469 #define check_pow_603        check_pow_hid0
4470
4471 static void init_proc_603 (CPUPPCState *env)
4472 {
4473     gen_spr_ne_601(env);
4474     gen_spr_603(env);
4475     /* Time base */
4476     gen_tbl(env);
4477     /* hardware implementation registers */
4478     /* XXX : not implemented */
4479     spr_register(env, SPR_HID0, "HID0",
4480                  SPR_NOACCESS, SPR_NOACCESS,
4481                  &spr_read_generic, &spr_write_generic,
4482                  0x00000000);
4483     /* XXX : not implemented */
4484     spr_register(env, SPR_HID1, "HID1",
4485                  SPR_NOACCESS, SPR_NOACCESS,
4486                  &spr_read_generic, &spr_write_generic,
4487                  0x00000000);
4488     /* Memory management */
4489     gen_low_BATs(env);
4490     gen_6xx_7xx_soft_tlb(env, 64, 2);
4491     init_excp_603(env);
4492     env->dcache_line_size = 32;
4493     env->icache_line_size = 32;
4494     /* Allocate hardware IRQ controller */
4495     ppc6xx_irq_init(env);
4496 }
4497
4498 /* PowerPC 603e                                                              */
4499 #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4500                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4501                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4502                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4503                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4504                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4505                               PPC_SEGMENT | PPC_EXTERN)
4506 #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4507 #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4508 //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4509 #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4510 #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4511 #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4512                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4513 #define check_pow_603E       check_pow_hid0
4514
4515 static void init_proc_603E (CPUPPCState *env)
4516 {
4517     gen_spr_ne_601(env);
4518     gen_spr_603(env);
4519     /* Time base */
4520     gen_tbl(env);
4521     /* hardware implementation registers */
4522     /* XXX : not implemented */
4523     spr_register(env, SPR_HID0, "HID0",
4524                  SPR_NOACCESS, SPR_NOACCESS,
4525                  &spr_read_generic, &spr_write_generic,
4526                  0x00000000);
4527     /* XXX : not implemented */
4528     spr_register(env, SPR_HID1, "HID1",
4529                  SPR_NOACCESS, SPR_NOACCESS,
4530                  &spr_read_generic, &spr_write_generic,
4531                  0x00000000);
4532     /* XXX : not implemented */
4533     spr_register(env, SPR_IABR, "IABR",
4534                  SPR_NOACCESS, SPR_NOACCESS,
4535                  &spr_read_generic, &spr_write_generic,
4536                  0x00000000);
4537     /* Memory management */
4538     gen_low_BATs(env);
4539     gen_6xx_7xx_soft_tlb(env, 64, 2);
4540     init_excp_603(env);
4541     env->dcache_line_size = 32;
4542     env->icache_line_size = 32;
4543     /* Allocate hardware IRQ controller */
4544     ppc6xx_irq_init(env);
4545 }
4546
4547 /* PowerPC 604                                                               */
4548 #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4549                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4550                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4551                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4552                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4553                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4554                               PPC_SEGMENT | PPC_EXTERN)
4555 #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4556 #define POWERPC_MMU_604      (POWERPC_MMU_32B)
4557 //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4558 #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4559 #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4560 #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4561                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4562 #define check_pow_604        check_pow_nocheck
4563
4564 static void init_proc_604 (CPUPPCState *env)
4565 {
4566     gen_spr_ne_601(env);
4567     gen_spr_604(env);
4568     /* Time base */
4569     gen_tbl(env);
4570     /* Hardware implementation registers */
4571     /* XXX : not implemented */
4572     spr_register(env, SPR_HID0, "HID0",
4573                  SPR_NOACCESS, SPR_NOACCESS,
4574                  &spr_read_generic, &spr_write_generic,
4575                  0x00000000);
4576     /* Memory management */
4577     gen_low_BATs(env);
4578     init_excp_604(env);
4579     env->dcache_line_size = 32;
4580     env->icache_line_size = 32;
4581     /* Allocate hardware IRQ controller */
4582     ppc6xx_irq_init(env);
4583 }
4584
4585 /* PowerPC 604E                                                              */
4586 #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4587                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4588                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4589                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4590                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4591                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4592                               PPC_SEGMENT | PPC_EXTERN)
4593 #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4594 #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4595 #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4596 #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4597 #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4598 #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4599                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4600 #define check_pow_604E       check_pow_nocheck
4601
4602 static void init_proc_604E (CPUPPCState *env)
4603 {
4604     gen_spr_ne_601(env);
4605     gen_spr_604(env);
4606     /* XXX : not implemented */
4607     spr_register(env, SPR_MMCR1, "MMCR1",
4608                  SPR_NOACCESS, SPR_NOACCESS,
4609                  &spr_read_generic, &spr_write_generic,
4610                  0x00000000);
4611     /* XXX : not implemented */
4612     spr_register(env, SPR_PMC3, "PMC3",
4613                  SPR_NOACCESS, SPR_NOACCESS,
4614                  &spr_read_generic, &spr_write_generic,
4615                  0x00000000);
4616     /* XXX : not implemented */
4617     spr_register(env, SPR_PMC4, "PMC4",
4618                  SPR_NOACCESS, SPR_NOACCESS,
4619                  &spr_read_generic, &spr_write_generic,
4620                  0x00000000);
4621     /* Time base */
4622     gen_tbl(env);
4623     /* Hardware implementation registers */
4624     /* XXX : not implemented */
4625     spr_register(env, SPR_HID0, "HID0",
4626                  SPR_NOACCESS, SPR_NOACCESS,
4627                  &spr_read_generic, &spr_write_generic,
4628                  0x00000000);
4629     /* XXX : not implemented */
4630     spr_register(env, SPR_HID1, "HID1",
4631                  SPR_NOACCESS, SPR_NOACCESS,
4632                  &spr_read_generic, &spr_write_generic,
4633                  0x00000000);
4634     /* Memory management */
4635     gen_low_BATs(env);
4636     init_excp_604(env);
4637     env->dcache_line_size = 32;
4638     env->icache_line_size = 32;
4639     /* Allocate hardware IRQ controller */
4640     ppc6xx_irq_init(env);
4641 }
4642
4643 /* PowerPC 740                                                               */
4644 #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4645                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4646                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4647                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4648                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4649                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4650                               PPC_SEGMENT | PPC_EXTERN)
4651 #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
4652 #define POWERPC_MMU_740      (POWERPC_MMU_32B)
4653 #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
4654 #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
4655 #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
4656 #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4657                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4658 #define check_pow_740        check_pow_hid0
4659
4660 static void init_proc_740 (CPUPPCState *env)
4661 {
4662     gen_spr_ne_601(env);
4663     gen_spr_7xx(env);
4664     /* Time base */
4665     gen_tbl(env);
4666     /* Thermal management */
4667     gen_spr_thrm(env);
4668     /* Hardware implementation registers */
4669     /* XXX : not implemented */
4670     spr_register(env, SPR_HID0, "HID0",
4671                  SPR_NOACCESS, SPR_NOACCESS,
4672                  &spr_read_generic, &spr_write_generic,
4673                  0x00000000);
4674     /* XXX : not implemented */
4675     spr_register(env, SPR_HID1, "HID1",
4676                  SPR_NOACCESS, SPR_NOACCESS,
4677                  &spr_read_generic, &spr_write_generic,
4678                  0x00000000);
4679     /* Memory management */
4680     gen_low_BATs(env);
4681     init_excp_7x0(env);
4682     env->dcache_line_size = 32;
4683     env->icache_line_size = 32;
4684     /* Allocate hardware IRQ controller */
4685     ppc6xx_irq_init(env);
4686 }
4687
4688 /* PowerPC 750                                                               */
4689 #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4690                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4691                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4692                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4693                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4694                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4695                               PPC_SEGMENT | PPC_EXTERN)
4696 #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
4697 #define POWERPC_MMU_750      (POWERPC_MMU_32B)
4698 #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
4699 #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
4700 #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
4701 #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4702                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4703 #define check_pow_750        check_pow_hid0
4704
4705 static void init_proc_750 (CPUPPCState *env)
4706 {
4707     gen_spr_ne_601(env);
4708     gen_spr_7xx(env);
4709     /* XXX : not implemented */
4710     spr_register(env, SPR_L2CR, "L2CR",
4711                  SPR_NOACCESS, SPR_NOACCESS,
4712                  &spr_read_generic, &spr_write_generic,
4713                  0x00000000);
4714     /* Time base */
4715     gen_tbl(env);
4716     /* Thermal management */
4717     gen_spr_thrm(env);
4718     /* Hardware implementation registers */
4719     /* XXX : not implemented */
4720     spr_register(env, SPR_HID0, "HID0",
4721                  SPR_NOACCESS, SPR_NOACCESS,
4722                  &spr_read_generic, &spr_write_generic,
4723                  0x00000000);
4724     /* XXX : not implemented */
4725     spr_register(env, SPR_HID1, "HID1",
4726                  SPR_NOACCESS, SPR_NOACCESS,
4727                  &spr_read_generic, &spr_write_generic,
4728                  0x00000000);
4729     /* Memory management */
4730     gen_low_BATs(env);
4731     /* XXX: high BATs are also present but are known to be bugged on
4732      *      die version 1.x
4733      */
4734     init_excp_7x0(env);
4735     env->dcache_line_size = 32;
4736     env->icache_line_size = 32;
4737     /* Allocate hardware IRQ controller */
4738     ppc6xx_irq_init(env);
4739 }
4740
4741 /* PowerPC 750 CL                                                            */
4742 /* XXX: not implemented:
4743  * cache lock instructions:
4744  * dcbz_l
4745  * floating point paired instructions
4746  * psq_lux
4747  * psq_lx
4748  * psq_stux
4749  * psq_stx
4750  * ps_abs
4751  * ps_add
4752  * ps_cmpo0
4753  * ps_cmpo1
4754  * ps_cmpu0
4755  * ps_cmpu1
4756  * ps_div
4757  * ps_madd
4758  * ps_madds0
4759  * ps_madds1
4760  * ps_merge00
4761  * ps_merge01
4762  * ps_merge10
4763  * ps_merge11
4764  * ps_mr
4765  * ps_msub
4766  * ps_mul
4767  * ps_muls0
4768  * ps_muls1
4769  * ps_nabs
4770  * ps_neg
4771  * ps_nmadd
4772  * ps_nmsub
4773  * ps_res
4774  * ps_rsqrte
4775  * ps_sel
4776  * ps_sub
4777  * ps_sum0
4778  * ps_sum1
4779  */
4780 #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4781                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4782                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4783                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4784                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4785                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4786                               PPC_SEGMENT | PPC_EXTERN)
4787 #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
4788 #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
4789 #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
4790 #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
4791 #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
4792 #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4793                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4794 #define check_pow_750cl      check_pow_hid0
4795
4796 static void init_proc_750cl (CPUPPCState *env)
4797 {
4798     gen_spr_ne_601(env);
4799     gen_spr_7xx(env);
4800     /* XXX : not implemented */
4801     spr_register(env, SPR_L2CR, "L2CR",
4802                  SPR_NOACCESS, SPR_NOACCESS,
4803                  &spr_read_generic, &spr_write_generic,
4804                  0x00000000);
4805     /* Time base */
4806     gen_tbl(env);
4807     /* Thermal management */
4808     /* Those registers are fake on 750CL */
4809     spr_register(env, SPR_THRM1, "THRM1",
4810                  SPR_NOACCESS, SPR_NOACCESS,
4811                  &spr_read_generic, &spr_write_generic,
4812                  0x00000000);
4813     spr_register(env, SPR_THRM2, "THRM2",
4814                  SPR_NOACCESS, SPR_NOACCESS,
4815                  &spr_read_generic, &spr_write_generic,
4816                  0x00000000);
4817     spr_register(env, SPR_THRM3, "THRM3",
4818                  SPR_NOACCESS, SPR_NOACCESS,
4819                  &spr_read_generic, &spr_write_generic,
4820                  0x00000000);
4821     /* XXX: not implemented */
4822     spr_register(env, SPR_750_TDCL, "TDCL",
4823                  SPR_NOACCESS, SPR_NOACCESS,
4824                  &spr_read_generic, &spr_write_generic,
4825                  0x00000000);
4826     spr_register(env, SPR_750_TDCH, "TDCH",
4827                  SPR_NOACCESS, SPR_NOACCESS,
4828                  &spr_read_generic, &spr_write_generic,
4829                  0x00000000);
4830     /* DMA */
4831     /* XXX : not implemented */
4832     spr_register(env, SPR_750_WPAR, "WPAR",
4833                  SPR_NOACCESS, SPR_NOACCESS,
4834                  &spr_read_generic, &spr_write_generic,
4835                  0x00000000);
4836     spr_register(env, SPR_750_DMAL, "DMAL",
4837                  SPR_NOACCESS, SPR_NOACCESS,
4838                  &spr_read_generic, &spr_write_generic,
4839                  0x00000000);
4840     spr_register(env, SPR_750_DMAU, "DMAU",
4841                  SPR_NOACCESS, SPR_NOACCESS,
4842                  &spr_read_generic, &spr_write_generic,
4843                  0x00000000);
4844     /* Hardware implementation registers */
4845     /* XXX : not implemented */
4846     spr_register(env, SPR_HID0, "HID0",
4847                  SPR_NOACCESS, SPR_NOACCESS,
4848                  &spr_read_generic, &spr_write_generic,
4849                  0x00000000);
4850     /* XXX : not implemented */
4851     spr_register(env, SPR_HID1, "HID1",
4852                  SPR_NOACCESS, SPR_NOACCESS,
4853                  &spr_read_generic, &spr_write_generic,
4854                  0x00000000);
4855     /* XXX : not implemented */
4856     spr_register(env, SPR_750CL_HID2, "HID2",
4857                  SPR_NOACCESS, SPR_NOACCESS,
4858                  &spr_read_generic, &spr_write_generic,
4859                  0x00000000);
4860     /* XXX : not implemented */
4861     spr_register(env, SPR_750CL_HID4, "HID4",
4862                  SPR_NOACCESS, SPR_NOACCESS,
4863                  &spr_read_generic, &spr_write_generic,
4864                  0x00000000);
4865     /* Quantization registers */
4866     /* XXX : not implemented */
4867     spr_register(env, SPR_750_GQR0, "GQR0",
4868                  SPR_NOACCESS, SPR_NOACCESS,
4869                  &spr_read_generic, &spr_write_generic,
4870                  0x00000000);
4871     /* XXX : not implemented */
4872     spr_register(env, SPR_750_GQR1, "GQR1",
4873                  SPR_NOACCESS, SPR_NOACCESS,
4874                  &spr_read_generic, &spr_write_generic,
4875                  0x00000000);
4876     /* XXX : not implemented */
4877     spr_register(env, SPR_750_GQR2, "GQR2",
4878                  SPR_NOACCESS, SPR_NOACCESS,
4879                  &spr_read_generic, &spr_write_generic,
4880                  0x00000000);
4881     /* XXX : not implemented */
4882     spr_register(env, SPR_750_GQR3, "GQR3",
4883                  SPR_NOACCESS, SPR_NOACCESS,
4884                  &spr_read_generic, &spr_write_generic,
4885                  0x00000000);
4886     /* XXX : not implemented */
4887     spr_register(env, SPR_750_GQR4, "GQR4",
4888                  SPR_NOACCESS, SPR_NOACCESS,
4889                  &spr_read_generic, &spr_write_generic,
4890                  0x00000000);
4891     /* XXX : not implemented */
4892     spr_register(env, SPR_750_GQR5, "GQR5",
4893                  SPR_NOACCESS, SPR_NOACCESS,
4894                  &spr_read_generic, &spr_write_generic,
4895                  0x00000000);
4896     /* XXX : not implemented */
4897     spr_register(env, SPR_750_GQR6, "GQR6",
4898                  SPR_NOACCESS, SPR_NOACCESS,
4899                  &spr_read_generic, &spr_write_generic,
4900                  0x00000000);
4901     /* XXX : not implemented */
4902     spr_register(env, SPR_750_GQR7, "GQR7",
4903                  SPR_NOACCESS, SPR_NOACCESS,
4904                  &spr_read_generic, &spr_write_generic,
4905                  0x00000000);
4906     /* Memory management */
4907     gen_low_BATs(env);
4908     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4909     gen_high_BATs(env);
4910     init_excp_750cl(env);
4911     env->dcache_line_size = 32;
4912     env->icache_line_size = 32;
4913     /* Allocate hardware IRQ controller */
4914     ppc6xx_irq_init(env);
4915 }
4916
4917 /* PowerPC 750CX                                                             */
4918 #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4919                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4920                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4921                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4922                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4923                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4924                               PPC_SEGMENT | PPC_EXTERN)
4925 #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
4926 #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
4927 #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
4928 #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
4929 #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
4930 #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4931                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4932 #define check_pow_750cx      check_pow_hid0
4933
4934 static void init_proc_750cx (CPUPPCState *env)
4935 {
4936     gen_spr_ne_601(env);
4937     gen_spr_7xx(env);
4938     /* XXX : not implemented */
4939     spr_register(env, SPR_L2CR, "L2CR",
4940                  SPR_NOACCESS, SPR_NOACCESS,
4941                  &spr_read_generic, &spr_write_generic,
4942                  0x00000000);
4943     /* Time base */
4944     gen_tbl(env);
4945     /* Thermal management */
4946     gen_spr_thrm(env);
4947     /* This register is not implemented but is present for compatibility */
4948     spr_register(env, SPR_SDA, "SDA",
4949                  SPR_NOACCESS, SPR_NOACCESS,
4950                  &spr_read_generic, &spr_write_generic,
4951                  0x00000000);
4952     /* Hardware implementation registers */
4953     /* XXX : not implemented */
4954     spr_register(env, SPR_HID0, "HID0",
4955                  SPR_NOACCESS, SPR_NOACCESS,
4956                  &spr_read_generic, &spr_write_generic,
4957                  0x00000000);
4958     /* XXX : not implemented */
4959     spr_register(env, SPR_HID1, "HID1",
4960                  SPR_NOACCESS, SPR_NOACCESS,
4961                  &spr_read_generic, &spr_write_generic,
4962                  0x00000000);
4963     /* Memory management */
4964     gen_low_BATs(env);
4965     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4966     gen_high_BATs(env);
4967     init_excp_750cx(env);
4968     env->dcache_line_size = 32;
4969     env->icache_line_size = 32;
4970     /* Allocate hardware IRQ controller */
4971     ppc6xx_irq_init(env);
4972 }
4973
4974 /* PowerPC 750FX                                                             */
4975 #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4976                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4977                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4978                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4979                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4980                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4981                               PPC_SEGMENT  | PPC_EXTERN)
4982 #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
4983 #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
4984 #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
4985 #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
4986 #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
4987 #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4988                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4989 #define check_pow_750fx      check_pow_hid0
4990
4991 static void init_proc_750fx (CPUPPCState *env)
4992 {
4993     gen_spr_ne_601(env);
4994     gen_spr_7xx(env);
4995     /* XXX : not implemented */
4996     spr_register(env, SPR_L2CR, "L2CR",
4997                  SPR_NOACCESS, SPR_NOACCESS,
4998                  &spr_read_generic, &spr_write_generic,
4999                  0x00000000);
5000     /* Time base */
5001     gen_tbl(env);
5002     /* Thermal management */
5003     gen_spr_thrm(env);
5004     /* XXX : not implemented */
5005     spr_register(env, SPR_750_THRM4, "THRM4",
5006                  SPR_NOACCESS, SPR_NOACCESS,
5007                  &spr_read_generic, &spr_write_generic,
5008                  0x00000000);
5009     /* Hardware implementation registers */
5010     /* XXX : not implemented */
5011     spr_register(env, SPR_HID0, "HID0",
5012                  SPR_NOACCESS, SPR_NOACCESS,
5013                  &spr_read_generic, &spr_write_generic,
5014                  0x00000000);
5015     /* XXX : not implemented */
5016     spr_register(env, SPR_HID1, "HID1",
5017                  SPR_NOACCESS, SPR_NOACCESS,
5018                  &spr_read_generic, &spr_write_generic,
5019                  0x00000000);
5020     /* XXX : not implemented */
5021     spr_register(env, SPR_750FX_HID2, "HID2",
5022                  SPR_NOACCESS, SPR_NOACCESS,
5023                  &spr_read_generic, &spr_write_generic,
5024                  0x00000000);
5025     /* Memory management */
5026     gen_low_BATs(env);
5027     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5028     gen_high_BATs(env);
5029     init_excp_7x0(env);
5030     env->dcache_line_size = 32;
5031     env->icache_line_size = 32;
5032     /* Allocate hardware IRQ controller */
5033     ppc6xx_irq_init(env);
5034 }
5035
5036 /* PowerPC 750GX                                                             */
5037 #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5038                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5039                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5040                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5041                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5042                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5043                               PPC_SEGMENT  | PPC_EXTERN)
5044 #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
5045 #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
5046 #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
5047 #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
5048 #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
5049 #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5050                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5051 #define check_pow_750gx      check_pow_hid0
5052
5053 static void init_proc_750gx (CPUPPCState *env)
5054 {
5055     gen_spr_ne_601(env);
5056     gen_spr_7xx(env);
5057     /* XXX : not implemented (XXX: different from 750fx) */
5058     spr_register(env, SPR_L2CR, "L2CR",
5059                  SPR_NOACCESS, SPR_NOACCESS,
5060                  &spr_read_generic, &spr_write_generic,
5061                  0x00000000);
5062     /* Time base */
5063     gen_tbl(env);
5064     /* Thermal management */
5065     gen_spr_thrm(env);
5066     /* XXX : not implemented */
5067     spr_register(env, SPR_750_THRM4, "THRM4",
5068                  SPR_NOACCESS, SPR_NOACCESS,
5069                  &spr_read_generic, &spr_write_generic,
5070                  0x00000000);
5071     /* Hardware implementation registers */
5072     /* XXX : not implemented (XXX: different from 750fx) */
5073     spr_register(env, SPR_HID0, "HID0",
5074                  SPR_NOACCESS, SPR_NOACCESS,
5075                  &spr_read_generic, &spr_write_generic,
5076                  0x00000000);
5077     /* XXX : not implemented */
5078     spr_register(env, SPR_HID1, "HID1",
5079                  SPR_NOACCESS, SPR_NOACCESS,
5080                  &spr_read_generic, &spr_write_generic,
5081                  0x00000000);
5082     /* XXX : not implemented (XXX: different from 750fx) */
5083     spr_register(env, SPR_750FX_HID2, "HID2",
5084                  SPR_NOACCESS, SPR_NOACCESS,
5085                  &spr_read_generic, &spr_write_generic,
5086                  0x00000000);
5087     /* Memory management */
5088     gen_low_BATs(env);
5089     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5090     gen_high_BATs(env);
5091     init_excp_7x0(env);
5092     env->dcache_line_size = 32;
5093     env->icache_line_size = 32;
5094     /* Allocate hardware IRQ controller */
5095     ppc6xx_irq_init(env);
5096 }
5097
5098 /* PowerPC 745                                                               */
5099 #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5100                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5101                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5102                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5103                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5104                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5105                               PPC_SEGMENT | PPC_EXTERN)
5106 #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
5107 #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
5108 #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
5109 #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
5110 #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
5111 #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5112                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5113 #define check_pow_745        check_pow_hid0
5114
5115 static void init_proc_745 (CPUPPCState *env)
5116 {
5117     gen_spr_ne_601(env);
5118     gen_spr_7xx(env);
5119     gen_spr_G2_755(env);
5120     /* Time base */
5121     gen_tbl(env);
5122     /* Thermal management */
5123     gen_spr_thrm(env);
5124     /* Hardware implementation registers */
5125     /* XXX : not implemented */
5126     spr_register(env, SPR_HID0, "HID0",
5127                  SPR_NOACCESS, SPR_NOACCESS,
5128                  &spr_read_generic, &spr_write_generic,
5129                  0x00000000);
5130     /* XXX : not implemented */
5131     spr_register(env, SPR_HID1, "HID1",
5132                  SPR_NOACCESS, SPR_NOACCESS,
5133                  &spr_read_generic, &spr_write_generic,
5134                  0x00000000);
5135     /* XXX : not implemented */
5136     spr_register(env, SPR_HID2, "HID2",
5137                  SPR_NOACCESS, SPR_NOACCESS,
5138                  &spr_read_generic, &spr_write_generic,
5139                  0x00000000);
5140     /* Memory management */
5141     gen_low_BATs(env);
5142     gen_high_BATs(env);
5143     gen_6xx_7xx_soft_tlb(env, 64, 2);
5144     init_excp_7x5(env);
5145     env->dcache_line_size = 32;
5146     env->icache_line_size = 32;
5147     /* Allocate hardware IRQ controller */
5148     ppc6xx_irq_init(env);
5149 }
5150
5151 /* PowerPC 755                                                               */
5152 #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5153                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5154                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5155                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5156                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5157                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5158                               PPC_SEGMENT | PPC_EXTERN)
5159 #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
5160 #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
5161 #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
5162 #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
5163 #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
5164 #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5165                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5166 #define check_pow_755        check_pow_hid0
5167
5168 static void init_proc_755 (CPUPPCState *env)
5169 {
5170     gen_spr_ne_601(env);
5171     gen_spr_7xx(env);
5172     gen_spr_G2_755(env);
5173     /* Time base */
5174     gen_tbl(env);
5175     /* L2 cache control */
5176     /* XXX : not implemented */
5177     spr_register(env, SPR_L2CR, "L2CR",
5178                  SPR_NOACCESS, SPR_NOACCESS,
5179                  &spr_read_generic, &spr_write_generic,
5180                  0x00000000);
5181     /* XXX : not implemented */
5182     spr_register(env, SPR_L2PMCR, "L2PMCR",
5183                  SPR_NOACCESS, SPR_NOACCESS,
5184                  &spr_read_generic, &spr_write_generic,
5185                  0x00000000);
5186     /* Thermal management */
5187     gen_spr_thrm(env);
5188     /* Hardware implementation registers */
5189     /* XXX : not implemented */
5190     spr_register(env, SPR_HID0, "HID0",
5191                  SPR_NOACCESS, SPR_NOACCESS,
5192                  &spr_read_generic, &spr_write_generic,
5193                  0x00000000);
5194     /* XXX : not implemented */
5195     spr_register(env, SPR_HID1, "HID1",
5196                  SPR_NOACCESS, SPR_NOACCESS,
5197                  &spr_read_generic, &spr_write_generic,
5198                  0x00000000);
5199     /* XXX : not implemented */
5200     spr_register(env, SPR_HID2, "HID2",
5201                  SPR_NOACCESS, SPR_NOACCESS,
5202                  &spr_read_generic, &spr_write_generic,
5203                  0x00000000);
5204     /* Memory management */
5205     gen_low_BATs(env);
5206     gen_high_BATs(env);
5207     gen_6xx_7xx_soft_tlb(env, 64, 2);
5208     init_excp_7x5(env);
5209     env->dcache_line_size = 32;
5210     env->icache_line_size = 32;
5211     /* Allocate hardware IRQ controller */
5212     ppc6xx_irq_init(env);
5213 }
5214
5215 /* PowerPC 7400 (aka G4)                                                     */
5216 #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5217                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5218                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5219                               PPC_FLOAT_STFIWX |                              \
5220                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5221                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5222                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5223                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5224                               PPC_MEM_TLBIA |                                 \
5225                               PPC_SEGMENT | PPC_EXTERN |                      \
5226                               PPC_ALTIVEC)
5227 #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
5228 #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
5229 #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
5230 #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
5231 #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
5232 #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5233                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5234                               POWERPC_FLAG_BUS_CLK)
5235 #define check_pow_7400       check_pow_hid0_74xx
5236
5237 static void init_proc_7400 (CPUPPCState *env)
5238 {
5239     gen_spr_ne_601(env);
5240     gen_spr_7xx(env);
5241     /* Time base */
5242     gen_tbl(env);
5243     /* 74xx specific SPR */
5244     gen_spr_74xx(env);
5245     /* XXX : not implemented */
5246     spr_register(env, SPR_UBAMR, "UBAMR",
5247                  &spr_read_ureg, SPR_NOACCESS,
5248                  &spr_read_ureg, SPR_NOACCESS,
5249                  0x00000000);
5250     /* XXX: this seems not implemented on all revisions. */
5251     /* XXX : not implemented */
5252     spr_register(env, SPR_MSSCR1, "MSSCR1",
5253                  SPR_NOACCESS, SPR_NOACCESS,
5254                  &spr_read_generic, &spr_write_generic,
5255                  0x00000000);
5256     /* Thermal management */
5257     gen_spr_thrm(env);
5258     /* Memory management */
5259     gen_low_BATs(env);
5260     init_excp_7400(env);
5261     env->dcache_line_size = 32;
5262     env->icache_line_size = 32;
5263     /* Allocate hardware IRQ controller */
5264     ppc6xx_irq_init(env);
5265 }
5266
5267 /* PowerPC 7410 (aka G4)                                                     */
5268 #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5269                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5270                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5271                               PPC_FLOAT_STFIWX |                              \
5272                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5273                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5274                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5275                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5276                               PPC_MEM_TLBIA |                                 \
5277                               PPC_SEGMENT | PPC_EXTERN |                      \
5278                               PPC_ALTIVEC)
5279 #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
5280 #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
5281 #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
5282 #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
5283 #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
5284 #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5285                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5286                               POWERPC_FLAG_BUS_CLK)
5287 #define check_pow_7410       check_pow_hid0_74xx
5288
5289 static void init_proc_7410 (CPUPPCState *env)
5290 {
5291     gen_spr_ne_601(env);
5292     gen_spr_7xx(env);
5293     /* Time base */
5294     gen_tbl(env);
5295     /* 74xx specific SPR */
5296     gen_spr_74xx(env);
5297     /* XXX : not implemented */
5298     spr_register(env, SPR_UBAMR, "UBAMR",
5299                  &spr_read_ureg, SPR_NOACCESS,
5300                  &spr_read_ureg, SPR_NOACCESS,
5301                  0x00000000);
5302     /* Thermal management */
5303     gen_spr_thrm(env);
5304     /* L2PMCR */
5305     /* XXX : not implemented */
5306     spr_register(env, SPR_L2PMCR, "L2PMCR",
5307                  SPR_NOACCESS, SPR_NOACCESS,
5308                  &spr_read_generic, &spr_write_generic,
5309                  0x00000000);
5310     /* LDSTDB */
5311     /* XXX : not implemented */
5312     spr_register(env, SPR_LDSTDB, "LDSTDB",
5313                  SPR_NOACCESS, SPR_NOACCESS,
5314                  &spr_read_generic, &spr_write_generic,
5315                  0x00000000);
5316     /* Memory management */
5317     gen_low_BATs(env);
5318     init_excp_7400(env);
5319     env->dcache_line_size = 32;
5320     env->icache_line_size = 32;
5321     /* Allocate hardware IRQ controller */
5322     ppc6xx_irq_init(env);
5323 }
5324
5325 /* PowerPC 7440 (aka G4)                                                     */
5326 #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5327                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5328                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5329                               PPC_FLOAT_STFIWX |                              \
5330                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5331                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5332                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5333                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5334                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5335                               PPC_SEGMENT | PPC_EXTERN |                      \
5336                               PPC_ALTIVEC)
5337 #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
5338 #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
5339 #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
5340 #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
5341 #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
5342 #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5343                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5344                               POWERPC_FLAG_BUS_CLK)
5345 #define check_pow_7440       check_pow_hid0_74xx
5346
5347 __attribute__ (( unused ))
5348 static void init_proc_7440 (CPUPPCState *env)
5349 {
5350     gen_spr_ne_601(env);
5351     gen_spr_7xx(env);
5352     /* Time base */
5353     gen_tbl(env);
5354     /* 74xx specific SPR */
5355     gen_spr_74xx(env);
5356     /* XXX : not implemented */
5357     spr_register(env, SPR_UBAMR, "UBAMR",
5358                  &spr_read_ureg, SPR_NOACCESS,
5359                  &spr_read_ureg, SPR_NOACCESS,
5360                  0x00000000);
5361     /* LDSTCR */
5362     /* XXX : not implemented */
5363     spr_register(env, SPR_LDSTCR, "LDSTCR",
5364                  SPR_NOACCESS, SPR_NOACCESS,
5365                  &spr_read_generic, &spr_write_generic,
5366                  0x00000000);
5367     /* ICTRL */
5368     /* XXX : not implemented */
5369     spr_register(env, SPR_ICTRL, "ICTRL",
5370                  SPR_NOACCESS, SPR_NOACCESS,
5371                  &spr_read_generic, &spr_write_generic,
5372                  0x00000000);
5373     /* MSSSR0 */
5374     /* XXX : not implemented */
5375     spr_register(env, SPR_MSSSR0, "MSSSR0",
5376                  SPR_NOACCESS, SPR_NOACCESS,
5377                  &spr_read_generic, &spr_write_generic,
5378                  0x00000000);
5379     /* PMC */
5380     /* XXX : not implemented */
5381     spr_register(env, SPR_PMC5, "PMC5",
5382                  SPR_NOACCESS, SPR_NOACCESS,
5383                  &spr_read_generic, &spr_write_generic,
5384                  0x00000000);
5385     /* XXX : not implemented */
5386     spr_register(env, SPR_UPMC5, "UPMC5",
5387                  &spr_read_ureg, SPR_NOACCESS,
5388                  &spr_read_ureg, SPR_NOACCESS,
5389                  0x00000000);
5390     /* XXX : not implemented */
5391     spr_register(env, SPR_PMC6, "PMC6",
5392                  SPR_NOACCESS, SPR_NOACCESS,
5393                  &spr_read_generic, &spr_write_generic,
5394                  0x00000000);
5395     /* XXX : not implemented */
5396     spr_register(env, SPR_UPMC6, "UPMC6",
5397                  &spr_read_ureg, SPR_NOACCESS,
5398                  &spr_read_ureg, SPR_NOACCESS,
5399                  0x00000000);
5400     /* Memory management */
5401     gen_low_BATs(env);
5402     gen_74xx_soft_tlb(env, 128, 2);
5403     init_excp_7450(env);
5404     env->dcache_line_size = 32;
5405     env->icache_line_size = 32;
5406     /* Allocate hardware IRQ controller */
5407     ppc6xx_irq_init(env);
5408 }
5409
5410 /* PowerPC 7450 (aka G4)                                                     */
5411 #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5412                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5413                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5414                               PPC_FLOAT_STFIWX |                              \
5415                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5416                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5417                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5418                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5419                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5420                               PPC_SEGMENT | PPC_EXTERN |                      \
5421                               PPC_ALTIVEC)
5422 #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
5423 #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
5424 #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
5425 #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
5426 #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
5427 #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5428                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5429                               POWERPC_FLAG_BUS_CLK)
5430 #define check_pow_7450       check_pow_hid0_74xx
5431
5432 __attribute__ (( unused ))
5433 static void init_proc_7450 (CPUPPCState *env)
5434 {
5435     gen_spr_ne_601(env);
5436     gen_spr_7xx(env);
5437     /* Time base */
5438     gen_tbl(env);
5439     /* 74xx specific SPR */
5440     gen_spr_74xx(env);
5441     /* Level 3 cache control */
5442     gen_l3_ctrl(env);
5443     /* L3ITCR1 */
5444     /* XXX : not implemented */
5445     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5446                  SPR_NOACCESS, SPR_NOACCESS,
5447                  &spr_read_generic, &spr_write_generic,
5448                  0x00000000);
5449     /* L3ITCR2 */
5450     /* XXX : not implemented */
5451     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5452                  SPR_NOACCESS, SPR_NOACCESS,
5453                  &spr_read_generic, &spr_write_generic,
5454                  0x00000000);
5455     /* L3ITCR3 */
5456     /* XXX : not implemented */
5457     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5458                  SPR_NOACCESS, SPR_NOACCESS,
5459                  &spr_read_generic, &spr_write_generic,
5460                  0x00000000);
5461     /* L3OHCR */
5462     /* XXX : not implemented */
5463     spr_register(env, SPR_L3OHCR, "L3OHCR",
5464                  SPR_NOACCESS, SPR_NOACCESS,
5465                  &spr_read_generic, &spr_write_generic,
5466                  0x00000000);
5467     /* XXX : not implemented */
5468     spr_register(env, SPR_UBAMR, "UBAMR",
5469                  &spr_read_ureg, SPR_NOACCESS,
5470                  &spr_read_ureg, SPR_NOACCESS,
5471                  0x00000000);
5472     /* LDSTCR */
5473     /* XXX : not implemented */
5474     spr_register(env, SPR_LDSTCR, "LDSTCR",
5475                  SPR_NOACCESS, SPR_NOACCESS,
5476                  &spr_read_generic, &spr_write_generic,
5477                  0x00000000);
5478     /* ICTRL */
5479     /* XXX : not implemented */
5480     spr_register(env, SPR_ICTRL, "ICTRL",
5481                  SPR_NOACCESS, SPR_NOACCESS,
5482                  &spr_read_generic, &spr_write_generic,
5483                  0x00000000);
5484     /* MSSSR0 */
5485     /* XXX : not implemented */
5486     spr_register(env, SPR_MSSSR0, "MSSSR0",
5487                  SPR_NOACCESS, SPR_NOACCESS,
5488                  &spr_read_generic, &spr_write_generic,
5489                  0x00000000);
5490     /* PMC */
5491     /* XXX : not implemented */
5492     spr_register(env, SPR_PMC5, "PMC5",
5493                  SPR_NOACCESS, SPR_NOACCESS,
5494                  &spr_read_generic, &spr_write_generic,
5495                  0x00000000);
5496     /* XXX : not implemented */
5497     spr_register(env, SPR_UPMC5, "UPMC5",
5498                  &spr_read_ureg, SPR_NOACCESS,
5499                  &spr_read_ureg, SPR_NOACCESS,
5500                  0x00000000);
5501     /* XXX : not implemented */
5502     spr_register(env, SPR_PMC6, "PMC6",
5503                  SPR_NOACCESS, SPR_NOACCESS,
5504                  &spr_read_generic, &spr_write_generic,
5505                  0x00000000);
5506     /* XXX : not implemented */
5507     spr_register(env, SPR_UPMC6, "UPMC6",
5508                  &spr_read_ureg, SPR_NOACCESS,
5509                  &spr_read_ureg, SPR_NOACCESS,
5510                  0x00000000);
5511     /* Memory management */
5512     gen_low_BATs(env);
5513     gen_74xx_soft_tlb(env, 128, 2);
5514     init_excp_7450(env);
5515     env->dcache_line_size = 32;
5516     env->icache_line_size = 32;
5517     /* Allocate hardware IRQ controller */
5518     ppc6xx_irq_init(env);
5519 }
5520
5521 /* PowerPC 7445 (aka G4)                                                     */
5522 #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5523                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5524                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5525                               PPC_FLOAT_STFIWX |                              \
5526                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5527                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5528                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5529                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5530                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5531                               PPC_SEGMENT | PPC_EXTERN |                      \
5532                               PPC_ALTIVEC)
5533 #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
5534 #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
5535 #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
5536 #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
5537 #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
5538 #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5539                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5540                               POWERPC_FLAG_BUS_CLK)
5541 #define check_pow_7445       check_pow_hid0_74xx
5542
5543 __attribute__ (( unused ))
5544 static void init_proc_7445 (CPUPPCState *env)
5545 {
5546     gen_spr_ne_601(env);
5547     gen_spr_7xx(env);
5548     /* Time base */
5549     gen_tbl(env);
5550     /* 74xx specific SPR */
5551     gen_spr_74xx(env);
5552     /* LDSTCR */
5553     /* XXX : not implemented */
5554     spr_register(env, SPR_LDSTCR, "LDSTCR",
5555                  SPR_NOACCESS, SPR_NOACCESS,
5556                  &spr_read_generic, &spr_write_generic,
5557                  0x00000000);
5558     /* ICTRL */
5559     /* XXX : not implemented */
5560     spr_register(env, SPR_ICTRL, "ICTRL",
5561                  SPR_NOACCESS, SPR_NOACCESS,
5562                  &spr_read_generic, &spr_write_generic,
5563                  0x00000000);
5564     /* MSSSR0 */
5565     /* XXX : not implemented */
5566     spr_register(env, SPR_MSSSR0, "MSSSR0",
5567                  SPR_NOACCESS, SPR_NOACCESS,
5568                  &spr_read_generic, &spr_write_generic,
5569                  0x00000000);
5570     /* PMC */
5571     /* XXX : not implemented */
5572     spr_register(env, SPR_PMC5, "PMC5",
5573                  SPR_NOACCESS, SPR_NOACCESS,
5574                  &spr_read_generic, &spr_write_generic,
5575                  0x00000000);
5576     /* XXX : not implemented */
5577     spr_register(env, SPR_UPMC5, "UPMC5",
5578                  &spr_read_ureg, SPR_NOACCESS,
5579                  &spr_read_ureg, SPR_NOACCESS,
5580                  0x00000000);
5581     /* XXX : not implemented */
5582     spr_register(env, SPR_PMC6, "PMC6",
5583                  SPR_NOACCESS, SPR_NOACCESS,
5584                  &spr_read_generic, &spr_write_generic,
5585                  0x00000000);
5586     /* XXX : not implemented */
5587     spr_register(env, SPR_UPMC6, "UPMC6",
5588                  &spr_read_ureg, SPR_NOACCESS,
5589                  &spr_read_ureg, SPR_NOACCESS,
5590                  0x00000000);
5591     /* SPRGs */
5592     spr_register(env, SPR_SPRG4, "SPRG4",
5593                  SPR_NOACCESS, SPR_NOACCESS,
5594                  &spr_read_generic, &spr_write_generic,
5595                  0x00000000);
5596     spr_register(env, SPR_USPRG4, "USPRG4",
5597                  &spr_read_ureg, SPR_NOACCESS,
5598                  &spr_read_ureg, SPR_NOACCESS,
5599                  0x00000000);
5600     spr_register(env, SPR_SPRG5, "SPRG5",
5601                  SPR_NOACCESS, SPR_NOACCESS,
5602                  &spr_read_generic, &spr_write_generic,
5603                  0x00000000);
5604     spr_register(env, SPR_USPRG5, "USPRG5",
5605                  &spr_read_ureg, SPR_NOACCESS,
5606                  &spr_read_ureg, SPR_NOACCESS,
5607                  0x00000000);
5608     spr_register(env, SPR_SPRG6, "SPRG6",
5609                  SPR_NOACCESS, SPR_NOACCESS,
5610                  &spr_read_generic, &spr_write_generic,
5611                  0x00000000);
5612     spr_register(env, SPR_USPRG6, "USPRG6",
5613                  &spr_read_ureg, SPR_NOACCESS,
5614                  &spr_read_ureg, SPR_NOACCESS,
5615                  0x00000000);
5616     spr_register(env, SPR_SPRG7, "SPRG7",
5617                  SPR_NOACCESS, SPR_NOACCESS,
5618                  &spr_read_generic, &spr_write_generic,
5619                  0x00000000);
5620     spr_register(env, SPR_USPRG7, "USPRG7",
5621                  &spr_read_ureg, SPR_NOACCESS,
5622                  &spr_read_ureg, SPR_NOACCESS,
5623                  0x00000000);
5624     /* Memory management */
5625     gen_low_BATs(env);
5626     gen_high_BATs(env);
5627     gen_74xx_soft_tlb(env, 128, 2);
5628     init_excp_7450(env);
5629     env->dcache_line_size = 32;
5630     env->icache_line_size = 32;
5631     /* Allocate hardware IRQ controller */
5632     ppc6xx_irq_init(env);
5633 }
5634
5635 /* PowerPC 7455 (aka G4)                                                     */
5636 #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5637                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5638                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5639                               PPC_FLOAT_STFIWX |                              \
5640                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5641                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5642                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5643                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5644                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5645                               PPC_SEGMENT | PPC_EXTERN |                      \
5646                               PPC_ALTIVEC)
5647 #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
5648 #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
5649 #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
5650 #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
5651 #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
5652 #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5653                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5654                               POWERPC_FLAG_BUS_CLK)
5655 #define check_pow_7455       check_pow_hid0_74xx
5656
5657 __attribute__ (( unused ))
5658 static void init_proc_7455 (CPUPPCState *env)
5659 {
5660     gen_spr_ne_601(env);
5661     gen_spr_7xx(env);
5662     /* Time base */
5663     gen_tbl(env);
5664     /* 74xx specific SPR */
5665     gen_spr_74xx(env);
5666     /* Level 3 cache control */
5667     gen_l3_ctrl(env);
5668     /* LDSTCR */
5669     /* XXX : not implemented */
5670     spr_register(env, SPR_LDSTCR, "LDSTCR",
5671                  SPR_NOACCESS, SPR_NOACCESS,
5672                  &spr_read_generic, &spr_write_generic,
5673                  0x00000000);
5674     /* ICTRL */
5675     /* XXX : not implemented */
5676     spr_register(env, SPR_ICTRL, "ICTRL",
5677                  SPR_NOACCESS, SPR_NOACCESS,
5678                  &spr_read_generic, &spr_write_generic,
5679                  0x00000000);
5680     /* MSSSR0 */
5681     /* XXX : not implemented */
5682     spr_register(env, SPR_MSSSR0, "MSSSR0",
5683                  SPR_NOACCESS, SPR_NOACCESS,
5684                  &spr_read_generic, &spr_write_generic,
5685                  0x00000000);
5686     /* PMC */
5687     /* XXX : not implemented */
5688     spr_register(env, SPR_PMC5, "PMC5",
5689                  SPR_NOACCESS, SPR_NOACCESS,
5690                  &spr_read_generic, &spr_write_generic,
5691                  0x00000000);
5692     /* XXX : not implemented */
5693     spr_register(env, SPR_UPMC5, "UPMC5",
5694                  &spr_read_ureg, SPR_NOACCESS,
5695                  &spr_read_ureg, SPR_NOACCESS,
5696                  0x00000000);
5697     /* XXX : not implemented */
5698     spr_register(env, SPR_PMC6, "PMC6",
5699                  SPR_NOACCESS, SPR_NOACCESS,
5700                  &spr_read_generic, &spr_write_generic,
5701                  0x00000000);
5702     /* XXX : not implemented */
5703     spr_register(env, SPR_UPMC6, "UPMC6",
5704                  &spr_read_ureg, SPR_NOACCESS,
5705                  &spr_read_ureg, SPR_NOACCESS,
5706                  0x00000000);
5707     /* SPRGs */
5708     spr_register(env, SPR_SPRG4, "SPRG4",
5709                  SPR_NOACCESS, SPR_NOACCESS,
5710                  &spr_read_generic, &spr_write_generic,
5711                  0x00000000);
5712     spr_register(env, SPR_USPRG4, "USPRG4",
5713                  &spr_read_ureg, SPR_NOACCESS,
5714                  &spr_read_ureg, SPR_NOACCESS,
5715                  0x00000000);
5716     spr_register(env, SPR_SPRG5, "SPRG5",
5717                  SPR_NOACCESS, SPR_NOACCESS,
5718                  &spr_read_generic, &spr_write_generic,
5719                  0x00000000);
5720     spr_register(env, SPR_USPRG5, "USPRG5",
5721                  &spr_read_ureg, SPR_NOACCESS,
5722                  &spr_read_ureg, SPR_NOACCESS,
5723                  0x00000000);
5724     spr_register(env, SPR_SPRG6, "SPRG6",
5725                  SPR_NOACCESS, SPR_NOACCESS,
5726                  &spr_read_generic, &spr_write_generic,
5727                  0x00000000);
5728     spr_register(env, SPR_USPRG6, "USPRG6",
5729                  &spr_read_ureg, SPR_NOACCESS,
5730                  &spr_read_ureg, SPR_NOACCESS,
5731                  0x00000000);
5732     spr_register(env, SPR_SPRG7, "SPRG7",
5733                  SPR_NOACCESS, SPR_NOACCESS,
5734                  &spr_read_generic, &spr_write_generic,
5735                  0x00000000);
5736     spr_register(env, SPR_USPRG7, "USPRG7",
5737                  &spr_read_ureg, SPR_NOACCESS,
5738                  &spr_read_ureg, SPR_NOACCESS,
5739                  0x00000000);
5740     /* Memory management */
5741     gen_low_BATs(env);
5742     gen_high_BATs(env);
5743     gen_74xx_soft_tlb(env, 128, 2);
5744     init_excp_7450(env);
5745     env->dcache_line_size = 32;
5746     env->icache_line_size = 32;
5747     /* Allocate hardware IRQ controller */
5748     ppc6xx_irq_init(env);
5749 }
5750
5751 /* PowerPC 7457 (aka G4)                                                     */
5752 #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5753                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5754                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5755                               PPC_FLOAT_STFIWX |                              \
5756                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5757                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5758                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5759                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5760                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5761                               PPC_SEGMENT | PPC_EXTERN |                      \
5762                               PPC_ALTIVEC)
5763 #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
5764 #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
5765 #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
5766 #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
5767 #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
5768 #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5769                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5770                               POWERPC_FLAG_BUS_CLK)
5771 #define check_pow_7457       check_pow_hid0_74xx
5772
5773 __attribute__ (( unused ))
5774 static void init_proc_7457 (CPUPPCState *env)
5775 {
5776     gen_spr_ne_601(env);
5777     gen_spr_7xx(env);
5778     /* Time base */
5779     gen_tbl(env);
5780     /* 74xx specific SPR */
5781     gen_spr_74xx(env);
5782     /* Level 3 cache control */
5783     gen_l3_ctrl(env);
5784     /* L3ITCR1 */
5785     /* XXX : not implemented */
5786     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5787                  SPR_NOACCESS, SPR_NOACCESS,
5788                  &spr_read_generic, &spr_write_generic,
5789                  0x00000000);
5790     /* L3ITCR2 */
5791     /* XXX : not implemented */
5792     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5793                  SPR_NOACCESS, SPR_NOACCESS,
5794                  &spr_read_generic, &spr_write_generic,
5795                  0x00000000);
5796     /* L3ITCR3 */
5797     /* XXX : not implemented */
5798     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5799                  SPR_NOACCESS, SPR_NOACCESS,
5800                  &spr_read_generic, &spr_write_generic,
5801                  0x00000000);
5802     /* L3OHCR */
5803     /* XXX : not implemented */
5804     spr_register(env, SPR_L3OHCR, "L3OHCR",
5805                  SPR_NOACCESS, SPR_NOACCESS,
5806                  &spr_read_generic, &spr_write_generic,
5807                  0x00000000);
5808     /* LDSTCR */
5809     /* XXX : not implemented */
5810     spr_register(env, SPR_LDSTCR, "LDSTCR",
5811                  SPR_NOACCESS, SPR_NOACCESS,
5812                  &spr_read_generic, &spr_write_generic,
5813                  0x00000000);
5814     /* ICTRL */
5815     /* XXX : not implemented */
5816     spr_register(env, SPR_ICTRL, "ICTRL",
5817                  SPR_NOACCESS, SPR_NOACCESS,
5818                  &spr_read_generic, &spr_write_generic,
5819                  0x00000000);
5820     /* MSSSR0 */
5821     /* XXX : not implemented */
5822     spr_register(env, SPR_MSSSR0, "MSSSR0",
5823                  SPR_NOACCESS, SPR_NOACCESS,
5824                  &spr_read_generic, &spr_write_generic,
5825                  0x00000000);
5826     /* PMC */
5827     /* XXX : not implemented */
5828     spr_register(env, SPR_PMC5, "PMC5",
5829                  SPR_NOACCESS, SPR_NOACCESS,
5830                  &spr_read_generic, &spr_write_generic,
5831                  0x00000000);
5832     /* XXX : not implemented */
5833     spr_register(env, SPR_UPMC5, "UPMC5",
5834                  &spr_read_ureg, SPR_NOACCESS,
5835                  &spr_read_ureg, SPR_NOACCESS,
5836                  0x00000000);
5837     /* XXX : not implemented */
5838     spr_register(env, SPR_PMC6, "PMC6",
5839                  SPR_NOACCESS, SPR_NOACCESS,
5840                  &spr_read_generic, &spr_write_generic,
5841                  0x00000000);
5842     /* XXX : not implemented */
5843     spr_register(env, SPR_UPMC6, "UPMC6",
5844                  &spr_read_ureg, SPR_NOACCESS,
5845                  &spr_read_ureg, SPR_NOACCESS,
5846                  0x00000000);
5847     /* SPRGs */
5848     spr_register(env, SPR_SPRG4, "SPRG4",
5849                  SPR_NOACCESS, SPR_NOACCESS,
5850                  &spr_read_generic, &spr_write_generic,
5851                  0x00000000);
5852     spr_register(env, SPR_USPRG4, "USPRG4",
5853                  &spr_read_ureg, SPR_NOACCESS,
5854                  &spr_read_ureg, SPR_NOACCESS,
5855                  0x00000000);
5856     spr_register(env, SPR_SPRG5, "SPRG5",
5857                  SPR_NOACCESS, SPR_NOACCESS,
5858                  &spr_read_generic, &spr_write_generic,
5859                  0x00000000);
5860     spr_register(env, SPR_USPRG5, "USPRG5",
5861                  &spr_read_ureg, SPR_NOACCESS,
5862                  &spr_read_ureg, SPR_NOACCESS,
5863                  0x00000000);
5864     spr_register(env, SPR_SPRG6, "SPRG6",
5865                  SPR_NOACCESS, SPR_NOACCESS,
5866                  &spr_read_generic, &spr_write_generic,
5867                  0x00000000);
5868     spr_register(env, SPR_USPRG6, "USPRG6",
5869                  &spr_read_ureg, SPR_NOACCESS,
5870                  &spr_read_ureg, SPR_NOACCESS,
5871                  0x00000000);
5872     spr_register(env, SPR_SPRG7, "SPRG7",
5873                  SPR_NOACCESS, SPR_NOACCESS,
5874                  &spr_read_generic, &spr_write_generic,
5875                  0x00000000);
5876     spr_register(env, SPR_USPRG7, "USPRG7",
5877                  &spr_read_ureg, SPR_NOACCESS,
5878                  &spr_read_ureg, SPR_NOACCESS,
5879                  0x00000000);
5880     /* Memory management */
5881     gen_low_BATs(env);
5882     gen_high_BATs(env);
5883     gen_74xx_soft_tlb(env, 128, 2);
5884     init_excp_7450(env);
5885     env->dcache_line_size = 32;
5886     env->icache_line_size = 32;
5887     /* Allocate hardware IRQ controller */
5888     ppc6xx_irq_init(env);
5889 }
5890
5891 #if defined (TARGET_PPC64)
5892 /* PowerPC 970                                                               */
5893 #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5894                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5895                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5896                               PPC_FLOAT_STFIWX |                              \
5897                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5898                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5899                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5900                               PPC_64B | PPC_ALTIVEC |                         \
5901                               PPC_SEGMENT_64B | PPC_SLBI)
5902 #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
5903 #define POWERPC_MMU_970      (POWERPC_MMU_64B)
5904 //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
5905 #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
5906 #define POWERPC_BFDM_970     (bfd_mach_ppc64)
5907 #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5908                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5909                               POWERPC_FLAG_BUS_CLK)
5910
5911 #if defined(CONFIG_USER_ONLY)
5912 #define POWERPC970_HID5_INIT 0x00000080
5913 #else
5914 #define POWERPC970_HID5_INIT 0x00000000
5915 #endif
5916
5917 static int check_pow_970 (CPUPPCState *env)
5918 {
5919     if (env->spr[SPR_HID0] & 0x00600000)
5920         return 1;
5921
5922     return 0;
5923 }
5924
5925 static void init_proc_970 (CPUPPCState *env)
5926 {
5927     gen_spr_ne_601(env);
5928     gen_spr_7xx(env);
5929     /* Time base */
5930     gen_tbl(env);
5931     /* Hardware implementation registers */
5932     /* XXX : not implemented */
5933     spr_register(env, SPR_HID0, "HID0",
5934                  SPR_NOACCESS, SPR_NOACCESS,
5935                  &spr_read_generic, &spr_write_clear,
5936                  0x60000000);
5937     /* XXX : not implemented */
5938     spr_register(env, SPR_HID1, "HID1",
5939                  SPR_NOACCESS, SPR_NOACCESS,
5940                  &spr_read_generic, &spr_write_generic,
5941                  0x00000000);
5942     /* XXX : not implemented */
5943     spr_register(env, SPR_750FX_HID2, "HID2",
5944                  SPR_NOACCESS, SPR_NOACCESS,
5945                  &spr_read_generic, &spr_write_generic,
5946                  0x00000000);
5947     /* XXX : not implemented */
5948     spr_register(env, SPR_970_HID5, "HID5",
5949                  SPR_NOACCESS, SPR_NOACCESS,
5950                  &spr_read_generic, &spr_write_generic,
5951                  POWERPC970_HID5_INIT);
5952     /* XXX : not implemented */
5953     spr_register(env, SPR_L2CR, "L2CR",
5954                  SPR_NOACCESS, SPR_NOACCESS,
5955                  &spr_read_generic, &spr_write_generic,
5956                  0x00000000);
5957     /* Memory management */
5958     /* XXX: not correct */
5959     gen_low_BATs(env);
5960     /* XXX : not implemented */
5961     spr_register(env, SPR_MMUCFG, "MMUCFG",
5962                  SPR_NOACCESS, SPR_NOACCESS,
5963                  &spr_read_generic, SPR_NOACCESS,
5964                  0x00000000); /* TOFIX */
5965     /* XXX : not implemented */
5966     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5967                  SPR_NOACCESS, SPR_NOACCESS,
5968                  &spr_read_generic, &spr_write_generic,
5969                  0x00000000); /* TOFIX */
5970     spr_register(env, SPR_HIOR, "SPR_HIOR",
5971                  SPR_NOACCESS, SPR_NOACCESS,
5972                  &spr_read_hior, &spr_write_hior,
5973                  0x00000000);
5974 #if !defined(CONFIG_USER_ONLY)
5975     env->slb_nr = 32;
5976 #endif
5977     init_excp_970(env);
5978     env->dcache_line_size = 128;
5979     env->icache_line_size = 128;
5980     /* Allocate hardware IRQ controller */
5981     ppc970_irq_init(env);
5982     /* Can't find information on what this should be on reset.  This
5983      * value is the one used by 74xx processors. */
5984     vscr_init(env, 0x00010000);
5985 }
5986
5987 /* PowerPC 970FX (aka G5)                                                    */
5988 #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5989                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5990                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5991                               PPC_FLOAT_STFIWX |                              \
5992                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5993                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5994                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5995                               PPC_64B | PPC_ALTIVEC |                         \
5996                               PPC_SEGMENT_64B | PPC_SLBI)
5997 #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
5998 #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
5999 #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
6000 #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
6001 #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
6002 #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6003                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6004                               POWERPC_FLAG_BUS_CLK)
6005
6006 static int check_pow_970FX (CPUPPCState *env)
6007 {
6008     if (env->spr[SPR_HID0] & 0x00600000)
6009         return 1;
6010
6011     return 0;
6012 }
6013
6014 static void init_proc_970FX (CPUPPCState *env)
6015 {
6016     gen_spr_ne_601(env);
6017     gen_spr_7xx(env);
6018     /* Time base */
6019     gen_tbl(env);
6020     /* Hardware implementation registers */
6021     /* XXX : not implemented */
6022     spr_register(env, SPR_HID0, "HID0",
6023                  SPR_NOACCESS, SPR_NOACCESS,
6024                  &spr_read_generic, &spr_write_clear,
6025                  0x60000000);
6026     /* XXX : not implemented */
6027     spr_register(env, SPR_HID1, "HID1",
6028                  SPR_NOACCESS, SPR_NOACCESS,
6029                  &spr_read_generic, &spr_write_generic,
6030                  0x00000000);
6031     /* XXX : not implemented */
6032     spr_register(env, SPR_750FX_HID2, "HID2",
6033                  SPR_NOACCESS, SPR_NOACCESS,
6034                  &spr_read_generic, &spr_write_generic,
6035                  0x00000000);
6036     /* XXX : not implemented */
6037     spr_register(env, SPR_970_HID5, "HID5",
6038                  SPR_NOACCESS, SPR_NOACCESS,
6039                  &spr_read_generic, &spr_write_generic,
6040                  POWERPC970_HID5_INIT);
6041     /* XXX : not implemented */
6042     spr_register(env, SPR_L2CR, "L2CR",
6043                  SPR_NOACCESS, SPR_NOACCESS,
6044                  &spr_read_generic, &spr_write_generic,
6045                  0x00000000);
6046     /* Memory management */
6047     /* XXX: not correct */
6048     gen_low_BATs(env);
6049     /* XXX : not implemented */
6050     spr_register(env, SPR_MMUCFG, "MMUCFG",
6051                  SPR_NOACCESS, SPR_NOACCESS,
6052                  &spr_read_generic, SPR_NOACCESS,
6053                  0x00000000); /* TOFIX */
6054     /* XXX : not implemented */
6055     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6056                  SPR_NOACCESS, SPR_NOACCESS,
6057                  &spr_read_generic, &spr_write_generic,
6058                  0x00000000); /* TOFIX */
6059     spr_register(env, SPR_HIOR, "SPR_HIOR",
6060                  SPR_NOACCESS, SPR_NOACCESS,
6061                  &spr_read_hior, &spr_write_hior,
6062                  0x00000000);
6063     spr_register(env, SPR_CTRL, "SPR_CTRL",
6064                  SPR_NOACCESS, SPR_NOACCESS,
6065                  &spr_read_generic, &spr_write_generic,
6066                  0x00000000);
6067     spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6068                  SPR_NOACCESS, SPR_NOACCESS,
6069                  &spr_read_generic, &spr_write_generic,
6070                  0x00000000);
6071     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6072                  &spr_read_generic, &spr_write_generic,
6073                  &spr_read_generic, &spr_write_generic,
6074                  0x00000000);
6075 #if !defined(CONFIG_USER_ONLY)
6076     env->slb_nr = 64;
6077 #endif
6078     init_excp_970(env);
6079     env->dcache_line_size = 128;
6080     env->icache_line_size = 128;
6081     /* Allocate hardware IRQ controller */
6082     ppc970_irq_init(env);
6083     /* Can't find information on what this should be on reset.  This
6084      * value is the one used by 74xx processors. */
6085     vscr_init(env, 0x00010000);
6086 }
6087
6088 /* PowerPC 970 GX                                                            */
6089 #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6090                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6091                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6092                               PPC_FLOAT_STFIWX |                              \
6093                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6094                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6095                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6096                               PPC_64B | PPC_ALTIVEC |                         \
6097                               PPC_SEGMENT_64B | PPC_SLBI)
6098 #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
6099 #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
6100 #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
6101 #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
6102 #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
6103 #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6104                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6105                               POWERPC_FLAG_BUS_CLK)
6106
6107 static int check_pow_970GX (CPUPPCState *env)
6108 {
6109     if (env->spr[SPR_HID0] & 0x00600000)
6110         return 1;
6111
6112     return 0;
6113 }
6114
6115 static void init_proc_970GX (CPUPPCState *env)
6116 {
6117     gen_spr_ne_601(env);
6118     gen_spr_7xx(env);
6119     /* Time base */
6120     gen_tbl(env);
6121     /* Hardware implementation registers */
6122     /* XXX : not implemented */
6123     spr_register(env, SPR_HID0, "HID0",
6124                  SPR_NOACCESS, SPR_NOACCESS,
6125                  &spr_read_generic, &spr_write_clear,
6126                  0x60000000);
6127     /* XXX : not implemented */
6128     spr_register(env, SPR_HID1, "HID1",
6129                  SPR_NOACCESS, SPR_NOACCESS,
6130                  &spr_read_generic, &spr_write_generic,
6131                  0x00000000);
6132     /* XXX : not implemented */
6133     spr_register(env, SPR_750FX_HID2, "HID2",
6134                  SPR_NOACCESS, SPR_NOACCESS,
6135                  &spr_read_generic, &spr_write_generic,
6136                  0x00000000);
6137     /* XXX : not implemented */
6138     spr_register(env, SPR_970_HID5, "HID5",
6139                  SPR_NOACCESS, SPR_NOACCESS,
6140                  &spr_read_generic, &spr_write_generic,
6141                  POWERPC970_HID5_INIT);
6142     /* XXX : not implemented */
6143     spr_register(env, SPR_L2CR, "L2CR",
6144                  SPR_NOACCESS, SPR_NOACCESS,
6145                  &spr_read_generic, &spr_write_generic,
6146                  0x00000000);
6147     /* Memory management */
6148     /* XXX: not correct */
6149     gen_low_BATs(env);
6150     /* XXX : not implemented */
6151     spr_register(env, SPR_MMUCFG, "MMUCFG",
6152                  SPR_NOACCESS, SPR_NOACCESS,
6153                  &spr_read_generic, SPR_NOACCESS,
6154                  0x00000000); /* TOFIX */
6155     /* XXX : not implemented */
6156     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6157                  SPR_NOACCESS, SPR_NOACCESS,
6158                  &spr_read_generic, &spr_write_generic,
6159                  0x00000000); /* TOFIX */
6160     spr_register(env, SPR_HIOR, "SPR_HIOR",
6161                  SPR_NOACCESS, SPR_NOACCESS,
6162                  &spr_read_hior, &spr_write_hior,
6163                  0x00000000);
6164 #if !defined(CONFIG_USER_ONLY)
6165     env->slb_nr = 32;
6166 #endif
6167     init_excp_970(env);
6168     env->dcache_line_size = 128;
6169     env->icache_line_size = 128;
6170     /* Allocate hardware IRQ controller */
6171     ppc970_irq_init(env);
6172     /* Can't find information on what this should be on reset.  This
6173      * value is the one used by 74xx processors. */
6174     vscr_init(env, 0x00010000);
6175 }
6176
6177 /* PowerPC 970 MP                                                            */
6178 #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6179                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6180                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6181                               PPC_FLOAT_STFIWX |                              \
6182                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6183                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6184                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6185                               PPC_64B | PPC_ALTIVEC |                         \
6186                               PPC_SEGMENT_64B | PPC_SLBI)
6187 #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
6188 #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
6189 #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
6190 #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
6191 #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
6192 #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6193                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6194                               POWERPC_FLAG_BUS_CLK)
6195
6196 static int check_pow_970MP (CPUPPCState *env)
6197 {
6198     if (env->spr[SPR_HID0] & 0x01C00000)
6199         return 1;
6200
6201     return 0;
6202 }
6203
6204 static void init_proc_970MP (CPUPPCState *env)
6205 {
6206     gen_spr_ne_601(env);
6207     gen_spr_7xx(env);
6208     /* Time base */
6209     gen_tbl(env);
6210     /* Hardware implementation registers */
6211     /* XXX : not implemented */
6212     spr_register(env, SPR_HID0, "HID0",
6213                  SPR_NOACCESS, SPR_NOACCESS,
6214                  &spr_read_generic, &spr_write_clear,
6215                  0x60000000);
6216     /* XXX : not implemented */
6217     spr_register(env, SPR_HID1, "HID1",
6218                  SPR_NOACCESS, SPR_NOACCESS,
6219                  &spr_read_generic, &spr_write_generic,
6220                  0x00000000);
6221     /* XXX : not implemented */
6222     spr_register(env, SPR_750FX_HID2, "HID2",
6223                  SPR_NOACCESS, SPR_NOACCESS,
6224                  &spr_read_generic, &spr_write_generic,
6225                  0x00000000);
6226     /* XXX : not implemented */
6227     spr_register(env, SPR_970_HID5, "HID5",
6228                  SPR_NOACCESS, SPR_NOACCESS,
6229                  &spr_read_generic, &spr_write_generic,
6230                  POWERPC970_HID5_INIT);
6231     /* XXX : not implemented */
6232     spr_register(env, SPR_L2CR, "L2CR",
6233                  SPR_NOACCESS, SPR_NOACCESS,
6234                  &spr_read_generic, &spr_write_generic,
6235                  0x00000000);
6236     /* Memory management */
6237     /* XXX: not correct */
6238     gen_low_BATs(env);
6239     /* XXX : not implemented */
6240     spr_register(env, SPR_MMUCFG, "MMUCFG",
6241                  SPR_NOACCESS, SPR_NOACCESS,
6242                  &spr_read_generic, SPR_NOACCESS,
6243                  0x00000000); /* TOFIX */
6244     /* XXX : not implemented */
6245     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6246                  SPR_NOACCESS, SPR_NOACCESS,
6247                  &spr_read_generic, &spr_write_generic,
6248                  0x00000000); /* TOFIX */
6249     spr_register(env, SPR_HIOR, "SPR_HIOR",
6250                  SPR_NOACCESS, SPR_NOACCESS,
6251                  &spr_read_hior, &spr_write_hior,
6252                  0x00000000);
6253 #if !defined(CONFIG_USER_ONLY)
6254     env->slb_nr = 32;
6255 #endif
6256     init_excp_970(env);
6257     env->dcache_line_size = 128;
6258     env->icache_line_size = 128;
6259     /* Allocate hardware IRQ controller */
6260     ppc970_irq_init(env);
6261     /* Can't find information on what this should be on reset.  This
6262      * value is the one used by 74xx processors. */
6263     vscr_init(env, 0x00010000);
6264 }
6265
6266 /* PowerPC 620                                                               */
6267 #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6268                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6269                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6270                               PPC_FLOAT_STFIWX |                              \
6271                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
6272                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6273                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6274                               PPC_SEGMENT | PPC_EXTERN |                      \
6275                               PPC_64B | PPC_SLBI)
6276 #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
6277 //#define POWERPC_MMU_620      (POWERPC_MMU_620)
6278 #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
6279 #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
6280 #define POWERPC_BFDM_620     (bfd_mach_ppc64)
6281 #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
6282                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6283 #define check_pow_620        check_pow_nocheck /* Check this */
6284
6285 __attribute__ (( unused ))
6286 static void init_proc_620 (CPUPPCState *env)
6287 {
6288     gen_spr_ne_601(env);
6289     gen_spr_620(env);
6290     /* Time base */
6291     gen_tbl(env);
6292     /* Hardware implementation registers */
6293     /* XXX : not implemented */
6294     spr_register(env, SPR_HID0, "HID0",
6295                  SPR_NOACCESS, SPR_NOACCESS,
6296                  &spr_read_generic, &spr_write_generic,
6297                  0x00000000);
6298     /* Memory management */
6299     gen_low_BATs(env);
6300     init_excp_620(env);
6301     env->dcache_line_size = 64;
6302     env->icache_line_size = 64;
6303     /* Allocate hardware IRQ controller */
6304     ppc6xx_irq_init(env);
6305 }
6306 #endif /* defined (TARGET_PPC64) */
6307
6308 /* Default 32 bits PowerPC target will be 604 */
6309 #define CPU_POWERPC_PPC32     CPU_POWERPC_604
6310 #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
6311 #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
6312 #define POWERPC_MMU_PPC32     POWERPC_MMU_604
6313 #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
6314 #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
6315 #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
6316 #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
6317 #define check_pow_PPC32       check_pow_604
6318 #define init_proc_PPC32       init_proc_604
6319
6320 /* Default 64 bits PowerPC target will be 970 FX */
6321 #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
6322 #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
6323 #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
6324 #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
6325 #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
6326 #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
6327 #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
6328 #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
6329 #define check_pow_PPC64       check_pow_970FX
6330 #define init_proc_PPC64       init_proc_970FX
6331
6332 /* Default PowerPC target will be PowerPC 32 */
6333 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6334 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
6335 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6336 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
6337 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
6338 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
6339 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6340 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
6341 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
6342 #define check_pow_DEFAULT     check_pow_PPC64
6343 #define init_proc_DEFAULT     init_proc_PPC64
6344 #else
6345 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
6346 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6347 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
6348 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
6349 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
6350 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6351 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
6352 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
6353 #define check_pow_DEFAULT     check_pow_PPC32
6354 #define init_proc_DEFAULT     init_proc_PPC32
6355 #endif
6356
6357 /*****************************************************************************/
6358 /* PVR definitions for most known PowerPC                                    */
6359 enum {
6360     /* PowerPC 401 family */
6361     /* Generic PowerPC 401 */
6362 #define CPU_POWERPC_401              CPU_POWERPC_401G2
6363     /* PowerPC 401 cores */
6364     CPU_POWERPC_401A1              = 0x00210000,
6365     CPU_POWERPC_401B2              = 0x00220000,
6366 #if 0
6367     CPU_POWERPC_401B3              = xxx,
6368 #endif
6369     CPU_POWERPC_401C2              = 0x00230000,
6370     CPU_POWERPC_401D2              = 0x00240000,
6371     CPU_POWERPC_401E2              = 0x00250000,
6372     CPU_POWERPC_401F2              = 0x00260000,
6373     CPU_POWERPC_401G2              = 0x00270000,
6374     /* PowerPC 401 microcontrolers */
6375 #if 0
6376     CPU_POWERPC_401GF              = xxx,
6377 #endif
6378 #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
6379     /* IBM Processor for Network Resources */
6380     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
6381 #if 0
6382     CPU_POWERPC_XIPCHIP            = xxx,
6383 #endif
6384     /* PowerPC 403 family */
6385     /* Generic PowerPC 403 */
6386 #define CPU_POWERPC_403              CPU_POWERPC_403GC
6387     /* PowerPC 403 microcontrollers */
6388     CPU_POWERPC_403GA              = 0x00200011,
6389     CPU_POWERPC_403GB              = 0x00200100,
6390     CPU_POWERPC_403GC              = 0x00200200,
6391     CPU_POWERPC_403GCX             = 0x00201400,
6392 #if 0
6393     CPU_POWERPC_403GP              = xxx,
6394 #endif
6395     /* PowerPC 405 family */
6396     /* Generic PowerPC 405 */
6397 #define CPU_POWERPC_405              CPU_POWERPC_405D4
6398     /* PowerPC 405 cores */
6399 #if 0
6400     CPU_POWERPC_405A3              = xxx,
6401 #endif
6402 #if 0
6403     CPU_POWERPC_405A4              = xxx,
6404 #endif
6405 #if 0
6406     CPU_POWERPC_405B3              = xxx,
6407 #endif
6408 #if 0
6409     CPU_POWERPC_405B4              = xxx,
6410 #endif
6411 #if 0
6412     CPU_POWERPC_405C3              = xxx,
6413 #endif
6414 #if 0
6415     CPU_POWERPC_405C4              = xxx,
6416 #endif
6417     CPU_POWERPC_405D2              = 0x20010000,
6418 #if 0
6419     CPU_POWERPC_405D3              = xxx,
6420 #endif
6421     CPU_POWERPC_405D4              = 0x41810000,
6422 #if 0
6423     CPU_POWERPC_405D5              = xxx,
6424 #endif
6425 #if 0
6426     CPU_POWERPC_405E4              = xxx,
6427 #endif
6428 #if 0
6429     CPU_POWERPC_405F4              = xxx,
6430 #endif
6431 #if 0
6432     CPU_POWERPC_405F5              = xxx,
6433 #endif
6434 #if 0
6435     CPU_POWERPC_405F6              = xxx,
6436 #endif
6437     /* PowerPC 405 microcontrolers */
6438     /* XXX: missing 0x200108a0 */
6439 #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
6440     CPU_POWERPC_405CRa             = 0x40110041,
6441     CPU_POWERPC_405CRb             = 0x401100C5,
6442     CPU_POWERPC_405CRc             = 0x40110145,
6443     CPU_POWERPC_405EP              = 0x51210950,
6444 #if 0
6445     CPU_POWERPC_405EXr             = xxx,
6446 #endif
6447     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
6448 #if 0
6449     CPU_POWERPC_405FX              = xxx,
6450 #endif
6451 #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
6452     CPU_POWERPC_405GPa             = 0x40110000,
6453     CPU_POWERPC_405GPb             = 0x40110040,
6454     CPU_POWERPC_405GPc             = 0x40110082,
6455     CPU_POWERPC_405GPd             = 0x401100C4,
6456 #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
6457     CPU_POWERPC_405GPR             = 0x50910951,
6458 #if 0
6459     CPU_POWERPC_405H               = xxx,
6460 #endif
6461 #if 0
6462     CPU_POWERPC_405L               = xxx,
6463 #endif
6464     CPU_POWERPC_405LP              = 0x41F10000,
6465 #if 0
6466     CPU_POWERPC_405PM              = xxx,
6467 #endif
6468 #if 0
6469     CPU_POWERPC_405PS              = xxx,
6470 #endif
6471 #if 0
6472     CPU_POWERPC_405S               = xxx,
6473 #endif
6474     /* IBM network processors */
6475     CPU_POWERPC_NPE405H            = 0x414100C0,
6476     CPU_POWERPC_NPE405H2           = 0x41410140,
6477     CPU_POWERPC_NPE405L            = 0x416100C0,
6478     CPU_POWERPC_NPE4GS3            = 0x40B10000,
6479 #if 0
6480     CPU_POWERPC_NPCxx1             = xxx,
6481 #endif
6482 #if 0
6483     CPU_POWERPC_NPR161             = xxx,
6484 #endif
6485 #if 0
6486     CPU_POWERPC_LC77700            = xxx,
6487 #endif
6488     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6489 #if 0
6490     CPU_POWERPC_STB01000           = xxx,
6491 #endif
6492 #if 0
6493     CPU_POWERPC_STB01010           = xxx,
6494 #endif
6495 #if 0
6496     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
6497 #endif
6498     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
6499 #if 0
6500     CPU_POWERPC_STB043             = xxx,
6501 #endif
6502 #if 0
6503     CPU_POWERPC_STB045             = xxx,
6504 #endif
6505     CPU_POWERPC_STB04              = 0x41810000,
6506     CPU_POWERPC_STB25              = 0x51510950,
6507 #if 0
6508     CPU_POWERPC_STB130             = xxx,
6509 #endif
6510     /* Xilinx cores */
6511     CPU_POWERPC_X2VP4              = 0x20010820,
6512 #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
6513     CPU_POWERPC_X2VP20             = 0x20010860,
6514 #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
6515 #if 0
6516     CPU_POWERPC_ZL10310            = xxx,
6517 #endif
6518 #if 0
6519     CPU_POWERPC_ZL10311            = xxx,
6520 #endif
6521 #if 0
6522     CPU_POWERPC_ZL10320            = xxx,
6523 #endif
6524 #if 0
6525     CPU_POWERPC_ZL10321            = xxx,
6526 #endif
6527     /* PowerPC 440 family */
6528     /* Generic PowerPC 440 */
6529 #define CPU_POWERPC_440              CPU_POWERPC_440GXf
6530     /* PowerPC 440 cores */
6531 #if 0
6532     CPU_POWERPC_440A4              = xxx,
6533 #endif
6534 #if 0
6535     CPU_POWERPC_440A5              = xxx,
6536 #endif
6537 #if 0
6538     CPU_POWERPC_440B4              = xxx,
6539 #endif
6540 #if 0
6541     CPU_POWERPC_440F5              = xxx,
6542 #endif
6543 #if 0
6544     CPU_POWERPC_440G5              = xxx,
6545 #endif
6546 #if 0
6547     CPU_POWERPC_440H4              = xxx,
6548 #endif
6549 #if 0
6550     CPU_POWERPC_440H6              = xxx,
6551 #endif
6552     /* PowerPC 440 microcontrolers */
6553 #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
6554     CPU_POWERPC_440EPa             = 0x42221850,
6555     CPU_POWERPC_440EPb             = 0x422218D3,
6556 #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
6557     CPU_POWERPC_440GPb             = 0x40120440,
6558     CPU_POWERPC_440GPc             = 0x40120481,
6559 #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
6560 #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
6561     CPU_POWERPC_440GRX             = 0x200008D0,
6562 #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
6563 #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
6564     CPU_POWERPC_440GXa             = 0x51B21850,
6565     CPU_POWERPC_440GXb             = 0x51B21851,
6566     CPU_POWERPC_440GXc             = 0x51B21892,
6567     CPU_POWERPC_440GXf             = 0x51B21894,
6568 #if 0
6569     CPU_POWERPC_440S               = xxx,
6570 #endif
6571     CPU_POWERPC_440SP              = 0x53221850,
6572     CPU_POWERPC_440SP2             = 0x53221891,
6573     CPU_POWERPC_440SPE             = 0x53421890,
6574     /* PowerPC 460 family */
6575 #if 0
6576     /* Generic PowerPC 464 */
6577 #define CPU_POWERPC_464              CPU_POWERPC_464H90
6578 #endif
6579     /* PowerPC 464 microcontrolers */
6580 #if 0
6581     CPU_POWERPC_464H90             = xxx,
6582 #endif
6583 #if 0
6584     CPU_POWERPC_464H90FP           = xxx,
6585 #endif
6586     /* Freescale embedded PowerPC cores */
6587     /* PowerPC MPC 5xx cores (aka RCPU) */
6588     CPU_POWERPC_MPC5xx             = 0x00020020,
6589 #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
6590 #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
6591 #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
6592 #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
6593 #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
6594 #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
6595 #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
6596 #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
6597 #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
6598 #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
6599 #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
6600 #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
6601 #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
6602     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6603     CPU_POWERPC_MPC8xx             = 0x00500000,
6604 #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
6605 #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
6606 #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
6607 #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
6608 #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
6609 #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
6610 #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
6611 #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
6612 #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
6613 #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
6614 #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
6615 #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
6616 #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
6617 #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
6618 #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
6619     /* G2 cores (aka PowerQUICC-II) */
6620     CPU_POWERPC_G2                 = 0x00810011,
6621     CPU_POWERPC_G2H4               = 0x80811010,
6622     CPU_POWERPC_G2gp               = 0x80821010,
6623     CPU_POWERPC_G2ls               = 0x90810010,
6624     CPU_POWERPC_MPC603             = 0x00810100,
6625     CPU_POWERPC_G2_HIP3            = 0x00810101,
6626     CPU_POWERPC_G2_HIP4            = 0x80811014,
6627     /*   G2_LE core (aka PowerQUICC-II) */
6628     CPU_POWERPC_G2LE               = 0x80820010,
6629     CPU_POWERPC_G2LEgp             = 0x80822010,
6630     CPU_POWERPC_G2LEls             = 0xA0822010,
6631     CPU_POWERPC_G2LEgp1            = 0x80822011,
6632     CPU_POWERPC_G2LEgp3            = 0x80822013,
6633     /* MPC52xx microcontrollers  */
6634     /* XXX: MPC 5121 ? */
6635 #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
6636 #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
6637 #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
6638 #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
6639 #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
6640 #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
6641 #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
6642 #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
6643     /* MPC82xx microcontrollers */
6644 #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
6645 #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
6646 #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
6647 #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
6648 #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
6649 #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
6650 #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
6651 #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
6652 #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
6653 #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
6654 #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
6655 #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
6656 #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
6657 #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
6658 #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
6659 #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
6660 #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
6661 #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
6662 #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
6663 #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
6664 #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
6665 #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
6666 #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
6667 #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
6668 #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
6669 #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
6670 #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
6671 #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
6672 #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
6673     /* e200 family */
6674     /* e200 cores */
6675 #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
6676 #if 0
6677     CPU_POWERPC_e200z0             = xxx,
6678 #endif
6679 #if 0
6680     CPU_POWERPC_e200z1             = xxx,
6681 #endif
6682 #if 0 /* ? */
6683     CPU_POWERPC_e200z3             = 0x81120000,
6684 #endif
6685     CPU_POWERPC_e200z5             = 0x81000000,
6686     CPU_POWERPC_e200z6             = 0x81120000,
6687     /* MPC55xx microcontrollers */
6688 #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
6689 #if 0
6690 #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
6691 #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
6692 #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
6693 #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
6694 #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
6695 #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
6696 #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
6697 #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
6698 #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
6699 #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
6700 #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
6701 #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
6702 #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
6703 #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
6704 #endif
6705 #if 0
6706 #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
6707 #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
6708 #endif
6709 #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
6710 #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
6711 #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
6712 #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
6713 #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
6714 #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
6715     /* e300 family */
6716     /* e300 cores */
6717 #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
6718     CPU_POWERPC_e300c1             = 0x00830010,
6719     CPU_POWERPC_e300c2             = 0x00840010,
6720     CPU_POWERPC_e300c3             = 0x00850010,
6721     CPU_POWERPC_e300c4             = 0x00860010,
6722     /* MPC83xx microcontrollers */
6723 #define CPU_POWERPC_MPC8313          CPU_POWERPC_e300c3
6724 #define CPU_POWERPC_MPC8313E         CPU_POWERPC_e300c3
6725 #define CPU_POWERPC_MPC8314          CPU_POWERPC_e300c3
6726 #define CPU_POWERPC_MPC8314E         CPU_POWERPC_e300c3
6727 #define CPU_POWERPC_MPC8315          CPU_POWERPC_e300c3
6728 #define CPU_POWERPC_MPC8315E         CPU_POWERPC_e300c3
6729 #define CPU_POWERPC_MPC8321          CPU_POWERPC_e300c2
6730 #define CPU_POWERPC_MPC8321E         CPU_POWERPC_e300c2
6731 #define CPU_POWERPC_MPC8323          CPU_POWERPC_e300c2
6732 #define CPU_POWERPC_MPC8323E         CPU_POWERPC_e300c2
6733 #define CPU_POWERPC_MPC8343A         CPU_POWERPC_e300c1
6734 #define CPU_POWERPC_MPC8343EA        CPU_POWERPC_e300c1
6735 #define CPU_POWERPC_MPC8347A         CPU_POWERPC_e300c1
6736 #define CPU_POWERPC_MPC8347AT        CPU_POWERPC_e300c1
6737 #define CPU_POWERPC_MPC8347AP        CPU_POWERPC_e300c1
6738 #define CPU_POWERPC_MPC8347EA        CPU_POWERPC_e300c1
6739 #define CPU_POWERPC_MPC8347EAT       CPU_POWERPC_e300c1
6740 #define CPU_POWERPC_MPC8347EAP       CPU_POWERPC_e300c1
6741 #define CPU_POWERPC_MPC8349          CPU_POWERPC_e300c1
6742 #define CPU_POWERPC_MPC8349A         CPU_POWERPC_e300c1
6743 #define CPU_POWERPC_MPC8349E         CPU_POWERPC_e300c1
6744 #define CPU_POWERPC_MPC8349EA        CPU_POWERPC_e300c1
6745 #define CPU_POWERPC_MPC8358E         CPU_POWERPC_e300c1
6746 #define CPU_POWERPC_MPC8360E         CPU_POWERPC_e300c1
6747 #define CPU_POWERPC_MPC8377          CPU_POWERPC_e300c4
6748 #define CPU_POWERPC_MPC8377E         CPU_POWERPC_e300c4
6749 #define CPU_POWERPC_MPC8378          CPU_POWERPC_e300c4
6750 #define CPU_POWERPC_MPC8378E         CPU_POWERPC_e300c4
6751 #define CPU_POWERPC_MPC8379          CPU_POWERPC_e300c4
6752 #define CPU_POWERPC_MPC8379E         CPU_POWERPC_e300c4
6753     /* e500 family */
6754     /* e500 cores  */
6755 #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
6756 #define CPU_POWERPC_e500v1           CPU_POWERPC_e500v1_v20
6757 #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
6758     CPU_POWERPC_e500v1_v10         = 0x80200010,
6759     CPU_POWERPC_e500v1_v20         = 0x80200020,
6760     CPU_POWERPC_e500v2_v10         = 0x80210010,
6761     CPU_POWERPC_e500v2_v11         = 0x80210011,
6762     CPU_POWERPC_e500v2_v20         = 0x80210020,
6763     CPU_POWERPC_e500v2_v21         = 0x80210021,
6764     CPU_POWERPC_e500v2_v22         = 0x80210022,
6765     CPU_POWERPC_e500v2_v30         = 0x80210030,
6766     /* MPC85xx microcontrollers */
6767 #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
6768 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
6769 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
6770 #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
6771 #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
6772 #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
6773 #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
6774 #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500v1_v10
6775 #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500v1_v20
6776 #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500v1_v20
6777 #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
6778 #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500v1_v20
6779 #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500v1_v20
6780 #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
6781 #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500v1_v20
6782 #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500v1_v20
6783 #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
6784 #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
6785 #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
6786 #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
6787 #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
6788 #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
6789 #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
6790 #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
6791 #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
6792 #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
6793 #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
6794 #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
6795 #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
6796 #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
6797 #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
6798 #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
6799 #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
6800 #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
6801 #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
6802 #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
6803 #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
6804 #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
6805 #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
6806 #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
6807 #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
6808 #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
6809 #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
6810 #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
6811 #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
6812 #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
6813 #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
6814 #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
6815 #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
6816 #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
6817 #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
6818 #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
6819 #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
6820 #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
6821 #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
6822 #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
6823 #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
6824 #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
6825 #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
6826 #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
6827 #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
6828 #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
6829 #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
6830 #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
6831 #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
6832 #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
6833 #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
6834 #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
6835 #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
6836 #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
6837     /* e600 family */
6838     /* e600 cores */
6839     CPU_POWERPC_e600               = 0x80040010,
6840     /* MPC86xx microcontrollers */
6841 #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
6842 #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
6843 #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
6844     /* PowerPC 6xx cores */
6845 #define CPU_POWERPC_601              CPU_POWERPC_601_v2
6846     CPU_POWERPC_601_v0             = 0x00010001,
6847     CPU_POWERPC_601_v1             = 0x00010001,
6848 #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
6849     CPU_POWERPC_601_v2             = 0x00010002,
6850     CPU_POWERPC_602                = 0x00050100,
6851     CPU_POWERPC_603                = 0x00030100,
6852 #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
6853     CPU_POWERPC_603E_v11           = 0x00060101,
6854     CPU_POWERPC_603E_v12           = 0x00060102,
6855     CPU_POWERPC_603E_v13           = 0x00060103,
6856     CPU_POWERPC_603E_v14           = 0x00060104,
6857     CPU_POWERPC_603E_v22           = 0x00060202,
6858     CPU_POWERPC_603E_v3            = 0x00060300,
6859     CPU_POWERPC_603E_v4            = 0x00060400,
6860     CPU_POWERPC_603E_v41           = 0x00060401,
6861     CPU_POWERPC_603E7t             = 0x00071201,
6862     CPU_POWERPC_603E7v             = 0x00070100,
6863     CPU_POWERPC_603E7v1            = 0x00070101,
6864     CPU_POWERPC_603E7v2            = 0x00070201,
6865     CPU_POWERPC_603E7              = 0x00070200,
6866     CPU_POWERPC_603P               = 0x00070000,
6867 #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
6868     /* XXX: missing 0x00040303 (604) */
6869     CPU_POWERPC_604                = 0x00040103,
6870 #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
6871     /* XXX: missing 0x00091203 */
6872     /* XXX: missing 0x00092110 */
6873     /* XXX: missing 0x00092120 */
6874     CPU_POWERPC_604E_v10           = 0x00090100,
6875     CPU_POWERPC_604E_v22           = 0x00090202,
6876     CPU_POWERPC_604E_v24           = 0x00090204,
6877     /* XXX: missing 0x000a0100 */
6878     /* XXX: missing 0x00093102 */
6879     CPU_POWERPC_604R               = 0x000a0101,
6880 #if 0
6881     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
6882 #endif
6883     /* PowerPC 740/750 cores (aka G3) */
6884     /* XXX: missing 0x00084202 */
6885 #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
6886     CPU_POWERPC_7x0_v10            = 0x00080100,
6887     CPU_POWERPC_7x0_v20            = 0x00080200,
6888     CPU_POWERPC_7x0_v21            = 0x00080201,
6889     CPU_POWERPC_7x0_v22            = 0x00080202,
6890     CPU_POWERPC_7x0_v30            = 0x00080300,
6891     CPU_POWERPC_7x0_v31            = 0x00080301,
6892     CPU_POWERPC_740E               = 0x00080100,
6893     CPU_POWERPC_750E               = 0x00080200,
6894     CPU_POWERPC_7x0P               = 0x10080000,
6895     /* XXX: missing 0x00087010 (CL ?) */
6896 #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
6897     CPU_POWERPC_750CL_v10          = 0x00087200,
6898     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
6899 #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
6900     CPU_POWERPC_750CX_v10          = 0x00082100,
6901     CPU_POWERPC_750CX_v20          = 0x00082200,
6902     CPU_POWERPC_750CX_v21          = 0x00082201,
6903     CPU_POWERPC_750CX_v22          = 0x00082202,
6904 #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
6905     CPU_POWERPC_750CXE_v21         = 0x00082211,
6906     CPU_POWERPC_750CXE_v22         = 0x00082212,
6907     CPU_POWERPC_750CXE_v23         = 0x00082213,
6908     CPU_POWERPC_750CXE_v24         = 0x00082214,
6909     CPU_POWERPC_750CXE_v24b        = 0x00083214,
6910     CPU_POWERPC_750CXE_v30         = 0x00082310,
6911     CPU_POWERPC_750CXE_v31         = 0x00082311,
6912     CPU_POWERPC_750CXE_v31b        = 0x00083311,
6913     CPU_POWERPC_750CXR             = 0x00083410,
6914     CPU_POWERPC_750FL              = 0x70000203,
6915 #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
6916     CPU_POWERPC_750FX_v10          = 0x70000100,
6917     CPU_POWERPC_750FX_v20          = 0x70000200,
6918     CPU_POWERPC_750FX_v21          = 0x70000201,
6919     CPU_POWERPC_750FX_v22          = 0x70000202,
6920     CPU_POWERPC_750FX_v23          = 0x70000203,
6921     CPU_POWERPC_750GL              = 0x70020102,
6922 #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
6923     CPU_POWERPC_750GX_v10          = 0x70020100,
6924     CPU_POWERPC_750GX_v11          = 0x70020101,
6925     CPU_POWERPC_750GX_v12          = 0x70020102,
6926 #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
6927     CPU_POWERPC_750L_v20           = 0x00088200,
6928     CPU_POWERPC_750L_v21           = 0x00088201,
6929     CPU_POWERPC_750L_v22           = 0x00088202,
6930     CPU_POWERPC_750L_v30           = 0x00088300,
6931     CPU_POWERPC_750L_v32           = 0x00088302,
6932     /* PowerPC 745/755 cores */
6933 #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
6934     CPU_POWERPC_7x5_v10            = 0x00083100,
6935     CPU_POWERPC_7x5_v11            = 0x00083101,
6936     CPU_POWERPC_7x5_v20            = 0x00083200,
6937     CPU_POWERPC_7x5_v21            = 0x00083201,
6938     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
6939     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
6940     CPU_POWERPC_7x5_v24            = 0x00083204,
6941     CPU_POWERPC_7x5_v25            = 0x00083205,
6942     CPU_POWERPC_7x5_v26            = 0x00083206,
6943     CPU_POWERPC_7x5_v27            = 0x00083207,
6944     CPU_POWERPC_7x5_v28            = 0x00083208,
6945 #if 0
6946     CPU_POWERPC_7x5P               = xxx,
6947 #endif
6948     /* PowerPC 74xx cores (aka G4) */
6949     /* XXX: missing 0x000C1101 */
6950 #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
6951     CPU_POWERPC_7400_v10           = 0x000C0100,
6952     CPU_POWERPC_7400_v11           = 0x000C0101,
6953     CPU_POWERPC_7400_v20           = 0x000C0200,
6954     CPU_POWERPC_7400_v21           = 0x000C0201,
6955     CPU_POWERPC_7400_v22           = 0x000C0202,
6956     CPU_POWERPC_7400_v26           = 0x000C0206,
6957     CPU_POWERPC_7400_v27           = 0x000C0207,
6958     CPU_POWERPC_7400_v28           = 0x000C0208,
6959     CPU_POWERPC_7400_v29           = 0x000C0209,
6960 #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
6961     CPU_POWERPC_7410_v10           = 0x800C1100,
6962     CPU_POWERPC_7410_v11           = 0x800C1101,
6963     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
6964     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
6965     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
6966 #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
6967     CPU_POWERPC_7448_v10           = 0x80040100,
6968     CPU_POWERPC_7448_v11           = 0x80040101,
6969     CPU_POWERPC_7448_v20           = 0x80040200,
6970     CPU_POWERPC_7448_v21           = 0x80040201,
6971 #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
6972     CPU_POWERPC_7450_v10           = 0x80000100,
6973     CPU_POWERPC_7450_v11           = 0x80000101,
6974     CPU_POWERPC_7450_v12           = 0x80000102,
6975     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
6976     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
6977 #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
6978     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
6979     /* XXX: this entry might be a bug in some documentation */
6980     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
6981 #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
6982     CPU_POWERPC_74x5_v10           = 0x80010100,
6983     /* XXX: missing 0x80010200 */
6984     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
6985     CPU_POWERPC_74x5_v32           = 0x80010302,
6986     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
6987     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
6988 #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
6989     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
6990     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
6991     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
6992 #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
6993     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
6994     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
6995     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
6996     /* 64 bits PowerPC */
6997 #if defined(TARGET_PPC64)
6998     CPU_POWERPC_620                = 0x00140000,
6999     CPU_POWERPC_630                = 0x00400000,
7000     CPU_POWERPC_631                = 0x00410104,
7001     CPU_POWERPC_POWER4             = 0x00350000,
7002     CPU_POWERPC_POWER4P            = 0x00380000,
7003      /* XXX: missing 0x003A0201 */
7004     CPU_POWERPC_POWER5             = 0x003A0203,
7005 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
7006     CPU_POWERPC_POWER5P            = 0x003B0000,
7007 #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
7008     CPU_POWERPC_POWER6             = 0x003E0000,
7009     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
7010     CPU_POWERPC_POWER6A            = 0x0F000002,
7011     CPU_POWERPC_970                = 0x00390202,
7012 #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
7013     CPU_POWERPC_970FX_v10          = 0x00391100,
7014     CPU_POWERPC_970FX_v20          = 0x003C0200,
7015     CPU_POWERPC_970FX_v21          = 0x003C0201,
7016     CPU_POWERPC_970FX_v30          = 0x003C0300,
7017     CPU_POWERPC_970FX_v31          = 0x003C0301,
7018     CPU_POWERPC_970GX              = 0x00450000,
7019 #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
7020     CPU_POWERPC_970MP_v10          = 0x00440100,
7021     CPU_POWERPC_970MP_v11          = 0x00440101,
7022 #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
7023     CPU_POWERPC_CELL_v10           = 0x00700100,
7024     CPU_POWERPC_CELL_v20           = 0x00700400,
7025     CPU_POWERPC_CELL_v30           = 0x00700500,
7026     CPU_POWERPC_CELL_v31           = 0x00700501,
7027 #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
7028     CPU_POWERPC_RS64               = 0x00330000,
7029     CPU_POWERPC_RS64II             = 0x00340000,
7030     CPU_POWERPC_RS64III            = 0x00360000,
7031     CPU_POWERPC_RS64IV             = 0x00370000,
7032 #endif /* defined(TARGET_PPC64) */
7033     /* Original POWER */
7034     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7035      * POWER2 (RIOS2) & RSC2 (P2SC) here
7036      */
7037 #if 0
7038     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7039 #endif
7040 #if 0
7041     CPU_POWER2                     = xxx, /* 0x40000 ? */
7042 #endif
7043     /* PA Semi core */
7044     CPU_POWERPC_PA6T               = 0x00900000,
7045 };
7046
7047 /* System version register (used on MPC 8xxx)                                */
7048 enum {
7049     POWERPC_SVR_NONE               = 0x00000000,
7050 #define POWERPC_SVR_52xx             POWERPC_SVR_5200
7051 #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
7052     POWERPC_SVR_5200_v10           = 0x80110010,
7053     POWERPC_SVR_5200_v11           = 0x80110011,
7054     POWERPC_SVR_5200_v12           = 0x80110012,
7055 #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
7056     POWERPC_SVR_5200B_v20          = 0x80110020,
7057     POWERPC_SVR_5200B_v21          = 0x80110021,
7058 #define POWERPC_SVR_55xx             POWERPC_SVR_5567
7059 #if 0
7060     POWERPC_SVR_5533               = xxx,
7061 #endif
7062 #if 0
7063     POWERPC_SVR_5534               = xxx,
7064 #endif
7065 #if 0
7066     POWERPC_SVR_5553               = xxx,
7067 #endif
7068 #if 0
7069     POWERPC_SVR_5554               = xxx,
7070 #endif
7071 #if 0
7072     POWERPC_SVR_5561               = xxx,
7073 #endif
7074 #if 0
7075     POWERPC_SVR_5565               = xxx,
7076 #endif
7077 #if 0
7078     POWERPC_SVR_5566               = xxx,
7079 #endif
7080 #if 0
7081     POWERPC_SVR_5567               = xxx,
7082 #endif
7083 #if 0
7084     POWERPC_SVR_8313               = xxx,
7085 #endif
7086 #if 0
7087     POWERPC_SVR_8313E              = xxx,
7088 #endif
7089 #if 0
7090     POWERPC_SVR_8314               = xxx,
7091 #endif
7092 #if 0
7093     POWERPC_SVR_8314E              = xxx,
7094 #endif
7095 #if 0
7096     POWERPC_SVR_8315               = xxx,
7097 #endif
7098 #if 0
7099     POWERPC_SVR_8315E              = xxx,
7100 #endif
7101 #if 0
7102     POWERPC_SVR_8321               = xxx,
7103 #endif
7104 #if 0
7105     POWERPC_SVR_8321E              = xxx,
7106 #endif
7107 #if 0
7108     POWERPC_SVR_8323               = xxx,
7109 #endif
7110 #if 0
7111     POWERPC_SVR_8323E              = xxx,
7112 #endif
7113     POWERPC_SVR_8343A              = 0x80570030,
7114     POWERPC_SVR_8343EA             = 0x80560030,
7115 #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
7116     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
7117     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
7118 #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
7119     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
7120     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
7121     POWERPC_SVR_8349               = 0x80510010,
7122     POWERPC_SVR_8349A              = 0x80510030,
7123     POWERPC_SVR_8349E              = 0x80500010,
7124     POWERPC_SVR_8349EA             = 0x80500030,
7125 #if 0
7126     POWERPC_SVR_8358E              = xxx,
7127 #endif
7128 #if 0
7129     POWERPC_SVR_8360E              = xxx,
7130 #endif
7131 #define POWERPC_SVR_E500             0x40000000
7132     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
7133     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
7134     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
7135     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
7136     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
7137     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
7138 #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
7139     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
7140     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
7141 #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
7142     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
7143     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
7144 #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
7145     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
7146     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
7147     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
7148 #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
7149     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
7150     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
7151 #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
7152     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
7153     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
7154 #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
7155     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
7156     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
7157     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
7158     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
7159 #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
7160     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
7161     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
7162     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
7163     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
7164 #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
7165     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
7166     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
7167 #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
7168     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
7169     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
7170 #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
7171     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
7172     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
7173 #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
7174     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
7175     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
7176 #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
7177     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
7178     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
7179 #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
7180     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
7181     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
7182     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
7183     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
7184 #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
7185     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
7186     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
7187     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
7188     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
7189 #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
7190     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
7191     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
7192 #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
7193     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
7194     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
7195 #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
7196     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
7197     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
7198     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
7199     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
7200     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
7201     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
7202     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
7203     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
7204     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
7205 #if 0
7206     POWERPC_SVR_8610               = xxx,
7207 #endif
7208     POWERPC_SVR_8641               = 0x80900021,
7209     POWERPC_SVR_8641D              = 0x80900121,
7210 };
7211
7212 /*****************************************************************************/
7213 /* PowerPC CPU definitions                                                   */
7214 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
7215     {                                                                         \
7216         .name        = _name,                                                 \
7217         .pvr         = _pvr,                                                  \
7218         .svr         = _svr,                                                  \
7219         .insns_flags = glue(POWERPC_INSNS_,_type),                            \
7220         .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
7221         .mmu_model   = glue(POWERPC_MMU_,_type),                              \
7222         .excp_model  = glue(POWERPC_EXCP_,_type),                             \
7223         .bus_model   = glue(POWERPC_INPUT_,_type),                            \
7224         .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
7225         .flags       = glue(POWERPC_FLAG_,_type),                             \
7226         .init_proc   = &glue(init_proc_,_type),                               \
7227         .check_pow   = &glue(check_pow_,_type),                               \
7228     }
7229 #define POWERPC_DEF(_name, _pvr, _type)                                       \
7230 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7231
7232 static const ppc_def_t ppc_defs[] = {
7233     /* Embedded PowerPC                                                      */
7234     /* PowerPC 401 family                                                    */
7235     /* Generic PowerPC 401 */
7236     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
7237     /* PowerPC 401 cores                                                     */
7238     /* PowerPC 401A1 */
7239     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
7240     /* PowerPC 401B2                                                         */
7241     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
7242 #if defined (TODO)
7243     /* PowerPC 401B3                                                         */
7244     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
7245 #endif
7246     /* PowerPC 401C2                                                         */
7247     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
7248     /* PowerPC 401D2                                                         */
7249     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
7250     /* PowerPC 401E2                                                         */
7251     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
7252     /* PowerPC 401F2                                                         */
7253     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
7254     /* PowerPC 401G2                                                         */
7255     /* XXX: to be checked */
7256     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
7257     /* PowerPC 401 microcontrolers                                           */
7258 #if defined (TODO)
7259     /* PowerPC 401GF                                                         */
7260     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
7261 #endif
7262     /* IOP480 (401 microcontroler)                                           */
7263     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
7264     /* IBM Processor for Network Resources                                   */
7265     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
7266 #if defined (TODO)
7267     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
7268 #endif
7269     /* PowerPC 403 family                                                    */
7270     /* Generic PowerPC 403                                                   */
7271     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
7272     /* PowerPC 403 microcontrolers                                           */
7273     /* PowerPC 403 GA                                                        */
7274     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
7275     /* PowerPC 403 GB                                                        */
7276     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
7277     /* PowerPC 403 GC                                                        */
7278     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
7279     /* PowerPC 403 GCX                                                       */
7280     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
7281 #if defined (TODO)
7282     /* PowerPC 403 GP                                                        */
7283     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
7284 #endif
7285     /* PowerPC 405 family                                                    */
7286     /* Generic PowerPC 405                                                   */
7287     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
7288     /* PowerPC 405 cores                                                     */
7289 #if defined (TODO)
7290     /* PowerPC 405 A3                                                        */
7291     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
7292 #endif
7293 #if defined (TODO)
7294     /* PowerPC 405 A4                                                        */
7295     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
7296 #endif
7297 #if defined (TODO)
7298     /* PowerPC 405 B3                                                        */
7299     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
7300 #endif
7301 #if defined (TODO)
7302     /* PowerPC 405 B4                                                        */
7303     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
7304 #endif
7305 #if defined (TODO)
7306     /* PowerPC 405 C3                                                        */
7307     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
7308 #endif
7309 #if defined (TODO)
7310     /* PowerPC 405 C4                                                        */
7311     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
7312 #endif
7313     /* PowerPC 405 D2                                                        */
7314     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
7315 #if defined (TODO)
7316     /* PowerPC 405 D3                                                        */
7317     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
7318 #endif
7319     /* PowerPC 405 D4                                                        */
7320     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
7321 #if defined (TODO)
7322     /* PowerPC 405 D5                                                        */
7323     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
7324 #endif
7325 #if defined (TODO)
7326     /* PowerPC 405 E4                                                        */
7327     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
7328 #endif
7329 #if defined (TODO)
7330     /* PowerPC 405 F4                                                        */
7331     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
7332 #endif
7333 #if defined (TODO)
7334     /* PowerPC 405 F5                                                        */
7335     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
7336 #endif
7337 #if defined (TODO)
7338     /* PowerPC 405 F6                                                        */
7339     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
7340 #endif
7341     /* PowerPC 405 microcontrolers                                           */
7342     /* PowerPC 405 CR                                                        */
7343     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
7344     /* PowerPC 405 CRa                                                       */
7345     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
7346     /* PowerPC 405 CRb                                                       */
7347     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
7348     /* PowerPC 405 CRc                                                       */
7349     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
7350     /* PowerPC 405 EP                                                        */
7351     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
7352 #if defined(TODO)
7353     /* PowerPC 405 EXr                                                       */
7354     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
7355 #endif
7356     /* PowerPC 405 EZ                                                        */
7357     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
7358 #if defined(TODO)
7359     /* PowerPC 405 FX                                                        */
7360     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
7361 #endif
7362     /* PowerPC 405 GP                                                        */
7363     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
7364     /* PowerPC 405 GPa                                                       */
7365     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
7366     /* PowerPC 405 GPb                                                       */
7367     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
7368     /* PowerPC 405 GPc                                                       */
7369     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
7370     /* PowerPC 405 GPd                                                       */
7371     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
7372     /* PowerPC 405 GPe                                                       */
7373     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
7374     /* PowerPC 405 GPR                                                       */
7375     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
7376 #if defined(TODO)
7377     /* PowerPC 405 H                                                         */
7378     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
7379 #endif
7380 #if defined(TODO)
7381     /* PowerPC 405 L                                                         */
7382     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
7383 #endif
7384     /* PowerPC 405 LP                                                        */
7385     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
7386 #if defined(TODO)
7387     /* PowerPC 405 PM                                                        */
7388     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
7389 #endif
7390 #if defined(TODO)
7391     /* PowerPC 405 PS                                                        */
7392     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
7393 #endif
7394 #if defined(TODO)
7395     /* PowerPC 405 S                                                         */
7396     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
7397 #endif
7398     /* Npe405 H                                                              */
7399     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
7400     /* Npe405 H2                                                             */
7401     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
7402     /* Npe405 L                                                              */
7403     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
7404     /* Npe4GS3                                                               */
7405     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
7406 #if defined (TODO)
7407     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
7408 #endif
7409 #if defined (TODO)
7410     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
7411 #endif
7412 #if defined (TODO)
7413     /* PowerPC LC77700 (Sanyo)                                               */
7414     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
7415 #endif
7416     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
7417 #if defined (TODO)
7418     /* STB010000                                                             */
7419     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
7420 #endif
7421 #if defined (TODO)
7422     /* STB01010                                                              */
7423     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
7424 #endif
7425 #if defined (TODO)
7426     /* STB0210                                                               */
7427     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
7428 #endif
7429     /* STB03xx                                                               */
7430     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
7431 #if defined (TODO)
7432     /* STB043x                                                               */
7433     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
7434 #endif
7435 #if defined (TODO)
7436     /* STB045x                                                               */
7437     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
7438 #endif
7439     /* STB04xx                                                               */
7440     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
7441     /* STB25xx                                                               */
7442     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
7443 #if defined (TODO)
7444     /* STB130                                                                */
7445     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
7446 #endif
7447     /* Xilinx PowerPC 405 cores                                              */
7448     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
7449     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
7450     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
7451     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
7452 #if defined (TODO)
7453     /* Zarlink ZL10310                                                       */
7454     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
7455 #endif
7456 #if defined (TODO)
7457     /* Zarlink ZL10311                                                       */
7458     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
7459 #endif
7460 #if defined (TODO)
7461     /* Zarlink ZL10320                                                       */
7462     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
7463 #endif
7464 #if defined (TODO)
7465     /* Zarlink ZL10321                                                       */
7466     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
7467 #endif
7468     /* PowerPC 440 family                                                    */
7469 #if defined(TODO_USER_ONLY)
7470     /* Generic PowerPC 440                                                   */
7471     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
7472 #endif
7473     /* PowerPC 440 cores                                                     */
7474 #if defined (TODO)
7475     /* PowerPC 440 A4                                                        */
7476     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
7477 #endif
7478 #if defined (TODO)
7479     /* PowerPC 440 A5                                                        */
7480     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
7481 #endif
7482 #if defined (TODO)
7483     /* PowerPC 440 B4                                                        */
7484     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
7485 #endif
7486 #if defined (TODO)
7487     /* PowerPC 440 G4                                                        */
7488     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
7489 #endif
7490 #if defined (TODO)
7491     /* PowerPC 440 F5                                                        */
7492     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
7493 #endif
7494 #if defined (TODO)
7495     /* PowerPC 440 G5                                                        */
7496     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
7497 #endif
7498 #if defined (TODO)
7499     /* PowerPC 440H4                                                         */
7500     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
7501 #endif
7502 #if defined (TODO)
7503     /* PowerPC 440H6                                                         */
7504     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
7505 #endif
7506     /* PowerPC 440 microcontrolers                                           */
7507 #if defined(TODO_USER_ONLY)
7508     /* PowerPC 440 EP                                                        */
7509     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
7510 #endif
7511 #if defined(TODO_USER_ONLY)
7512     /* PowerPC 440 EPa                                                       */
7513     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
7514 #endif
7515 #if defined(TODO_USER_ONLY)
7516     /* PowerPC 440 EPb                                                       */
7517     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
7518 #endif
7519 #if defined(TODO_USER_ONLY)
7520     /* PowerPC 440 EPX                                                       */
7521     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
7522 #endif
7523 #if defined(TODO_USER_ONLY)
7524     /* PowerPC 440 GP                                                        */
7525     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
7526 #endif
7527 #if defined(TODO_USER_ONLY)
7528     /* PowerPC 440 GPb                                                       */
7529     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
7530 #endif
7531 #if defined(TODO_USER_ONLY)
7532     /* PowerPC 440 GPc                                                       */
7533     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
7534 #endif
7535 #if defined(TODO_USER_ONLY)
7536     /* PowerPC 440 GR                                                        */
7537     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
7538 #endif
7539 #if defined(TODO_USER_ONLY)
7540     /* PowerPC 440 GRa                                                       */
7541     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
7542 #endif
7543 #if defined(TODO_USER_ONLY)
7544     /* PowerPC 440 GRX                                                       */
7545     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
7546 #endif
7547 #if defined(TODO_USER_ONLY)
7548     /* PowerPC 440 GX                                                        */
7549     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
7550 #endif
7551 #if defined(TODO_USER_ONLY)
7552     /* PowerPC 440 GXa                                                       */
7553     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
7554 #endif
7555 #if defined(TODO_USER_ONLY)
7556     /* PowerPC 440 GXb                                                       */
7557     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
7558 #endif
7559 #if defined(TODO_USER_ONLY)
7560     /* PowerPC 440 GXc                                                       */
7561     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
7562 #endif
7563 #if defined(TODO_USER_ONLY)
7564     /* PowerPC 440 GXf                                                       */
7565     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
7566 #endif
7567 #if defined(TODO)
7568     /* PowerPC 440 S                                                         */
7569     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
7570 #endif
7571 #if defined(TODO_USER_ONLY)
7572     /* PowerPC 440 SP                                                        */
7573     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
7574 #endif
7575 #if defined(TODO_USER_ONLY)
7576     /* PowerPC 440 SP2                                                       */
7577     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
7578 #endif
7579 #if defined(TODO_USER_ONLY)
7580     /* PowerPC 440 SPE                                                       */
7581     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
7582 #endif
7583     /* PowerPC 460 family                                                    */
7584 #if defined (TODO)
7585     /* Generic PowerPC 464                                                   */
7586     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
7587 #endif
7588     /* PowerPC 464 microcontrolers                                           */
7589 #if defined (TODO)
7590     /* PowerPC 464H90                                                        */
7591     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
7592 #endif
7593 #if defined (TODO)
7594     /* PowerPC 464H90F                                                       */
7595     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
7596 #endif
7597     /* Freescale embedded PowerPC cores                                      */
7598     /* MPC5xx family (aka RCPU)                                              */
7599 #if defined(TODO_USER_ONLY)
7600     /* Generic MPC5xx core                                                   */
7601     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
7602 #endif
7603 #if defined(TODO_USER_ONLY)
7604     /* Codename for MPC5xx core                                              */
7605     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
7606 #endif
7607     /* MPC5xx microcontrollers                                               */
7608 #if defined(TODO_USER_ONLY)
7609     /* MGT560                                                                */
7610     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
7611 #endif
7612 #if defined(TODO_USER_ONLY)
7613     /* MPC509                                                                */
7614     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
7615 #endif
7616 #if defined(TODO_USER_ONLY)
7617     /* MPC533                                                                */
7618     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
7619 #endif
7620 #if defined(TODO_USER_ONLY)
7621     /* MPC534                                                                */
7622     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
7623 #endif
7624 #if defined(TODO_USER_ONLY)
7625     /* MPC555                                                                */
7626     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
7627 #endif
7628 #if defined(TODO_USER_ONLY)
7629     /* MPC556                                                                */
7630     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
7631 #endif
7632 #if defined(TODO_USER_ONLY)
7633     /* MPC560                                                                */
7634     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
7635 #endif
7636 #if defined(TODO_USER_ONLY)
7637     /* MPC561                                                                */
7638     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
7639 #endif
7640 #if defined(TODO_USER_ONLY)
7641     /* MPC562                                                                */
7642     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
7643 #endif
7644 #if defined(TODO_USER_ONLY)
7645     /* MPC563                                                                */
7646     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
7647 #endif
7648 #if defined(TODO_USER_ONLY)
7649     /* MPC564                                                                */
7650     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
7651 #endif
7652 #if defined(TODO_USER_ONLY)
7653     /* MPC565                                                                */
7654     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
7655 #endif
7656 #if defined(TODO_USER_ONLY)
7657     /* MPC566                                                                */
7658     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
7659 #endif
7660     /* MPC8xx family (aka PowerQUICC)                                        */
7661 #if defined(TODO_USER_ONLY)
7662     /* Generic MPC8xx core                                                   */
7663     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
7664 #endif
7665 #if defined(TODO_USER_ONLY)
7666     /* Codename for MPC8xx core                                              */
7667     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
7668 #endif
7669     /* MPC8xx microcontrollers                                               */
7670 #if defined(TODO_USER_ONLY)
7671     /* MGT823                                                                */
7672     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
7673 #endif
7674 #if defined(TODO_USER_ONLY)
7675     /* MPC821                                                                */
7676     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
7677 #endif
7678 #if defined(TODO_USER_ONLY)
7679     /* MPC823                                                                */
7680     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
7681 #endif
7682 #if defined(TODO_USER_ONLY)
7683     /* MPC850                                                                */
7684     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
7685 #endif
7686 #if defined(TODO_USER_ONLY)
7687     /* MPC852T                                                               */
7688     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
7689 #endif
7690 #if defined(TODO_USER_ONLY)
7691     /* MPC855T                                                               */
7692     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
7693 #endif
7694 #if defined(TODO_USER_ONLY)
7695     /* MPC857                                                                */
7696     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
7697 #endif
7698 #if defined(TODO_USER_ONLY)
7699     /* MPC859                                                                */
7700     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
7701 #endif
7702 #if defined(TODO_USER_ONLY)
7703     /* MPC860                                                                */
7704     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
7705 #endif
7706 #if defined(TODO_USER_ONLY)
7707     /* MPC862                                                                */
7708     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
7709 #endif
7710 #if defined(TODO_USER_ONLY)
7711     /* MPC866                                                                */
7712     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
7713 #endif
7714 #if defined(TODO_USER_ONLY)
7715     /* MPC870                                                                */
7716     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
7717 #endif
7718 #if defined(TODO_USER_ONLY)
7719     /* MPC875                                                                */
7720     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
7721 #endif
7722 #if defined(TODO_USER_ONLY)
7723     /* MPC880                                                                */
7724     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
7725 #endif
7726 #if defined(TODO_USER_ONLY)
7727     /* MPC885                                                                */
7728     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
7729 #endif
7730     /* MPC82xx family (aka PowerQUICC-II)                                    */
7731     /* Generic MPC52xx core                                                  */
7732     POWERPC_DEF_SVR("MPC52xx",
7733                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
7734     /* Generic MPC82xx core                                                  */
7735     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
7736     /* Codename for MPC82xx                                                  */
7737     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
7738     /* PowerPC G2 core                                                       */
7739     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
7740     /* PowerPC G2 H4 core                                                    */
7741     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
7742     /* PowerPC G2 GP core                                                    */
7743     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
7744     /* PowerPC G2 LS core                                                    */
7745     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
7746     /* PowerPC G2 HiP3 core                                                  */
7747     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
7748     /* PowerPC G2 HiP4 core                                                  */
7749     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
7750     /* PowerPC MPC603 core                                                   */
7751     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
7752     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
7753     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
7754     /* PowerPC G2LE GP core                                                  */
7755     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
7756     /* PowerPC G2LE LS core                                                  */
7757     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
7758     /* PowerPC G2LE GP1 core                                                 */
7759     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
7760     /* PowerPC G2LE GP3 core                                                 */
7761     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
7762     /* PowerPC MPC603 microcontrollers                                       */
7763     /* MPC8240                                                               */
7764     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
7765     /* PowerPC G2 microcontrollers                                           */
7766 #if defined(TODO)
7767     /* MPC5121                                                               */
7768     POWERPC_DEF_SVR("MPC5121",
7769                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
7770 #endif
7771     /* MPC5200                                                               */
7772     POWERPC_DEF_SVR("MPC5200",
7773                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
7774     /* MPC5200 v1.0                                                          */
7775     POWERPC_DEF_SVR("MPC5200_v10",
7776                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
7777     /* MPC5200 v1.1                                                          */
7778     POWERPC_DEF_SVR("MPC5200_v11",
7779                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
7780     /* MPC5200 v1.2                                                          */
7781     POWERPC_DEF_SVR("MPC5200_v12",
7782                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
7783     /* MPC5200B                                                              */
7784     POWERPC_DEF_SVR("MPC5200B",
7785                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
7786     /* MPC5200B v2.0                                                         */
7787     POWERPC_DEF_SVR("MPC5200B_v20",
7788                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7789     /* MPC5200B v2.1                                                         */
7790     POWERPC_DEF_SVR("MPC5200B_v21",
7791                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7792     /* MPC8241                                                               */
7793     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
7794     /* MPC8245                                                               */
7795     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
7796     /* MPC8247                                                               */
7797     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
7798     /* MPC8248                                                               */
7799     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
7800     /* MPC8250                                                               */
7801     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
7802     /* MPC8250 HiP3                                                          */
7803     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
7804     /* MPC8250 HiP4                                                          */
7805     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
7806     /* MPC8255                                                               */
7807     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
7808     /* MPC8255 HiP3                                                          */
7809     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
7810     /* MPC8255 HiP4                                                          */
7811     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
7812     /* MPC8260                                                               */
7813     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
7814     /* MPC8260 HiP3                                                          */
7815     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
7816     /* MPC8260 HiP4                                                          */
7817     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
7818     /* MPC8264                                                               */
7819     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
7820     /* MPC8264 HiP3                                                          */
7821     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
7822     /* MPC8264 HiP4                                                          */
7823     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
7824     /* MPC8265                                                               */
7825     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
7826     /* MPC8265 HiP3                                                          */
7827     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
7828     /* MPC8265 HiP4                                                          */
7829     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
7830     /* MPC8266                                                               */
7831     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
7832     /* MPC8266 HiP3                                                          */
7833     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
7834     /* MPC8266 HiP4                                                          */
7835     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
7836     /* MPC8270                                                               */
7837     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
7838     /* MPC8271                                                               */
7839     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
7840     /* MPC8272                                                               */
7841     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
7842     /* MPC8275                                                               */
7843     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
7844     /* MPC8280                                                               */
7845     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
7846     /* e200 family                                                           */
7847     /* Generic PowerPC e200 core                                             */
7848     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
7849     /* Generic MPC55xx core                                                  */
7850 #if defined (TODO)
7851     POWERPC_DEF_SVR("MPC55xx",
7852                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
7853 #endif
7854 #if defined (TODO)
7855     /* PowerPC e200z0 core                                                   */
7856     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
7857 #endif
7858 #if defined (TODO)
7859     /* PowerPC e200z1 core                                                   */
7860     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
7861 #endif
7862 #if defined (TODO)
7863     /* PowerPC e200z3 core                                                   */
7864     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
7865 #endif
7866     /* PowerPC e200z5 core                                                   */
7867     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
7868     /* PowerPC e200z6 core                                                   */
7869     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
7870     /* PowerPC e200 microcontrollers                                         */
7871 #if defined (TODO)
7872     /* MPC5514E                                                              */
7873     POWERPC_DEF_SVR("MPC5514E",
7874                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
7875 #endif
7876 #if defined (TODO)
7877     /* MPC5514E v0                                                           */
7878     POWERPC_DEF_SVR("MPC5514E_v0",
7879                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
7880 #endif
7881 #if defined (TODO)
7882     /* MPC5514E v1                                                           */
7883     POWERPC_DEF_SVR("MPC5514E_v1",
7884                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
7885 #endif
7886 #if defined (TODO)
7887     /* MPC5514G                                                              */
7888     POWERPC_DEF_SVR("MPC5514G",
7889                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
7890 #endif
7891 #if defined (TODO)
7892     /* MPC5514G v0                                                           */
7893     POWERPC_DEF_SVR("MPC5514G_v0",
7894                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
7895 #endif
7896 #if defined (TODO)
7897     /* MPC5514G v1                                                           */
7898     POWERPC_DEF_SVR("MPC5514G_v1",
7899                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
7900 #endif
7901 #if defined (TODO)
7902     /* MPC5515S                                                              */
7903     POWERPC_DEF_SVR("MPC5515S",
7904                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
7905 #endif
7906 #if defined (TODO)
7907     /* MPC5516E                                                              */
7908     POWERPC_DEF_SVR("MPC5516E",
7909                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
7910 #endif
7911 #if defined (TODO)
7912     /* MPC5516E v0                                                           */
7913     POWERPC_DEF_SVR("MPC5516E_v0",
7914                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
7915 #endif
7916 #if defined (TODO)
7917     /* MPC5516E v1                                                           */
7918     POWERPC_DEF_SVR("MPC5516E_v1",
7919                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
7920 #endif
7921 #if defined (TODO)
7922     /* MPC5516G                                                              */
7923     POWERPC_DEF_SVR("MPC5516G",
7924                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
7925 #endif
7926 #if defined (TODO)
7927     /* MPC5516G v0                                                           */
7928     POWERPC_DEF_SVR("MPC5516G_v0",
7929                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
7930 #endif
7931 #if defined (TODO)
7932     /* MPC5516G v1                                                           */
7933     POWERPC_DEF_SVR("MPC5516G_v1",
7934                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
7935 #endif
7936 #if defined (TODO)
7937     /* MPC5516S                                                              */
7938     POWERPC_DEF_SVR("MPC5516S",
7939                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
7940 #endif
7941 #if defined (TODO)
7942     /* MPC5533                                                               */
7943     POWERPC_DEF_SVR("MPC5533",
7944                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
7945 #endif
7946 #if defined (TODO)
7947     /* MPC5534                                                               */
7948     POWERPC_DEF_SVR("MPC5534",
7949                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
7950 #endif
7951 #if defined (TODO)
7952     /* MPC5553                                                               */
7953     POWERPC_DEF_SVR("MPC5553",
7954                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
7955 #endif
7956 #if defined (TODO)
7957     /* MPC5554                                                               */
7958     POWERPC_DEF_SVR("MPC5554",
7959                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
7960 #endif
7961 #if defined (TODO)
7962     /* MPC5561                                                               */
7963     POWERPC_DEF_SVR("MPC5561",
7964                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
7965 #endif
7966 #if defined (TODO)
7967     /* MPC5565                                                               */
7968     POWERPC_DEF_SVR("MPC5565",
7969                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
7970 #endif
7971 #if defined (TODO)
7972     /* MPC5566                                                               */
7973     POWERPC_DEF_SVR("MPC5566",
7974                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
7975 #endif
7976 #if defined (TODO)
7977     /* MPC5567                                                               */
7978     POWERPC_DEF_SVR("MPC5567",
7979                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
7980 #endif
7981     /* e300 family                                                           */
7982     /* Generic PowerPC e300 core                                             */
7983     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
7984     /* PowerPC e300c1 core                                                   */
7985     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
7986     /* PowerPC e300c2 core                                                   */
7987     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
7988     /* PowerPC e300c3 core                                                   */
7989     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
7990     /* PowerPC e300c4 core                                                   */
7991     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
7992     /* PowerPC e300 microcontrollers                                         */
7993 #if defined (TODO)
7994     /* MPC8313                                                               */
7995     POWERPC_DEF_SVR("MPC8313",
7996                     CPU_POWERPC_MPC8313,      POWERPC_SVR_8313,      e300),
7997 #endif
7998 #if defined (TODO)
7999     /* MPC8313E                                                              */
8000     POWERPC_DEF_SVR("MPC8313E",
8001                     CPU_POWERPC_MPC8313E,     POWERPC_SVR_8313E,     e300),
8002 #endif
8003 #if defined (TODO)
8004     /* MPC8314                                                               */
8005     POWERPC_DEF_SVR("MPC8314",
8006                     CPU_POWERPC_MPC8314,      POWERPC_SVR_8314,      e300),
8007 #endif
8008 #if defined (TODO)
8009     /* MPC8314E                                                              */
8010     POWERPC_DEF_SVR("MPC8314E",
8011                     CPU_POWERPC_MPC8314E,     POWERPC_SVR_8314E,     e300),
8012 #endif
8013 #if defined (TODO)
8014     /* MPC8315                                                               */
8015     POWERPC_DEF_SVR("MPC8315",
8016                     CPU_POWERPC_MPC8315,      POWERPC_SVR_8315,      e300),
8017 #endif
8018 #if defined (TODO)
8019     /* MPC8315E                                                              */
8020     POWERPC_DEF_SVR("MPC8315E",
8021                     CPU_POWERPC_MPC8315E,     POWERPC_SVR_8315E,     e300),
8022 #endif
8023 #if defined (TODO)
8024     /* MPC8321                                                               */
8025     POWERPC_DEF_SVR("MPC8321",
8026                     CPU_POWERPC_MPC8321,      POWERPC_SVR_8321,      e300),
8027 #endif
8028 #if defined (TODO)
8029     /* MPC8321E                                                              */
8030     POWERPC_DEF_SVR("MPC8321E",
8031                     CPU_POWERPC_MPC8321E,     POWERPC_SVR_8321E,     e300),
8032 #endif
8033 #if defined (TODO)
8034     /* MPC8323                                                               */
8035     POWERPC_DEF_SVR("MPC8323",
8036                     CPU_POWERPC_MPC8323,      POWERPC_SVR_8323,      e300),
8037 #endif
8038 #if defined (TODO)
8039     /* MPC8323E                                                              */
8040     POWERPC_DEF_SVR("MPC8323E",
8041                     CPU_POWERPC_MPC8323E,     POWERPC_SVR_8323E,     e300),
8042 #endif
8043     /* MPC8343A                                                              */
8044     POWERPC_DEF_SVR("MPC8343A",
8045                     CPU_POWERPC_MPC8343A,     POWERPC_SVR_8343A,     e300),
8046     /* MPC8343EA                                                             */
8047     POWERPC_DEF_SVR("MPC8343EA",
8048                     CPU_POWERPC_MPC8343EA,    POWERPC_SVR_8343EA,    e300),
8049     /* MPC8347A                                                              */
8050     POWERPC_DEF_SVR("MPC8347A",
8051                     CPU_POWERPC_MPC8347A,     POWERPC_SVR_8347A,     e300),
8052     /* MPC8347AT                                                             */
8053     POWERPC_DEF_SVR("MPC8347AT",
8054                     CPU_POWERPC_MPC8347AT,    POWERPC_SVR_8347AT,    e300),
8055     /* MPC8347AP                                                             */
8056     POWERPC_DEF_SVR("MPC8347AP",
8057                     CPU_POWERPC_MPC8347AP,    POWERPC_SVR_8347AP,    e300),
8058     /* MPC8347EA                                                             */
8059     POWERPC_DEF_SVR("MPC8347EA",
8060                     CPU_POWERPC_MPC8347EA,    POWERPC_SVR_8347EA,    e300),
8061     /* MPC8347EAT                                                            */
8062     POWERPC_DEF_SVR("MPC8347EAT",
8063                     CPU_POWERPC_MPC8347EAT,   POWERPC_SVR_8347EAT,   e300),
8064     /* MPC8343EAP                                                            */
8065     POWERPC_DEF_SVR("MPC8347EAP",
8066                     CPU_POWERPC_MPC8347EAP,   POWERPC_SVR_8347EAP,   e300),
8067     /* MPC8349                                                               */
8068     POWERPC_DEF_SVR("MPC8349",
8069                     CPU_POWERPC_MPC8349,      POWERPC_SVR_8349,      e300),
8070     /* MPC8349A                                                              */
8071     POWERPC_DEF_SVR("MPC8349A",
8072                     CPU_POWERPC_MPC8349A,     POWERPC_SVR_8349A,     e300),
8073     /* MPC8349E                                                              */
8074     POWERPC_DEF_SVR("MPC8349E",
8075                     CPU_POWERPC_MPC8349E,     POWERPC_SVR_8349E,     e300),
8076     /* MPC8349EA                                                             */
8077     POWERPC_DEF_SVR("MPC8349EA",
8078                     CPU_POWERPC_MPC8349EA,    POWERPC_SVR_8349EA,    e300),
8079 #if defined (TODO)
8080     /* MPC8358E                                                              */
8081     POWERPC_DEF_SVR("MPC8358E",
8082                     CPU_POWERPC_MPC8358E,     POWERPC_SVR_8358E,     e300),
8083 #endif
8084 #if defined (TODO)
8085     /* MPC8360E                                                              */
8086     POWERPC_DEF_SVR("MPC8360E",
8087                     CPU_POWERPC_MPC8360E,     POWERPC_SVR_8360E,     e300),
8088 #endif
8089     /* MPC8377                                                               */
8090     POWERPC_DEF_SVR("MPC8377",
8091                     CPU_POWERPC_MPC8377,      POWERPC_SVR_8377,      e300),
8092     /* MPC8377E                                                              */
8093     POWERPC_DEF_SVR("MPC8377E",
8094                     CPU_POWERPC_MPC8377E,     POWERPC_SVR_8377E,     e300),
8095     /* MPC8378                                                               */
8096     POWERPC_DEF_SVR("MPC8378",
8097                     CPU_POWERPC_MPC8378,      POWERPC_SVR_8378,      e300),
8098     /* MPC8378E                                                              */
8099     POWERPC_DEF_SVR("MPC8378E",
8100                     CPU_POWERPC_MPC8378E,     POWERPC_SVR_8378E,     e300),
8101     /* MPC8379                                                               */
8102     POWERPC_DEF_SVR("MPC8379",
8103                     CPU_POWERPC_MPC8379,      POWERPC_SVR_8379,      e300),
8104     /* MPC8379E                                                              */
8105     POWERPC_DEF_SVR("MPC8379E",
8106                     CPU_POWERPC_MPC8379E,     POWERPC_SVR_8379E,     e300),
8107     /* e500 family                                                           */
8108     /* PowerPC e500 core                                                     */
8109     POWERPC_DEF("e500",          CPU_POWERPC_e500v2_v22,             e500v2),
8110     /* PowerPC e500v1 core                                                   */
8111     POWERPC_DEF("e500v1",        CPU_POWERPC_e500v1,                 e500v1),
8112     /* PowerPC e500 v1.0 core                                                */
8113     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500v1_v10,             e500v1),
8114     /* PowerPC e500 v2.0 core                                                */
8115     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500v1_v20,             e500v1),
8116     /* PowerPC e500v2 core                                                   */
8117     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500v2),
8118     /* PowerPC e500v2 v1.0 core                                              */
8119     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500v2),
8120     /* PowerPC e500v2 v2.0 core                                              */
8121     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500v2),
8122     /* PowerPC e500v2 v2.1 core                                              */
8123     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500v2),
8124     /* PowerPC e500v2 v2.2 core                                              */
8125     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500v2),
8126     /* PowerPC e500v2 v3.0 core                                              */
8127     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500v2),
8128     /* PowerPC e500 microcontrollers                                         */
8129     /* MPC8533                                                               */
8130     POWERPC_DEF_SVR("MPC8533",
8131                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500v2),
8132     /* MPC8533 v1.0                                                          */
8133     POWERPC_DEF_SVR("MPC8533_v10",
8134                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500v2),
8135     /* MPC8533 v1.1                                                          */
8136     POWERPC_DEF_SVR("MPC8533_v11",
8137                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500v2),
8138     /* MPC8533E                                                              */
8139     POWERPC_DEF_SVR("MPC8533E",
8140                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500v2),
8141     /* MPC8533E v1.0                                                         */
8142     POWERPC_DEF_SVR("MPC8533E_v10",
8143                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8144     POWERPC_DEF_SVR("MPC8533E_v11",
8145                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8146     /* MPC8540                                                               */
8147     POWERPC_DEF_SVR("MPC8540",
8148                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500v1),
8149     /* MPC8540 v1.0                                                          */
8150     POWERPC_DEF_SVR("MPC8540_v10",
8151                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500v1),
8152     /* MPC8540 v2.0                                                          */
8153     POWERPC_DEF_SVR("MPC8540_v20",
8154                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500v1),
8155     /* MPC8540 v2.1                                                          */
8156     POWERPC_DEF_SVR("MPC8540_v21",
8157                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500v1),
8158     /* MPC8541                                                               */
8159     POWERPC_DEF_SVR("MPC8541",
8160                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500v1),
8161     /* MPC8541 v1.0                                                          */
8162     POWERPC_DEF_SVR("MPC8541_v10",
8163                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500v1),
8164     /* MPC8541 v1.1                                                          */
8165     POWERPC_DEF_SVR("MPC8541_v11",
8166                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500v1),
8167     /* MPC8541E                                                              */
8168     POWERPC_DEF_SVR("MPC8541E",
8169                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500v1),
8170     /* MPC8541E v1.0                                                         */
8171     POWERPC_DEF_SVR("MPC8541E_v10",
8172                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8173     /* MPC8541E v1.1                                                         */
8174     POWERPC_DEF_SVR("MPC8541E_v11",
8175                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8176     /* MPC8543                                                               */
8177     POWERPC_DEF_SVR("MPC8543",
8178                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500v2),
8179     /* MPC8543 v1.0                                                          */
8180     POWERPC_DEF_SVR("MPC8543_v10",
8181                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500v2),
8182     /* MPC8543 v1.1                                                          */
8183     POWERPC_DEF_SVR("MPC8543_v11",
8184                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500v2),
8185     /* MPC8543 v2.0                                                          */
8186     POWERPC_DEF_SVR("MPC8543_v20",
8187                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500v2),
8188     /* MPC8543 v2.1                                                          */
8189     POWERPC_DEF_SVR("MPC8543_v21",
8190                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500v2),
8191     /* MPC8543E                                                              */
8192     POWERPC_DEF_SVR("MPC8543E",
8193                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500v2),
8194     /* MPC8543E v1.0                                                         */
8195     POWERPC_DEF_SVR("MPC8543E_v10",
8196                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8197     /* MPC8543E v1.1                                                         */
8198     POWERPC_DEF_SVR("MPC8543E_v11",
8199                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8200     /* MPC8543E v2.0                                                         */
8201     POWERPC_DEF_SVR("MPC8543E_v20",
8202                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8203     /* MPC8543E v2.1                                                         */
8204     POWERPC_DEF_SVR("MPC8543E_v21",
8205                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8206     /* MPC8544                                                               */
8207     POWERPC_DEF_SVR("MPC8544",
8208                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500v2),
8209     /* MPC8544 v1.0                                                          */
8210     POWERPC_DEF_SVR("MPC8544_v10",
8211                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500v2),
8212     /* MPC8544 v1.1                                                          */
8213     POWERPC_DEF_SVR("MPC8544_v11",
8214                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500v2),
8215     /* MPC8544E                                                              */
8216     POWERPC_DEF_SVR("MPC8544E",
8217                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500v2),
8218     /* MPC8544E v1.0                                                         */
8219     POWERPC_DEF_SVR("MPC8544E_v10",
8220                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8221     /* MPC8544E v1.1                                                         */
8222     POWERPC_DEF_SVR("MPC8544E_v11",
8223                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8224     /* MPC8545                                                               */
8225     POWERPC_DEF_SVR("MPC8545",
8226                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500v2),
8227     /* MPC8545 v2.0                                                          */
8228     POWERPC_DEF_SVR("MPC8545_v20",
8229                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500v2),
8230     /* MPC8545 v2.1                                                          */
8231     POWERPC_DEF_SVR("MPC8545_v21",
8232                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500v2),
8233     /* MPC8545E                                                              */
8234     POWERPC_DEF_SVR("MPC8545E",
8235                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500v2),
8236     /* MPC8545E v2.0                                                         */
8237     POWERPC_DEF_SVR("MPC8545E_v20",
8238                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8239     /* MPC8545E v2.1                                                         */
8240     POWERPC_DEF_SVR("MPC8545E_v21",
8241                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8242     /* MPC8547E                                                              */
8243     POWERPC_DEF_SVR("MPC8547E",
8244                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500v2),
8245     /* MPC8547E v2.0                                                         */
8246     POWERPC_DEF_SVR("MPC8547E_v20",
8247                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8248     /* MPC8547E v2.1                                                         */
8249     POWERPC_DEF_SVR("MPC8547E_v21",
8250                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8251     /* MPC8548                                                               */
8252     POWERPC_DEF_SVR("MPC8548",
8253                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500v2),
8254     /* MPC8548 v1.0                                                          */
8255     POWERPC_DEF_SVR("MPC8548_v10",
8256                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500v2),
8257     /* MPC8548 v1.1                                                          */
8258     POWERPC_DEF_SVR("MPC8548_v11",
8259                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500v2),
8260     /* MPC8548 v2.0                                                          */
8261     POWERPC_DEF_SVR("MPC8548_v20",
8262                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500v2),
8263     /* MPC8548 v2.1                                                          */
8264     POWERPC_DEF_SVR("MPC8548_v21",
8265                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500v2),
8266     /* MPC8548E                                                              */
8267     POWERPC_DEF_SVR("MPC8548E",
8268                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500v2),
8269     /* MPC8548E v1.0                                                         */
8270     POWERPC_DEF_SVR("MPC8548E_v10",
8271                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8272     /* MPC8548E v1.1                                                         */
8273     POWERPC_DEF_SVR("MPC8548E_v11",
8274                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8275     /* MPC8548E v2.0                                                         */
8276     POWERPC_DEF_SVR("MPC8548E_v20",
8277                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8278     /* MPC8548E v2.1                                                         */
8279     POWERPC_DEF_SVR("MPC8548E_v21",
8280                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8281     /* MPC8555                                                               */
8282     POWERPC_DEF_SVR("MPC8555",
8283                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500v2),
8284     /* MPC8555 v1.0                                                          */
8285     POWERPC_DEF_SVR("MPC8555_v10",
8286                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500v2),
8287     /* MPC8555 v1.1                                                          */
8288     POWERPC_DEF_SVR("MPC8555_v11",
8289                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500v2),
8290     /* MPC8555E                                                              */
8291     POWERPC_DEF_SVR("MPC8555E",
8292                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500v2),
8293     /* MPC8555E v1.0                                                         */
8294     POWERPC_DEF_SVR("MPC8555E_v10",
8295                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8296     /* MPC8555E v1.1                                                         */
8297     POWERPC_DEF_SVR("MPC8555E_v11",
8298                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8299     /* MPC8560                                                               */
8300     POWERPC_DEF_SVR("MPC8560",
8301                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500v2),
8302     /* MPC8560 v1.0                                                          */
8303     POWERPC_DEF_SVR("MPC8560_v10",
8304                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500v2),
8305     /* MPC8560 v2.0                                                          */
8306     POWERPC_DEF_SVR("MPC8560_v20",
8307                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500v2),
8308     /* MPC8560 v2.1                                                          */
8309     POWERPC_DEF_SVR("MPC8560_v21",
8310                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500v2),
8311     /* MPC8567                                                               */
8312     POWERPC_DEF_SVR("MPC8567",
8313                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500v2),
8314     /* MPC8567E                                                              */
8315     POWERPC_DEF_SVR("MPC8567E",
8316                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500v2),
8317     /* MPC8568                                                               */
8318     POWERPC_DEF_SVR("MPC8568",
8319                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500v2),
8320     /* MPC8568E                                                              */
8321     POWERPC_DEF_SVR("MPC8568E",
8322                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500v2),
8323     /* MPC8572                                                               */
8324     POWERPC_DEF_SVR("MPC8572",
8325                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500v2),
8326     /* MPC8572E                                                              */
8327     POWERPC_DEF_SVR("MPC8572E",
8328                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500v2),
8329     /* e600 family                                                           */
8330     /* PowerPC e600 core                                                     */
8331     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
8332     /* PowerPC e600 microcontrollers                                         */
8333 #if defined (TODO)
8334     /* MPC8610                                                               */
8335     POWERPC_DEF_SVR("MPC8610",
8336                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
8337 #endif
8338     /* MPC8641                                                               */
8339     POWERPC_DEF_SVR("MPC8641",
8340                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
8341     /* MPC8641D                                                              */
8342     POWERPC_DEF_SVR("MPC8641D",
8343                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
8344     /* 32 bits "classic" PowerPC                                             */
8345     /* PowerPC 6xx family                                                    */
8346     /* PowerPC 601                                                           */
8347     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
8348     /* PowerPC 601v0                                                         */
8349     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
8350     /* PowerPC 601v1                                                         */
8351     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
8352     /* PowerPC 601v                                                          */
8353     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
8354     /* PowerPC 601v2                                                         */
8355     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
8356     /* PowerPC 602                                                           */
8357     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
8358     /* PowerPC 603                                                           */
8359     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
8360     /* Code name for PowerPC 603                                             */
8361     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
8362     /* PowerPC 603e (aka PID6)                                               */
8363     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
8364     /* Code name for PowerPC 603e                                            */
8365     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
8366     /* PowerPC 603e v1.1                                                     */
8367     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
8368     /* PowerPC 603e v1.2                                                     */
8369     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
8370     /* PowerPC 603e v1.3                                                     */
8371     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
8372     /* PowerPC 603e v1.4                                                     */
8373     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
8374     /* PowerPC 603e v2.2                                                     */
8375     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
8376     /* PowerPC 603e v3                                                       */
8377     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
8378     /* PowerPC 603e v4                                                       */
8379     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
8380     /* PowerPC 603e v4.1                                                     */
8381     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
8382     /* PowerPC 603e (aka PID7)                                               */
8383     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
8384     /* PowerPC 603e7t                                                        */
8385     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
8386     /* PowerPC 603e7v                                                        */
8387     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
8388     /* Code name for PowerPC 603ev                                           */
8389     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
8390     /* PowerPC 603e7v1                                                       */
8391     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
8392     /* PowerPC 603e7v2                                                       */
8393     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
8394     /* PowerPC 603p (aka PID7v)                                              */
8395     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
8396     /* PowerPC 603r (aka PID7t)                                              */
8397     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
8398     /* Code name for PowerPC 603r                                            */
8399     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
8400     /* PowerPC 604                                                           */
8401     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
8402     /* PowerPC 604e (aka PID9)                                               */
8403     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
8404     /* Code name for PowerPC 604e                                            */
8405     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
8406     /* PowerPC 604e v1.0                                                     */
8407     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
8408     /* PowerPC 604e v2.2                                                     */
8409     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
8410     /* PowerPC 604e v2.4                                                     */
8411     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
8412     /* PowerPC 604r (aka PIDA)                                               */
8413     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
8414     /* Code name for PowerPC 604r                                            */
8415     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
8416 #if defined(TODO)
8417     /* PowerPC 604ev                                                         */
8418     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
8419 #endif
8420     /* PowerPC 7xx family                                                    */
8421     /* Generic PowerPC 740 (G3)                                              */
8422     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
8423     /* Code name for PowerPC 740                                             */
8424     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
8425     /* Generic PowerPC 750 (G3)                                              */
8426     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
8427     /* Code name for PowerPC 750                                             */
8428     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
8429     /* PowerPC 740/750 is also known as G3                                   */
8430     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
8431     /* PowerPC 740 v1.0 (G3)                                                 */
8432     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
8433     /* PowerPC 750 v1.0 (G3)                                                 */
8434     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
8435     /* PowerPC 740 v2.0 (G3)                                                 */
8436     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
8437     /* PowerPC 750 v2.0 (G3)                                                 */
8438     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
8439     /* PowerPC 740 v2.1 (G3)                                                 */
8440     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
8441     /* PowerPC 750 v2.1 (G3)                                                 */
8442     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
8443     /* PowerPC 740 v2.2 (G3)                                                 */
8444     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
8445     /* PowerPC 750 v2.2 (G3)                                                 */
8446     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
8447     /* PowerPC 740 v3.0 (G3)                                                 */
8448     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
8449     /* PowerPC 750 v3.0 (G3)                                                 */
8450     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
8451     /* PowerPC 740 v3.1 (G3)                                                 */
8452     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
8453     /* PowerPC 750 v3.1 (G3)                                                 */
8454     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
8455     /* PowerPC 740E (G3)                                                     */
8456     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
8457     /* PowerPC 750E (G3)                                                     */
8458     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
8459     /* PowerPC 740P (G3)                                                     */
8460     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
8461     /* PowerPC 750P (G3)                                                     */
8462     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
8463     /* Code name for PowerPC 740P/750P (G3)                                  */
8464     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
8465     /* PowerPC 750CL (G3 embedded)                                           */
8466     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
8467     /* PowerPC 750CL v1.0                                                    */
8468     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
8469     /* PowerPC 750CL v2.0                                                    */
8470     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
8471     /* PowerPC 750CX (G3 embedded)                                           */
8472     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
8473     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
8474     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
8475     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8476     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
8477     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8478     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
8479     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
8480     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
8481     /* PowerPC 750CXe (G3 embedded)                                          */
8482     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
8483     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
8484     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
8485     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
8486     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
8487     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
8488     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
8489     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
8490     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
8491     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
8492     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
8493     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
8494     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
8495     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
8496     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
8497     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
8498     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
8499     /* PowerPC 750CXr (G3 embedded)                                          */
8500     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
8501     /* PowerPC 750FL (G3 embedded)                                           */
8502     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
8503     /* PowerPC 750FX (G3 embedded)                                           */
8504     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
8505     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
8506     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
8507     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
8508     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
8509     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
8510     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
8511     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
8512     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
8513     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
8514     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
8515     /* PowerPC 750GL (G3 embedded)                                           */
8516     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
8517     /* PowerPC 750GX (G3 embedded)                                           */
8518     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
8519     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
8520     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
8521     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
8522     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
8523     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
8524     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
8525     /* PowerPC 750L (G3 embedded)                                            */
8526     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
8527     /* Code name for PowerPC 750L (G3 embedded)                              */
8528     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
8529     /* PowerPC 750L v2.0 (G3 embedded)                                       */
8530     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
8531     /* PowerPC 750L v2.1 (G3 embedded)                                       */
8532     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
8533     /* PowerPC 750L v2.2 (G3 embedded)                                       */
8534     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
8535     /* PowerPC 750L v3.0 (G3 embedded)                                       */
8536     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
8537     /* PowerPC 750L v3.2 (G3 embedded)                                       */
8538     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
8539     /* Generic PowerPC 745                                                   */
8540     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
8541     /* Generic PowerPC 755                                                   */
8542     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
8543     /* Code name for PowerPC 745/755                                         */
8544     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
8545     /* PowerPC 745 v1.0                                                      */
8546     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
8547     /* PowerPC 755 v1.0                                                      */
8548     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
8549     /* PowerPC 745 v1.1                                                      */
8550     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
8551     /* PowerPC 755 v1.1                                                      */
8552     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
8553     /* PowerPC 745 v2.0                                                      */
8554     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
8555     /* PowerPC 755 v2.0                                                      */
8556     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
8557     /* PowerPC 745 v2.1                                                      */
8558     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
8559     /* PowerPC 755 v2.1                                                      */
8560     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
8561     /* PowerPC 745 v2.2                                                      */
8562     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
8563     /* PowerPC 755 v2.2                                                      */
8564     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
8565     /* PowerPC 745 v2.3                                                      */
8566     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
8567     /* PowerPC 755 v2.3                                                      */
8568     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
8569     /* PowerPC 745 v2.4                                                      */
8570     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
8571     /* PowerPC 755 v2.4                                                      */
8572     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
8573     /* PowerPC 745 v2.5                                                      */
8574     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
8575     /* PowerPC 755 v2.5                                                      */
8576     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
8577     /* PowerPC 745 v2.6                                                      */
8578     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
8579     /* PowerPC 755 v2.6                                                      */
8580     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
8581     /* PowerPC 745 v2.7                                                      */
8582     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
8583     /* PowerPC 755 v2.7                                                      */
8584     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
8585     /* PowerPC 745 v2.8                                                      */
8586     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
8587     /* PowerPC 755 v2.8                                                      */
8588     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
8589 #if defined (TODO)
8590     /* PowerPC 745P (G3)                                                     */
8591     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
8592     /* PowerPC 755P (G3)                                                     */
8593     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
8594 #endif
8595     /* PowerPC 74xx family                                                   */
8596     /* PowerPC 7400 (G4)                                                     */
8597     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
8598     /* Code name for PowerPC 7400                                            */
8599     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
8600     /* PowerPC 74xx is also well known as G4                                 */
8601     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
8602     /* PowerPC 7400 v1.0 (G4)                                                */
8603     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
8604     /* PowerPC 7400 v1.1 (G4)                                                */
8605     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
8606     /* PowerPC 7400 v2.0 (G4)                                                */
8607     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
8608     /* PowerPC 7400 v2.1 (G4)                                                */
8609     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
8610     /* PowerPC 7400 v2.2 (G4)                                                */
8611     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
8612     /* PowerPC 7400 v2.6 (G4)                                                */
8613     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
8614     /* PowerPC 7400 v2.7 (G4)                                                */
8615     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
8616     /* PowerPC 7400 v2.8 (G4)                                                */
8617     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
8618     /* PowerPC 7400 v2.9 (G4)                                                */
8619     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
8620     /* PowerPC 7410 (G4)                                                     */
8621     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
8622     /* Code name for PowerPC 7410                                            */
8623     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
8624     /* PowerPC 7410 v1.0 (G4)                                                */
8625     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
8626     /* PowerPC 7410 v1.1 (G4)                                                */
8627     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
8628     /* PowerPC 7410 v1.2 (G4)                                                */
8629     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
8630     /* PowerPC 7410 v1.3 (G4)                                                */
8631     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
8632     /* PowerPC 7410 v1.4 (G4)                                                */
8633     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
8634     /* PowerPC 7448 (G4)                                                     */
8635     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
8636     /* PowerPC 7448 v1.0 (G4)                                                */
8637     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
8638     /* PowerPC 7448 v1.1 (G4)                                                */
8639     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
8640     /* PowerPC 7448 v2.0 (G4)                                                */
8641     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
8642     /* PowerPC 7448 v2.1 (G4)                                                */
8643     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
8644     /* PowerPC 7450 (G4)                                                     */
8645     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
8646     /* Code name for PowerPC 7450                                            */
8647     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
8648     /* PowerPC 7450 v1.0 (G4)                                                */
8649     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
8650     /* PowerPC 7450 v1.1 (G4)                                                */
8651     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
8652     /* PowerPC 7450 v1.2 (G4)                                                */
8653     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
8654     /* PowerPC 7450 v2.0 (G4)                                                */
8655     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
8656     /* PowerPC 7450 v2.1 (G4)                                                */
8657     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
8658     /* PowerPC 7441 (G4)                                                     */
8659     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
8660     /* PowerPC 7451 (G4)                                                     */
8661     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
8662     /* PowerPC 7441 v2.1 (G4)                                                */
8663     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
8664     /* PowerPC 7441 v2.3 (G4)                                                */
8665     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
8666     /* PowerPC 7451 v2.3 (G4)                                                */
8667     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
8668     /* PowerPC 7441 v2.10 (G4)                                                */
8669     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
8670     /* PowerPC 7451 v2.10 (G4)                                               */
8671     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
8672     /* PowerPC 7445 (G4)                                                     */
8673     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
8674     /* PowerPC 7455 (G4)                                                     */
8675     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
8676     /* Code name for PowerPC 7445/7455                                       */
8677     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
8678     /* PowerPC 7445 v1.0 (G4)                                                */
8679     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
8680     /* PowerPC 7455 v1.0 (G4)                                                */
8681     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
8682     /* PowerPC 7445 v2.1 (G4)                                                */
8683     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
8684     /* PowerPC 7455 v2.1 (G4)                                                */
8685     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
8686     /* PowerPC 7445 v3.2 (G4)                                                */
8687     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
8688     /* PowerPC 7455 v3.2 (G4)                                                */
8689     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
8690     /* PowerPC 7445 v3.3 (G4)                                                */
8691     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
8692     /* PowerPC 7455 v3.3 (G4)                                                */
8693     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
8694     /* PowerPC 7445 v3.4 (G4)                                                */
8695     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
8696     /* PowerPC 7455 v3.4 (G4)                                                */
8697     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
8698     /* PowerPC 7447 (G4)                                                     */
8699     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
8700     /* PowerPC 7457 (G4)                                                     */
8701     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
8702     /* Code name for PowerPC 7447/7457                                       */
8703     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
8704     /* PowerPC 7447 v1.0 (G4)                                                */
8705     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
8706     /* PowerPC 7457 v1.0 (G4)                                                */
8707     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
8708     /* PowerPC 7447 v1.1 (G4)                                                */
8709     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
8710     /* PowerPC 7457 v1.1 (G4)                                                */
8711     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
8712     /* PowerPC 7457 v1.2 (G4)                                                */
8713     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
8714     /* PowerPC 7447A (G4)                                                    */
8715     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
8716     /* PowerPC 7457A (G4)                                                    */
8717     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
8718     /* PowerPC 7447A v1.0 (G4)                                               */
8719     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
8720     /* PowerPC 7457A v1.0 (G4)                                               */
8721     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
8722     /* Code name for PowerPC 7447A/7457A                                     */
8723     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
8724     /* PowerPC 7447A v1.1 (G4)                                               */
8725     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
8726     /* PowerPC 7457A v1.1 (G4)                                               */
8727     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
8728     /* PowerPC 7447A v1.2 (G4)                                               */
8729     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
8730     /* PowerPC 7457A v1.2 (G4)                                               */
8731     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
8732     /* 64 bits PowerPC                                                       */
8733 #if defined (TARGET_PPC64)
8734     /* PowerPC 620                                                           */
8735     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
8736     /* Code name for PowerPC 620                                             */
8737     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
8738 #if defined (TODO)
8739     /* PowerPC 630 (POWER3)                                                  */
8740     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
8741     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
8742     /* Code names for POWER3                                                 */
8743     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
8744     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
8745 #endif
8746 #if defined (TODO)
8747     /* PowerPC 631 (Power 3+)                                                */
8748     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
8749     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
8750 #endif
8751 #if defined (TODO)
8752     /* POWER4                                                                */
8753     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
8754 #endif
8755 #if defined (TODO)
8756     /* POWER4p                                                               */
8757     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
8758 #endif
8759 #if defined (TODO)
8760     /* POWER5                                                                */
8761     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
8762     /* POWER5GR                                                              */
8763     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
8764 #endif
8765 #if defined (TODO)
8766     /* POWER5+                                                               */
8767     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
8768     /* POWER5GS                                                              */
8769     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
8770 #endif
8771 #if defined (TODO)
8772     /* POWER6                                                                */
8773     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
8774     /* POWER6 running in POWER5 mode                                         */
8775     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
8776     /* POWER6A                                                               */
8777     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
8778 #endif
8779     /* PowerPC 970                                                           */
8780     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
8781     /* PowerPC 970FX (G5)                                                    */
8782     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
8783     /* PowerPC 970FX v1.0 (G5)                                               */
8784     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
8785     /* PowerPC 970FX v2.0 (G5)                                               */
8786     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
8787     /* PowerPC 970FX v2.1 (G5)                                               */
8788     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
8789     /* PowerPC 970FX v3.0 (G5)                                               */
8790     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
8791     /* PowerPC 970FX v3.1 (G5)                                               */
8792     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
8793     /* PowerPC 970GX (G5)                                                    */
8794     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
8795     /* PowerPC 970MP                                                         */
8796     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
8797     /* PowerPC 970MP v1.0                                                    */
8798     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
8799     /* PowerPC 970MP v1.1                                                    */
8800     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
8801 #if defined (TODO)
8802     /* PowerPC Cell                                                          */
8803     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
8804 #endif
8805 #if defined (TODO)
8806     /* PowerPC Cell v1.0                                                     */
8807     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
8808 #endif
8809 #if defined (TODO)
8810     /* PowerPC Cell v2.0                                                     */
8811     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
8812 #endif
8813 #if defined (TODO)
8814     /* PowerPC Cell v3.0                                                     */
8815     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
8816 #endif
8817 #if defined (TODO)
8818     /* PowerPC Cell v3.1                                                     */
8819     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
8820 #endif
8821 #if defined (TODO)
8822     /* PowerPC Cell v3.2                                                     */
8823     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
8824 #endif
8825 #if defined (TODO)
8826     /* RS64 (Apache/A35)                                                     */
8827     /* This one seems to support the whole POWER2 instruction set
8828      * and the PowerPC 64 one.
8829      */
8830     /* What about A10 & A30 ? */
8831     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
8832     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
8833     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
8834 #endif
8835 #if defined (TODO)
8836     /* RS64-II (NorthStar/A50)                                               */
8837     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
8838     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
8839     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
8840 #endif
8841 #if defined (TODO)
8842     /* RS64-III (Pulsar)                                                     */
8843     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
8844     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
8845 #endif
8846 #if defined (TODO)
8847     /* RS64-IV (IceStar/IStar/SStar)                                         */
8848     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
8849     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
8850     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
8851     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
8852 #endif
8853 #endif /* defined (TARGET_PPC64) */
8854     /* POWER                                                                 */
8855 #if defined (TODO)
8856     /* Original POWER                                                        */
8857     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
8858     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
8859     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
8860     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
8861     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
8862 #endif
8863 #if defined (TODO)
8864     /* POWER2                                                                */
8865     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
8866     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
8867     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
8868 #endif
8869     /* PA semi cores                                                         */
8870 #if defined (TODO)
8871     /* PA PA6T */
8872     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
8873 #endif
8874     /* Generic PowerPCs                                                      */
8875 #if defined (TARGET_PPC64)
8876     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
8877 #endif
8878     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
8879     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
8880     /* Fallback                                                              */
8881     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
8882 };
8883
8884 /*****************************************************************************/
8885 /* Generic CPU instanciation routine                                         */
8886 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8887 {
8888 #if !defined(CONFIG_USER_ONLY)
8889     int i;
8890
8891     env->irq_inputs = NULL;
8892     /* Set all exception vectors to an invalid address */
8893     for (i = 0; i < POWERPC_EXCP_NB; i++)
8894         env->excp_vectors[i] = (target_ulong)(-1ULL);
8895     env->hreset_excp_prefix = 0x00000000;
8896     env->ivor_mask = 0x00000000;
8897     env->ivpr_mask = 0x00000000;
8898     /* Default MMU definitions */
8899     env->nb_BATs = 0;
8900     env->nb_tlb = 0;
8901     env->nb_ways = 0;
8902 #endif
8903     /* Register SPR common to all PowerPC implementations */
8904     gen_spr_generic(env);
8905     spr_register(env, SPR_PVR, "PVR",
8906                  SPR_NOACCESS, SPR_NOACCESS,
8907                  &spr_read_generic, SPR_NOACCESS,
8908                  def->pvr);
8909     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8910     if (def->svr != POWERPC_SVR_NONE) {
8911         if (def->svr & POWERPC_SVR_E500) {
8912             spr_register(env, SPR_E500_SVR, "SVR",
8913                          SPR_NOACCESS, SPR_NOACCESS,
8914                          &spr_read_generic, SPR_NOACCESS,
8915                          def->svr & ~POWERPC_SVR_E500);
8916         } else {
8917             spr_register(env, SPR_SVR, "SVR",
8918                          SPR_NOACCESS, SPR_NOACCESS,
8919                          &spr_read_generic, SPR_NOACCESS,
8920                          def->svr);
8921         }
8922     }
8923     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8924     (*def->init_proc)(env);
8925 #if !defined(CONFIG_USER_ONLY)
8926     env->excp_prefix = env->hreset_excp_prefix;
8927 #endif
8928     /* MSR bits & flags consistency checks */
8929     if (env->msr_mask & (1 << 25)) {
8930         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8931         case POWERPC_FLAG_SPE:
8932         case POWERPC_FLAG_VRE:
8933             break;
8934         default:
8935             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8936                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8937             exit(1);
8938         }
8939     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8940         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8941                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8942         exit(1);
8943     }
8944     if (env->msr_mask & (1 << 17)) {
8945         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8946         case POWERPC_FLAG_TGPR:
8947         case POWERPC_FLAG_CE:
8948             break;
8949         default:
8950             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8951                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8952             exit(1);
8953         }
8954     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8955         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8956                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8957         exit(1);
8958     }
8959     if (env->msr_mask & (1 << 10)) {
8960         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8961                               POWERPC_FLAG_UBLE)) {
8962         case POWERPC_FLAG_SE:
8963         case POWERPC_FLAG_DWE:
8964         case POWERPC_FLAG_UBLE:
8965             break;
8966         default:
8967             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8968                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8969                     "POWERPC_FLAG_UBLE\n");
8970             exit(1);
8971         }
8972     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8973                              POWERPC_FLAG_UBLE)) {
8974         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8975                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8976                 "POWERPC_FLAG_UBLE\n");
8977             exit(1);
8978     }
8979     if (env->msr_mask & (1 << 9)) {
8980         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8981         case POWERPC_FLAG_BE:
8982         case POWERPC_FLAG_DE:
8983             break;
8984         default:
8985             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8986                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8987             exit(1);
8988         }
8989     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8990         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8991                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8992         exit(1);
8993     }
8994     if (env->msr_mask & (1 << 2)) {
8995         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8996         case POWERPC_FLAG_PX:
8997         case POWERPC_FLAG_PMM:
8998             break;
8999         default:
9000             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9001                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9002             exit(1);
9003         }
9004     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9005         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9006                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9007         exit(1);
9008     }
9009     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9010         fprintf(stderr, "PowerPC flags inconsistency\n"
9011                 "Should define the time-base and decrementer clock source\n");
9012         exit(1);
9013     }
9014     /* Allocate TLBs buffer when needed */
9015 #if !defined(CONFIG_USER_ONLY)
9016     if (env->nb_tlb != 0) {
9017         int nb_tlb = env->nb_tlb;
9018         if (env->id_tlbs != 0)
9019             nb_tlb *= 2;
9020         env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
9021         /* Pre-compute some useful values */
9022         env->tlb_per_way = env->nb_tlb / env->nb_ways;
9023     }
9024     if (env->irq_inputs == NULL) {
9025         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9026                 " Attempt Qemu to crash very soon !\n");
9027     }
9028 #endif
9029     if (env->check_pow == NULL) {
9030         fprintf(stderr, "WARNING: no power management check handler "
9031                 "registered.\n"
9032                 " Attempt Qemu to crash very soon !\n");
9033     }
9034 }
9035
9036 #if defined(PPC_DUMP_CPU)
9037 static void dump_ppc_sprs (CPUPPCState *env)
9038 {
9039     ppc_spr_t *spr;
9040 #if !defined(CONFIG_USER_ONLY)
9041     uint32_t sr, sw;
9042 #endif
9043     uint32_t ur, uw;
9044     int i, j, n;
9045
9046     printf("Special purpose registers:\n");
9047     for (i = 0; i < 32; i++) {
9048         for (j = 0; j < 32; j++) {
9049             n = (i << 5) | j;
9050             spr = &env->spr_cb[n];
9051             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9052             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9053 #if !defined(CONFIG_USER_ONLY)
9054             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9055             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9056             if (sw || sr || uw || ur) {
9057                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9058                        (i << 5) | j, (i << 5) | j, spr->name,
9059                        sw ? 'w' : '-', sr ? 'r' : '-',
9060                        uw ? 'w' : '-', ur ? 'r' : '-');
9061             }
9062 #else
9063             if (uw || ur) {
9064                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9065                        (i << 5) | j, (i << 5) | j, spr->name,
9066                        uw ? 'w' : '-', ur ? 'r' : '-');
9067             }
9068 #endif
9069         }
9070     }
9071     fflush(stdout);
9072     fflush(stderr);
9073 }
9074 #endif
9075
9076 /*****************************************************************************/
9077 #include <stdlib.h>
9078 #include <string.h>
9079
9080 /* Opcode types */
9081 enum {
9082     PPC_DIRECT   = 0, /* Opcode routine        */
9083     PPC_INDIRECT = 1, /* Indirect opcode table */
9084 };
9085
9086 static inline int is_indirect_opcode (void *handler)
9087 {
9088     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9089 }
9090
9091 static inline opc_handler_t **ind_table(void *handler)
9092 {
9093     return (opc_handler_t **)((unsigned long)handler & ~3);
9094 }
9095
9096 /* Instruction table creation */
9097 /* Opcodes tables creation */
9098 static void fill_new_table (opc_handler_t **table, int len)
9099 {
9100     int i;
9101
9102     for (i = 0; i < len; i++)
9103         table[i] = &invalid_handler;
9104 }
9105
9106 static int create_new_table (opc_handler_t **table, unsigned char idx)
9107 {
9108     opc_handler_t **tmp;
9109
9110     tmp = malloc(0x20 * sizeof(opc_handler_t));
9111     fill_new_table(tmp, 0x20);
9112     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9113
9114     return 0;
9115 }
9116
9117 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9118                             opc_handler_t *handler)
9119 {
9120     if (table[idx] != &invalid_handler)
9121         return -1;
9122     table[idx] = handler;
9123
9124     return 0;
9125 }
9126
9127 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9128                                  unsigned char idx, opc_handler_t *handler)
9129 {
9130     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9131         printf("*** ERROR: opcode %02x already assigned in main "
9132                "opcode table\n", idx);
9133 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9134         printf("           Registered handler '%s' - new handler '%s'\n",
9135                ppc_opcodes[idx]->oname, handler->oname);
9136 #endif
9137         return -1;
9138     }
9139
9140     return 0;
9141 }
9142
9143 static int register_ind_in_table (opc_handler_t **table,
9144                                   unsigned char idx1, unsigned char idx2,
9145                                   opc_handler_t *handler)
9146 {
9147     if (table[idx1] == &invalid_handler) {
9148         if (create_new_table(table, idx1) < 0) {
9149             printf("*** ERROR: unable to create indirect table "
9150                    "idx=%02x\n", idx1);
9151             return -1;
9152         }
9153     } else {
9154         if (!is_indirect_opcode(table[idx1])) {
9155             printf("*** ERROR: idx %02x already assigned to a direct "
9156                    "opcode\n", idx1);
9157 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9158             printf("           Registered handler '%s' - new handler '%s'\n",
9159                    ind_table(table[idx1])[idx2]->oname, handler->oname);
9160 #endif
9161             return -1;
9162         }
9163     }
9164     if (handler != NULL &&
9165         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9166         printf("*** ERROR: opcode %02x already assigned in "
9167                "opcode table %02x\n", idx2, idx1);
9168 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9169         printf("           Registered handler '%s' - new handler '%s'\n",
9170                ind_table(table[idx1])[idx2]->oname, handler->oname);
9171 #endif
9172         return -1;
9173     }
9174
9175     return 0;
9176 }
9177
9178 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9179                               unsigned char idx1, unsigned char idx2,
9180                               opc_handler_t *handler)
9181 {
9182     int ret;
9183
9184     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9185
9186     return ret;
9187 }
9188
9189 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9190                                  unsigned char idx1, unsigned char idx2,
9191                                  unsigned char idx3, opc_handler_t *handler)
9192 {
9193     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9194         printf("*** ERROR: unable to join indirect table idx "
9195                "[%02x-%02x]\n", idx1, idx2);
9196         return -1;
9197     }
9198     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9199                               handler) < 0) {
9200         printf("*** ERROR: unable to insert opcode "
9201                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9202         return -1;
9203     }
9204
9205     return 0;
9206 }
9207
9208 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9209 {
9210     if (insn->opc2 != 0xFF) {
9211         if (insn->opc3 != 0xFF) {
9212             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9213                                      insn->opc3, &insn->handler) < 0)
9214                 return -1;
9215         } else {
9216             if (register_ind_insn(ppc_opcodes, insn->opc1,
9217                                   insn->opc2, &insn->handler) < 0)
9218                 return -1;
9219         }
9220     } else {
9221         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9222             return -1;
9223     }
9224
9225     return 0;
9226 }
9227
9228 static int test_opcode_table (opc_handler_t **table, int len)
9229 {
9230     int i, count, tmp;
9231
9232     for (i = 0, count = 0; i < len; i++) {
9233         /* Consistency fixup */
9234         if (table[i] == NULL)
9235             table[i] = &invalid_handler;
9236         if (table[i] != &invalid_handler) {
9237             if (is_indirect_opcode(table[i])) {
9238                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9239                 if (tmp == 0) {
9240                     free(table[i]);
9241                     table[i] = &invalid_handler;
9242                 } else {
9243                     count++;
9244                 }
9245             } else {
9246                 count++;
9247             }
9248         }
9249     }
9250
9251     return count;
9252 }
9253
9254 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9255 {
9256     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9257         printf("*** WARNING: no opcode defined !\n");
9258 }
9259
9260 /*****************************************************************************/
9261 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9262 {
9263     opcode_t *opc, *start, *end;
9264
9265     fill_new_table(env->opcodes, 0x40);
9266     if (&opc_start < &opc_end) {
9267         start = &opc_start;
9268         end = &opc_end;
9269     } else {
9270         start = &opc_end;
9271         end = &opc_start;
9272     }
9273     for (opc = start + 1; opc != end; opc++) {
9274         if ((opc->handler.type & def->insns_flags) != 0) {
9275             if (register_insn(env->opcodes, opc) < 0) {
9276                 printf("*** ERROR initializing PowerPC instruction "
9277                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9278                        opc->opc3);
9279                 return -1;
9280             }
9281         }
9282     }
9283     fix_opcode_tables(env->opcodes);
9284     fflush(stdout);
9285     fflush(stderr);
9286
9287     return 0;
9288 }
9289
9290 #if defined(PPC_DUMP_CPU)
9291 static void dump_ppc_insns (CPUPPCState *env)
9292 {
9293     opc_handler_t **table, *handler;
9294     const char *p, *q;
9295     uint8_t opc1, opc2, opc3;
9296
9297     printf("Instructions set:\n");
9298     /* opc1 is 6 bits long */
9299     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9300         table = env->opcodes;
9301         handler = table[opc1];
9302         if (is_indirect_opcode(handler)) {
9303             /* opc2 is 5 bits long */
9304             for (opc2 = 0; opc2 < 0x20; opc2++) {
9305                 table = env->opcodes;
9306                 handler = env->opcodes[opc1];
9307                 table = ind_table(handler);
9308                 handler = table[opc2];
9309                 if (is_indirect_opcode(handler)) {
9310                     table = ind_table(handler);
9311                     /* opc3 is 5 bits long */
9312                     for (opc3 = 0; opc3 < 0x20; opc3++) {
9313                         handler = table[opc3];
9314                         if (handler->handler != &gen_invalid) {
9315                             /* Special hack to properly dump SPE insns */
9316                             p = strchr(handler->oname, '_');
9317                             if (p == NULL) {
9318                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
9319                                        "%s\n",
9320                                        opc1, opc2, opc3, opc1,
9321                                        (opc3 << 5) | opc2,
9322                                        handler->oname);
9323                             } else {
9324                                 q = "speundef";
9325                                 if ((p - handler->oname) != strlen(q) ||
9326                                     memcmp(handler->oname, q, strlen(q)) != 0) {
9327                                     /* First instruction */
9328                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9329                                            "%.*s\n",
9330                                            opc1, opc2 << 1, opc3, opc1,
9331                                            (opc3 << 6) | (opc2 << 1),
9332                                            (int)(p - handler->oname),
9333                                            handler->oname);
9334                                 }
9335                                 if (strcmp(p + 1, q) != 0) {
9336                                     /* Second instruction */
9337                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9338                                            "%s\n",
9339                                            opc1, (opc2 << 1) | 1, opc3, opc1,
9340                                            (opc3 << 6) | (opc2 << 1) | 1,
9341                                            p + 1);
9342                                 }
9343                             }
9344                         }
9345                     }
9346                 } else {
9347                     if (handler->handler != &gen_invalid) {
9348                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9349                                opc1, opc2, opc1, opc2, handler->oname);
9350                     }
9351                 }
9352             }
9353         } else {
9354             if (handler->handler != &gen_invalid) {
9355                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9356                        opc1, opc1, handler->oname);
9357             }
9358         }
9359     }
9360 }
9361 #endif
9362
9363 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9364 {
9365     if (n < 32) {
9366         stfq_p(mem_buf, env->fpr[n]);
9367         return 8;
9368     }
9369     if (n == 32) {
9370         /* FPSCR not implemented  */
9371         memset(mem_buf, 0, 4);
9372         return 4;
9373     }
9374     return 0;
9375 }
9376
9377 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9378 {
9379     if (n < 32) {
9380         env->fpr[n] = ldfq_p(mem_buf);
9381         return 8;
9382     }
9383     if (n == 32) {
9384         /* FPSCR not implemented  */
9385         return 4;
9386     }
9387     return 0;
9388 }
9389
9390 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9391 {
9392     if (n < 32) {
9393 #ifdef WORDS_BIGENDIAN
9394         stq_p(mem_buf, env->avr[n].u64[0]);
9395         stq_p(mem_buf+8, env->avr[n].u64[1]);
9396 #else
9397         stq_p(mem_buf, env->avr[n].u64[1]);
9398         stq_p(mem_buf+8, env->avr[n].u64[0]);
9399 #endif
9400         return 16;
9401     }
9402     if (n == 32) {
9403         stl_p(mem_buf, env->vscr);
9404         return 4;
9405     }
9406     if (n == 33) {
9407         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9408         return 4;
9409     }
9410     return 0;
9411 }
9412
9413 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9414 {
9415     if (n < 32) {
9416 #ifdef WORDS_BIGENDIAN
9417         env->avr[n].u64[0] = ldq_p(mem_buf);
9418         env->avr[n].u64[1] = ldq_p(mem_buf+8);
9419 #else
9420         env->avr[n].u64[1] = ldq_p(mem_buf);
9421         env->avr[n].u64[0] = ldq_p(mem_buf+8);
9422 #endif
9423         return 16;
9424     }
9425     if (n == 32) {
9426         env->vscr = ldl_p(mem_buf);
9427         return 4;
9428     }
9429     if (n == 33) {
9430         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9431         return 4;
9432     }
9433     return 0;
9434 }
9435
9436 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9437 {
9438     if (n < 32) {
9439 #if defined(TARGET_PPC64)
9440         stl_p(mem_buf, env->gpr[n] >> 32);
9441 #else
9442         stl_p(mem_buf, env->gprh[n]);
9443 #endif
9444         return 4;
9445     }
9446     if (n == 32) {
9447         stq_p(mem_buf, env->spe_acc);
9448         return 8;
9449     }
9450     if (n == 33) {
9451         stl_p(mem_buf, env->spe_fscr);
9452         return 4;
9453     }
9454     return 0;
9455 }
9456
9457 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9458 {
9459     if (n < 32) {
9460 #if defined(TARGET_PPC64)
9461         target_ulong lo = (uint32_t)env->gpr[n];
9462         target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9463         env->gpr[n] = lo | hi;
9464 #else
9465         env->gprh[n] = ldl_p(mem_buf);
9466 #endif
9467         return 4;
9468     }
9469     if (n == 32) {
9470         env->spe_acc = ldq_p(mem_buf);
9471         return 8;
9472     }
9473     if (n == 33) {
9474         env->spe_fscr = ldl_p(mem_buf);
9475         return 4;
9476     }
9477     return 0;
9478 }
9479
9480 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9481 {
9482     env->msr_mask = def->msr_mask;
9483     env->mmu_model = def->mmu_model;
9484     env->excp_model = def->excp_model;
9485     env->bus_model = def->bus_model;
9486     env->insns_flags = def->insns_flags;
9487     env->flags = def->flags;
9488     env->bfd_mach = def->bfd_mach;
9489     env->check_pow = def->check_pow;
9490     if (create_ppc_opcodes(env, def) < 0)
9491         return -1;
9492     init_ppc_proc(env, def);
9493
9494     if (def->insns_flags & PPC_FLOAT) {
9495         gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9496                                  33, "power-fpu.xml", 0);
9497     }
9498     if (def->insns_flags & PPC_ALTIVEC) {
9499         gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9500                                  34, "power-altivec.xml", 0);
9501     }
9502     if (def->insns_flags & PPC_SPE) {
9503         gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9504                                  34, "power-spe.xml", 0);
9505     }
9506
9507 #if defined(PPC_DUMP_CPU)
9508     {
9509         const char *mmu_model, *excp_model, *bus_model;
9510         switch (env->mmu_model) {
9511         case POWERPC_MMU_32B:
9512             mmu_model = "PowerPC 32";
9513             break;
9514         case POWERPC_MMU_SOFT_6xx:
9515             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9516             break;
9517         case POWERPC_MMU_SOFT_74xx:
9518             mmu_model = "PowerPC 74xx with software driven TLBs";
9519             break;
9520         case POWERPC_MMU_SOFT_4xx:
9521             mmu_model = "PowerPC 4xx with software driven TLBs";
9522             break;
9523         case POWERPC_MMU_SOFT_4xx_Z:
9524             mmu_model = "PowerPC 4xx with software driven TLBs "
9525                 "and zones protections";
9526             break;
9527         case POWERPC_MMU_REAL:
9528             mmu_model = "PowerPC real mode only";
9529             break;
9530         case POWERPC_MMU_MPC8xx:
9531             mmu_model = "PowerPC MPC8xx";
9532             break;
9533         case POWERPC_MMU_BOOKE:
9534             mmu_model = "PowerPC BookE";
9535             break;
9536         case POWERPC_MMU_BOOKE_FSL:
9537             mmu_model = "PowerPC BookE FSL";
9538             break;
9539         case POWERPC_MMU_601:
9540             mmu_model = "PowerPC 601";
9541             break;
9542 #if defined (TARGET_PPC64)
9543         case POWERPC_MMU_64B:
9544             mmu_model = "PowerPC 64";
9545             break;
9546         case POWERPC_MMU_620:
9547             mmu_model = "PowerPC 620";
9548             break;
9549 #endif
9550         default:
9551             mmu_model = "Unknown or invalid";
9552             break;
9553         }
9554         switch (env->excp_model) {
9555         case POWERPC_EXCP_STD:
9556             excp_model = "PowerPC";
9557             break;
9558         case POWERPC_EXCP_40x:
9559             excp_model = "PowerPC 40x";
9560             break;
9561         case POWERPC_EXCP_601:
9562             excp_model = "PowerPC 601";
9563             break;
9564         case POWERPC_EXCP_602:
9565             excp_model = "PowerPC 602";
9566             break;
9567         case POWERPC_EXCP_603:
9568             excp_model = "PowerPC 603";
9569             break;
9570         case POWERPC_EXCP_603E:
9571             excp_model = "PowerPC 603e";
9572             break;
9573         case POWERPC_EXCP_604:
9574             excp_model = "PowerPC 604";
9575             break;
9576         case POWERPC_EXCP_7x0:
9577             excp_model = "PowerPC 740/750";
9578             break;
9579         case POWERPC_EXCP_7x5:
9580             excp_model = "PowerPC 745/755";
9581             break;
9582         case POWERPC_EXCP_74xx:
9583             excp_model = "PowerPC 74xx";
9584             break;
9585         case POWERPC_EXCP_BOOKE:
9586             excp_model = "PowerPC BookE";
9587             break;
9588 #if defined (TARGET_PPC64)
9589         case POWERPC_EXCP_970:
9590             excp_model = "PowerPC 970";
9591             break;
9592 #endif
9593         default:
9594             excp_model = "Unknown or invalid";
9595             break;
9596         }
9597         switch (env->bus_model) {
9598         case PPC_FLAGS_INPUT_6xx:
9599             bus_model = "PowerPC 6xx";
9600             break;
9601         case PPC_FLAGS_INPUT_BookE:
9602             bus_model = "PowerPC BookE";
9603             break;
9604         case PPC_FLAGS_INPUT_405:
9605             bus_model = "PowerPC 405";
9606             break;
9607         case PPC_FLAGS_INPUT_401:
9608             bus_model = "PowerPC 401/403";
9609             break;
9610         case PPC_FLAGS_INPUT_RCPU:
9611             bus_model = "RCPU / MPC8xx";
9612             break;
9613 #if defined (TARGET_PPC64)
9614         case PPC_FLAGS_INPUT_970:
9615             bus_model = "PowerPC 970";
9616             break;
9617 #endif
9618         default:
9619             bus_model = "Unknown or invalid";
9620             break;
9621         }
9622         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9623                "    MMU model        : %s\n",
9624                def->name, def->pvr, def->msr_mask, mmu_model);
9625 #if !defined(CONFIG_USER_ONLY)
9626         if (env->tlb != NULL) {
9627             printf("                       %d %s TLB in %d ways\n",
9628                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9629                    env->nb_ways);
9630         }
9631 #endif
9632         printf("    Exceptions model : %s\n"
9633                "    Bus model        : %s\n",
9634                excp_model, bus_model);
9635         printf("    MSR features     :\n");
9636         if (env->flags & POWERPC_FLAG_SPE)
9637             printf("                        signal processing engine enable"
9638                    "\n");
9639         else if (env->flags & POWERPC_FLAG_VRE)
9640             printf("                        vector processor enable\n");
9641         if (env->flags & POWERPC_FLAG_TGPR)
9642             printf("                        temporary GPRs\n");
9643         else if (env->flags & POWERPC_FLAG_CE)
9644             printf("                        critical input enable\n");
9645         if (env->flags & POWERPC_FLAG_SE)
9646             printf("                        single-step trace mode\n");
9647         else if (env->flags & POWERPC_FLAG_DWE)
9648             printf("                        debug wait enable\n");
9649         else if (env->flags & POWERPC_FLAG_UBLE)
9650             printf("                        user BTB lock enable\n");
9651         if (env->flags & POWERPC_FLAG_BE)
9652             printf("                        branch-step trace mode\n");
9653         else if (env->flags & POWERPC_FLAG_DE)
9654             printf("                        debug interrupt enable\n");
9655         if (env->flags & POWERPC_FLAG_PX)
9656             printf("                        inclusive protection\n");
9657         else if (env->flags & POWERPC_FLAG_PMM)
9658             printf("                        performance monitor mark\n");
9659         if (env->flags == POWERPC_FLAG_NONE)
9660             printf("                        none\n");
9661         printf("    Time-base/decrementer clock source: %s\n",
9662                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9663     }
9664     dump_ppc_insns(env);
9665     dump_ppc_sprs(env);
9666     fflush(stdout);
9667 #endif
9668
9669     return 0;
9670 }
9671
9672 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9673 {
9674     const ppc_def_t *ret;
9675     uint32_t pvr_rev;
9676     int i, best, match, best_match, max;
9677
9678     ret = NULL;
9679     max = ARRAY_SIZE(ppc_defs);
9680     best = -1;
9681     pvr_rev = pvr & 0xFFFF;
9682     /* We want all specified bits to match */
9683     best_match = 32 - ctz32(pvr_rev);
9684     for (i = 0; i < max; i++) {
9685         /* We check that the 16 higher bits are the same to ensure the CPU
9686          * model will be the choosen one.
9687          */
9688         if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9689             /* We want as much as possible of the low-level 16 bits
9690              * to be the same but we allow inexact matches.
9691              */
9692             match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9693             /* We check '>=' instead of '>' because the PPC_defs table
9694              * is ordered by increasing revision.
9695              * Then, we will match the higher revision compatible
9696              * with the requested PVR
9697              */
9698             if (match >= best_match) {
9699                 best = i;
9700                 best_match = match;
9701             }
9702         }
9703     }
9704     if (best != -1)
9705         ret = &ppc_defs[best];
9706
9707     return ret;
9708 }
9709
9710 #include <ctype.h>
9711
9712 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9713 {
9714     const ppc_def_t *ret;
9715     const char *p;
9716     int i, max, len;
9717
9718     /* Check if the given name is a PVR */
9719     len = strlen(name);
9720     if (len == 10 && name[0] == '0' && name[1] == 'x') {
9721         p = name + 2;
9722         goto check_pvr;
9723     } else if (len == 8) {
9724         p = name;
9725     check_pvr:
9726         for (i = 0; i < 8; i++) {
9727             if (!qemu_isxdigit(*p++))
9728                 break;
9729         }
9730         if (i == 8)
9731             return ppc_find_by_pvr(strtoul(name, NULL, 16));
9732     }
9733     ret = NULL;
9734     max = ARRAY_SIZE(ppc_defs);
9735     for (i = 0; i < max; i++) {
9736         if (strcasecmp(name, ppc_defs[i].name) == 0) {
9737             ret = &ppc_defs[i];
9738             break;
9739         }
9740     }
9741
9742     return ret;
9743 }
9744
9745 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9746 {
9747     int i, max;
9748
9749     max = ARRAY_SIZE(ppc_defs);
9750     for (i = 0; i < max; i++) {
9751         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9752                        ppc_defs[i].name, ppc_defs[i].pvr);
9753     }
9754 }