target-ppc: remove dead code
[qemu/aliguori-queue.git] / hw / slavio_intctl.c
blobb76d3acadd7b1858ae5d348d7bd4aba6128796a2
1 /*
2 * QEMU Sparc SLAVIO interrupt controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "sun4m.h"
26 #include "monitor.h"
27 #include "sysbus.h"
29 //#define DEBUG_IRQ_COUNT
30 //#define DEBUG_IRQ
32 #ifdef DEBUG_IRQ
33 #define DPRINTF(fmt, ...) \
34 do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
35 #else
36 #define DPRINTF(fmt, ...)
37 #endif
40 * Registers of interrupt controller in sun4m.
42 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
43 * produced as NCR89C105. See
44 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
46 * There is a system master controller and one for each cpu.
50 #define MAX_CPUS 16
51 #define MAX_PILS 16
53 struct SLAVIO_INTCTLState;
55 typedef struct SLAVIO_CPUINTCTLState {
56 uint32_t intreg_pending;
57 struct SLAVIO_INTCTLState *master;
58 uint32_t cpu;
59 uint32_t irl_out;
60 } SLAVIO_CPUINTCTLState;
62 typedef struct SLAVIO_INTCTLState {
63 SysBusDevice busdev;
64 uint32_t intregm_pending;
65 uint32_t intregm_disabled;
66 uint32_t target_cpu;
67 #ifdef DEBUG_IRQ_COUNT
68 uint64_t irq_count[32];
69 #endif
70 qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
71 SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
72 } SLAVIO_INTCTLState;
74 #define INTCTL_MAXADDR 0xf
75 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
76 #define INTCTLM_SIZE 0x14
77 #define MASTER_IRQ_MASK ~0x0fa2007f
78 #define MASTER_DISABLE 0x80000000
79 #define CPU_SOFTIRQ_MASK 0xfffe0000
80 #define CPU_IRQ_INT15_IN (1 << 15)
81 #define CPU_IRQ_TIMER_IN (1 << 14)
83 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
85 // per-cpu interrupt controller
86 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
88 SLAVIO_CPUINTCTLState *s = opaque;
89 uint32_t saddr, ret;
91 saddr = addr >> 2;
92 switch (saddr) {
93 case 0:
94 ret = s->intreg_pending;
95 break;
96 default:
97 ret = 0;
98 break;
100 DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
102 return ret;
105 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
106 uint32_t val)
108 SLAVIO_CPUINTCTLState *s = opaque;
109 uint32_t saddr;
111 saddr = addr >> 2;
112 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
113 switch (saddr) {
114 case 1: // clear pending softints
115 val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
116 s->intreg_pending &= ~val;
117 slavio_check_interrupts(s->master, 1);
118 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
119 s->intreg_pending);
120 break;
121 case 2: // set softint
122 val &= CPU_SOFTIRQ_MASK;
123 s->intreg_pending |= val;
124 slavio_check_interrupts(s->master, 1);
125 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
126 s->intreg_pending);
127 break;
128 default:
129 break;
133 static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
134 NULL,
135 NULL,
136 slavio_intctl_mem_readl,
139 static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
140 NULL,
141 NULL,
142 slavio_intctl_mem_writel,
145 // master system interrupt controller
146 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
148 SLAVIO_INTCTLState *s = opaque;
149 uint32_t saddr, ret;
151 saddr = addr >> 2;
152 switch (saddr) {
153 case 0:
154 ret = s->intregm_pending & ~MASTER_DISABLE;
155 break;
156 case 1:
157 ret = s->intregm_disabled & MASTER_IRQ_MASK;
158 break;
159 case 4:
160 ret = s->target_cpu;
161 break;
162 default:
163 ret = 0;
164 break;
166 DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
168 return ret;
171 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
172 uint32_t val)
174 SLAVIO_INTCTLState *s = opaque;
175 uint32_t saddr;
177 saddr = addr >> 2;
178 DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
179 switch (saddr) {
180 case 2: // clear (enable)
181 // Force clear unused bits
182 val &= MASTER_IRQ_MASK;
183 s->intregm_disabled &= ~val;
184 DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
185 s->intregm_disabled);
186 slavio_check_interrupts(s, 1);
187 break;
188 case 3: // set (disable; doesn't affect pending)
189 // Force clear unused bits
190 val &= MASTER_IRQ_MASK;
191 s->intregm_disabled |= val;
192 slavio_check_interrupts(s, 1);
193 DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
194 s->intregm_disabled);
195 break;
196 case 4:
197 s->target_cpu = val & (MAX_CPUS - 1);
198 slavio_check_interrupts(s, 1);
199 DPRINTF("Set master irq cpu %d\n", s->target_cpu);
200 break;
201 default:
202 break;
206 static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
207 NULL,
208 NULL,
209 slavio_intctlm_mem_readl,
212 static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
213 NULL,
214 NULL,
215 slavio_intctlm_mem_writel,
218 void slavio_pic_info(Monitor *mon, DeviceState *dev)
220 SysBusDevice *sd;
221 SLAVIO_INTCTLState *s;
222 int i;
224 sd = sysbus_from_qdev(dev);
225 s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
226 for (i = 0; i < MAX_CPUS; i++) {
227 monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
228 s->slaves[i].intreg_pending);
230 monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
231 s->intregm_pending, s->intregm_disabled);
234 void slavio_irq_info(Monitor *mon, DeviceState *dev)
236 #ifndef DEBUG_IRQ_COUNT
237 monitor_printf(mon, "irq statistic code not compiled.\n");
238 #else
239 SysBusDevice *sd;
240 SLAVIO_INTCTLState *s;
241 int i;
242 int64_t count;
244 sd = sysbus_from_qdev(dev);
245 s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
246 monitor_printf(mon, "IRQ statistics:\n");
247 for (i = 0; i < 32; i++) {
248 count = s->irq_count[i];
249 if (count > 0)
250 monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
252 #endif
255 static const uint32_t intbit_to_level[] = {
256 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
257 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
260 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
262 uint32_t pending = s->intregm_pending, pil_pending;
263 unsigned int i, j;
265 pending &= ~s->intregm_disabled;
267 DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
268 for (i = 0; i < MAX_CPUS; i++) {
269 pil_pending = 0;
271 /* If we are the current interrupt target, get hard interrupts */
272 if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
273 (i == s->target_cpu)) {
274 for (j = 0; j < 32; j++) {
275 if ((pending & (1 << j)) && intbit_to_level[j]) {
276 pil_pending |= 1 << intbit_to_level[j];
281 /* Calculate current pending hard interrupts for display */
282 s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
283 CPU_IRQ_TIMER_IN;
284 if (i == s->target_cpu) {
285 for (j = 0; j < 32; j++) {
286 if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
287 s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
292 /* Level 15 and CPU timer interrupts are not maskable */
293 pil_pending |= s->slaves[i].intreg_pending &
294 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
296 /* Add soft interrupts */
297 pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
299 if (set_irqs) {
300 for (j = MAX_PILS; j > 0; j--) {
301 if (pil_pending & (1 << j)) {
302 if (!(s->slaves[i].irl_out & (1 << j))) {
303 qemu_irq_raise(s->cpu_irqs[i][j]);
305 } else {
306 if (s->slaves[i].irl_out & (1 << j)) {
307 qemu_irq_lower(s->cpu_irqs[i][j]);
312 s->slaves[i].irl_out = pil_pending;
317 * "irq" here is the bit number in the system interrupt register to
318 * separate serial and keyboard interrupts sharing a level.
320 static void slavio_set_irq(void *opaque, int irq, int level)
322 SLAVIO_INTCTLState *s = opaque;
323 uint32_t mask = 1 << irq;
324 uint32_t pil = intbit_to_level[irq];
325 unsigned int i;
327 DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
328 level);
329 if (pil > 0) {
330 if (level) {
331 #ifdef DEBUG_IRQ_COUNT
332 s->irq_count[pil]++;
333 #endif
334 s->intregm_pending |= mask;
335 if (pil == 15) {
336 for (i = 0; i < MAX_CPUS; i++) {
337 s->slaves[i].intreg_pending |= 1 << pil;
340 } else {
341 s->intregm_pending &= ~mask;
342 if (pil == 15) {
343 for (i = 0; i < MAX_CPUS; i++) {
344 s->slaves[i].intreg_pending &= ~(1 << pil);
348 slavio_check_interrupts(s, 1);
352 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
354 SLAVIO_INTCTLState *s = opaque;
356 DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
358 if (level) {
359 s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
360 } else {
361 s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
364 slavio_check_interrupts(s, 1);
367 static void slavio_set_irq_all(void *opaque, int irq, int level)
369 if (irq < 32) {
370 slavio_set_irq(opaque, irq, level);
371 } else {
372 slavio_set_timer_irq_cpu(opaque, irq - 32, level);
376 static int vmstate_intctl_post_load(void *opaque, int version_id)
378 SLAVIO_INTCTLState *s = opaque;
380 slavio_check_interrupts(s, 0);
381 return 0;
384 static const VMStateDescription vmstate_intctl_cpu = {
385 .name ="slavio_intctl_cpu",
386 .version_id = 1,
387 .minimum_version_id = 1,
388 .minimum_version_id_old = 1,
389 .fields = (VMStateField []) {
390 VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
391 VMSTATE_END_OF_LIST()
395 static const VMStateDescription vmstate_intctl = {
396 .name ="slavio_intctl",
397 .version_id = 1,
398 .minimum_version_id = 1,
399 .minimum_version_id_old = 1,
400 .post_load = vmstate_intctl_post_load,
401 .fields = (VMStateField []) {
402 VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
403 vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
404 VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
405 VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
406 VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
407 VMSTATE_END_OF_LIST()
411 static void slavio_intctl_reset(DeviceState *d)
413 SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
414 int i;
416 for (i = 0; i < MAX_CPUS; i++) {
417 s->slaves[i].intreg_pending = 0;
418 s->slaves[i].irl_out = 0;
420 s->intregm_disabled = ~MASTER_IRQ_MASK;
421 s->intregm_pending = 0;
422 s->target_cpu = 0;
423 slavio_check_interrupts(s, 0);
426 static int slavio_intctl_init1(SysBusDevice *dev)
428 SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
429 int io_memory;
430 unsigned int i, j;
432 qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
433 io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
434 slavio_intctlm_mem_write, s);
435 sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
441 io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
442 slavio_intctl_mem_write,
443 &s->slaves[i]);
444 sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
445 s->slaves[i].cpu = i;
446 s->slaves[i].master = s;
449 return 0;
452 static SysBusDeviceInfo slavio_intctl_info = {
453 .init = slavio_intctl_init1,
454 .qdev.name = "slavio_intctl",
455 .qdev.size = sizeof(SLAVIO_INTCTLState),
456 .qdev.vmsd = &vmstate_intctl,
457 .qdev.reset = slavio_intctl_reset,
460 static void slavio_intctl_register_devices(void)
462 sysbus_register_withprop(&slavio_intctl_info);
465 device_init(slavio_intctl_register_devices)