hw/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "hw.h"
  40 #include "flash.h"
  41 #include "block.h"
  42 #include "qemu-timer.h"
  43
  44 #define PFLASH_BUG(fmt, ...) \
  45 do { \
  46     printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  47     exit(1); \
  48 } while(0)
  49
  50 /* #define PFLASH_DEBUG */
  51 #ifdef PFLASH_DEBUG
  52 #define DPRINTF(fmt, ...)                          \
  53 do {                                               \
  54     printf("PFLASH: " fmt , ## __VA_ARGS__);       \
  55 } while (0)
  56 #else
  57 #define DPRINTF(fmt, ...) do { } while (0)
  58 #endif
  59
  60 struct pflash_t {
  61     BlockDriverState *bs;
  62     target_phys_addr_t base;
  63     target_phys_addr_t sector_len;
  64     target_phys_addr_t total_len;
  65     int width;
  66     int wcycle; /* if 0, the flash is read normally */
  67     int bypass;
  68     int ro;
  69     uint8_t cmd;
  70     uint8_t status;
  71     uint16_t ident[4];
  72     uint8_t cfi_len;
  73     uint8_t cfi_table[0x52];
  74     target_phys_addr_t counter;
  75     unsigned int writeblock_size;
  76     QEMUTimer *timer;
  77     ram_addr_t off;
  78     int fl_mem;
  79     void *storage;
  80 };
  81
  82 static void pflash_timer (void *opaque)
  83 {
  84     pflash_t *pfl = opaque;
  85
  86     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  87     /* Reset flash */
  88     pfl->status ^= 0x80;
  89     if (pfl->bypass) {
  90         pfl->wcycle = 2;
  91     } else {
  92         cpu_register_physical_memory(pfl->base, pfl->total_len,
  93                         pfl->off | IO_MEM_ROMD | pfl->fl_mem);
  94         pfl->wcycle = 0;
  95     }
  96     pfl->cmd = 0;
  97 }
  98
  99 static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
 100                              int width, int be)
 101 {
 102     target_phys_addr_t boff;
 103     uint32_t ret;
 104     uint8_t *p;
 105
 106     ret = -1;
 107     boff = offset & 0xFF; /* why this here ?? */
 108
 109     if (pfl->width == 2)
 110         boff = boff >> 1;
 111     else if (pfl->width == 4)
 112         boff = boff >> 2;
 113
 114 #if 0
 115     DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
 116             __func__, offset, pfl->cmd, width);
 117 #endif
 118     switch (pfl->cmd) {
 119     case 0x00:
 120         /* Flash area read */
 121         p = pfl->storage;
 122         switch (width) {
 123         case 1:
 124             ret = p[offset];
 125             DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
 126                     __func__, offset, ret);
 127             break;
 128         case 2:
 129             if (be) {
 130                 ret = p[offset] << 8;
 131                 ret |= p[offset + 1];
 132             } else {
 133                 ret = p[offset];
 134                 ret |= p[offset + 1] << 8;
 135             }
 136             DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
 137                     __func__, offset, ret);
 138             break;
 139         case 4:
 140             if (be) {
 141                 ret = p[offset] << 24;
 142                 ret |= p[offset + 1] << 16;
 143                 ret |= p[offset + 2] << 8;
 144                 ret |= p[offset + 3];
 145             } else {
 146                 ret = p[offset];
 147                 ret |= p[offset + 1] << 8;
 148                 ret |= p[offset + 1] << 8;
 149                 ret |= p[offset + 2] << 16;
 150                 ret |= p[offset + 3] << 24;
 151             }
 152             DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
 153                     __func__, offset, ret);
 154             break;
 155         default:
 156             DPRINTF("BUG in %s\n", __func__);
 157         }
 158
 159         break;
 160     case 0x20: /* Block erase */
 161     case 0x50: /* Clear status register */
 162     case 0x60: /* Block /un)lock */
 163     case 0x70: /* Status Register */
 164     case 0xe8: /* Write block */
 165         /* Status register read */
 166         ret = pfl->status;
 167         DPRINTF("%s: status %x\n", __func__, ret);
 168         break;
 169     case 0x98: /* Query mode */
 170         if (boff > pfl->cfi_len)
 171             ret = 0;
 172         else
 173             ret = pfl->cfi_table[boff];
 174         break;
 175     default:
 176         /* This should never happen : reset state & treat it as a read */
 177         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 178         pfl->wcycle = 0;
 179         pfl->cmd = 0;
 180     }
 181     return ret;
 182 }
 183
 184 /* update flash content on disk */
 185 static void pflash_update(pflash_t *pfl, int offset,
 186                           int size)
 187 {
 188     int offset_end;
 189     if (pfl->bs) {
 190         offset_end = offset + size;
 191         /* round to sectors */
 192         offset = offset >> 9;
 193         offset_end = (offset_end + 511) >> 9;
 194         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 195                    offset_end - offset);
 196     }
 197 }
 198
 199 static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
 200                                      uint32_t value, int width, int be)
 201 {
 202     uint8_t *p = pfl->storage;
 203
 204     DPRINTF("%s: block write offset " TARGET_FMT_plx
 205             " value %x counter " TARGET_FMT_plx "\n",
 206             __func__, offset, value, pfl->counter);
 207     switch (width) {
 208     case 1:
 209         p[offset] = value;
 210         break;
 211     case 2:
 212         if (be) {
 213             p[offset] = value >> 8;
 214             p[offset + 1] = value;
 215         } else {
 216             p[offset] = value;
 217             p[offset + 1] = value >> 8;
 218         }
 219         break;
 220     case 4:
 221         if (be) {
 222             p[offset] = value >> 24;
 223             p[offset + 1] = value >> 16;
 224             p[offset + 2] = value >> 8;
 225             p[offset + 3] = value;
 226         } else {
 227             p[offset] = value;
 228             p[offset + 1] = value >> 8;
 229             p[offset + 2] = value >> 16;
 230             p[offset + 3] = value >> 24;
 231         }
 232         break;
 233     }
 234
 235 }
 236
 237 static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
 238                          uint32_t value, int width, int be)
 239 {
 240     uint8_t *p;
 241     uint8_t cmd;
 242
 243     cmd = value;
 244
 245     DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
 246             __func__, offset, value, width, pfl->wcycle);
 247
 248     if (!pfl->wcycle) {
 249         /* Set the device in I/O access mode */
 250         cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
 251     }
 252
 253     switch (pfl->wcycle) {
 254     case 0:
 255         /* read mode */
 256         switch (cmd) {
 257         case 0x00: /* ??? */
 258             goto reset_flash;
 259         case 0x10: /* Single Byte Program */
 260         case 0x40: /* Single Byte Program */
 261             DPRINTF("%s: Single Byte Program\n", __func__);
 262             break;
 263         case 0x20: /* Block erase */
 264             p = pfl->storage;
 265             offset &= ~(pfl->sector_len - 1);
 266
 267             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes "
 268                     TARGET_FMT_plx "\n",
 269                     __func__, offset, pfl->sector_len);
 270
 271             memset(p + offset, 0xff, pfl->sector_len);
 272             pflash_update(pfl, offset, pfl->sector_len);
 273             pfl->status |= 0x80; /* Ready! */
 274             break;
 275         case 0x50: /* Clear status bits */
 276             DPRINTF("%s: Clear status bits\n", __func__);
 277             pfl->status = 0x0;
 278             goto reset_flash;
 279         case 0x60: /* Block (un)lock */
 280             DPRINTF("%s: Block unlock\n", __func__);
 281             break;
 282         case 0x70: /* Status Register */
 283             DPRINTF("%s: Read status register\n", __func__);
 284             pfl->cmd = cmd;
 285             return;
 286         case 0x98: /* CFI query */
 287             DPRINTF("%s: CFI query\n", __func__);
 288             break;
 289         case 0xe8: /* Write to buffer */
 290             DPRINTF("%s: Write to buffer\n", __func__);
 291             pfl->status |= 0x80; /* Ready! */
 292             break;
 293         case 0xff: /* Read array mode */
 294             DPRINTF("%s: Read array mode\n", __func__);
 295             goto reset_flash;
 296         default:
 297             goto error_flash;
 298         }
 299         pfl->wcycle++;
 300         pfl->cmd = cmd;
 301         return;
 302     case 1:
 303         switch (pfl->cmd) {
 304         case 0x10: /* Single Byte Program */
 305         case 0x40: /* Single Byte Program */
 306             DPRINTF("%s: Single Byte Program\n", __func__);
 307             pflash_data_write(pfl, offset, value, width, be);
 308             pflash_update(pfl, offset, width);
 309             pfl->status |= 0x80; /* Ready! */
 310             pfl->wcycle = 0;
 311         break;
 312         case 0x20: /* Block erase */
 313         case 0x28:
 314             if (cmd == 0xd0) { /* confirm */
 315                 pfl->wcycle = 0;
 316                 pfl->status |= 0x80;
 317             } else if (cmd == 0xff) { /* read array mode */
 318                 goto reset_flash;
 319             } else
 320                 goto error_flash;
 321
 322             break;
 323         case 0xe8:
 324             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 325             pfl->counter = value;
 326             pfl->wcycle++;
 327             break;
 328         case 0x60:
 329             if (cmd == 0xd0) {
 330                 pfl->wcycle = 0;
 331                 pfl->status |= 0x80;
 332             } else if (cmd == 0x01) {
 333                 pfl->wcycle = 0;
 334                 pfl->status |= 0x80;
 335             } else if (cmd == 0xff) {
 336                 goto reset_flash;
 337             } else {
 338                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 339                 goto reset_flash;
 340             }
 341             break;
 342         case 0x98:
 343             if (cmd == 0xff) {
 344                 goto reset_flash;
 345             } else {
 346                 DPRINTF("%s: leaving query mode\n", __func__);
 347             }
 348             break;
 349         default:
 350             goto error_flash;
 351         }
 352         return;
 353     case 2:
 354         switch (pfl->cmd) {
 355         case 0xe8: /* Block write */
 356             pflash_data_write(pfl, offset, value, width, be);
 357
 358             pfl->status |= 0x80;
 359
 360             if (!pfl->counter) {
 361                 target_phys_addr_t mask = pfl->writeblock_size - 1;
 362                 mask = ~mask;
 363
 364                 DPRINTF("%s: block write finished\n", __func__);
 365                 pfl->wcycle++;
 366                 /* Flush the entire write buffer onto backing storage.  */
 367                 pflash_update(pfl, offset & mask, pfl->writeblock_size);
 368             }
 369
 370             pfl->counter--;
 371             break;
 372         default:
 373             goto error_flash;
 374         }
 375         return;
 376     case 3: /* Confirm mode */
 377         switch (pfl->cmd) {
 378         case 0xe8: /* Block write */
 379             if (cmd == 0xd0) {
 380                 pfl->wcycle = 0;
 381                 pfl->status |= 0x80;
 382             } else {
 383                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 384                 PFLASH_BUG("Write block confirm");
 385                 goto reset_flash;
 386             }
 387             break;
 388         default:
 389             goto error_flash;
 390         }
 391         return;
 392     default:
 393         /* Should never happen */
 394         DPRINTF("%s: invalid write state\n",  __func__);
 395         goto reset_flash;
 396     }
 397     return;
 398
 399  error_flash:
 400     printf("%s: Unimplemented flash cmd sequence "
 401            "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n",
 402            __func__, offset, pfl->wcycle, pfl->cmd, value);
 403
 404  reset_flash:
 405     cpu_register_physical_memory(pfl->base, pfl->total_len,
 406                     pfl->off | IO_MEM_ROMD | pfl->fl_mem);
 407
 408     pfl->bypass = 0;
 409     pfl->wcycle = 0;
 410     pfl->cmd = 0;
 411     return;
 412 }
 413
 414
 415 static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
 416 {
 417     return pflash_read(opaque, addr, 1, 1);
 418 }
 419
 420 static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
 421 {
 422     return pflash_read(opaque, addr, 1, 0);
 423 }
 424
 425 static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
 426 {
 427     pflash_t *pfl = opaque;
 428
 429     return pflash_read(pfl, addr, 2, 1);
 430 }
 431
 432 static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
 433 {
 434     pflash_t *pfl = opaque;
 435
 436     return pflash_read(pfl, addr, 2, 0);
 437 }
 438
 439 static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
 440 {
 441     pflash_t *pfl = opaque;
 442
 443     return pflash_read(pfl, addr, 4, 1);
 444 }
 445
 446 static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
 447 {
 448     pflash_t *pfl = opaque;
 449
 450     return pflash_read(pfl, addr, 4, 0);
 451 }
 452
 453 static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
 454                              uint32_t value)
 455 {
 456     pflash_write(opaque, addr, value, 1, 1);
 457 }
 458
 459 static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
 460                              uint32_t value)
 461 {
 462     pflash_write(opaque, addr, value, 1, 0);
 463 }
 464
 465 static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
 466                              uint32_t value)
 467 {
 468     pflash_t *pfl = opaque;
 469
 470     pflash_write(pfl, addr, value, 2, 1);
 471 }
 472
 473 static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
 474                              uint32_t value)
 475 {
 476     pflash_t *pfl = opaque;
 477
 478     pflash_write(pfl, addr, value, 2, 0);
 479 }
 480
 481 static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
 482                              uint32_t value)
 483 {
 484     pflash_t *pfl = opaque;
 485
 486     pflash_write(pfl, addr, value, 4, 1);
 487 }
 488
 489 static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
 490                              uint32_t value)
 491 {
 492     pflash_t *pfl = opaque;
 493
 494     pflash_write(pfl, addr, value, 4, 0);
 495 }
 496
 497 static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
 498     &pflash_writeb_be,
 499     &pflash_writew_be,
 500     &pflash_writel_be,
 501 };
 502
 503 static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
 504     &pflash_readb_be,
 505     &pflash_readw_be,
 506     &pflash_readl_be,
 507 };
 508
 509 static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
 510     &pflash_writeb_le,
 511     &pflash_writew_le,
 512     &pflash_writel_le,
 513 };
 514
 515 static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
 516     &pflash_readb_le,
 517     &pflash_readw_le,
 518     &pflash_readl_le,
 519 };
 520
 521 /* Count trailing zeroes of a 32 bits quantity */
 522 static int ctz32 (uint32_t n)
 523 {
 524     int ret;
 525
 526     ret = 0;
 527     if (!(n & 0xFFFF)) {
 528         ret += 16;
 529         n = n >> 16;
 530     }
 531     if (!(n & 0xFF)) {
 532         ret += 8;
 533         n = n >> 8;
 534     }
 535     if (!(n & 0xF)) {
 536         ret += 4;
 537         n = n >> 4;
 538     }
 539     if (!(n & 0x3)) {
 540         ret += 2;
 541         n = n >> 2;
 542     }
 543     if (!(n & 0x1)) {
 544         ret++;
 545 #if 0 /* This is not necessary as n is never 0 */
 546         n = n >> 1;
 547 #endif
 548     }
 549 #if 0 /* This is not necessary as n is never 0 */
 550     if (!n)
 551         ret++;
 552 #endif
 553
 554     return ret;
 555 }
 556
 557 pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
 558                                 BlockDriverState *bs, uint32_t sector_len,
 559                                 int nb_blocs, int width,
 560                                 uint16_t id0, uint16_t id1,
 561                                 uint16_t id2, uint16_t id3,
 562                                 int be)
 563 {
 564     pflash_t *pfl;
 565     target_phys_addr_t total_len;
 566     int ret;
 567
 568     total_len = sector_len * nb_blocs;
 569
 570     /* XXX: to be fixed */
 571 #if 0
 572     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 573         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 574         return NULL;
 575 #endif
 576
 577     pfl = qemu_mallocz(sizeof(pflash_t));
 578
 579     /* FIXME: Allocate ram ourselves.  */
 580     pfl->storage = qemu_get_ram_ptr(off);
 581     if (be) {
 582         pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
 583                                              pflash_write_ops_be, pfl);
 584     } else {
 585         pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
 586                                              pflash_write_ops_le, pfl);
 587     }
 588     pfl->off = off;
 589     cpu_register_physical_memory(base, total_len,
 590                     off | pfl->fl_mem | IO_MEM_ROMD);
 591
 592     pfl->bs = bs;
 593     if (pfl->bs) {
 594         /* read the initial flash content */
 595         ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 596         if (ret < 0) {
 597             cpu_unregister_io_memory(pfl->fl_mem);
 598             qemu_free(pfl);
 599             return NULL;
 600         }
 601     }
 602 #if 0 /* XXX: there should be a bit to set up read-only,
 603        *      the same way the hardware does (with WP pin).
 604        */
 605     pfl->ro = 1;
 606 #else
 607     pfl->ro = 0;
 608 #endif
 609     pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
 610     pfl->base = base;
 611     pfl->sector_len = sector_len;
 612     pfl->total_len = total_len;
 613     pfl->width = width;
 614     pfl->wcycle = 0;
 615     pfl->cmd = 0;
 616     pfl->status = 0;
 617     pfl->ident[0] = id0;
 618     pfl->ident[1] = id1;
 619     pfl->ident[2] = id2;
 620     pfl->ident[3] = id3;
 621     /* Hardcoded CFI table */
 622     pfl->cfi_len = 0x52;
 623     /* Standard "QRY" string */
 624     pfl->cfi_table[0x10] = 'Q';
 625     pfl->cfi_table[0x11] = 'R';
 626     pfl->cfi_table[0x12] = 'Y';
 627     /* Command set (Intel) */
 628     pfl->cfi_table[0x13] = 0x01;
 629     pfl->cfi_table[0x14] = 0x00;
 630     /* Primary extended table address (none) */
 631     pfl->cfi_table[0x15] = 0x31;
 632     pfl->cfi_table[0x16] = 0x00;
 633     /* Alternate command set (none) */
 634     pfl->cfi_table[0x17] = 0x00;
 635     pfl->cfi_table[0x18] = 0x00;
 636     /* Alternate extended table (none) */
 637     pfl->cfi_table[0x19] = 0x00;
 638     pfl->cfi_table[0x1A] = 0x00;
 639     /* Vcc min */
 640     pfl->cfi_table[0x1B] = 0x45;
 641     /* Vcc max */
 642     pfl->cfi_table[0x1C] = 0x55;
 643     /* Vpp min (no Vpp pin) */
 644     pfl->cfi_table[0x1D] = 0x00;
 645     /* Vpp max (no Vpp pin) */
 646     pfl->cfi_table[0x1E] = 0x00;
 647     /* Reserved */
 648     pfl->cfi_table[0x1F] = 0x07;
 649     /* Timeout for min size buffer write */
 650     pfl->cfi_table[0x20] = 0x07;
 651     /* Typical timeout for block erase */
 652     pfl->cfi_table[0x21] = 0x0a;
 653     /* Typical timeout for full chip erase (4096 ms) */
 654     pfl->cfi_table[0x22] = 0x00;
 655     /* Reserved */
 656     pfl->cfi_table[0x23] = 0x04;
 657     /* Max timeout for buffer write */
 658     pfl->cfi_table[0x24] = 0x04;
 659     /* Max timeout for block erase */
 660     pfl->cfi_table[0x25] = 0x04;
 661     /* Max timeout for chip erase */
 662     pfl->cfi_table[0x26] = 0x00;
 663     /* Device size */
 664     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 665     /* Flash device interface (8 & 16 bits) */
 666     pfl->cfi_table[0x28] = 0x02;
 667     pfl->cfi_table[0x29] = 0x00;
 668     /* Max number of bytes in multi-bytes write */
 669     if (width == 1) {
 670         pfl->cfi_table[0x2A] = 0x08;
 671     } else {
 672         pfl->cfi_table[0x2A] = 0x0B;
 673     }
 674     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 675
 676     pfl->cfi_table[0x2B] = 0x00;
 677     /* Number of erase block regions (uniform) */
 678     pfl->cfi_table[0x2C] = 0x01;
 679     /* Erase block region 1 */
 680     pfl->cfi_table[0x2D] = nb_blocs - 1;
 681     pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
 682     pfl->cfi_table[0x2F] = sector_len >> 8;
 683     pfl->cfi_table[0x30] = sector_len >> 16;
 684
 685     /* Extended */
 686     pfl->cfi_table[0x31] = 'P';
 687     pfl->cfi_table[0x32] = 'R';
 688     pfl->cfi_table[0x33] = 'I';
 689
 690     pfl->cfi_table[0x34] = '1';
 691     pfl->cfi_table[0x35] = '1';
 692
 693     pfl->cfi_table[0x36] = 0x00;
 694     pfl->cfi_table[0x37] = 0x00;
 695     pfl->cfi_table[0x38] = 0x00;
 696     pfl->cfi_table[0x39] = 0x00;
 697
 698     pfl->cfi_table[0x3a] = 0x00;
 699
 700     pfl->cfi_table[0x3b] = 0x00;
 701     pfl->cfi_table[0x3c] = 0x00;
 702
 703     return pfl;
 704 }