target-ppc: remove dead code
[qemu/aliguori-queue.git] / hw / mac_dbdma.c
blobe2697d3a742c7c64bc146e1bea2157dd6df98550
1 /*
2 * PowerMac descriptor-based DMA emulation
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2009 Laurent Vivier
8 * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
10 * Definitions for using the Apple Descriptor-Based DMA controller
11 * in Power Macintosh computers.
13 * Copyright (C) 1996 Paul Mackerras.
15 * some parts from mol 0.9.71
17 * Descriptor based DMA emulation
19 * Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
21 * Permission is hereby granted, free of charge, to any person obtaining a copy
22 * of this software and associated documentation files (the "Software"), to deal
23 * in the Software without restriction, including without limitation the rights
24 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
25 * copies of the Software, and to permit persons to whom the Software is
26 * furnished to do so, subject to the following conditions:
28 * The above copyright notice and this permission notice shall be included in
29 * all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
32 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
34 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
35 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
36 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
37 * THE SOFTWARE.
39 #include "hw.h"
40 #include "isa.h"
41 #include "mac_dbdma.h"
43 /* debug DBDMA */
44 //#define DEBUG_DBDMA
46 #ifdef DEBUG_DBDMA
47 #define DBDMA_DPRINTF(fmt, ...) \
48 do { printf("DBDMA: " fmt , ## __VA_ARGS__); } while (0)
49 #else
50 #define DBDMA_DPRINTF(fmt, ...)
51 #endif
57 * DBDMA control/status registers. All little-endian.
60 #define DBDMA_CONTROL 0x00
61 #define DBDMA_STATUS 0x01
62 #define DBDMA_CMDPTR_HI 0x02
63 #define DBDMA_CMDPTR_LO 0x03
64 #define DBDMA_INTR_SEL 0x04
65 #define DBDMA_BRANCH_SEL 0x05
66 #define DBDMA_WAIT_SEL 0x06
67 #define DBDMA_XFER_MODE 0x07
68 #define DBDMA_DATA2PTR_HI 0x08
69 #define DBDMA_DATA2PTR_LO 0x09
70 #define DBDMA_RES1 0x0A
71 #define DBDMA_ADDRESS_HI 0x0B
72 #define DBDMA_BRANCH_ADDR_HI 0x0C
73 #define DBDMA_RES2 0x0D
74 #define DBDMA_RES3 0x0E
75 #define DBDMA_RES4 0x0F
77 #define DBDMA_REGS 16
78 #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
80 #define DBDMA_CHANNEL_SHIFT 7
81 #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
83 #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
85 /* Bits in control and status registers */
87 #define RUN 0x8000
88 #define PAUSE 0x4000
89 #define FLUSH 0x2000
90 #define WAKE 0x1000
91 #define DEAD 0x0800
92 #define ACTIVE 0x0400
93 #define BT 0x0100
94 #define DEVSTAT 0x00ff
97 * DBDMA command structure. These fields are all little-endian!
100 typedef struct dbdma_cmd {
101 uint16_t req_count; /* requested byte transfer count */
102 uint16_t command; /* command word (has bit-fields) */
103 uint32_t phy_addr; /* physical data address */
104 uint32_t cmd_dep; /* command-dependent field */
105 uint16_t res_count; /* residual count after completion */
106 uint16_t xfer_status; /* transfer status */
107 } dbdma_cmd;
109 /* DBDMA command values in command field */
111 #define COMMAND_MASK 0xf000
112 #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
113 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
114 #define INPUT_MORE 0x2000 /* transfer stream data to memory */
115 #define INPUT_LAST 0x3000 /* ditto, expect end marker */
116 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
117 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
118 #define DBDMA_NOP 0x6000 /* do nothing */
119 #define DBDMA_STOP 0x7000 /* suspend processing */
121 /* Key values in command field */
123 #define KEY_MASK 0x0700
124 #define KEY_STREAM0 0x0000 /* usual data stream */
125 #define KEY_STREAM1 0x0100 /* control/status stream */
126 #define KEY_STREAM2 0x0200 /* device-dependent stream */
127 #define KEY_STREAM3 0x0300 /* device-dependent stream */
128 #define KEY_STREAM4 0x0400 /* reserved */
129 #define KEY_REGS 0x0500 /* device register space */
130 #define KEY_SYSTEM 0x0600 /* system memory-mapped space */
131 #define KEY_DEVICE 0x0700 /* device memory-mapped space */
133 /* Interrupt control values in command field */
135 #define INTR_MASK 0x0030
136 #define INTR_NEVER 0x0000 /* don't interrupt */
137 #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
138 #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
139 #define INTR_ALWAYS 0x0030 /* always interrupt */
141 /* Branch control values in command field */
143 #define BR_MASK 0x000c
144 #define BR_NEVER 0x0000 /* don't branch */
145 #define BR_IFSET 0x0004 /* branch if condition bit is 1 */
146 #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
147 #define BR_ALWAYS 0x000c /* always branch */
149 /* Wait control values in command field */
151 #define WAIT_MASK 0x0003
152 #define WAIT_NEVER 0x0000 /* don't wait */
153 #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
154 #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
155 #define WAIT_ALWAYS 0x0003 /* always wait */
157 typedef struct DBDMA_channel {
158 int channel;
159 uint32_t regs[DBDMA_REGS];
160 qemu_irq irq;
161 DBDMA_io io;
162 DBDMA_rw rw;
163 DBDMA_flush flush;
164 dbdma_cmd current;
165 int processing;
166 } DBDMA_channel;
168 #ifdef DEBUG_DBDMA
169 static void dump_dbdma_cmd(dbdma_cmd *cmd)
171 printf("dbdma_cmd %p\n", cmd);
172 printf(" req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
173 printf(" command 0x%04x\n", le16_to_cpu(cmd->command));
174 printf(" phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
175 printf(" cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
176 printf(" res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
177 printf(" xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
179 #else
180 static void dump_dbdma_cmd(dbdma_cmd *cmd)
183 #endif
184 static void dbdma_cmdptr_load(DBDMA_channel *ch)
186 DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
187 ch->regs[DBDMA_CMDPTR_LO]);
188 cpu_physical_memory_read(ch->regs[DBDMA_CMDPTR_LO],
189 (uint8_t*)&ch->current, sizeof(dbdma_cmd));
192 static void dbdma_cmdptr_save(DBDMA_channel *ch)
194 DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
195 ch->regs[DBDMA_CMDPTR_LO]);
196 DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
197 le16_to_cpu(ch->current.xfer_status),
198 le16_to_cpu(ch->current.res_count));
199 cpu_physical_memory_write(ch->regs[DBDMA_CMDPTR_LO],
200 (uint8_t*)&ch->current, sizeof(dbdma_cmd));
203 static void kill_channel(DBDMA_channel *ch)
205 DBDMA_DPRINTF("kill_channel\n");
207 ch->regs[DBDMA_STATUS] |= DEAD;
208 ch->regs[DBDMA_STATUS] &= ~ACTIVE;
210 qemu_irq_raise(ch->irq);
213 static void conditional_interrupt(DBDMA_channel *ch)
215 dbdma_cmd *current = &ch->current;
216 uint16_t intr;
217 uint16_t sel_mask, sel_value;
218 uint32_t status;
219 int cond;
221 DBDMA_DPRINTF("conditional_interrupt\n");
223 intr = le16_to_cpu(current->command) & INTR_MASK;
225 switch(intr) {
226 case INTR_NEVER: /* don't interrupt */
227 return;
228 case INTR_ALWAYS: /* always interrupt */
229 qemu_irq_raise(ch->irq);
230 return;
233 status = ch->regs[DBDMA_STATUS] & DEVSTAT;
235 sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f;
236 sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f;
238 cond = (status & sel_mask) == (sel_value & sel_mask);
240 switch(intr) {
241 case INTR_IFSET: /* intr if condition bit is 1 */
242 if (cond)
243 qemu_irq_raise(ch->irq);
244 return;
245 case INTR_IFCLR: /* intr if condition bit is 0 */
246 if (!cond)
247 qemu_irq_raise(ch->irq);
248 return;
252 static int conditional_wait(DBDMA_channel *ch)
254 dbdma_cmd *current = &ch->current;
255 uint16_t wait;
256 uint16_t sel_mask, sel_value;
257 uint32_t status;
258 int cond;
260 DBDMA_DPRINTF("conditional_wait\n");
262 wait = le16_to_cpu(current->command) & WAIT_MASK;
264 switch(wait) {
265 case WAIT_NEVER: /* don't wait */
266 return 0;
267 case WAIT_ALWAYS: /* always wait */
268 return 1;
271 status = ch->regs[DBDMA_STATUS] & DEVSTAT;
273 sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f;
274 sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f;
276 cond = (status & sel_mask) == (sel_value & sel_mask);
278 switch(wait) {
279 case WAIT_IFSET: /* wait if condition bit is 1 */
280 if (cond)
281 return 1;
282 return 0;
283 case WAIT_IFCLR: /* wait if condition bit is 0 */
284 if (!cond)
285 return 1;
286 return 0;
288 return 0;
291 static void next(DBDMA_channel *ch)
293 uint32_t cp;
295 ch->regs[DBDMA_STATUS] &= ~BT;
297 cp = ch->regs[DBDMA_CMDPTR_LO];
298 ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd);
299 dbdma_cmdptr_load(ch);
302 static void branch(DBDMA_channel *ch)
304 dbdma_cmd *current = &ch->current;
306 ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
307 ch->regs[DBDMA_STATUS] |= BT;
308 dbdma_cmdptr_load(ch);
311 static void conditional_branch(DBDMA_channel *ch)
313 dbdma_cmd *current = &ch->current;
314 uint16_t br;
315 uint16_t sel_mask, sel_value;
316 uint32_t status;
317 int cond;
319 DBDMA_DPRINTF("conditional_branch\n");
321 /* check if we must branch */
323 br = le16_to_cpu(current->command) & BR_MASK;
325 switch(br) {
326 case BR_NEVER: /* don't branch */
327 next(ch);
328 return;
329 case BR_ALWAYS: /* always branch */
330 branch(ch);
331 return;
334 status = ch->regs[DBDMA_STATUS] & DEVSTAT;
336 sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f;
337 sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f;
339 cond = (status & sel_mask) == (sel_value & sel_mask);
341 switch(br) {
342 case BR_IFSET: /* branch if condition bit is 1 */
343 if (cond)
344 branch(ch);
345 else
346 next(ch);
347 return;
348 case BR_IFCLR: /* branch if condition bit is 0 */
349 if (!cond)
350 branch(ch);
351 else
352 next(ch);
353 return;
357 static QEMUBH *dbdma_bh;
358 static void channel_run(DBDMA_channel *ch);
360 static void dbdma_end(DBDMA_io *io)
362 DBDMA_channel *ch = io->channel;
363 dbdma_cmd *current = &ch->current;
365 if (conditional_wait(ch))
366 goto wait;
368 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
369 current->res_count = cpu_to_le16(io->len);
370 dbdma_cmdptr_save(ch);
371 if (io->is_last)
372 ch->regs[DBDMA_STATUS] &= ~FLUSH;
374 conditional_interrupt(ch);
375 conditional_branch(ch);
377 wait:
378 ch->processing = 0;
379 if ((ch->regs[DBDMA_STATUS] & RUN) &&
380 (ch->regs[DBDMA_STATUS] & ACTIVE))
381 channel_run(ch);
384 static void start_output(DBDMA_channel *ch, int key, uint32_t addr,
385 uint16_t req_count, int is_last)
387 DBDMA_DPRINTF("start_output\n");
389 /* KEY_REGS, KEY_DEVICE and KEY_STREAM
390 * are not implemented in the mac-io chip
393 DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
394 if (!addr || key > KEY_STREAM3) {
395 kill_channel(ch);
396 return;
399 ch->io.addr = addr;
400 ch->io.len = req_count;
401 ch->io.is_last = is_last;
402 ch->io.dma_end = dbdma_end;
403 ch->io.is_dma_out = 1;
404 ch->processing = 1;
405 if (ch->rw) {
406 ch->rw(&ch->io);
410 static void start_input(DBDMA_channel *ch, int key, uint32_t addr,
411 uint16_t req_count, int is_last)
413 DBDMA_DPRINTF("start_input\n");
415 /* KEY_REGS, KEY_DEVICE and KEY_STREAM
416 * are not implemented in the mac-io chip
419 if (!addr || key > KEY_STREAM3) {
420 kill_channel(ch);
421 return;
424 ch->io.addr = addr;
425 ch->io.len = req_count;
426 ch->io.is_last = is_last;
427 ch->io.dma_end = dbdma_end;
428 ch->io.is_dma_out = 0;
429 ch->processing = 1;
430 if (ch->rw) {
431 ch->rw(&ch->io);
435 static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
436 uint16_t len)
438 dbdma_cmd *current = &ch->current;
439 uint32_t val;
441 DBDMA_DPRINTF("load_word\n");
443 /* only implements KEY_SYSTEM */
445 if (key != KEY_SYSTEM) {
446 printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
447 kill_channel(ch);
448 return;
451 cpu_physical_memory_read(addr, (uint8_t*)&val, len);
453 if (len == 2)
454 val = (val << 16) | (current->cmd_dep & 0x0000ffff);
455 else if (len == 1)
456 val = (val << 24) | (current->cmd_dep & 0x00ffffff);
458 current->cmd_dep = val;
460 if (conditional_wait(ch))
461 goto wait;
463 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
464 dbdma_cmdptr_save(ch);
465 ch->regs[DBDMA_STATUS] &= ~FLUSH;
467 conditional_interrupt(ch);
468 next(ch);
470 wait:
471 qemu_bh_schedule(dbdma_bh);
474 static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
475 uint16_t len)
477 dbdma_cmd *current = &ch->current;
478 uint32_t val;
480 DBDMA_DPRINTF("store_word\n");
482 /* only implements KEY_SYSTEM */
484 if (key != KEY_SYSTEM) {
485 printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
486 kill_channel(ch);
487 return;
490 val = current->cmd_dep;
491 if (len == 2)
492 val >>= 16;
493 else if (len == 1)
494 val >>= 24;
496 cpu_physical_memory_write(addr, (uint8_t*)&val, len);
498 if (conditional_wait(ch))
499 goto wait;
501 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
502 dbdma_cmdptr_save(ch);
503 ch->regs[DBDMA_STATUS] &= ~FLUSH;
505 conditional_interrupt(ch);
506 next(ch);
508 wait:
509 qemu_bh_schedule(dbdma_bh);
512 static void nop(DBDMA_channel *ch)
514 dbdma_cmd *current = &ch->current;
516 if (conditional_wait(ch))
517 goto wait;
519 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
520 dbdma_cmdptr_save(ch);
522 conditional_interrupt(ch);
523 conditional_branch(ch);
525 wait:
526 qemu_bh_schedule(dbdma_bh);
529 static void stop(DBDMA_channel *ch)
531 ch->regs[DBDMA_STATUS] &= ~(ACTIVE|DEAD|FLUSH);
533 /* the stop command does not increment command pointer */
536 static void channel_run(DBDMA_channel *ch)
538 dbdma_cmd *current = &ch->current;
539 uint16_t cmd, key;
540 uint16_t req_count;
541 uint32_t phy_addr;
543 DBDMA_DPRINTF("channel_run\n");
544 dump_dbdma_cmd(current);
546 /* clear WAKE flag at command fetch */
548 ch->regs[DBDMA_STATUS] &= ~WAKE;
550 cmd = le16_to_cpu(current->command) & COMMAND_MASK;
552 switch (cmd) {
553 case DBDMA_NOP:
554 nop(ch);
555 return;
557 case DBDMA_STOP:
558 stop(ch);
559 return;
562 key = le16_to_cpu(current->command) & 0x0700;
563 req_count = le16_to_cpu(current->req_count);
564 phy_addr = le32_to_cpu(current->phy_addr);
566 if (key == KEY_STREAM4) {
567 printf("command %x, invalid key 4\n", cmd);
568 kill_channel(ch);
569 return;
572 switch (cmd) {
573 case OUTPUT_MORE:
574 start_output(ch, key, phy_addr, req_count, 0);
575 return;
577 case OUTPUT_LAST:
578 start_output(ch, key, phy_addr, req_count, 1);
579 return;
581 case INPUT_MORE:
582 start_input(ch, key, phy_addr, req_count, 0);
583 return;
585 case INPUT_LAST:
586 start_input(ch, key, phy_addr, req_count, 1);
587 return;
590 if (key < KEY_REGS) {
591 printf("command %x, invalid key %x\n", cmd, key);
592 key = KEY_SYSTEM;
595 /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
596 * and BRANCH is invalid
599 req_count = req_count & 0x0007;
600 if (req_count & 0x4) {
601 req_count = 4;
602 phy_addr &= ~3;
603 } else if (req_count & 0x2) {
604 req_count = 2;
605 phy_addr &= ~1;
606 } else
607 req_count = 1;
609 switch (cmd) {
610 case LOAD_WORD:
611 load_word(ch, key, phy_addr, req_count);
612 return;
614 case STORE_WORD:
615 store_word(ch, key, phy_addr, req_count);
616 return;
620 static void DBDMA_run (DBDMA_channel *ch)
622 int channel;
624 for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
625 uint32_t status = ch->regs[DBDMA_STATUS];
626 if (!ch->processing && (status & RUN) && (status & ACTIVE))
627 channel_run(ch);
631 static void DBDMA_run_bh(void *opaque)
633 DBDMA_channel *ch = opaque;
635 DBDMA_DPRINTF("DBDMA_run_bh\n");
637 DBDMA_run(ch);
640 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
641 DBDMA_rw rw, DBDMA_flush flush,
642 void *opaque)
644 DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
646 DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
648 ch->irq = irq;
649 ch->channel = nchan;
650 ch->rw = rw;
651 ch->flush = flush;
652 ch->io.opaque = opaque;
653 ch->io.channel = ch;
656 void DBDMA_schedule(void)
658 qemu_notify_event();
661 static void
662 dbdma_control_write(DBDMA_channel *ch)
664 uint16_t mask, value;
665 uint32_t status;
667 mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff;
668 value = ch->regs[DBDMA_CONTROL] & 0xffff;
670 value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
672 status = ch->regs[DBDMA_STATUS];
674 status = (value & mask) | (status & ~mask);
676 if (status & WAKE)
677 status |= ACTIVE;
678 if (status & RUN) {
679 status |= ACTIVE;
680 status &= ~DEAD;
682 if (status & PAUSE)
683 status &= ~ACTIVE;
684 if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
685 /* RUN is cleared */
686 status &= ~(ACTIVE|DEAD);
689 DBDMA_DPRINTF(" status 0x%08x\n", status);
691 ch->regs[DBDMA_STATUS] = status;
693 if (status & ACTIVE)
694 qemu_bh_schedule(dbdma_bh);
695 if ((status & FLUSH) && ch->flush)
696 ch->flush(&ch->io);
699 static void dbdma_writel (void *opaque,
700 target_phys_addr_t addr, uint32_t value)
702 int channel = addr >> DBDMA_CHANNEL_SHIFT;
703 DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
704 int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
706 DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
707 DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
708 (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
710 value = bswap32(value);
712 /* cmdptr cannot be modified if channel is RUN or ACTIVE */
714 if (reg == DBDMA_CMDPTR_LO &&
715 (ch->regs[DBDMA_STATUS] & (RUN | ACTIVE)))
716 return;
718 ch->regs[reg] = value;
720 switch(reg) {
721 case DBDMA_CONTROL:
722 dbdma_control_write(ch);
723 break;
724 case DBDMA_CMDPTR_LO:
725 /* 16-byte aligned */
726 ch->regs[DBDMA_CMDPTR_LO] &= ~0xf;
727 dbdma_cmdptr_load(ch);
728 break;
729 case DBDMA_STATUS:
730 case DBDMA_INTR_SEL:
731 case DBDMA_BRANCH_SEL:
732 case DBDMA_WAIT_SEL:
733 /* nothing to do */
734 break;
735 case DBDMA_XFER_MODE:
736 case DBDMA_CMDPTR_HI:
737 case DBDMA_DATA2PTR_HI:
738 case DBDMA_DATA2PTR_LO:
739 case DBDMA_ADDRESS_HI:
740 case DBDMA_BRANCH_ADDR_HI:
741 case DBDMA_RES1:
742 case DBDMA_RES2:
743 case DBDMA_RES3:
744 case DBDMA_RES4:
745 /* unused */
746 break;
750 static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
752 uint32_t value;
753 int channel = addr >> DBDMA_CHANNEL_SHIFT;
754 DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
755 int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
757 value = ch->regs[reg];
759 DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
760 DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
761 (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
763 switch(reg) {
764 case DBDMA_CONTROL:
765 value = 0;
766 break;
767 case DBDMA_STATUS:
768 case DBDMA_CMDPTR_LO:
769 case DBDMA_INTR_SEL:
770 case DBDMA_BRANCH_SEL:
771 case DBDMA_WAIT_SEL:
772 /* nothing to do */
773 break;
774 case DBDMA_XFER_MODE:
775 case DBDMA_CMDPTR_HI:
776 case DBDMA_DATA2PTR_HI:
777 case DBDMA_DATA2PTR_LO:
778 case DBDMA_ADDRESS_HI:
779 case DBDMA_BRANCH_ADDR_HI:
780 /* unused */
781 value = 0;
782 break;
783 case DBDMA_RES1:
784 case DBDMA_RES2:
785 case DBDMA_RES3:
786 case DBDMA_RES4:
787 /* reserved */
788 break;
791 value = bswap32(value);
792 return value;
795 static CPUWriteMemoryFunc * const dbdma_write[] = {
796 NULL,
797 NULL,
798 dbdma_writel,
801 static CPUReadMemoryFunc * const dbdma_read[] = {
802 NULL,
803 NULL,
804 dbdma_readl,
807 static void dbdma_save(QEMUFile *f, void *opaque)
809 DBDMA_channel *s = opaque;
810 unsigned int i, j;
812 for (i = 0; i < DBDMA_CHANNELS; i++)
813 for (j = 0; j < DBDMA_REGS; j++)
814 qemu_put_be32s(f, &s[i].regs[j]);
817 static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
819 DBDMA_channel *s = opaque;
820 unsigned int i, j;
822 if (version_id != 2)
823 return -EINVAL;
825 for (i = 0; i < DBDMA_CHANNELS; i++)
826 for (j = 0; j < DBDMA_REGS; j++)
827 qemu_get_be32s(f, &s[i].regs[j]);
829 return 0;
832 static void dbdma_reset(void *opaque)
834 DBDMA_channel *s = opaque;
835 int i;
837 for (i = 0; i < DBDMA_CHANNELS; i++)
838 memset(s[i].regs, 0, DBDMA_SIZE);
841 void* DBDMA_init (int *dbdma_mem_index)
843 DBDMA_channel *s;
845 s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
847 *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
848 register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
849 qemu_register_reset(dbdma_reset, s);
851 dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
853 return s;