hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 //#define DEBUG_IRQ_LATENCY
  34 //#define DEBUG_IRQ_COUNT
  35
  36 typedef struct PicState {
  37     uint8_t last_irr; /* edge detection */
  38     uint8_t irr; /* interrupt request register */
  39     uint8_t imr; /* interrupt mask register */
  40     uint8_t isr; /* interrupt service register */
  41     uint8_t priority_add; /* highest irq priority */
  42     uint8_t irq_base;
  43     uint8_t read_reg_select;
  44     uint8_t poll;
  45     uint8_t special_mask;
  46     uint8_t init_state;
  47     uint8_t auto_eoi;
  48     uint8_t rotate_on_auto_eoi;
  49     uint8_t special_fully_nested_mode;
  50     uint8_t init4; /* true if 4 byte init */
  51     uint8_t single_mode; /* true if slave pic is not initialized */
  52     uint8_t elcr; /* PIIX edge/trigger selection*/
  53     uint8_t elcr_mask;
  54     PicState2 *pics_state;
  55 } PicState;
  56
  57 struct PicState2 {
  58     /* 0 is master pic, 1 is slave pic */
  59     /* XXX: better separation between the two pics */
  60     PicState pics[2];
  61     qemu_irq parent_irq;
  62     void *irq_request_opaque;
  63 };
  64
  65 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  66 static int irq_level[16];
  67 #endif
  68 #ifdef DEBUG_IRQ_COUNT
  69 static uint64_t irq_count[16];
  70 #endif
  71 PicState2 *isa_pic;
  72
  73 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  74 static inline void pic_set_irq1(PicState *s, int irq, int level)
  75 {
  76     int mask;
  77     mask = 1 << irq;
  78     if (s->elcr & mask) {
  79         /* level triggered */
  80         if (level) {
  81             s->irr |= mask;
  82             s->last_irr |= mask;
  83         } else {
  84             s->irr &= ~mask;
  85             s->last_irr &= ~mask;
  86         }
  87     } else {
  88         /* edge triggered */
  89         if (level) {
  90             if ((s->last_irr & mask) == 0)
  91                 s->irr |= mask;
  92             s->last_irr |= mask;
  93         } else {
  94             s->last_irr &= ~mask;
  95         }
  96     }
  97 }
  98
  99 /* return the highest priority found in mask (highest = smallest
 100    number). Return 8 if no irq */
 101 static inline int get_priority(PicState *s, int mask)
 102 {
 103     int priority;
 104     if (mask == 0)
 105         return 8;
 106     priority = 0;
 107     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 108         priority++;
 109     return priority;
 110 }
 111
 112 /* return the pic wanted interrupt. return -1 if none */
 113 static int pic_get_irq(PicState *s)
 114 {
 115     int mask, cur_priority, priority;
 116
 117     mask = s->irr & ~s->imr;
 118     priority = get_priority(s, mask);
 119     if (priority == 8)
 120         return -1;
 121     /* compute current priority. If special fully nested mode on the
 122        master, the IRQ coming from the slave is not taken into account
 123        for the priority computation. */
 124     mask = s->isr;
 125     if (s->special_mask)
 126         mask &= ~s->imr;
 127     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 128         mask &= ~(1 << 2);
 129     cur_priority = get_priority(s, mask);
 130     if (priority < cur_priority) {
 131         /* higher priority found: an irq should be generated */
 132         return (priority + s->priority_add) & 7;
 133     } else {
 134         return -1;
 135     }
 136 }
 137
 138 /* raise irq to CPU if necessary. must be called every time the active
 139    irq may change */
 140 /* XXX: should not export it, but it is needed for an APIC kludge */
 141 void pic_update_irq(PicState2 *s)
 142 {
 143     int irq2, irq;
 144
 145     /* first look at slave pic */
 146     irq2 = pic_get_irq(&s->pics[1]);
 147     if (irq2 >= 0) {
 148         /* if irq request by slave pic, signal master PIC */
 149         pic_set_irq1(&s->pics[0], 2, 1);
 150         pic_set_irq1(&s->pics[0], 2, 0);
 151     }
 152     /* look at requested irq */
 153     irq = pic_get_irq(&s->pics[0]);
 154     if (irq >= 0) {
 155 #if defined(DEBUG_PIC)
 156         {
 157             int i;
 158             for(i = 0; i < 2; i++) {
 159                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 160                        i, s->pics[i].imr, s->pics[i].irr,
 161                        s->pics[i].priority_add);
 162
 163             }
 164         }
 165         printf("pic: cpu_interrupt\n");
 166 #endif
 167         qemu_irq_raise(s->parent_irq);
 168     }
 169
 170 /* all targets should do this rather than acking the IRQ in the cpu */
 171 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 172     else {
 173         qemu_irq_lower(s->parent_irq);
 174     }
 175 #endif
 176 }
 177
 178 #ifdef DEBUG_IRQ_LATENCY
 179 int64_t irq_time[16];
 180 #endif
 181
 182 static void i8259_set_irq(void *opaque, int irq, int level)
 183 {
 184     PicState2 *s = opaque;
 185
 186 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 187     if (level != irq_level[irq]) {
 188 #if defined(DEBUG_PIC)
 189         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 190 #endif
 191         irq_level[irq] = level;
 192 #ifdef DEBUG_IRQ_COUNT
 193         if (level == 1)
 194             irq_count[irq]++;
 195 #endif
 196     }
 197 #endif
 198 #ifdef DEBUG_IRQ_LATENCY
 199     if (level) {
 200         irq_time[irq] = qemu_get_clock(vm_clock);
 201     }
 202 #endif
 203     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 204     pic_update_irq(s);
 205 }
 206
 207 /* acknowledge interrupt 'irq' */
 208 static inline void pic_intack(PicState *s, int irq)
 209 {
 210     if (s->auto_eoi) {
 211         if (s->rotate_on_auto_eoi)
 212             s->priority_add = (irq + 1) & 7;
 213     } else {
 214         s->isr |= (1 << irq);
 215     }
 216     /* We don't clear a level sensitive interrupt here */
 217     if (!(s->elcr & (1 << irq)))
 218         s->irr &= ~(1 << irq);
 219 }
 220
 221 int pic_read_irq(PicState2 *s)
 222 {
 223     int irq, irq2, intno;
 224
 225     irq = pic_get_irq(&s->pics[0]);
 226     if (irq >= 0) {
 227         pic_intack(&s->pics[0], irq);
 228         if (irq == 2) {
 229             irq2 = pic_get_irq(&s->pics[1]);
 230             if (irq2 >= 0) {
 231                 pic_intack(&s->pics[1], irq2);
 232             } else {
 233                 /* spurious IRQ on slave controller */
 234                 irq2 = 7;
 235             }
 236             intno = s->pics[1].irq_base + irq2;
 237 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 238             irq = irq2 + 8;
 239 #endif
 240         } else {
 241             intno = s->pics[0].irq_base + irq;
 242         }
 243     } else {
 244         /* spurious IRQ on host controller */
 245         irq = 7;
 246         intno = s->pics[0].irq_base + irq;
 247     }
 248     pic_update_irq(s);
 249
 250 #ifdef DEBUG_IRQ_LATENCY
 251     printf("IRQ%d latency=%0.3fus\n",
 252            irq,
 253            (double)(qemu_get_clock(vm_clock) -
 254                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 255 #endif
 256 #if defined(DEBUG_PIC)
 257     printf("pic_interrupt: irq=%d\n", irq);
 258 #endif
 259     return intno;
 260 }
 261
 262 static void pic_reset(void *opaque)
 263 {
 264     PicState *s = opaque;
 265
 266     s->last_irr = 0;
 267     s->irr = 0;
 268     s->imr = 0;
 269     s->isr = 0;
 270     s->priority_add = 0;
 271     s->irq_base = 0;
 272     s->read_reg_select = 0;
 273     s->poll = 0;
 274     s->special_mask = 0;
 275     s->init_state = 0;
 276     s->auto_eoi = 0;
 277     s->rotate_on_auto_eoi = 0;
 278     s->special_fully_nested_mode = 0;
 279     s->init4 = 0;
 280     s->single_mode = 0;
 281     /* Note: ELCR is not reset */
 282 }
 283
 284 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 285 {
 286     PicState *s = opaque;
 287     int priority, cmd, irq;
 288
 289 #ifdef DEBUG_PIC
 290     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 291 #endif
 292     addr &= 1;
 293     if (addr == 0) {
 294         if (val & 0x10) {
 295             /* init */
 296             pic_reset(s);
 297             /* deassert a pending interrupt */
 298             qemu_irq_lower(s->pics_state->parent_irq);
 299             s->init_state = 1;
 300             s->init4 = val & 1;
 301             s->single_mode = val & 2;
 302             if (val & 0x08)
 303                 hw_error("level sensitive irq not supported");
 304         } else if (val & 0x08) {
 305             if (val & 0x04)
 306                 s->poll = 1;
 307             if (val & 0x02)
 308                 s->read_reg_select = val & 1;
 309             if (val & 0x40)
 310                 s->special_mask = (val >> 5) & 1;
 311         } else {
 312             cmd = val >> 5;
 313             switch(cmd) {
 314             case 0:
 315             case 4:
 316                 s->rotate_on_auto_eoi = cmd >> 2;
 317                 break;
 318             case 1: /* end of interrupt */
 319             case 5:
 320                 priority = get_priority(s, s->isr);
 321                 if (priority != 8) {
 322                     irq = (priority + s->priority_add) & 7;
 323                     s->isr &= ~(1 << irq);
 324                     if (cmd == 5)
 325                         s->priority_add = (irq + 1) & 7;
 326                     pic_update_irq(s->pics_state);
 327                 }
 328                 break;
 329             case 3:
 330                 irq = val & 7;
 331                 s->isr &= ~(1 << irq);
 332                 pic_update_irq(s->pics_state);
 333                 break;
 334             case 6:
 335                 s->priority_add = (val + 1) & 7;
 336                 pic_update_irq(s->pics_state);
 337                 break;
 338             case 7:
 339                 irq = val & 7;
 340                 s->isr &= ~(1 << irq);
 341                 s->priority_add = (irq + 1) & 7;
 342                 pic_update_irq(s->pics_state);
 343                 break;
 344             default:
 345                 /* no operation */
 346                 break;
 347             }
 348         }
 349     } else {
 350         switch(s->init_state) {
 351         case 0:
 352             /* normal mode */
 353             s->imr = val;
 354             pic_update_irq(s->pics_state);
 355             break;
 356         case 1:
 357             s->irq_base = val & 0xf8;
 358             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 359             break;
 360         case 2:
 361             if (s->init4) {
 362                 s->init_state = 3;
 363             } else {
 364                 s->init_state = 0;
 365             }
 366             break;
 367         case 3:
 368             s->special_fully_nested_mode = (val >> 4) & 1;
 369             s->auto_eoi = (val >> 1) & 1;
 370             s->init_state = 0;
 371             break;
 372         }
 373     }
 374 }
 375
 376 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 377 {
 378     int ret;
 379
 380     ret = pic_get_irq(s);
 381     if (ret >= 0) {
 382         if (addr1 >> 7) {
 383             s->pics_state->pics[0].isr &= ~(1 << 2);
 384             s->pics_state->pics[0].irr &= ~(1 << 2);
 385         }
 386         s->irr &= ~(1 << ret);
 387         s->isr &= ~(1 << ret);
 388         if (addr1 >> 7 || ret != 2)
 389             pic_update_irq(s->pics_state);
 390     } else {
 391         ret = 0x07;
 392         pic_update_irq(s->pics_state);
 393     }
 394
 395     return ret;
 396 }
 397
 398 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 399 {
 400     PicState *s = opaque;
 401     unsigned int addr;
 402     int ret;
 403
 404     addr = addr1;
 405     addr &= 1;
 406     if (s->poll) {
 407         ret = pic_poll_read(s, addr1);
 408         s->poll = 0;
 409     } else {
 410         if (addr == 0) {
 411             if (s->read_reg_select)
 412                 ret = s->isr;
 413             else
 414                 ret = s->irr;
 415         } else {
 416             ret = s->imr;
 417         }
 418     }
 419 #ifdef DEBUG_PIC
 420     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 421 #endif
 422     return ret;
 423 }
 424
 425 /* memory mapped interrupt status */
 426 /* XXX: may be the same than pic_read_irq() */
 427 uint32_t pic_intack_read(PicState2 *s)
 428 {
 429     int ret;
 430
 431     ret = pic_poll_read(&s->pics[0], 0x00);
 432     if (ret == 2)
 433         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 434     /* Prepare for ISR read */
 435     s->pics[0].read_reg_select = 1;
 436
 437     return ret;
 438 }
 439
 440 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 441 {
 442     PicState *s = opaque;
 443     s->elcr = val & s->elcr_mask;
 444 }
 445
 446 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 447 {
 448     PicState *s = opaque;
 449     return s->elcr;
 450 }
 451
 452 static const VMStateDescription vmstate_pic = {
 453     .name = "i8259",
 454     .version_id = 1,
 455     .minimum_version_id = 1,
 456     .minimum_version_id_old = 1,
 457     .fields      = (VMStateField []) {
 458         VMSTATE_UINT8(last_irr, PicState),
 459         VMSTATE_UINT8(irr, PicState),
 460         VMSTATE_UINT8(imr, PicState),
 461         VMSTATE_UINT8(isr, PicState),
 462         VMSTATE_UINT8(priority_add, PicState),
 463         VMSTATE_UINT8(irq_base, PicState),
 464         VMSTATE_UINT8(read_reg_select, PicState),
 465         VMSTATE_UINT8(poll, PicState),
 466         VMSTATE_UINT8(special_mask, PicState),
 467         VMSTATE_UINT8(init_state, PicState),
 468         VMSTATE_UINT8(auto_eoi, PicState),
 469         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 470         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 471         VMSTATE_UINT8(init4, PicState),
 472         VMSTATE_UINT8(single_mode, PicState),
 473         VMSTATE_UINT8(elcr, PicState),
 474         VMSTATE_END_OF_LIST()
 475     }
 476 };
 477
 478 /* XXX: add generic master/slave system */
 479 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 480 {
 481     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 482     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 483     if (elcr_addr >= 0) {
 484         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 485         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 486     }
 487     vmstate_register(io_addr, &vmstate_pic, s);
 488     qemu_register_reset(pic_reset, s);
 489 }
 490
 491 void pic_info(Monitor *mon)
 492 {
 493     int i;
 494     PicState *s;
 495
 496     if (!isa_pic)
 497         return;
 498
 499     for(i=0;i<2;i++) {
 500         s = &isa_pic->pics[i];
 501         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 502                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 503                        i, s->irr, s->imr, s->isr, s->priority_add,
 504                        s->irq_base, s->read_reg_select, s->elcr,
 505                        s->special_fully_nested_mode);
 506     }
 507 }
 508
 509 void irq_info(Monitor *mon)
 510 {
 511 #ifndef DEBUG_IRQ_COUNT
 512     monitor_printf(mon, "irq statistic code not compiled.\n");
 513 #else
 514     int i;
 515     int64_t count;
 516
 517     monitor_printf(mon, "IRQ statistics:\n");
 518     for (i = 0; i < 16; i++) {
 519         count = irq_count[i];
 520         if (count > 0)
 521             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 522     }
 523 #endif
 524 }
 525
 526 qemu_irq *i8259_init(qemu_irq parent_irq)
 527 {
 528     PicState2 *s;
 529
 530     s = qemu_mallocz(sizeof(PicState2));
 531     pic_init1(0x20, 0x4d0, &s->pics[0]);
 532     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 533     s->pics[0].elcr_mask = 0xf8;
 534     s->pics[1].elcr_mask = 0xde;
 535     s->parent_irq = parent_irq;
 536     s->pics[0].pics_state = s;
 537     s->pics[1].pics_state = s;
 538     isa_pic = s;
 539     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 540 }