hw/apb_pci.c

   1 /*
   2  * QEMU Ultrasparc APB PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* XXX This file and most of its contents are somewhat misnamed.  The
  26    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
  27    the secondary PCI bridge.  */
  28
  29 #include "sysbus.h"
  30 #include "pci.h"
  31 #include "pci_host.h"
  32 #include "rwhandler.h"
  33 #include "apb_pci.h"
  34
  35 /* debug APB */
  36 //#define DEBUG_APB
  37
  38 #ifdef DEBUG_APB
  39 #define APB_DPRINTF(fmt, ...) \
  40 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
  41 #else
  42 #define APB_DPRINTF(fmt, ...)
  43 #endif
  44
  45 /*
  46  * Chipset docs:
  47  * PBM: "UltraSPARC IIi User's Manual",
  48  * http://www.sun.com/processors/manuals/805-0087.pdf
  49  *
  50  * APB: "Advanced PCI Bridge (APB) User's Manual",
  51  * http://www.sun.com/processors/manuals/805-1251.pdf
  52  */
  53
  54 #define PBM_PCI_IMR_MASK    0x7fffffff
  55 #define PBM_PCI_IMR_ENABLED 0x80000000
  56
  57 #define POR          (1 << 31)
  58 #define SOFT_POR     (1 << 30)
  59 #define SOFT_XIR     (1 << 29)
  60 #define BTN_POR      (1 << 28)
  61 #define BTN_XIR      (1 << 27)
  62 #define RESET_MASK   0xf8000000
  63 #define RESET_WCMASK 0x98000000
  64 #define RESET_WMASK  0x60000000
  65
  66 typedef struct APBState {
  67     SysBusDevice busdev;
  68     PCIHostState host_state;
  69     ReadWriteHandler pci_config_handler;
  70     uint32_t iommu[4];
  71     uint32_t pci_control[16];
  72     uint32_t pci_irq_map[8];
  73     uint32_t obio_irq_map[32];
  74     qemu_irq pci_irqs[32];
  75     uint32_t reset_control;
  76 } APBState;
  77
  78 static unsigned int nr_resets;
  79
  80 static void apb_config_writel (void *opaque, target_phys_addr_t addr,
  81                                uint32_t val)
  82 {
  83     APBState *s = opaque;
  84
  85     APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
  86
  87     switch (addr & 0xffff) {
  88     case 0x30 ... 0x4f: /* DMA error registers */
  89         /* XXX: not implemented yet */
  90         break;
  91     case 0x200 ... 0x20b: /* IOMMU */
  92         s->iommu[(addr & 0xf) >> 2] = val;
  93         break;
  94     case 0x20c ... 0x3ff: /* IOMMU flush */
  95         break;
  96     case 0xc00 ... 0xc3f: /* PCI interrupt control */
  97         if (addr & 4) {
  98             s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
  99             s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
 100         }
 101         break;
 102     case 0x2000 ... 0x202f: /* PCI control */
 103         s->pci_control[(addr & 0x3f) >> 2] = val;
 104         break;
 105     case 0xf020 ... 0xf027: /* Reset control */
 106         if (addr & 4) {
 107             val &= RESET_MASK;
 108             s->reset_control &= ~(val & RESET_WCMASK);
 109             s->reset_control |= val & RESET_WMASK;
 110             if (val & SOFT_POR) {
 111                 nr_resets = 0;
 112                 qemu_system_reset_request();
 113             } else if (val & SOFT_XIR) {
 114                 qemu_system_reset_request();
 115             }
 116         }
 117         break;
 118     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 119     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 120     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 121     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 122         /* we don't care */
 123     default:
 124         break;
 125     }
 126 }
 127
 128 static uint32_t apb_config_readl (void *opaque,
 129                                   target_phys_addr_t addr)
 130 {
 131     APBState *s = opaque;
 132     uint32_t val;
 133
 134     switch (addr & 0xffff) {
 135     case 0x30 ... 0x4f: /* DMA error registers */
 136         val = 0;
 137         /* XXX: not implemented yet */
 138         break;
 139     case 0x200 ... 0x20b: /* IOMMU */
 140         val = s->iommu[(addr & 0xf) >> 2];
 141         break;
 142     case 0x20c ... 0x3ff: /* IOMMU flush */
 143         val = 0;
 144         break;
 145     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 146         if (addr & 4) {
 147             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 148         } else {
 149             val = 0;
 150         }
 151         break;
 152     case 0x2000 ... 0x202f: /* PCI control */
 153         val = s->pci_control[(addr & 0x3f) >> 2];
 154         break;
 155     case 0xf020 ... 0xf027: /* Reset control */
 156         if (addr & 4) {
 157             val = s->reset_control;
 158         } else {
 159             val = 0;
 160         }
 161         break;
 162     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 163     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 164     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 165     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 166         /* we don't care */
 167     default:
 168         val = 0;
 169         break;
 170     }
 171     APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
 172
 173     return val;
 174 }
 175
 176 static CPUWriteMemoryFunc * const apb_config_write[] = {
 177     &apb_config_writel,
 178     &apb_config_writel,
 179     &apb_config_writel,
 180 };
 181
 182 static CPUReadMemoryFunc * const apb_config_read[] = {
 183     &apb_config_readl,
 184     &apb_config_readl,
 185     &apb_config_readl,
 186 };
 187
 188 static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
 189                                  uint32_t val, int size)
 190 {
 191     APBState *s = container_of(h, APBState, pci_config_handler);
 192
 193     val = qemu_bswap_len(val, size);
 194     APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
 195     pci_data_write(s->host_state.bus, addr, val, size);
 196 }
 197
 198 static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
 199                                     int size)
 200 {
 201     uint32_t ret;
 202     APBState *s = container_of(h, APBState, pci_config_handler);
 203
 204     ret = pci_data_read(s->host_state.bus, addr, size);
 205     ret = qemu_bswap_len(ret, size);
 206     APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
 207     return ret;
 208 }
 209
 210 static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
 211                                   uint32_t val)
 212 {
 213     cpu_outb(addr & IOPORTS_MASK, val);
 214 }
 215
 216 static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
 217                                   uint32_t val)
 218 {
 219     cpu_outw(addr & IOPORTS_MASK, bswap16(val));
 220 }
 221
 222 static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
 223                                 uint32_t val)
 224 {
 225     cpu_outl(addr & IOPORTS_MASK, bswap32(val));
 226 }
 227
 228 static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
 229 {
 230     uint32_t val;
 231
 232     val = cpu_inb(addr & IOPORTS_MASK);
 233     return val;
 234 }
 235
 236 static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
 237 {
 238     uint32_t val;
 239
 240     val = bswap16(cpu_inw(addr & IOPORTS_MASK));
 241     return val;
 242 }
 243
 244 static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
 245 {
 246     uint32_t val;
 247
 248     val = bswap32(cpu_inl(addr & IOPORTS_MASK));
 249     return val;
 250 }
 251
 252 static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
 253     &pci_apb_iowriteb,
 254     &pci_apb_iowritew,
 255     &pci_apb_iowritel,
 256 };
 257
 258 static CPUReadMemoryFunc * const pci_apb_ioread[] = {
 259     &pci_apb_ioreadb,
 260     &pci_apb_ioreadw,
 261     &pci_apb_ioreadl,
 262 };
 263
 264 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 265 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
 266 {
 267     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 268 }
 269
 270 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
 271 {
 272     int bus_offset;
 273     if (pci_dev->devfn & 1)
 274         bus_offset = 16;
 275     else
 276         bus_offset = 0;
 277     return bus_offset + irq_num;
 278 }
 279
 280 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 281 {
 282     APBState *s = opaque;
 283
 284     /* PCI IRQ map onto the first 32 INO.  */
 285     if (irq_num < 32) {
 286         if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 287             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
 288             qemu_set_irq(s->pci_irqs[irq_num], level);
 289         } else {
 290             APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
 291             qemu_irq_lower(s->pci_irqs[irq_num]);
 292         }
 293     }
 294 }
 295
 296 static void apb_pci_bridge_init(PCIBus *b)
 297 {
 298     PCIDevice *dev = pci_bridge_get_device(b);
 299
 300     /*
 301      * command register:
 302      * According to PCI bridge spec, after reset
 303      *   bus master bit is off
 304      *   memory space enable bit is off
 305      * According to manual (805-1251.pdf).
 306      *   the reset value should be zero unless the boot pin is tied high
 307      *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
 308      */
 309     pci_set_word(dev->config + PCI_COMMAND,
 310                  PCI_COMMAND_MEMORY);
 311     pci_set_word(dev->config + PCI_STATUS,
 312                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 313                  PCI_STATUS_DEVSEL_MEDIUM);
 314     pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
 315     pci_set_byte(dev->config + PCI_HEADER_TYPE,
 316                  pci_get_byte(dev->config + PCI_HEADER_TYPE) |
 317                  PCI_HEADER_TYPE_MULTI_FUNCTION);
 318 }
 319
 320 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 321                      target_phys_addr_t mem_base,
 322                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
 323 {
 324     DeviceState *dev;
 325     SysBusDevice *s;
 326     APBState *d;
 327     unsigned int i;
 328
 329     /* Ultrasparc PBM main bus */
 330     dev = qdev_create(NULL, "pbm");
 331     qdev_init_nofail(dev);
 332     s = sysbus_from_qdev(dev);
 333     /* apb_config */
 334     sysbus_mmio_map(s, 0, special_base);
 335     /* pci_ioport */
 336     sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
 337     /* pci_config */
 338     sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
 339     /* mem_data */
 340     sysbus_mmio_map(s, 3, mem_base);
 341     d = FROM_SYSBUS(APBState, s);
 342     d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
 343                                          pci_apb_set_irq, pci_pbm_map_irq, d,
 344                                          0, 32);
 345     pci_bus_set_mem_base(d->host_state.bus, mem_base);
 346
 347     for (i = 0; i < 32; i++) {
 348         sysbus_connect_irq(s, i, pic[i]);
 349     }
 350
 351     pci_create_simple(d->host_state.bus, 0, "pbm");
 352     /* APB secondary busses */
 353     *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
 354                             PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
 355                             pci_apb_map_irq,
 356                             "Advanced PCI Bus secondary bridge 1");
 357     apb_pci_bridge_init(*bus2);
 358
 359     *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
 360                             PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
 361                             pci_apb_map_irq,
 362                             "Advanced PCI Bus secondary bridge 2");
 363     apb_pci_bridge_init(*bus3);
 364
 365     return d->host_state.bus;
 366 }
 367
 368 static void pci_pbm_reset(DeviceState *d)
 369 {
 370     unsigned int i;
 371     APBState *s = container_of(d, APBState, busdev.qdev);
 372
 373     for (i = 0; i < 8; i++) {
 374         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 375     }
 376
 377     if (nr_resets++ == 0) {
 378         /* Power on reset */
 379         s->reset_control = POR;
 380     }
 381 }
 382
 383 static int pci_pbm_init_device(SysBusDevice *dev)
 384 {
 385     APBState *s;
 386     int pci_mem_data, apb_config, pci_ioport, pci_config;
 387     unsigned int i;
 388
 389     s = FROM_SYSBUS(APBState, dev);
 390     for (i = 0; i < 8; i++) {
 391         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 392     }
 393     for (i = 0; i < 32; i++) {
 394         sysbus_init_irq(dev, &s->pci_irqs[i]);
 395     }
 396
 397     /* apb_config */
 398     apb_config = cpu_register_io_memory(apb_config_read,
 399                                         apb_config_write, s);
 400     sysbus_init_mmio(dev, 0x10000ULL, apb_config);
 401     /* pci_ioport */
 402     pci_ioport = cpu_register_io_memory(pci_apb_ioread,
 403                                           pci_apb_iowrite, s);
 404     sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
 405     /* pci_config */
 406     s->pci_config_handler.read = apb_pci_config_read;
 407     s->pci_config_handler.write = apb_pci_config_write;
 408     pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
 409     assert(pci_config >= 0);
 410     sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
 411     /* mem_data */
 412     pci_mem_data = pci_host_data_register_mmio(&s->host_state);
 413     sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
 414     return 0;
 415 }
 416
 417 static int pbm_pci_host_init(PCIDevice *d)
 418 {
 419     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
 420     pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
 421     pci_set_word(d->config + PCI_COMMAND,
 422                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 423     pci_set_word(d->config + PCI_STATUS,
 424                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 425                  PCI_STATUS_DEVSEL_MEDIUM);
 426     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 427     pci_set_byte(d->config + PCI_HEADER_TYPE,
 428                  PCI_HEADER_TYPE_NORMAL);
 429     return 0;
 430 }
 431
 432 static PCIDeviceInfo pbm_pci_host_info = {
 433     .qdev.name = "pbm",
 434     .qdev.size = sizeof(PCIDevice),
 435     .init      = pbm_pci_host_init,
 436     .header_type  = PCI_HEADER_TYPE_BRIDGE,
 437 };
 438
 439 static SysBusDeviceInfo pbm_host_info = {
 440     .qdev.name = "pbm",
 441     .qdev.size = sizeof(APBState),
 442     .qdev.reset = pci_pbm_reset,
 443     .init = pci_pbm_init_device,
 444 };
 445 static void pbm_register_devices(void)
 446 {
 447     sysbus_register_withprop(&pbm_host_info);
 448     pci_qdev_register(&pbm_pci_host_info);
 449 }
 450
 451 device_init(pbm_register_devices)