target-arm/helper.c

   1 #include <stdio.h>
   2 #include <stdlib.h>
   3 #include <string.h>
   4
   5 #include "cpu.h"
   6 #include "exec-all.h"
   7 #include "gdbstub.h"
   8 #include "helpers.h"
   9 #include "qemu-common.h"
  10 #include "host-utils.h"
  11
  12 static uint32_t cortexa9_cp15_c0_c1[8] =
  13 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
  14
  15 static uint32_t cortexa9_cp15_c0_c2[8] =
  16 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
  17
  18 static uint32_t cortexa8_cp15_c0_c1[8] =
  19 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
  20
  21 static uint32_t cortexa8_cp15_c0_c2[8] =
  22 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
  23
  24 static uint32_t mpcore_cp15_c0_c1[8] =
  25 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
  26
  27 static uint32_t mpcore_cp15_c0_c2[8] =
  28 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
  29
  30 static uint32_t arm1136_cp15_c0_c1[8] =
  31 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
  32
  33 static uint32_t arm1136_cp15_c0_c2[8] =
  34 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
  35
  36 static uint32_t cpu_arm_find_by_name(const char *name);
  37
  38 static inline void set_feature(CPUARMState *env, int feature)
  39 {
  40     env->features |= 1u << feature;
  41 }
  42
  43 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
  44 {
  45     env->cp15.c0_cpuid = id;
  46     switch (id) {
  47     case ARM_CPUID_ARM926:
  48         set_feature(env, ARM_FEATURE_VFP);
  49         env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
  50         env->cp15.c0_cachetype = 0x1dd20d2;
  51         env->cp15.c1_sys = 0x00090078;
  52         break;
  53     case ARM_CPUID_ARM946:
  54         set_feature(env, ARM_FEATURE_MPU);
  55         env->cp15.c0_cachetype = 0x0f004006;
  56         env->cp15.c1_sys = 0x00000078;
  57         break;
  58     case ARM_CPUID_ARM1026:
  59         set_feature(env, ARM_FEATURE_VFP);
  60         set_feature(env, ARM_FEATURE_AUXCR);
  61         env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
  62         env->cp15.c0_cachetype = 0x1dd20d2;
  63         env->cp15.c1_sys = 0x00090078;
  64         break;
  65     case ARM_CPUID_ARM1136_R2:
  66     case ARM_CPUID_ARM1136:
  67         set_feature(env, ARM_FEATURE_V6);
  68         set_feature(env, ARM_FEATURE_VFP);
  69         set_feature(env, ARM_FEATURE_AUXCR);
  70         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
  71         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
  72         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
  73         memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
  74         memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
  75         env->cp15.c0_cachetype = 0x1dd20d2;
  76         break;
  77     case ARM_CPUID_ARM11MPCORE:
  78         set_feature(env, ARM_FEATURE_V6);
  79         set_feature(env, ARM_FEATURE_V6K);
  80         set_feature(env, ARM_FEATURE_VFP);
  81         set_feature(env, ARM_FEATURE_AUXCR);
  82         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
  83         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
  84         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
  85         memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
  86         memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
  87         env->cp15.c0_cachetype = 0x1dd20d2;
  88         break;
  89     case ARM_CPUID_CORTEXA8:
  90         set_feature(env, ARM_FEATURE_V6);
  91         set_feature(env, ARM_FEATURE_V6K);
  92         set_feature(env, ARM_FEATURE_V7);
  93         set_feature(env, ARM_FEATURE_AUXCR);
  94         set_feature(env, ARM_FEATURE_THUMB2);
  95         set_feature(env, ARM_FEATURE_VFP);
  96         set_feature(env, ARM_FEATURE_VFP3);
  97         set_feature(env, ARM_FEATURE_NEON);
  98         set_feature(env, ARM_FEATURE_THUMB2EE);
  99         env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
 100         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
 101         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
 102         memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
 103         memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
 104         env->cp15.c0_cachetype = 0x82048004;
 105         env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
 106         env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
 107         env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
 108         env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
 109         break;
 110     case ARM_CPUID_CORTEXA9:
 111         set_feature(env, ARM_FEATURE_V6);
 112         set_feature(env, ARM_FEATURE_V6K);
 113         set_feature(env, ARM_FEATURE_V7);
 114         set_feature(env, ARM_FEATURE_AUXCR);
 115         set_feature(env, ARM_FEATURE_THUMB2);
 116         set_feature(env, ARM_FEATURE_VFP);
 117         set_feature(env, ARM_FEATURE_VFP3);
 118         set_feature(env, ARM_FEATURE_VFP_FP16);
 119         set_feature(env, ARM_FEATURE_NEON);
 120         set_feature(env, ARM_FEATURE_THUMB2EE);
 121         env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
 122         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
 123         env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
 124         memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
 125         memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
 126         env->cp15.c0_cachetype = 0x80038003;
 127         env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
 128         env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
 129         env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
 130         break;
 131     case ARM_CPUID_CORTEXM3:
 132         set_feature(env, ARM_FEATURE_V6);
 133         set_feature(env, ARM_FEATURE_THUMB2);
 134         set_feature(env, ARM_FEATURE_V7);
 135         set_feature(env, ARM_FEATURE_M);
 136         set_feature(env, ARM_FEATURE_DIV);
 137         break;
 138     case ARM_CPUID_ANY: /* For userspace emulation.  */
 139         set_feature(env, ARM_FEATURE_V6);
 140         set_feature(env, ARM_FEATURE_V6K);
 141         set_feature(env, ARM_FEATURE_V7);
 142         set_feature(env, ARM_FEATURE_THUMB2);
 143         set_feature(env, ARM_FEATURE_VFP);
 144         set_feature(env, ARM_FEATURE_VFP3);
 145         set_feature(env, ARM_FEATURE_VFP_FP16);
 146         set_feature(env, ARM_FEATURE_NEON);
 147         set_feature(env, ARM_FEATURE_THUMB2EE);
 148         set_feature(env, ARM_FEATURE_DIV);
 149         break;
 150     case ARM_CPUID_TI915T:
 151     case ARM_CPUID_TI925T:
 152         set_feature(env, ARM_FEATURE_OMAPCP);
 153         env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring.  */
 154         env->cp15.c0_cachetype = 0x5109149;
 155         env->cp15.c1_sys = 0x00000070;
 156         env->cp15.c15_i_max = 0x000;
 157         env->cp15.c15_i_min = 0xff0;
 158         break;
 159     case ARM_CPUID_PXA250:
 160     case ARM_CPUID_PXA255:
 161     case ARM_CPUID_PXA260:
 162     case ARM_CPUID_PXA261:
 163     case ARM_CPUID_PXA262:
 164         set_feature(env, ARM_FEATURE_XSCALE);
 165         /* JTAG_ID is ((id << 28) | 0x09265013) */
 166         env->cp15.c0_cachetype = 0xd172172;
 167         env->cp15.c1_sys = 0x00000078;
 168         break;
 169     case ARM_CPUID_PXA270_A0:
 170     case ARM_CPUID_PXA270_A1:
 171     case ARM_CPUID_PXA270_B0:
 172     case ARM_CPUID_PXA270_B1:
 173     case ARM_CPUID_PXA270_C0:
 174     case ARM_CPUID_PXA270_C5:
 175         set_feature(env, ARM_FEATURE_XSCALE);
 176         /* JTAG_ID is ((id << 28) | 0x09265013) */
 177         set_feature(env, ARM_FEATURE_IWMMXT);
 178         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 179         env->cp15.c0_cachetype = 0xd172172;
 180         env->cp15.c1_sys = 0x00000078;
 181         break;
 182     default:
 183         cpu_abort(env, "Bad CPU ID: %x\n", id);
 184         break;
 185     }
 186 }
 187
 188 void cpu_reset(CPUARMState *env)
 189 {
 190     uint32_t id;
 191
 192     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 193         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
 194         log_cpu_state(env, 0);
 195     }
 196
 197     id = env->cp15.c0_cpuid;
 198     memset(env, 0, offsetof(CPUARMState, breakpoints));
 199     if (id)
 200         cpu_reset_model_id(env, id);
 201 #if defined (CONFIG_USER_ONLY)
 202     env->uncached_cpsr = ARM_CPU_MODE_USR;
 203     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 204 #else
 205     /* SVC mode with interrupts disabled.  */
 206     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 207     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 208        clear at reset.  */
 209     if (IS_M(env))
 210         env->uncached_cpsr &= ~CPSR_I;
 211     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 212     env->cp15.c2_base_mask = 0xffffc000u;
 213 #endif
 214     env->regs[15] = 0;
 215     tlb_flush(env, 1);
 216 }
 217
 218 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
 219 {
 220     int nregs;
 221
 222     /* VFP data registers are always little-endian.  */
 223     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
 224     if (reg < nregs) {
 225         stfq_le_p(buf, env->vfp.regs[reg]);
 226         return 8;
 227     }
 228     if (arm_feature(env, ARM_FEATURE_NEON)) {
 229         /* Aliases for Q regs.  */
 230         nregs += 16;
 231         if (reg < nregs) {
 232             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
 233             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
 234             return 16;
 235         }
 236     }
 237     switch (reg - nregs) {
 238     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
 239     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
 240     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
 241     }
 242     return 0;
 243 }
 244
 245 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
 246 {
 247     int nregs;
 248
 249     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
 250     if (reg < nregs) {
 251         env->vfp.regs[reg] = ldfq_le_p(buf);
 252         return 8;
 253     }
 254     if (arm_feature(env, ARM_FEATURE_NEON)) {
 255         nregs += 16;
 256         if (reg < nregs) {
 257             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
 258             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
 259             return 16;
 260         }
 261     }
 262     switch (reg - nregs) {
 263     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
 264     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
 265     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
 266     }
 267     return 0;
 268 }
 269
 270 CPUARMState *cpu_arm_init(const char *cpu_model)
 271 {
 272     CPUARMState *env;
 273     uint32_t id;
 274     static int inited = 0;
 275
 276     id = cpu_arm_find_by_name(cpu_model);
 277     if (id == 0)
 278         return NULL;
 279     env = qemu_mallocz(sizeof(CPUARMState));
 280     cpu_exec_init(env);
 281     if (!inited) {
 282         inited = 1;
 283         arm_translate_init();
 284     }
 285
 286     env->cpu_model_str = cpu_model;
 287     env->cp15.c0_cpuid = id;
 288     cpu_reset(env);
 289     if (arm_feature(env, ARM_FEATURE_NEON)) {
 290         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
 291                                  51, "arm-neon.xml", 0);
 292     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
 293         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
 294                                  35, "arm-vfp3.xml", 0);
 295     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
 296         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
 297                                  19, "arm-vfp.xml", 0);
 298     }
 299     qemu_init_vcpu(env);
 300     return env;
 301 }
 302
 303 struct arm_cpu_t {
 304     uint32_t id;
 305     const char *name;
 306 };
 307
 308 static const struct arm_cpu_t arm_cpu_names[] = {
 309     { ARM_CPUID_ARM926, "arm926"},
 310     { ARM_CPUID_ARM946, "arm946"},
 311     { ARM_CPUID_ARM1026, "arm1026"},
 312     { ARM_CPUID_ARM1136, "arm1136"},
 313     { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
 314     { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
 315     { ARM_CPUID_CORTEXM3, "cortex-m3"},
 316     { ARM_CPUID_CORTEXA8, "cortex-a8"},
 317     { ARM_CPUID_CORTEXA9, "cortex-a9"},
 318     { ARM_CPUID_TI925T, "ti925t" },
 319     { ARM_CPUID_PXA250, "pxa250" },
 320     { ARM_CPUID_PXA255, "pxa255" },
 321     { ARM_CPUID_PXA260, "pxa260" },
 322     { ARM_CPUID_PXA261, "pxa261" },
 323     { ARM_CPUID_PXA262, "pxa262" },
 324     { ARM_CPUID_PXA270, "pxa270" },
 325     { ARM_CPUID_PXA270_A0, "pxa270-a0" },
 326     { ARM_CPUID_PXA270_A1, "pxa270-a1" },
 327     { ARM_CPUID_PXA270_B0, "pxa270-b0" },
 328     { ARM_CPUID_PXA270_B1, "pxa270-b1" },
 329     { ARM_CPUID_PXA270_C0, "pxa270-c0" },
 330     { ARM_CPUID_PXA270_C5, "pxa270-c5" },
 331     { ARM_CPUID_ANY, "any"},
 332     { 0, NULL}
 333 };
 334
 335 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 336 {
 337     int i;
 338
 339     (*cpu_fprintf)(f, "Available CPUs:\n");
 340     for (i = 0; arm_cpu_names[i].name; i++) {
 341         (*cpu_fprintf)(f, "  %s\n", arm_cpu_names[i].name);
 342     }
 343 }
 344
 345 /* return 0 if not found */
 346 static uint32_t cpu_arm_find_by_name(const char *name)
 347 {
 348     int i;
 349     uint32_t id;
 350
 351     id = 0;
 352     for (i = 0; arm_cpu_names[i].name; i++) {
 353         if (strcmp(name, arm_cpu_names[i].name) == 0) {
 354             id = arm_cpu_names[i].id;
 355             break;
 356         }
 357     }
 358     return id;
 359 }
 360
 361 void cpu_arm_close(CPUARMState *env)
 362 {
 363     free(env);
 364 }
 365
 366 uint32_t cpsr_read(CPUARMState *env)
 367 {
 368     int ZF;
 369     ZF = (env->ZF == 0);
 370     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
 371         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 372         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
 373         | ((env->condexec_bits & 0xfc) << 8)
 374         | (env->GE << 16);
 375 }
 376
 377 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 378 {
 379     if (mask & CPSR_NZCV) {
 380         env->ZF = (~val) & CPSR_Z;
 381         env->NF = val;
 382         env->CF = (val >> 29) & 1;
 383         env->VF = (val << 3) & 0x80000000;
 384     }
 385     if (mask & CPSR_Q)
 386         env->QF = ((val & CPSR_Q) != 0);
 387     if (mask & CPSR_T)
 388         env->thumb = ((val & CPSR_T) != 0);
 389     if (mask & CPSR_IT_0_1) {
 390         env->condexec_bits &= ~3;
 391         env->condexec_bits |= (val >> 25) & 3;
 392     }
 393     if (mask & CPSR_IT_2_7) {
 394         env->condexec_bits &= 3;
 395         env->condexec_bits |= (val >> 8) & 0xfc;
 396     }
 397     if (mask & CPSR_GE) {
 398         env->GE = (val >> 16) & 0xf;
 399     }
 400
 401     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
 402         switch_mode(env, val & CPSR_M);
 403     }
 404     mask &= ~CACHED_CPSR_BITS;
 405     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
 406 }
 407
 408 /* Sign/zero extend */
 409 uint32_t HELPER(sxtb16)(uint32_t x)
 410 {
 411     uint32_t res;
 412     res = (uint16_t)(int8_t)x;
 413     res |= (uint32_t)(int8_t)(x >> 16) << 16;
 414     return res;
 415 }
 416
 417 uint32_t HELPER(uxtb16)(uint32_t x)
 418 {
 419     uint32_t res;
 420     res = (uint16_t)(uint8_t)x;
 421     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
 422     return res;
 423 }
 424
 425 uint32_t HELPER(clz)(uint32_t x)
 426 {
 427     return clz32(x);
 428 }
 429
 430 int32_t HELPER(sdiv)(int32_t num, int32_t den)
 431 {
 432     if (den == 0)
 433       return 0;
 434     if (num == INT_MIN && den == -1)
 435       return INT_MIN;
 436     return num / den;
 437 }
 438
 439 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
 440 {
 441     if (den == 0)
 442       return 0;
 443     return num / den;
 444 }
 445
 446 uint32_t HELPER(rbit)(uint32_t x)
 447 {
 448     x =  ((x & 0xff000000) >> 24)
 449        | ((x & 0x00ff0000) >> 8)
 450        | ((x & 0x0000ff00) << 8)
 451        | ((x & 0x000000ff) << 24);
 452     x =  ((x & 0xf0f0f0f0) >> 4)
 453        | ((x & 0x0f0f0f0f) << 4);
 454     x =  ((x & 0x88888888) >> 3)
 455        | ((x & 0x44444444) >> 1)
 456        | ((x & 0x22222222) << 1)
 457        | ((x & 0x11111111) << 3);
 458     return x;
 459 }
 460
 461 uint32_t HELPER(abs)(uint32_t x)
 462 {
 463     return ((int32_t)x < 0) ? -x : x;
 464 }
 465
 466 #if defined(CONFIG_USER_ONLY)
 467
 468 void do_interrupt (CPUState *env)
 469 {
 470     env->exception_index = -1;
 471 }
 472
 473 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 474                               int mmu_idx, int is_softmmu)
 475 {
 476     if (rw == 2) {
 477         env->exception_index = EXCP_PREFETCH_ABORT;
 478         env->cp15.c6_insn = address;
 479     } else {
 480         env->exception_index = EXCP_DATA_ABORT;
 481         env->cp15.c6_data = address;
 482     }
 483     return 1;
 484 }
 485
 486 /* These should probably raise undefined insn exceptions.  */
 487 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
 488 {
 489     int op1 = (insn >> 8) & 0xf;
 490     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
 491     return;
 492 }
 493
 494 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
 495 {
 496     int op1 = (insn >> 8) & 0xf;
 497     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
 498     return 0;
 499 }
 500
 501 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
 502 {
 503     cpu_abort(env, "cp15 insn %08x\n", insn);
 504 }
 505
 506 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
 507 {
 508     cpu_abort(env, "cp15 insn %08x\n", insn);
 509 }
 510
 511 /* These should probably raise undefined insn exceptions.  */
 512 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
 513 {
 514     cpu_abort(env, "v7m_mrs %d\n", reg);
 515 }
 516
 517 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
 518 {
 519     cpu_abort(env, "v7m_mrs %d\n", reg);
 520     return 0;
 521 }
 522
 523 void switch_mode(CPUState *env, int mode)
 524 {
 525     if (mode != ARM_CPU_MODE_USR)
 526         cpu_abort(env, "Tried to switch out of user mode\n");
 527 }
 528
 529 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
 530 {
 531     cpu_abort(env, "banked r13 write\n");
 532 }
 533
 534 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
 535 {
 536     cpu_abort(env, "banked r13 read\n");
 537     return 0;
 538 }
 539
 540 #else
 541
 542 extern int semihosting_enabled;
 543
 544 /* Map CPU modes onto saved register banks.  */
 545 static inline int bank_number (int mode)
 546 {
 547     switch (mode) {
 548     case ARM_CPU_MODE_USR:
 549     case ARM_CPU_MODE_SYS:
 550         return 0;
 551     case ARM_CPU_MODE_SVC:
 552         return 1;
 553     case ARM_CPU_MODE_ABT:
 554         return 2;
 555     case ARM_CPU_MODE_UND:
 556         return 3;
 557     case ARM_CPU_MODE_IRQ:
 558         return 4;
 559     case ARM_CPU_MODE_FIQ:
 560         return 5;
 561     }
 562     cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
 563     return -1;
 564 }
 565
 566 void switch_mode(CPUState *env, int mode)
 567 {
 568     int old_mode;
 569     int i;
 570
 571     old_mode = env->uncached_cpsr & CPSR_M;
 572     if (mode == old_mode)
 573         return;
 574
 575     if (old_mode == ARM_CPU_MODE_FIQ) {
 576         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 577         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 578     } else if (mode == ARM_CPU_MODE_FIQ) {
 579         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 580         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 581     }
 582
 583     i = bank_number(old_mode);
 584     env->banked_r13[i] = env->regs[13];
 585     env->banked_r14[i] = env->regs[14];
 586     env->banked_spsr[i] = env->spsr;
 587
 588     i = bank_number(mode);
 589     env->regs[13] = env->banked_r13[i];
 590     env->regs[14] = env->banked_r14[i];
 591     env->spsr = env->banked_spsr[i];
 592 }
 593
 594 static void v7m_push(CPUARMState *env, uint32_t val)
 595 {
 596     env->regs[13] -= 4;
 597     stl_phys(env->regs[13], val);
 598 }
 599
 600 static uint32_t v7m_pop(CPUARMState *env)
 601 {
 602     uint32_t val;
 603     val = ldl_phys(env->regs[13]);
 604     env->regs[13] += 4;
 605     return val;
 606 }
 607
 608 /* Switch to V7M main or process stack pointer.  */
 609 static void switch_v7m_sp(CPUARMState *env, int process)
 610 {
 611     uint32_t tmp;
 612     if (env->v7m.current_sp != process) {
 613         tmp = env->v7m.other_sp;
 614         env->v7m.other_sp = env->regs[13];
 615         env->regs[13] = tmp;
 616         env->v7m.current_sp = process;
 617     }
 618 }
 619
 620 static void do_v7m_exception_exit(CPUARMState *env)
 621 {
 622     uint32_t type;
 623     uint32_t xpsr;
 624
 625     type = env->regs[15];
 626     if (env->v7m.exception != 0)
 627         armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
 628
 629     /* Switch to the target stack.  */
 630     switch_v7m_sp(env, (type & 4) != 0);
 631     /* Pop registers.  */
 632     env->regs[0] = v7m_pop(env);
 633     env->regs[1] = v7m_pop(env);
 634     env->regs[2] = v7m_pop(env);
 635     env->regs[3] = v7m_pop(env);
 636     env->regs[12] = v7m_pop(env);
 637     env->regs[14] = v7m_pop(env);
 638     env->regs[15] = v7m_pop(env);
 639     xpsr = v7m_pop(env);
 640     xpsr_write(env, xpsr, 0xfffffdff);
 641     /* Undo stack alignment.  */
 642     if (xpsr & 0x200)
 643         env->regs[13] |= 4;
 644     /* ??? The exception return type specifies Thread/Handler mode.  However
 645        this is also implied by the xPSR value. Not sure what to do
 646        if there is a mismatch.  */
 647     /* ??? Likewise for mismatches between the CONTROL register and the stack
 648        pointer.  */
 649 }
 650
 651 static void do_interrupt_v7m(CPUARMState *env)
 652 {
 653     uint32_t xpsr = xpsr_read(env);
 654     uint32_t lr;
 655     uint32_t addr;
 656
 657     lr = 0xfffffff1;
 658     if (env->v7m.current_sp)
 659         lr |= 4;
 660     if (env->v7m.exception == 0)
 661         lr |= 8;
 662
 663     /* For exceptions we just mark as pending on the NVIC, and let that
 664        handle it.  */
 665     /* TODO: Need to escalate if the current priority is higher than the
 666        one we're raising.  */
 667     switch (env->exception_index) {
 668     case EXCP_UDEF:
 669         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
 670         return;
 671     case EXCP_SWI:
 672         env->regs[15] += 2;
 673         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
 674         return;
 675     case EXCP_PREFETCH_ABORT:
 676     case EXCP_DATA_ABORT:
 677         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
 678         return;
 679     case EXCP_BKPT:
 680         if (semihosting_enabled) {
 681             int nr;
 682             nr = lduw_code(env->regs[15]) & 0xff;
 683             if (nr == 0xab) {
 684                 env->regs[15] += 2;
 685                 env->regs[0] = do_arm_semihosting(env);
 686                 return;
 687             }
 688         }
 689         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
 690         return;
 691     case EXCP_IRQ:
 692         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
 693         break;
 694     case EXCP_EXCEPTION_EXIT:
 695         do_v7m_exception_exit(env);
 696         return;
 697     default:
 698         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
 699         return; /* Never happens.  Keep compiler happy.  */
 700     }
 701
 702     /* Align stack pointer.  */
 703     /* ??? Should only do this if Configuration Control Register
 704        STACKALIGN bit is set.  */
 705     if (env->regs[13] & 4) {
 706         env->regs[13] -= 4;
 707         xpsr |= 0x200;
 708     }
 709     /* Switch to the handler mode.  */
 710     v7m_push(env, xpsr);
 711     v7m_push(env, env->regs[15]);
 712     v7m_push(env, env->regs[14]);
 713     v7m_push(env, env->regs[12]);
 714     v7m_push(env, env->regs[3]);
 715     v7m_push(env, env->regs[2]);
 716     v7m_push(env, env->regs[1]);
 717     v7m_push(env, env->regs[0]);
 718     switch_v7m_sp(env, 0);
 719     env->uncached_cpsr &= ~CPSR_IT;
 720     env->regs[14] = lr;
 721     addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
 722     env->regs[15] = addr & 0xfffffffe;
 723     env->thumb = addr & 1;
 724 }
 725
 726 /* Handle a CPU exception.  */
 727 void do_interrupt(CPUARMState *env)
 728 {
 729     uint32_t addr;
 730     uint32_t mask;
 731     int new_mode;
 732     uint32_t offset;
 733
 734     if (IS_M(env)) {
 735         do_interrupt_v7m(env);
 736         return;
 737     }
 738     /* TODO: Vectored interrupt controller.  */
 739     switch (env->exception_index) {
 740     case EXCP_UDEF:
 741         new_mode = ARM_CPU_MODE_UND;
 742         addr = 0x04;
 743         mask = CPSR_I;
 744         if (env->thumb)
 745             offset = 2;
 746         else
 747             offset = 4;
 748         break;
 749     case EXCP_SWI:
 750         if (semihosting_enabled) {
 751             /* Check for semihosting interrupt.  */
 752             if (env->thumb) {
 753                 mask = lduw_code(env->regs[15] - 2) & 0xff;
 754             } else {
 755                 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
 756             }
 757             /* Only intercept calls from privileged modes, to provide some
 758                semblance of security.  */
 759             if (((mask == 0x123456 && !env->thumb)
 760                     || (mask == 0xab && env->thumb))
 761                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
 762                 env->regs[0] = do_arm_semihosting(env);
 763                 return;
 764             }
 765         }
 766         new_mode = ARM_CPU_MODE_SVC;
 767         addr = 0x08;
 768         mask = CPSR_I;
 769         /* The PC already points to the next instruction.  */
 770         offset = 0;
 771         break;
 772     case EXCP_BKPT:
 773         /* See if this is a semihosting syscall.  */
 774         if (env->thumb && semihosting_enabled) {
 775             mask = lduw_code(env->regs[15]) & 0xff;
 776             if (mask == 0xab
 777                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
 778                 env->regs[15] += 2;
 779                 env->regs[0] = do_arm_semihosting(env);
 780                 return;
 781             }
 782         }
 783         /* Fall through to prefetch abort.  */
 784     case EXCP_PREFETCH_ABORT:
 785         new_mode = ARM_CPU_MODE_ABT;
 786         addr = 0x0c;
 787         mask = CPSR_A | CPSR_I;
 788         offset = 4;
 789         break;
 790     case EXCP_DATA_ABORT:
 791         new_mode = ARM_CPU_MODE_ABT;
 792         addr = 0x10;
 793         mask = CPSR_A | CPSR_I;
 794         offset = 8;
 795         break;
 796     case EXCP_IRQ:
 797         new_mode = ARM_CPU_MODE_IRQ;
 798         addr = 0x18;
 799         /* Disable IRQ and imprecise data aborts.  */
 800         mask = CPSR_A | CPSR_I;
 801         offset = 4;
 802         break;
 803     case EXCP_FIQ:
 804         new_mode = ARM_CPU_MODE_FIQ;
 805         addr = 0x1c;
 806         /* Disable FIQ, IRQ and imprecise data aborts.  */
 807         mask = CPSR_A | CPSR_I | CPSR_F;
 808         offset = 4;
 809         break;
 810     default:
 811         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
 812         return; /* Never happens.  Keep compiler happy.  */
 813     }
 814     /* High vectors.  */
 815     if (env->cp15.c1_sys & (1 << 13)) {
 816         addr += 0xffff0000;
 817     }
 818     switch_mode (env, new_mode);
 819     env->spsr = cpsr_read(env);
 820     /* Clear IT bits.  */
 821     env->condexec_bits = 0;
 822     /* Switch to the new mode, and to the correct instruction set.  */
 823     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
 824     env->uncached_cpsr |= mask;
 825     env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
 826     env->regs[14] = env->regs[15] + offset;
 827     env->regs[15] = addr;
 828     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 829 }
 830
 831 /* Check section/page access permissions.
 832    Returns the page protection flags, or zero if the access is not
 833    permitted.  */
 834 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
 835                            int is_user)
 836 {
 837   int prot_ro;
 838
 839   if (domain == 3)
 840     return PAGE_READ | PAGE_WRITE;
 841
 842   if (access_type == 1)
 843       prot_ro = 0;
 844   else
 845       prot_ro = PAGE_READ;
 846
 847   switch (ap) {
 848   case 0:
 849       if (access_type == 1)
 850           return 0;
 851       switch ((env->cp15.c1_sys >> 8) & 3) {
 852       case 1:
 853           return is_user ? 0 : PAGE_READ;
 854       case 2:
 855           return PAGE_READ;
 856       default:
 857           return 0;
 858       }
 859   case 1:
 860       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
 861   case 2:
 862       if (is_user)
 863           return prot_ro;
 864       else
 865           return PAGE_READ | PAGE_WRITE;
 866   case 3:
 867       return PAGE_READ | PAGE_WRITE;
 868   case 4: /* Reserved.  */
 869       return 0;
 870   case 5:
 871       return is_user ? 0 : prot_ro;
 872   case 6:
 873       return prot_ro;
 874   case 7:
 875       if (!arm_feature (env, ARM_FEATURE_V7))
 876           return 0;
 877       return prot_ro;
 878   default:
 879       abort();
 880   }
 881 }
 882
 883 static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
 884 {
 885     uint32_t table;
 886
 887     if (address & env->cp15.c2_mask)
 888         table = env->cp15.c2_base1 & 0xffffc000;
 889     else
 890         table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
 891
 892     table |= (address >> 18) & 0x3ffc;
 893     return table;
 894 }
 895
 896 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
 897                             int is_user, uint32_t *phys_ptr, int *prot,
 898                             target_ulong *page_size)
 899 {
 900     int code;
 901     uint32_t table;
 902     uint32_t desc;
 903     int type;
 904     int ap;
 905     int domain;
 906     uint32_t phys_addr;
 907
 908     /* Pagetable walk.  */
 909     /* Lookup l1 descriptor.  */
 910     table = get_level1_table_address(env, address);
 911     desc = ldl_phys(table);
 912     type = (desc & 3);
 913     domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
 914     if (type == 0) {
 915         /* Section translation fault.  */
 916         code = 5;
 917         goto do_fault;
 918     }
 919     if (domain == 0 || domain == 2) {
 920         if (type == 2)
 921             code = 9; /* Section domain fault.  */
 922         else
 923             code = 11; /* Page domain fault.  */
 924         goto do_fault;
 925     }
 926     if (type == 2) {
 927         /* 1Mb section.  */
 928         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
 929         ap = (desc >> 10) & 3;
 930         code = 13;
 931         *page_size = 1024 * 1024;
 932     } else {
 933         /* Lookup l2 entry.  */
 934         if (type == 1) {
 935             /* Coarse pagetable.  */
 936             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
 937         } else {
 938             /* Fine pagetable.  */
 939             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
 940         }
 941         desc = ldl_phys(table);
 942         switch (desc & 3) {
 943         case 0: /* Page translation fault.  */
 944             code = 7;
 945             goto do_fault;
 946         case 1: /* 64k page.  */
 947             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
 948             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
 949             *page_size = 0x10000;
 950             break;
 951         case 2: /* 4k page.  */
 952             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 953             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
 954             *page_size = 0x1000;
 955             break;
 956         case 3: /* 1k page.  */
 957             if (type == 1) {
 958                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 959                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 960                 } else {
 961                     /* Page translation fault.  */
 962                     code = 7;
 963                     goto do_fault;
 964                 }
 965             } else {
 966                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
 967             }
 968             ap = (desc >> 4) & 3;
 969             *page_size = 0x400;
 970             break;
 971         default:
 972             /* Never happens, but compiler isn't smart enough to tell.  */
 973             abort();
 974         }
 975         code = 15;
 976     }
 977     *prot = check_ap(env, ap, domain, access_type, is_user);
 978     if (!*prot) {
 979         /* Access permission fault.  */
 980         goto do_fault;
 981     }
 982     *prot |= PAGE_EXEC;
 983     *phys_ptr = phys_addr;
 984     return 0;
 985 do_fault:
 986     return code | (domain << 4);
 987 }
 988
 989 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
 990                             int is_user, uint32_t *phys_ptr, int *prot,
 991                             target_ulong *page_size)
 992 {
 993     int code;
 994     uint32_t table;
 995     uint32_t desc;
 996     uint32_t xn;
 997     int type;
 998     int ap;
 999     int domain;
1000     uint32_t phys_addr;
1001
1002     /* Pagetable walk.  */
1003     /* Lookup l1 descriptor.  */
1004     table = get_level1_table_address(env, address);
1005     desc = ldl_phys(table);
1006     type = (desc & 3);
1007     if (type == 0) {
1008         /* Section translation fault.  */
1009         code = 5;
1010         domain = 0;
1011         goto do_fault;
1012     } else if (type == 2 && (desc & (1 << 18))) {
1013         /* Supersection.  */
1014         domain = 0;
1015     } else {
1016         /* Section or page.  */
1017         domain = (desc >> 4) & 0x1e;
1018     }
1019     domain = (env->cp15.c3 >> domain) & 3;
1020     if (domain == 0 || domain == 2) {
1021         if (type == 2)
1022             code = 9; /* Section domain fault.  */
1023         else
1024             code = 11; /* Page domain fault.  */
1025         goto do_fault;
1026     }
1027     if (type == 2) {
1028         if (desc & (1 << 18)) {
1029             /* Supersection.  */
1030             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
1031             *page_size = 0x1000000;
1032         } else {
1033             /* Section.  */
1034             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1035             *page_size = 0x100000;
1036         }
1037         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1038         xn = desc & (1 << 4);
1039         code = 13;
1040     } else {
1041         /* Lookup l2 entry.  */
1042         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1043         desc = ldl_phys(table);
1044         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1045         switch (desc & 3) {
1046         case 0: /* Page translation fault.  */
1047             code = 7;
1048             goto do_fault;
1049         case 1: /* 64k page.  */
1050             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1051             xn = desc & (1 << 15);
1052             *page_size = 0x10000;
1053             break;
1054         case 2: case 3: /* 4k page.  */
1055             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1056             xn = desc & 1;
1057             *page_size = 0x1000;
1058             break;
1059         default:
1060             /* Never happens, but compiler isn't smart enough to tell.  */
1061             abort();
1062         }
1063         code = 15;
1064     }
1065     if (xn && access_type == 2)
1066         goto do_fault;
1067
1068     /* The simplified model uses AP[0] as an access control bit.  */
1069     if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1070         /* Access flag fault.  */
1071         code = (code == 15) ? 6 : 3;
1072         goto do_fault;
1073     }
1074     *prot = check_ap(env, ap, domain, access_type, is_user);
1075     if (!*prot) {
1076         /* Access permission fault.  */
1077         goto do_fault;
1078     }
1079     if (!xn) {
1080         *prot |= PAGE_EXEC;
1081     }
1082     *phys_ptr = phys_addr;
1083     return 0;
1084 do_fault:
1085     return code | (domain << 4);
1086 }
1087
1088 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1089                              int is_user, uint32_t *phys_ptr, int *prot)
1090 {
1091     int n;
1092     uint32_t mask;
1093     uint32_t base;
1094
1095     *phys_ptr = address;
1096     for (n = 7; n >= 0; n--) {
1097         base = env->cp15.c6_region[n];
1098         if ((base & 1) == 0)
1099             continue;
1100         mask = 1 << ((base >> 1) & 0x1f);
1101         /* Keep this shift separate from the above to avoid an
1102            (undefined) << 32.  */
1103         mask = (mask << 1) - 1;
1104         if (((base ^ address) & ~mask) == 0)
1105             break;
1106     }
1107     if (n < 0)
1108         return 2;
1109
1110     if (access_type == 2) {
1111         mask = env->cp15.c5_insn;
1112     } else {
1113         mask = env->cp15.c5_data;
1114     }
1115     mask = (mask >> (n * 4)) & 0xf;
1116     switch (mask) {
1117     case 0:
1118         return 1;
1119     case 1:
1120         if (is_user)
1121           return 1;
1122         *prot = PAGE_READ | PAGE_WRITE;
1123         break;
1124     case 2:
1125         *prot = PAGE_READ;
1126         if (!is_user)
1127             *prot |= PAGE_WRITE;
1128         break;
1129     case 3:
1130         *prot = PAGE_READ | PAGE_WRITE;
1131         break;
1132     case 5:
1133         if (is_user)
1134             return 1;
1135         *prot = PAGE_READ;
1136         break;
1137     case 6:
1138         *prot = PAGE_READ;
1139         break;
1140     default:
1141         /* Bad permission.  */
1142         return 1;
1143     }
1144     *prot |= PAGE_EXEC;
1145     return 0;
1146 }
1147
1148 static inline int get_phys_addr(CPUState *env, uint32_t address,
1149                                 int access_type, int is_user,
1150                                 uint32_t *phys_ptr, int *prot,
1151                                 target_ulong *page_size)
1152 {
1153     /* Fast Context Switch Extension.  */
1154     if (address < 0x02000000)
1155         address += env->cp15.c13_fcse;
1156
1157     if ((env->cp15.c1_sys & 1) == 0) {
1158         /* MMU/MPU disabled.  */
1159         *phys_ptr = address;
1160         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1161         *page_size = TARGET_PAGE_SIZE;
1162         return 0;
1163     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1164         *page_size = TARGET_PAGE_SIZE;
1165         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1166                                  prot);
1167     } else if (env->cp15.c1_sys & (1 << 23)) {
1168         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1169                                 prot, page_size);
1170     } else {
1171         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1172                                 prot, page_size);
1173     }
1174 }
1175
1176 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1177                               int access_type, int mmu_idx, int is_softmmu)
1178 {
1179     uint32_t phys_addr;
1180     target_ulong page_size;
1181     int prot;
1182     int ret, is_user;
1183
1184     is_user = mmu_idx == MMU_USER_IDX;
1185     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1186                         &page_size);
1187     if (ret == 0) {
1188         /* Map a single [sub]page.  */
1189         phys_addr &= ~(uint32_t)0x3ff;
1190         address &= ~(uint32_t)0x3ff;
1191         tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
1192         return 0;
1193     }
1194
1195     if (access_type == 2) {
1196         env->cp15.c5_insn = ret;
1197         env->cp15.c6_insn = address;
1198         env->exception_index = EXCP_PREFETCH_ABORT;
1199     } else {
1200         env->cp15.c5_data = ret;
1201         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1202             env->cp15.c5_data |= (1 << 11);
1203         env->cp15.c6_data = address;
1204         env->exception_index = EXCP_DATA_ABORT;
1205     }
1206     return 1;
1207 }
1208
1209 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1210 {
1211     uint32_t phys_addr;
1212     target_ulong page_size;
1213     int prot;
1214     int ret;
1215
1216     ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
1217
1218     if (ret != 0)
1219         return -1;
1220
1221     return phys_addr;
1222 }
1223
1224 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1225 {
1226     int cp_num = (insn >> 8) & 0xf;
1227     int cp_info = (insn >> 5) & 7;
1228     int src = (insn >> 16) & 0xf;
1229     int operand = insn & 0xf;
1230
1231     if (env->cp[cp_num].cp_write)
1232         env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1233                                  cp_info, src, operand, val);
1234 }
1235
1236 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
1237 {
1238     int cp_num = (insn >> 8) & 0xf;
1239     int cp_info = (insn >> 5) & 7;
1240     int dest = (insn >> 16) & 0xf;
1241     int operand = insn & 0xf;
1242
1243     if (env->cp[cp_num].cp_read)
1244         return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1245                                        cp_info, dest, operand);
1246     return 0;
1247 }
1248
1249 /* Return basic MPU access permission bits.  */
1250 static uint32_t simple_mpu_ap_bits(uint32_t val)
1251 {
1252     uint32_t ret;
1253     uint32_t mask;
1254     int i;
1255     ret = 0;
1256     mask = 3;
1257     for (i = 0; i < 16; i += 2) {
1258         ret |= (val >> i) & mask;
1259         mask <<= 2;
1260     }
1261     return ret;
1262 }
1263
1264 /* Pad basic MPU access permission bits to extended format.  */
1265 static uint32_t extended_mpu_ap_bits(uint32_t val)
1266 {
1267     uint32_t ret;
1268     uint32_t mask;
1269     int i;
1270     ret = 0;
1271     mask = 3;
1272     for (i = 0; i < 16; i += 2) {
1273         ret |= (val & mask) << i;
1274         mask <<= 2;
1275     }
1276     return ret;
1277 }
1278
1279 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1280 {
1281     int op1;
1282     int op2;
1283     int crm;
1284
1285     op1 = (insn >> 21) & 7;
1286     op2 = (insn >> 5) & 7;
1287     crm = insn & 0xf;
1288     switch ((insn >> 16) & 0xf) {
1289     case 0:
1290         /* ID codes.  */
1291         if (arm_feature(env, ARM_FEATURE_XSCALE))
1292             break;
1293         if (arm_feature(env, ARM_FEATURE_OMAPCP))
1294             break;
1295         if (arm_feature(env, ARM_FEATURE_V7)
1296                 && op1 == 2 && crm == 0 && op2 == 0) {
1297             env->cp15.c0_cssel = val & 0xf;
1298             break;
1299         }
1300         goto bad_reg;
1301     case 1: /* System configuration.  */
1302         if (arm_feature(env, ARM_FEATURE_OMAPCP))
1303             op2 = 0;
1304         switch (op2) {
1305         case 0:
1306             if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1307                 env->cp15.c1_sys = val;
1308             /* ??? Lots of these bits are not implemented.  */
1309             /* This may enable/disable the MMU, so do a TLB flush.  */
1310             tlb_flush(env, 1);
1311             break;
1312         case 1: /* Auxiliary cotrol register.  */
1313             if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1314                 env->cp15.c1_xscaleauxcr = val;
1315                 break;
1316             }
1317             /* Not implemented.  */
1318             break;
1319         case 2:
1320             if (arm_feature(env, ARM_FEATURE_XSCALE))
1321                 goto bad_reg;
1322             if (env->cp15.c1_coproc != val) {
1323                 env->cp15.c1_coproc = val;
1324                 /* ??? Is this safe when called from within a TB?  */
1325                 tb_flush(env);
1326             }
1327             break;
1328         default:
1329             goto bad_reg;
1330         }
1331         break;
1332     case 2: /* MMU Page table control / MPU cache control.  */
1333         if (arm_feature(env, ARM_FEATURE_MPU)) {
1334             switch (op2) {
1335             case 0:
1336                 env->cp15.c2_data = val;
1337                 break;
1338             case 1:
1339                 env->cp15.c2_insn = val;
1340                 break;
1341             default:
1342                 goto bad_reg;
1343             }
1344         } else {
1345             switch (op2) {
1346             case 0:
1347                 env->cp15.c2_base0 = val;
1348                 break;
1349             case 1:
1350                 env->cp15.c2_base1 = val;
1351                 break;
1352             case 2:
1353                 val &= 7;
1354                 env->cp15.c2_control = val;
1355                 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1356                 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1357                 break;
1358             default:
1359                 goto bad_reg;
1360             }
1361         }
1362         break;
1363     case 3: /* MMU Domain access control / MPU write buffer control.  */
1364         env->cp15.c3 = val;
1365         tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1366         break;
1367     case 4: /* Reserved.  */
1368         goto bad_reg;
1369     case 5: /* MMU Fault status / MPU access permission.  */
1370         if (arm_feature(env, ARM_FEATURE_OMAPCP))
1371             op2 = 0;
1372         switch (op2) {
1373         case 0:
1374             if (arm_feature(env, ARM_FEATURE_MPU))
1375                 val = extended_mpu_ap_bits(val);
1376             env->cp15.c5_data = val;
1377             break;
1378         case 1:
1379             if (arm_feature(env, ARM_FEATURE_MPU))
1380                 val = extended_mpu_ap_bits(val);
1381             env->cp15.c5_insn = val;
1382             break;
1383         case 2:
1384             if (!arm_feature(env, ARM_FEATURE_MPU))
1385                 goto bad_reg;
1386             env->cp15.c5_data = val;
1387             break;
1388         case 3:
1389             if (!arm_feature(env, ARM_FEATURE_MPU))
1390                 goto bad_reg;
1391             env->cp15.c5_insn = val;
1392             break;
1393         default:
1394             goto bad_reg;
1395         }
1396         break;
1397     case 6: /* MMU Fault address / MPU base/size.  */
1398         if (arm_feature(env, ARM_FEATURE_MPU)) {
1399             if (crm >= 8)
1400                 goto bad_reg;
1401             env->cp15.c6_region[crm] = val;
1402         } else {
1403             if (arm_feature(env, ARM_FEATURE_OMAPCP))
1404                 op2 = 0;
1405             switch (op2) {
1406             case 0:
1407                 env->cp15.c6_data = val;
1408                 break;
1409             case 1: /* ??? This is WFAR on armv6 */
1410             case 2:
1411                 env->cp15.c6_insn = val;
1412                 break;
1413             default:
1414                 goto bad_reg;
1415             }
1416         }
1417         break;
1418     case 7: /* Cache control.  */
1419         env->cp15.c15_i_max = 0x000;
1420         env->cp15.c15_i_min = 0xff0;
1421         /* No cache, so nothing to do.  */
1422         /* ??? MPCore has VA to PA translation functions.  */
1423         break;
1424     case 8: /* MMU TLB control.  */
1425         switch (op2) {
1426         case 0: /* Invalidate all.  */
1427             tlb_flush(env, 0);
1428             break;
1429         case 1: /* Invalidate single TLB entry.  */
1430             tlb_flush_page(env, val & TARGET_PAGE_MASK);
1431             break;
1432         case 2: /* Invalidate on ASID.  */
1433             tlb_flush(env, val == 0);
1434             break;
1435         case 3: /* Invalidate single entry on MVA.  */
1436             /* ??? This is like case 1, but ignores ASID.  */
1437             tlb_flush(env, 1);
1438             break;
1439         default:
1440             goto bad_reg;
1441         }
1442         break;
1443     case 9:
1444         if (arm_feature(env, ARM_FEATURE_OMAPCP))
1445             break;
1446         switch (crm) {
1447         case 0: /* Cache lockdown.  */
1448             switch (op1) {
1449             case 0: /* L1 cache.  */
1450                 switch (op2) {
1451                 case 0:
1452                     env->cp15.c9_data = val;
1453                     break;
1454                 case 1:
1455                     env->cp15.c9_insn = val;
1456                     break;
1457                 default:
1458                     goto bad_reg;
1459                 }
1460                 break;
1461             case 1: /* L2 cache.  */
1462                 /* Ignore writes to L2 lockdown/auxiliary registers.  */
1463                 break;
1464             default:
1465                 goto bad_reg;
1466             }
1467             break;
1468         case 1: /* TCM memory region registers.  */
1469             /* Not implemented.  */
1470             goto bad_reg;
1471         default:
1472             goto bad_reg;
1473         }
1474         break;
1475     case 10: /* MMU TLB lockdown.  */
1476         /* ??? TLB lockdown not implemented.  */
1477         break;
1478     case 12: /* Reserved.  */
1479         goto bad_reg;
1480     case 13: /* Process ID.  */
1481         switch (op2) {
1482         case 0:
1483             /* Unlike real hardware the qemu TLB uses virtual addresses,
1484                not modified virtual addresses, so this causes a TLB flush.
1485              */
1486             if (env->cp15.c13_fcse != val)
1487               tlb_flush(env, 1);
1488             env->cp15.c13_fcse = val;
1489             break;
1490         case 1:
1491             /* This changes the ASID, so do a TLB flush.  */
1492             if (env->cp15.c13_context != val
1493                 && !arm_feature(env, ARM_FEATURE_MPU))
1494               tlb_flush(env, 0);
1495             env->cp15.c13_context = val;
1496             break;
1497         default:
1498             goto bad_reg;
1499         }
1500         break;
1501     case 14: /* Reserved.  */
1502         goto bad_reg;
1503     case 15: /* Implementation specific.  */
1504         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1505             if (op2 == 0 && crm == 1) {
1506                 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1507                     /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1508                     tb_flush(env);
1509                     env->cp15.c15_cpar = val & 0x3fff;
1510                 }
1511                 break;
1512             }
1513             goto bad_reg;
1514         }
1515         if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1516             switch (crm) {
1517             case 0:
1518                 break;
1519             case 1: /* Set TI925T configuration.  */
1520                 env->cp15.c15_ticonfig = val & 0xe7;
1521                 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1522                         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1523                 break;
1524             case 2: /* Set I_max.  */
1525                 env->cp15.c15_i_max = val;
1526                 break;
1527             case 3: /* Set I_min.  */
1528                 env->cp15.c15_i_min = val;
1529                 break;
1530             case 4: /* Set thread-ID.  */
1531                 env->cp15.c15_threadid = val & 0xffff;
1532                 break;
1533             case 8: /* Wait-for-interrupt (deprecated).  */
1534                 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1535                 break;
1536             default:
1537                 goto bad_reg;
1538             }
1539         }
1540         break;
1541     }
1542     return;
1543 bad_reg:
1544     /* ??? For debugging only.  Should raise illegal instruction exception.  */
1545     cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1546               (insn >> 16) & 0xf, crm, op1, op2);
1547 }
1548
1549 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1550 {
1551     int op1;
1552     int op2;
1553     int crm;
1554
1555     op1 = (insn >> 21) & 7;
1556     op2 = (insn >> 5) & 7;
1557     crm = insn & 0xf;
1558     switch ((insn >> 16) & 0xf) {
1559     case 0: /* ID codes.  */
1560         switch (op1) {
1561         case 0:
1562             switch (crm) {
1563             case 0:
1564                 switch (op2) {
1565                 case 0: /* Device ID.  */
1566                     return env->cp15.c0_cpuid;
1567                 case 1: /* Cache Type.  */
1568                     return env->cp15.c0_cachetype;
1569                 case 2: /* TCM status.  */
1570                     return 0;
1571                 case 3: /* TLB type register.  */
1572                     return 0; /* No lockable TLB entries.  */
1573                 case 5: /* CPU ID */
1574                     if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1575                         return env->cpu_index | 0x80000900;
1576                     } else {
1577                         return env->cpu_index;
1578                     }
1579                 default:
1580                     goto bad_reg;
1581                 }
1582             case 1:
1583                 if (!arm_feature(env, ARM_FEATURE_V6))
1584                     goto bad_reg;
1585                 return env->cp15.c0_c1[op2];
1586             case 2:
1587                 if (!arm_feature(env, ARM_FEATURE_V6))
1588                     goto bad_reg;
1589                 return env->cp15.c0_c2[op2];
1590             case 3: case 4: case 5: case 6: case 7:
1591                 return 0;
1592             default:
1593                 goto bad_reg;
1594             }
1595         case 1:
1596             /* These registers aren't documented on arm11 cores.  However
1597                Linux looks at them anyway.  */
1598             if (!arm_feature(env, ARM_FEATURE_V6))
1599                 goto bad_reg;
1600             if (crm != 0)
1601                 goto bad_reg;
1602             if (!arm_feature(env, ARM_FEATURE_V7))
1603                 return 0;
1604
1605             switch (op2) {
1606             case 0:
1607                 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1608             case 1:
1609                 return env->cp15.c0_clid;
1610             case 7:
1611                 return 0;
1612             }
1613             goto bad_reg;
1614         case 2:
1615             if (op2 != 0 || crm != 0)
1616                 goto bad_reg;
1617             return env->cp15.c0_cssel;
1618         default:
1619             goto bad_reg;
1620         }
1621     case 1: /* System configuration.  */
1622         if (arm_feature(env, ARM_FEATURE_OMAPCP))
1623             op2 = 0;
1624         switch (op2) {
1625         case 0: /* Control register.  */
1626             return env->cp15.c1_sys;
1627         case 1: /* Auxiliary control register.  */
1628             if (arm_feature(env, ARM_FEATURE_XSCALE))
1629                 return env->cp15.c1_xscaleauxcr;
1630             if (!arm_feature(env, ARM_FEATURE_AUXCR))
1631                 goto bad_reg;
1632             switch (ARM_CPUID(env)) {
1633             case ARM_CPUID_ARM1026:
1634                 return 1;
1635             case ARM_CPUID_ARM1136:
1636             case ARM_CPUID_ARM1136_R2:
1637                 return 7;
1638             case ARM_CPUID_ARM11MPCORE:
1639                 return 1;
1640             case ARM_CPUID_CORTEXA8:
1641                 return 2;
1642             case ARM_CPUID_CORTEXA9:
1643                 return 0;
1644             default:
1645                 goto bad_reg;
1646             }
1647         case 2: /* Coprocessor access register.  */
1648             if (arm_feature(env, ARM_FEATURE_XSCALE))
1649                 goto bad_reg;
1650             return env->cp15.c1_coproc;
1651         default:
1652             goto bad_reg;
1653         }
1654     case 2: /* MMU Page table control / MPU cache control.  */
1655         if (arm_feature(env, ARM_FEATURE_MPU)) {
1656             switch (op2) {
1657             case 0:
1658                 return env->cp15.c2_data;
1659                 break;
1660             case 1:
1661                 return env->cp15.c2_insn;
1662                 break;
1663             default:
1664                 goto bad_reg;
1665             }
1666         } else {
1667             switch (op2) {
1668             case 0:
1669                 return env->cp15.c2_base0;
1670             case 1:
1671                 return env->cp15.c2_base1;
1672             case 2:
1673                 return env->cp15.c2_control;
1674             default:
1675                 goto bad_reg;
1676             }
1677         }
1678     case 3: /* MMU Domain access control / MPU write buffer control.  */
1679         return env->cp15.c3;
1680     case 4: /* Reserved.  */
1681         goto bad_reg;
1682     case 5: /* MMU Fault status / MPU access permission.  */
1683         if (arm_feature(env, ARM_FEATURE_OMAPCP))
1684             op2 = 0;
1685         switch (op2) {
1686         case 0:
1687             if (arm_feature(env, ARM_FEATURE_MPU))
1688                 return simple_mpu_ap_bits(env->cp15.c5_data);
1689             return env->cp15.c5_data;
1690         case 1:
1691             if (arm_feature(env, ARM_FEATURE_MPU))
1692                 return simple_mpu_ap_bits(env->cp15.c5_data);
1693             return env->cp15.c5_insn;
1694         case 2:
1695             if (!arm_feature(env, ARM_FEATURE_MPU))
1696                 goto bad_reg;
1697             return env->cp15.c5_data;
1698         case 3:
1699             if (!arm_feature(env, ARM_FEATURE_MPU))
1700                 goto bad_reg;
1701             return env->cp15.c5_insn;
1702         default:
1703             goto bad_reg;
1704         }
1705     case 6: /* MMU Fault address.  */
1706         if (arm_feature(env, ARM_FEATURE_MPU)) {
1707             if (crm >= 8)
1708                 goto bad_reg;
1709             return env->cp15.c6_region[crm];
1710         } else {
1711             if (arm_feature(env, ARM_FEATURE_OMAPCP))
1712                 op2 = 0;
1713             switch (op2) {
1714             case 0:
1715                 return env->cp15.c6_data;
1716             case 1:
1717                 if (arm_feature(env, ARM_FEATURE_V6)) {
1718                     /* Watchpoint Fault Adrress.  */
1719                     return 0; /* Not implemented.  */
1720                 } else {
1721                     /* Instruction Fault Adrress.  */
1722                     /* Arm9 doesn't have an IFAR, but implementing it anyway
1723                        shouldn't do any harm.  */
1724                     return env->cp15.c6_insn;
1725                 }
1726             case 2:
1727                 if (arm_feature(env, ARM_FEATURE_V6)) {
1728                     /* Instruction Fault Adrress.  */
1729                     return env->cp15.c6_insn;
1730                 } else {
1731                     goto bad_reg;
1732                 }
1733             default:
1734                 goto bad_reg;
1735             }
1736         }
1737     case 7: /* Cache control.  */
1738         /* FIXME: Should only clear Z flag if destination is r15.  */
1739         env->ZF = 0;
1740         return 0;
1741     case 8: /* MMU TLB control.  */
1742         goto bad_reg;
1743     case 9: /* Cache lockdown.  */
1744         switch (op1) {
1745         case 0: /* L1 cache.  */
1746             if (arm_feature(env, ARM_FEATURE_OMAPCP))
1747                 return 0;
1748             switch (op2) {
1749             case 0:
1750                 return env->cp15.c9_data;
1751             case 1:
1752                 return env->cp15.c9_insn;
1753             default:
1754                 goto bad_reg;
1755             }
1756         case 1: /* L2 cache */
1757             if (crm != 0)
1758                 goto bad_reg;
1759             /* L2 Lockdown and Auxiliary control.  */
1760             return 0;
1761         default:
1762             goto bad_reg;
1763         }
1764     case 10: /* MMU TLB lockdown.  */
1765         /* ??? TLB lockdown not implemented.  */
1766         return 0;
1767     case 11: /* TCM DMA control.  */
1768     case 12: /* Reserved.  */
1769         goto bad_reg;
1770     case 13: /* Process ID.  */
1771         switch (op2) {
1772         case 0:
1773             return env->cp15.c13_fcse;
1774         case 1:
1775             return env->cp15.c13_context;
1776         default:
1777             goto bad_reg;
1778         }
1779     case 14: /* Reserved.  */
1780         goto bad_reg;
1781     case 15: /* Implementation specific.  */
1782         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1783             if (op2 == 0 && crm == 1)
1784                 return env->cp15.c15_cpar;
1785
1786             goto bad_reg;
1787         }
1788         if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1789             switch (crm) {
1790             case 0:
1791                 return 0;
1792             case 1: /* Read TI925T configuration.  */
1793                 return env->cp15.c15_ticonfig;
1794             case 2: /* Read I_max.  */
1795                 return env->cp15.c15_i_max;
1796             case 3: /* Read I_min.  */
1797                 return env->cp15.c15_i_min;
1798             case 4: /* Read thread-ID.  */
1799                 return env->cp15.c15_threadid;
1800             case 8: /* TI925T_status */
1801                 return 0;
1802             }
1803             /* TODO: Peripheral port remap register:
1804              * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1805              * controller base address at $rn & ~0xfff and map size of
1806              * 0x200 << ($rn & 0xfff), when MMU is off.  */
1807             goto bad_reg;
1808         }
1809         return 0;
1810     }
1811 bad_reg:
1812     /* ??? For debugging only.  Should raise illegal instruction exception.  */
1813     cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1814               (insn >> 16) & 0xf, crm, op1, op2);
1815     return 0;
1816 }
1817
1818 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
1819 {
1820     env->banked_r13[bank_number(mode)] = val;
1821 }
1822
1823 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
1824 {
1825     return env->banked_r13[bank_number(mode)];
1826 }
1827
1828 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
1829 {
1830     switch (reg) {
1831     case 0: /* APSR */
1832         return xpsr_read(env) & 0xf8000000;
1833     case 1: /* IAPSR */
1834         return xpsr_read(env) & 0xf80001ff;
1835     case 2: /* EAPSR */
1836         return xpsr_read(env) & 0xff00fc00;
1837     case 3: /* xPSR */
1838         return xpsr_read(env) & 0xff00fdff;
1839     case 5: /* IPSR */
1840         return xpsr_read(env) & 0x000001ff;
1841     case 6: /* EPSR */
1842         return xpsr_read(env) & 0x0700fc00;
1843     case 7: /* IEPSR */
1844         return xpsr_read(env) & 0x0700edff;
1845     case 8: /* MSP */
1846         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1847     case 9: /* PSP */
1848         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1849     case 16: /* PRIMASK */
1850         return (env->uncached_cpsr & CPSR_I) != 0;
1851     case 17: /* FAULTMASK */
1852         return (env->uncached_cpsr & CPSR_F) != 0;
1853     case 18: /* BASEPRI */
1854     case 19: /* BASEPRI_MAX */
1855         return env->v7m.basepri;
1856     case 20: /* CONTROL */
1857         return env->v7m.control;
1858     default:
1859         /* ??? For debugging only.  */
1860         cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1861         return 0;
1862     }
1863 }
1864
1865 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
1866 {
1867     switch (reg) {
1868     case 0: /* APSR */
1869         xpsr_write(env, val, 0xf8000000);
1870         break;
1871     case 1: /* IAPSR */
1872         xpsr_write(env, val, 0xf8000000);
1873         break;
1874     case 2: /* EAPSR */
1875         xpsr_write(env, val, 0xfe00fc00);
1876         break;
1877     case 3: /* xPSR */
1878         xpsr_write(env, val, 0xfe00fc00);
1879         break;
1880     case 5: /* IPSR */
1881         /* IPSR bits are readonly.  */
1882         break;
1883     case 6: /* EPSR */
1884         xpsr_write(env, val, 0x0600fc00);
1885         break;
1886     case 7: /* IEPSR */
1887         xpsr_write(env, val, 0x0600fc00);
1888         break;
1889     case 8: /* MSP */
1890         if (env->v7m.current_sp)
1891             env->v7m.other_sp = val;
1892         else
1893             env->regs[13] = val;
1894         break;
1895     case 9: /* PSP */
1896         if (env->v7m.current_sp)
1897             env->regs[13] = val;
1898         else
1899             env->v7m.other_sp = val;
1900         break;
1901     case 16: /* PRIMASK */
1902         if (val & 1)
1903             env->uncached_cpsr |= CPSR_I;
1904         else
1905             env->uncached_cpsr &= ~CPSR_I;
1906         break;
1907     case 17: /* FAULTMASK */
1908         if (val & 1)
1909             env->uncached_cpsr |= CPSR_F;
1910         else
1911             env->uncached_cpsr &= ~CPSR_F;
1912         break;
1913     case 18: /* BASEPRI */
1914         env->v7m.basepri = val & 0xff;
1915         break;
1916     case 19: /* BASEPRI_MAX */
1917         val &= 0xff;
1918         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1919             env->v7m.basepri = val;
1920         break;
1921     case 20: /* CONTROL */
1922         env->v7m.control = val & 3;
1923         switch_v7m_sp(env, (val & 2) != 0);
1924         break;
1925     default:
1926         /* ??? For debugging only.  */
1927         cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1928         return;
1929     }
1930 }
1931
1932 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1933                 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1934                 void *opaque)
1935 {
1936     if (cpnum < 0 || cpnum > 14) {
1937         cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1938         return;
1939     }
1940
1941     env->cp[cpnum].cp_read = cp_read;
1942     env->cp[cpnum].cp_write = cp_write;
1943     env->cp[cpnum].opaque = opaque;
1944 }
1945
1946 #endif
1947
1948 /* Note that signed overflow is undefined in C.  The following routines are
1949    careful to use unsigned types where modulo arithmetic is required.
1950    Failure to do so _will_ break on newer gcc.  */
1951
1952 /* Signed saturating arithmetic.  */
1953
1954 /* Perform 16-bit signed saturating addition.  */
1955 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
1956 {
1957     uint16_t res;
1958
1959     res = a + b;
1960     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
1961         if (a & 0x8000)
1962             res = 0x8000;
1963         else
1964             res = 0x7fff;
1965     }
1966     return res;
1967 }
1968
1969 /* Perform 8-bit signed saturating addition.  */
1970 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
1971 {
1972     uint8_t res;
1973
1974     res = a + b;
1975     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
1976         if (a & 0x80)
1977             res = 0x80;
1978         else
1979             res = 0x7f;
1980     }
1981     return res;
1982 }
1983
1984 /* Perform 16-bit signed saturating subtraction.  */
1985 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
1986 {
1987     uint16_t res;
1988
1989     res = a - b;
1990     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
1991         if (a & 0x8000)
1992             res = 0x8000;
1993         else
1994             res = 0x7fff;
1995     }
1996     return res;
1997 }
1998
1999 /* Perform 8-bit signed saturating subtraction.  */
2000 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2001 {
2002     uint8_t res;
2003
2004     res = a - b;
2005     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2006         if (a & 0x80)
2007             res = 0x80;
2008         else
2009             res = 0x7f;
2010     }
2011     return res;
2012 }
2013
2014 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2015 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2016 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
2017 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
2018 #define PFX q
2019
2020 #include "op_addsub.h"
2021
2022 /* Unsigned saturating arithmetic.  */
2023 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2024 {
2025     uint16_t res;
2026     res = a + b;
2027     if (res < a)
2028         res = 0xffff;
2029     return res;
2030 }
2031
2032 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2033 {
2034     if (a < b)
2035         return a - b;
2036     else
2037         return 0;
2038 }
2039
2040 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2041 {
2042     uint8_t res;
2043     res = a + b;
2044     if (res < a)
2045         res = 0xff;
2046     return res;
2047 }
2048
2049 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2050 {
2051     if (a < b)
2052         return a - b;
2053     else
2054         return 0;
2055 }
2056
2057 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2058 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2059 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
2060 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
2061 #define PFX uq
2062
2063 #include "op_addsub.h"
2064
2065 /* Signed modulo arithmetic.  */
2066 #define SARITH16(a, b, n, op) do { \
2067     int32_t sum; \
2068     sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2069     RESULT(sum, n, 16); \
2070     if (sum >= 0) \
2071         ge |= 3 << (n * 2); \
2072     } while(0)
2073
2074 #define SARITH8(a, b, n, op) do { \
2075     int32_t sum; \
2076     sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2077     RESULT(sum, n, 8); \
2078     if (sum >= 0) \
2079         ge |= 1 << n; \
2080     } while(0)
2081
2082
2083 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2084 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2085 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
2086 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
2087 #define PFX s
2088 #define ARITH_GE
2089
2090 #include "op_addsub.h"
2091
2092 /* Unsigned modulo arithmetic.  */
2093 #define ADD16(a, b, n) do { \
2094     uint32_t sum; \
2095     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2096     RESULT(sum, n, 16); \
2097     if ((sum >> 16) == 1) \
2098         ge |= 3 << (n * 2); \
2099     } while(0)
2100
2101 #define ADD8(a, b, n) do { \
2102     uint32_t sum; \
2103     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2104     RESULT(sum, n, 8); \
2105     if ((sum >> 8) == 1) \
2106         ge |= 1 << n; \
2107     } while(0)
2108
2109 #define SUB16(a, b, n) do { \
2110     uint32_t sum; \
2111     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2112     RESULT(sum, n, 16); \
2113     if ((sum >> 16) == 0) \
2114         ge |= 3 << (n * 2); \
2115     } while(0)
2116
2117 #define SUB8(a, b, n) do { \
2118     uint32_t sum; \
2119     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2120     RESULT(sum, n, 8); \
2121     if ((sum >> 8) == 0) \
2122         ge |= 1 << n; \
2123     } while(0)
2124
2125 #define PFX u
2126 #define ARITH_GE
2127
2128 #include "op_addsub.h"
2129
2130 /* Halved signed arithmetic.  */
2131 #define ADD16(a, b, n) \
2132   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2133 #define SUB16(a, b, n) \
2134   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2135 #define ADD8(a, b, n) \
2136   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2137 #define SUB8(a, b, n) \
2138   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2139 #define PFX sh
2140
2141 #include "op_addsub.h"
2142
2143 /* Halved unsigned arithmetic.  */
2144 #define ADD16(a, b, n) \
2145   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2146 #define SUB16(a, b, n) \
2147   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2148 #define ADD8(a, b, n) \
2149   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2150 #define SUB8(a, b, n) \
2151   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2152 #define PFX uh
2153
2154 #include "op_addsub.h"
2155
2156 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2157 {
2158     if (a > b)
2159         return a - b;
2160     else
2161         return b - a;
2162 }
2163
2164 /* Unsigned sum of absolute byte differences.  */
2165 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2166 {
2167     uint32_t sum;
2168     sum = do_usad(a, b);
2169     sum += do_usad(a >> 8, b >> 8);
2170     sum += do_usad(a >> 16, b >>16);
2171     sum += do_usad(a >> 24, b >> 24);
2172     return sum;
2173 }
2174
2175 /* For ARMv6 SEL instruction.  */
2176 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2177 {
2178     uint32_t mask;
2179
2180     mask = 0;
2181     if (flags & 1)
2182         mask |= 0xff;
2183     if (flags & 2)
2184         mask |= 0xff00;
2185     if (flags & 4)
2186         mask |= 0xff0000;
2187     if (flags & 8)
2188         mask |= 0xff000000;
2189     return (a & mask) | (b & ~mask);
2190 }
2191
2192 uint32_t HELPER(logicq_cc)(uint64_t val)
2193 {
2194     return (val >> 32) | (val != 0);
2195 }
2196
2197 /* VFP support.  We follow the convention used for VFP instrunctions:
2198    Single precition routines have a "s" suffix, double precision a
2199    "d" suffix.  */
2200
2201 /* Convert host exception flags to vfp form.  */
2202 static inline int vfp_exceptbits_from_host(int host_bits)
2203 {
2204     int target_bits = 0;
2205
2206     if (host_bits & float_flag_invalid)
2207         target_bits |= 1;
2208     if (host_bits & float_flag_divbyzero)
2209         target_bits |= 2;
2210     if (host_bits & float_flag_overflow)
2211         target_bits |= 4;
2212     if (host_bits & float_flag_underflow)
2213         target_bits |= 8;
2214     if (host_bits & float_flag_inexact)
2215         target_bits |= 0x10;
2216     return target_bits;
2217 }
2218
2219 uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2220 {
2221     int i;
2222     uint32_t fpscr;
2223
2224     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2225             | (env->vfp.vec_len << 16)
2226             | (env->vfp.vec_stride << 20);
2227     i = get_float_exception_flags(&env->vfp.fp_status);
2228     fpscr |= vfp_exceptbits_from_host(i);
2229     return fpscr;
2230 }
2231
2232 /* Convert vfp exception flags to target form.  */
2233 static inline int vfp_exceptbits_to_host(int target_bits)
2234 {
2235     int host_bits = 0;
2236
2237     if (target_bits & 1)
2238         host_bits |= float_flag_invalid;
2239     if (target_bits & 2)
2240         host_bits |= float_flag_divbyzero;
2241     if (target_bits & 4)
2242         host_bits |= float_flag_overflow;
2243     if (target_bits & 8)
2244         host_bits |= float_flag_underflow;
2245     if (target_bits & 0x10)
2246         host_bits |= float_flag_inexact;
2247     return host_bits;
2248 }
2249
2250 void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2251 {
2252     int i;
2253     uint32_t changed;
2254
2255     changed = env->vfp.xregs[ARM_VFP_FPSCR];
2256     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2257     env->vfp.vec_len = (val >> 16) & 7;
2258     env->vfp.vec_stride = (val >> 20) & 3;
2259
2260     changed ^= val;
2261     if (changed & (3 << 22)) {
2262         i = (val >> 22) & 3;
2263         switch (i) {
2264         case 0:
2265             i = float_round_nearest_even;
2266             break;
2267         case 1:
2268             i = float_round_up;
2269             break;
2270         case 2:
2271             i = float_round_down;
2272             break;
2273         case 3:
2274             i = float_round_to_zero;
2275             break;
2276         }
2277         set_float_rounding_mode(i, &env->vfp.fp_status);
2278     }
2279     if (changed & (1 << 24))
2280         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2281     if (changed & (1 << 25))
2282         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2283
2284     i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2285     set_float_exception_flags(i, &env->vfp.fp_status);
2286 }
2287
2288 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2289
2290 #define VFP_BINOP(name) \
2291 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2292 { \
2293     return float32_ ## name (a, b, &env->vfp.fp_status); \
2294 } \
2295 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2296 { \
2297     return float64_ ## name (a, b, &env->vfp.fp_status); \
2298 }
2299 VFP_BINOP(add)
2300 VFP_BINOP(sub)
2301 VFP_BINOP(mul)
2302 VFP_BINOP(div)
2303 #undef VFP_BINOP
2304
2305 float32 VFP_HELPER(neg, s)(float32 a)
2306 {
2307     return float32_chs(a);
2308 }
2309
2310 float64 VFP_HELPER(neg, d)(float64 a)
2311 {
2312     return float64_chs(a);
2313 }
2314
2315 float32 VFP_HELPER(abs, s)(float32 a)
2316 {
2317     return float32_abs(a);
2318 }
2319
2320 float64 VFP_HELPER(abs, d)(float64 a)
2321 {
2322     return float64_abs(a);
2323 }
2324
2325 float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2326 {
2327     return float32_sqrt(a, &env->vfp.fp_status);
2328 }
2329
2330 float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2331 {
2332     return float64_sqrt(a, &env->vfp.fp_status);
2333 }
2334
2335 /* XXX: check quiet/signaling case */
2336 #define DO_VFP_cmp(p, type) \
2337 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env)  \
2338 { \
2339     uint32_t flags; \
2340     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2341     case 0: flags = 0x6; break; \
2342     case -1: flags = 0x8; break; \
2343     case 1: flags = 0x2; break; \
2344     default: case 2: flags = 0x3; break; \
2345     } \
2346     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2347         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2348 } \
2349 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2350 { \
2351     uint32_t flags; \
2352     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2353     case 0: flags = 0x6; break; \
2354     case -1: flags = 0x8; break; \
2355     case 1: flags = 0x2; break; \
2356     default: case 2: flags = 0x3; break; \
2357     } \
2358     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2359         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2360 }
2361 DO_VFP_cmp(s, float32)
2362 DO_VFP_cmp(d, float64)
2363 #undef DO_VFP_cmp
2364
2365 /* Helper routines to perform bitwise copies between float and int.  */
2366 static inline float32 vfp_itos(uint32_t i)
2367 {
2368     union {
2369         uint32_t i;
2370         float32 s;
2371     } v;
2372
2373     v.i = i;
2374     return v.s;
2375 }
2376
2377 static inline uint32_t vfp_stoi(float32 s)
2378 {
2379     union {
2380         uint32_t i;
2381         float32 s;
2382     } v;
2383
2384     v.s = s;
2385     return v.i;
2386 }
2387
2388 static inline float64 vfp_itod(uint64_t i)
2389 {
2390     union {
2391         uint64_t i;
2392         float64 d;
2393     } v;
2394
2395     v.i = i;
2396     return v.d;
2397 }
2398
2399 static inline uint64_t vfp_dtoi(float64 d)
2400 {
2401     union {
2402         uint64_t i;
2403         float64 d;
2404     } v;
2405
2406     v.d = d;
2407     return v.i;
2408 }
2409
2410 /* Integer to float conversion.  */
2411 float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2412 {
2413     return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2414 }
2415
2416 float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2417 {
2418     return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2419 }
2420
2421 float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2422 {
2423     return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2424 }
2425
2426 float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2427 {
2428     return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2429 }
2430
2431 /* Float to integer conversion.  */
2432 float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2433 {
2434     return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2435 }
2436
2437 float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2438 {
2439     return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2440 }
2441
2442 float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2443 {
2444     return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2445 }
2446
2447 float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2448 {
2449     return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2450 }
2451
2452 float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2453 {
2454     return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2455 }
2456
2457 float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2458 {
2459     return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2460 }
2461
2462 float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2463 {
2464     return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2465 }
2466
2467 float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2468 {
2469     return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2470 }
2471
2472 /* floating point conversion */
2473 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2474 {
2475     return float32_to_float64(x, &env->vfp.fp_status);
2476 }
2477
2478 float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2479 {
2480     return float64_to_float32(x, &env->vfp.fp_status);
2481 }
2482
2483 /* VFP3 fixed point conversion.  */
2484 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2485 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2486 { \
2487     ftype tmp; \
2488     tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2489                                   &env->vfp.fp_status); \
2490     return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2491 } \
2492 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2493 { \
2494     ftype tmp; \
2495     tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2496     return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2497         &env->vfp.fp_status)); \
2498 }
2499
2500 VFP_CONV_FIX(sh, d, float64, int16, )
2501 VFP_CONV_FIX(sl, d, float64, int32, )
2502 VFP_CONV_FIX(uh, d, float64, uint16, u)
2503 VFP_CONV_FIX(ul, d, float64, uint32, u)
2504 VFP_CONV_FIX(sh, s, float32, int16, )
2505 VFP_CONV_FIX(sl, s, float32, int32, )
2506 VFP_CONV_FIX(uh, s, float32, uint16, u)
2507 VFP_CONV_FIX(ul, s, float32, uint32, u)
2508 #undef VFP_CONV_FIX
2509
2510 /* Half precision conversions.  */
2511 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2512 {
2513     float_status *s = &env->vfp.fp_status;
2514     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2515     return float16_to_float32(a, ieee, s);
2516 }
2517
2518 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2519 {
2520     float_status *s = &env->vfp.fp_status;
2521     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2522     return float32_to_float16(a, ieee, s);
2523 }
2524
2525 float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2526 {
2527     float_status *s = &env->vfp.fp_status;
2528     float32 two = int32_to_float32(2, s);
2529     return float32_sub(two, float32_mul(a, b, s), s);
2530 }
2531
2532 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2533 {
2534     float_status *s = &env->vfp.fp_status;
2535     float32 three = int32_to_float32(3, s);
2536     return float32_sub(three, float32_mul(a, b, s), s);
2537 }
2538
2539 /* NEON helpers.  */
2540
2541 /* TODO: The architecture specifies the value that the estimate functions
2542    should return.  We return the exact reciprocal/root instead.  */
2543 float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2544 {
2545     float_status *s = &env->vfp.fp_status;
2546     float32 one = int32_to_float32(1, s);
2547     return float32_div(one, a, s);
2548 }
2549
2550 float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2551 {
2552     float_status *s = &env->vfp.fp_status;
2553     float32 one = int32_to_float32(1, s);
2554     return float32_div(one, float32_sqrt(a, s), s);
2555 }
2556
2557 uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2558 {
2559     float_status *s = &env->vfp.fp_status;
2560     float32 tmp;
2561     tmp = int32_to_float32(a, s);
2562     tmp = float32_scalbn(tmp, -32, s);
2563     tmp = helper_recpe_f32(tmp, env);
2564     tmp = float32_scalbn(tmp, 31, s);
2565     return float32_to_int32(tmp, s);
2566 }
2567
2568 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2569 {
2570     float_status *s = &env->vfp.fp_status;
2571     float32 tmp;
2572     tmp = int32_to_float32(a, s);
2573     tmp = float32_scalbn(tmp, -32, s);
2574     tmp = helper_rsqrte_f32(tmp, env);
2575     tmp = float32_scalbn(tmp, 31, s);
2576     return float32_to_int32(tmp, s);
2577 }
2578
2579 void HELPER(set_teecr)(CPUState *env, uint32_t val)
2580 {
2581     val &= 1;
2582     if (env->teecr != val) {
2583         env->teecr = val;
2584         tb_flush(env);
2585     }
2586 }