hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "boards.h"
  36 #include "fw_cfg.h"
  37 #include "escc.h"
  38 #include "ide.h"
  39 #include "loader.h"
  40 #include "elf.h"
  41
  42 #define MAX_IDE_BUS 2
  43 #define VGA_BIOS_SIZE 65536
  44 #define CFG_ADDR 0xf0000510
  45
  46 /* temporary frame buffer OSI calls for the video.x driver. The right
  47    solution is to modify the driver to use VGA PCI I/Os */
  48 /* XXX: to be removed. This is no way related to emulation */
  49 static int vga_osi_call (CPUState *env)
  50 {
  51     static int vga_vbl_enabled;
  52     int linesize;
  53
  54 #if 0
  55     printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
  56 #endif
  57
  58     /* same handler as PearPC, coming from the original MOL video
  59        driver. */
  60     switch(env->gpr[5]) {
  61     case 4:
  62         break;
  63     case 28: /* set_vmode */
  64         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  65             env->gpr[3] = 1;
  66         else
  67             env->gpr[3] = 0;
  68         break;
  69     case 29: /* get_vmode_info */
  70         if (env->gpr[6] != 0) {
  71             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  72                 env->gpr[3] = 1;
  73                 break;
  74             }
  75         }
  76         env->gpr[3] = 0;
  77         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  78         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  79         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  80         env->gpr[7] = 85 << 16; /* refresh rate */
  81         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  82         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  83         linesize = (linesize + 3) & ~3;
  84         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  85         break;
  86     case 31: /* set_video power */
  87         env->gpr[3] = 0;
  88         break;
  89     case 39: /* video_ctrl */
  90         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  91             vga_vbl_enabled = env->gpr[6];
  92         env->gpr[3] = 0;
  93         break;
  94     case 47:
  95         break;
  96     case 59: /* set_color */
  97         /* R6 = index, R7 = RGB */
  98         env->gpr[3] = 0;
  99         break;
 100     case 64: /* get color */
 101         /* R6 = index */
 102         env->gpr[3] = 0;
 103         break;
 104     case 116: /* set hwcursor */
 105         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 106         break;
 107     default:
 108         fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
 109                 ppc_dump_gpr(env, 5));
 110         break;
 111     }
 112
 113     return 1; /* osi_call handled */
 114 }
 115
 116 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 117 {
 118     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 119     return 0;
 120 }
 121
 122 static void ppc_heathrow_init (ram_addr_t ram_size,
 123                                const char *boot_device,
 124                                const char *kernel_filename,
 125                                const char *kernel_cmdline,
 126                                const char *initrd_filename,
 127                                const char *cpu_model)
 128 {
 129     CPUState *env = NULL, *envs[MAX_CPUS];
 130     char *filename;
 131     qemu_irq *pic, **heathrow_irqs;
 132     int linux_boot, i;
 133     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 134     uint32_t kernel_base, initrd_base;
 135     int32_t kernel_size, initrd_size;
 136     PCIBus *pci_bus;
 137     MacIONVRAMState *nvr;
 138     int vga_bios_size, bios_size;
 139     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 140     int escc_mem_index, ide_mem_index[2];
 141     uint16_t ppc_boot_device;
 142     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 143     void *fw_cfg;
 144     void *dbdma;
 145     uint8_t *vga_bios_ptr;
 146
 147     linux_boot = (kernel_filename != NULL);
 148
 149     /* init CPUs */
 150     if (cpu_model == NULL)
 151         cpu_model = "G3";
 152     for (i = 0; i < smp_cpus; i++) {
 153         env = cpu_init(cpu_model);
 154         if (!env) {
 155             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 156             exit(1);
 157         }
 158         /* Set time-base frequency to 16.6 Mhz */
 159         cpu_ppc_tb_init(env,  16600000UL);
 160         env->osi_call = vga_osi_call;
 161         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 162         envs[i] = env;
 163     }
 164
 165     /* allocate RAM */
 166     if (ram_size > (2047 << 20)) {
 167         fprintf(stderr,
 168                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 169                 ((unsigned int)ram_size / (1 << 20)));
 170         exit(1);
 171     }
 172
 173     ram_offset = qemu_ram_alloc(ram_size);
 174     cpu_register_physical_memory(0, ram_size, ram_offset);
 175
 176     /* allocate and load BIOS */
 177     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 178     if (bios_name == NULL)
 179         bios_name = PROM_FILENAME;
 180     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 181     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 182
 183     /* Load OpenBIOS (ELF) */
 184     if (filename) {
 185         bios_size = load_elf(filename, 0, NULL, NULL, NULL,
 186                                1, ELF_MACHINE, 0);
 187         qemu_free(filename);
 188     } else {
 189         bios_size = -1;
 190     }
 191     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 192         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 193         exit(1);
 194     }
 195
 196     /* allocate and load VGA BIOS */
 197     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 198     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 199     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 200     if (filename) {
 201         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 202         qemu_free(filename);
 203     } else {
 204         vga_bios_size = -1;
 205     }
 206     if (vga_bios_size < 0) {
 207         /* if no bios is present, we can still work */
 208         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 209                 VGABIOS_FILENAME);
 210         vga_bios_size = 0;
 211     } else {
 212         /* set a specific header (XXX: find real Apple format for NDRV
 213            drivers) */
 214         vga_bios_ptr[0] = 'N';
 215         vga_bios_ptr[1] = 'D';
 216         vga_bios_ptr[2] = 'R';
 217         vga_bios_ptr[3] = 'V';
 218         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 219         vga_bios_size += 8;
 220
 221         /* Round to page boundary */
 222         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 223             TARGET_PAGE_MASK;
 224     }
 225
 226     if (linux_boot) {
 227         uint64_t lowaddr = 0;
 228         int bswap_needed;
 229
 230 #ifdef BSWAP_NEEDED
 231         bswap_needed = 1;
 232 #else
 233         bswap_needed = 0;
 234 #endif
 235         kernel_base = KERNEL_LOAD_ADDR;
 236         /* Now we can load the kernel. The first step tries to load the kernel
 237            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 238            loaded again, the new PhysAddr being computed from lowaddr. */
 239         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL,
 240                                1, ELF_MACHINE, 0);
 241         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 242             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 243                                    NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 244         }
 245         if (kernel_size < 0)
 246             kernel_size = load_aout(kernel_filename, kernel_base,
 247                                     ram_size - kernel_base, bswap_needed,
 248                                     TARGET_PAGE_SIZE);
 249         if (kernel_size < 0)
 250             kernel_size = load_image_targphys(kernel_filename,
 251                                               kernel_base,
 252                                               ram_size - kernel_base);
 253         if (kernel_size < 0) {
 254             hw_error("qemu: could not load kernel '%s'\n",
 255                       kernel_filename);
 256             exit(1);
 257         }
 258         /* load initrd */
 259         if (initrd_filename) {
 260             initrd_base = INITRD_LOAD_ADDR;
 261             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 262                                               ram_size - initrd_base);
 263             if (initrd_size < 0) {
 264                 hw_error("qemu: could not load initial ram disk '%s'\n",
 265                          initrd_filename);
 266                 exit(1);
 267             }
 268         } else {
 269             initrd_base = 0;
 270             initrd_size = 0;
 271         }
 272         ppc_boot_device = 'm';
 273     } else {
 274         kernel_base = 0;
 275         kernel_size = 0;
 276         initrd_base = 0;
 277         initrd_size = 0;
 278         ppc_boot_device = '\0';
 279         for (i = 0; boot_device[i] != '\0'; i++) {
 280             /* TOFIX: for now, the second IDE channel is not properly
 281              *        used by OHW. The Mac floppy disk are not emulated.
 282              *        For now, OHW cannot boot from the network.
 283              */
 284 #if 0
 285             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 286                 ppc_boot_device = boot_device[i];
 287                 break;
 288             }
 289 #else
 290             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 291                 ppc_boot_device = boot_device[i];
 292                 break;
 293             }
 294 #endif
 295         }
 296         if (ppc_boot_device == '\0') {
 297             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 298             exit(1);
 299         }
 300     }
 301
 302     isa_mem_base = 0x80000000;
 303
 304     /* Register 2 MB of ISA IO space */
 305     isa_mmio_init(0xfe000000, 0x00200000);
 306
 307     /* XXX: we register only 1 output pin for heathrow PIC */
 308     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 309     heathrow_irqs[0] =
 310         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 311     /* Connect the heathrow PIC outputs to the 6xx bus */
 312     for (i = 0; i < smp_cpus; i++) {
 313         switch (PPC_INPUT(env)) {
 314         case PPC_FLAGS_INPUT_6xx:
 315             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 316             heathrow_irqs[i][0] =
 317                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 318             break;
 319         default:
 320             hw_error("Bus model not supported on OldWorld Mac machine\n");
 321         }
 322     }
 323
 324     /* init basic PC hardware */
 325     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 326         hw_error("Only 6xx bus is supported on heathrow machine\n");
 327     }
 328     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 329     pci_bus = pci_grackle_init(0xfec00000, pic);
 330     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 331
 332     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 333                                serial_hds[1], ESCC_CLOCK, 4);
 334
 335     for(i = 0; i < nb_nics; i++)
 336         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 337
 338
 339     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 340         fprintf(stderr, "qemu: too many IDE bus\n");
 341         exit(1);
 342     }
 343
 344     /* First IDE channel is a MAC IDE on the MacIO bus */
 345     hd[0] = drive_get(IF_IDE, 0, 0);
 346     hd[1] = drive_get(IF_IDE, 0, 1);
 347     dbdma = DBDMA_init(&dbdma_mem_index);
 348     ide_mem_index[0] = -1;
 349     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 350
 351     /* Second IDE channel is a CMD646 on the PCI bus */
 352     hd[0] = drive_get(IF_IDE, 1, 0);
 353     hd[1] = drive_get(IF_IDE, 1, 1);
 354     hd[3] = hd[2] = NULL;
 355     pci_cmd646_ide_init(pci_bus, hd, 0);
 356
 357     /* cuda also initialize ADB */
 358     cuda_init(&cuda_mem_index, pic[0x12]);
 359
 360     adb_kbd_init(&adb_bus);
 361     adb_mouse_init(&adb_bus);
 362
 363     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 364     pmac_format_nvram_partition(nvr, 0x2000);
 365
 366     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 367                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 368                escc_mem_index);
 369
 370     if (usb_enabled) {
 371         usb_ohci_init_pci(pci_bus, -1);
 372     }
 373
 374     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 375         graphic_depth = 15;
 376
 377     /* No PCI init: the BIOS will do it */
 378
 379     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 380     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 381     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 382     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 383     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 384     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 385     if (kernel_cmdline) {
 386         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 387         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 388     } else {
 389         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 390     }
 391     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 392     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 393     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 394
 395     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 396     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 397     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 398
 399     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 400 }
 401
 402 static QEMUMachine heathrow_machine = {
 403     .name = "g3beige",
 404     .desc = "Heathrow based PowerMAC",
 405     .init = ppc_heathrow_init,
 406     .max_cpus = MAX_CPUS,
 407     .is_default = 1,
 408 };
 409
 410 static void heathrow_machine_init(void)
 411 {
 412     qemu_register_machine(&heathrow_machine);
 413 }
 414
 415 machine_init(heathrow_machine_init);