hw/grackle_pci.c

   1 /*
   2  * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
   3  *
   4  * Copyright (c) 2006-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "sysbus.h"
  27 #include "ppc_mac.h"
  28 #include "pci.h"
  29 #include "pci_host.h"
  30
  31 /* debug Grackle */
  32 //#define DEBUG_GRACKLE
  33
  34 #ifdef DEBUG_GRACKLE
  35 #define GRACKLE_DPRINTF(fmt, ...)                               \
  36     do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0)
  37 #else
  38 #define GRACKLE_DPRINTF(fmt, ...)
  39 #endif
  40
  41 typedef struct GrackleState {
  42     SysBusDevice busdev;
  43     PCIHostState host_state;
  44 } GrackleState;
  45
  46 /* Don't know if this matches real hardware, but it agrees with OHW.  */
  47 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
  48 {
  49     return (irq_num + (pci_dev->devfn >> 3)) & 3;
  50 }
  51
  52 static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
  53 {
  54     qemu_irq *pic = opaque;
  55
  56     GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
  57     qemu_set_irq(pic[irq_num + 0x15], level);
  58 }
  59
  60 static void pci_grackle_save(QEMUFile* f, void *opaque)
  61 {
  62     PCIDevice *d = opaque;
  63
  64     pci_device_save(d, f);
  65 }
  66
  67 static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
  68 {
  69     PCIDevice *d = opaque;
  70
  71     if (version_id != 1)
  72         return -EINVAL;
  73
  74     return pci_device_load(d, f);
  75 }
  76
  77 static void pci_grackle_reset(void *opaque)
  78 {
  79 }
  80
  81 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
  82 {
  83     DeviceState *dev;
  84     SysBusDevice *s;
  85     GrackleState *d;
  86
  87     dev = qdev_create(NULL, "grackle");
  88     qdev_init_nofail(dev);
  89     s = sysbus_from_qdev(dev);
  90     d = FROM_SYSBUS(GrackleState, s);
  91     d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
  92                                          pci_grackle_set_irq,
  93                                          pci_grackle_map_irq,
  94                                          pic, 0, 4);
  95
  96     pci_create_simple(d->host_state.bus, 0, "grackle");
  97
  98     sysbus_mmio_map(s, 0, base);
  99     sysbus_mmio_map(s, 1, base + 0x00200000);
 100
 101     return d->host_state.bus;
 102 }
 103
 104 static int pci_grackle_init_device(SysBusDevice *dev)
 105 {
 106     GrackleState *s;
 107     int pci_mem_config, pci_mem_data;
 108
 109     s = FROM_SYSBUS(GrackleState, dev);
 110
 111     pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
 112     pci_mem_data = pci_host_data_register_mmio(&s->host_state);
 113     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 114     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 115
 116     register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
 117                     &s->host_state);
 118     qemu_register_reset(pci_grackle_reset, &s->host_state);
 119     return 0;
 120 }
 121
 122 static int pci_dec_21154_init_device(SysBusDevice *dev)
 123 {
 124     GrackleState *s;
 125     int pci_mem_config, pci_mem_data;
 126
 127     s = FROM_SYSBUS(GrackleState, dev);
 128
 129     pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
 130     pci_mem_data = pci_host_data_register_mmio(&s->host_state);
 131     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 132     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 133     return 0;
 134 }
 135
 136 static int grackle_pci_host_init(PCIDevice *d)
 137 {
 138     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 139     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
 140     d->config[0x08] = 0x00; // revision
 141     d->config[0x09] = 0x01;
 142     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 143     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 144     return 0;
 145 }
 146
 147 static int dec_21154_pci_host_init(PCIDevice *d)
 148 {
 149     /* PCI2PCI bridge same values as PearPC - check this */
 150     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
 151     pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
 152     d->config[0x08] = 0x02; // revision
 153     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 154     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
 155
 156     d->config[0x18] = 0x0;  // primary_bus
 157     d->config[0x19] = 0x1;  // secondary_bus
 158     d->config[0x1a] = 0x1;  // subordinate_bus
 159     d->config[0x1c] = 0x10; // io_base
 160     d->config[0x1d] = 0x20; // io_limit
 161
 162     d->config[0x20] = 0x80; // memory_base
 163     d->config[0x21] = 0x80;
 164     d->config[0x22] = 0x90; // memory_limit
 165     d->config[0x23] = 0x80;
 166
 167     d->config[0x24] = 0x00; // prefetchable_memory_base
 168     d->config[0x25] = 0x84;
 169     d->config[0x26] = 0x00; // prefetchable_memory_limit
 170     d->config[0x27] = 0x85;
 171     return 0;
 172 }
 173
 174 static PCIDeviceInfo grackle_pci_host_info = {
 175     .qdev.name = "grackle",
 176     .qdev.size = sizeof(PCIDevice),
 177     .init      = grackle_pci_host_init,
 178 };
 179
 180 static PCIDeviceInfo dec_21154_pci_host_info = {
 181     .qdev.name = "dec-21154",
 182     .qdev.size = sizeof(PCIDevice),
 183     .init      = dec_21154_pci_host_init,
 184 };
 185
 186 static void grackle_register_devices(void)
 187 {
 188     sysbus_register_dev("grackle", sizeof(GrackleState),
 189                         pci_grackle_init_device);
 190     pci_qdev_register(&grackle_pci_host_info);
 191     sysbus_register_dev("dec-21154", sizeof(GrackleState),
 192                         pci_dec_21154_init_device);
 193     pci_qdev_register(&dec_21154_pci_host_info);
 194 }
 195
 196 device_init(grackle_register_devices)