hw/ppce500_pci.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "ppc.h"
  19 #include "ppce500.h"
  20 typedef target_phys_addr_t pci_addr_t;
  21 #include "pci.h"
  22 #include "pci_host.h"
  23 #include "bswap.h"
  24 #include "qemu-log.h"
  25
  26 #ifdef DEBUG_PCI
  27 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  28 #else
  29 #define pci_debug(fmt, ...)
  30 #endif
  31
  32 #define PCIE500_CFGADDR       0x0
  33 #define PCIE500_CFGDATA       0x4
  34 #define PCIE500_REG_BASE      0xC00
  35 #define PCIE500_REG_SIZE      (0x1000 - PCIE500_REG_BASE)
  36
  37 #define PPCE500_PCI_CONFIG_ADDR         0x0
  38 #define PPCE500_PCI_CONFIG_DATA         0x4
  39 #define PPCE500_PCI_INTACK              0x8
  40
  41 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  42 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  43 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  44 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  45 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  46 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  47 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  48
  49 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  50
  51 #define PCI_POTAR               0x0
  52 #define PCI_POTEAR              0x4
  53 #define PCI_POWBAR              0x8
  54 #define PCI_POWAR               0x10
  55
  56 #define PCI_PITAR               0x0
  57 #define PCI_PIWBAR              0x8
  58 #define PCI_PIWBEAR             0xC
  59 #define PCI_PIWAR               0x10
  60
  61 #define PPCE500_PCI_NR_POBS     5
  62 #define PPCE500_PCI_NR_PIBS     3
  63
  64 struct  pci_outbound {
  65     uint32_t potar;
  66     uint32_t potear;
  67     uint32_t powbar;
  68     uint32_t powar;
  69 };
  70
  71 struct pci_inbound {
  72     uint32_t pitar;
  73     uint32_t piwbar;
  74     uint32_t piwbear;
  75     uint32_t piwar;
  76 };
  77
  78 struct PPCE500PCIState {
  79     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
  80     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
  81     uint32_t gasket_time;
  82     PCIHostState pci_state;
  83     PCIDevice *pci_dev;
  84 };
  85
  86 typedef struct PPCE500PCIState PPCE500PCIState;
  87
  88 static uint32_t pcie500_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
  89 {
  90     PPCE500PCIState *pci = opaque;
  91
  92     pci_debug("%s: (addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, addr,
  93               pci->pci_state.config_reg);
  94     return pci->pci_state.config_reg;
  95 }
  96
  97 static CPUReadMemoryFunc * const pcie500_cfgaddr_read[] = {
  98     &pcie500_cfgaddr_readl,
  99     &pcie500_cfgaddr_readl,
 100     &pcie500_cfgaddr_readl,
 101 };
 102
 103 static void pcie500_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
 104                                   uint32_t value)
 105 {
 106     PPCE500PCIState *controller = opaque;
 107
 108     pci_debug("%s: value:%x -> (addr:" TARGET_FMT_plx ")\n", __func__, value,
 109               addr);
 110     controller->pci_state.config_reg = value & ~0x3;
 111 }
 112
 113 static CPUWriteMemoryFunc * const pcie500_cfgaddr_write[] = {
 114     &pcie500_cfgaddr_writel,
 115     &pcie500_cfgaddr_writel,
 116     &pcie500_cfgaddr_writel,
 117 };
 118
 119 static CPUReadMemoryFunc * const pcie500_cfgdata_read[] = {
 120     &pci_host_data_readb,
 121     &pci_host_data_readw,
 122     &pci_host_data_readl,
 123 };
 124
 125 static CPUWriteMemoryFunc * const pcie500_cfgdata_write[] = {
 126     &pci_host_data_writeb,
 127     &pci_host_data_writew,
 128     &pci_host_data_writel,
 129 };
 130
 131 static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
 132 {
 133     PPCE500PCIState *pci = opaque;
 134     unsigned long win;
 135     uint32_t value = 0;
 136
 137     win = addr & 0xfe0;
 138
 139     switch (win) {
 140     case PPCE500_PCI_OW1:
 141     case PPCE500_PCI_OW2:
 142     case PPCE500_PCI_OW3:
 143     case PPCE500_PCI_OW4:
 144         switch (addr & 0xC) {
 145         case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
 146         case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
 147         case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
 148         case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
 149         default: break;
 150         }
 151         break;
 152
 153     case PPCE500_PCI_IW3:
 154     case PPCE500_PCI_IW2:
 155     case PPCE500_PCI_IW1:
 156         switch (addr & 0xC) {
 157         case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
 158         case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
 159         case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
 160         case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
 161         default: break;
 162         };
 163         break;
 164
 165     case PPCE500_PCI_GASKET_TIMR:
 166         value = pci->gasket_time;
 167         break;
 168
 169     default:
 170         break;
 171     }
 172
 173     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 174               win, addr, value);
 175     return value;
 176 }
 177
 178 static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
 179     &pci_reg_read4,
 180     &pci_reg_read4,
 181     &pci_reg_read4,
 182 };
 183
 184 static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
 185                                uint32_t value)
 186 {
 187     PPCE500PCIState *pci = opaque;
 188     unsigned long win;
 189
 190     win = addr & 0xfe0;
 191
 192     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 193               __func__, value, win, addr);
 194
 195     switch (win) {
 196     case PPCE500_PCI_OW1:
 197     case PPCE500_PCI_OW2:
 198     case PPCE500_PCI_OW3:
 199     case PPCE500_PCI_OW4:
 200         switch (addr & 0xC) {
 201         case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
 202         case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
 203         case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
 204         case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
 205         default: break;
 206         };
 207         break;
 208
 209     case PPCE500_PCI_IW3:
 210     case PPCE500_PCI_IW2:
 211     case PPCE500_PCI_IW1:
 212         switch (addr & 0xC) {
 213         case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
 214         case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
 215         case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
 216         case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
 217         default: break;
 218         };
 219         break;
 220
 221     case PPCE500_PCI_GASKET_TIMR:
 222         pci->gasket_time = value;
 223         break;
 224
 225     default:
 226         break;
 227     };
 228 }
 229
 230 static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
 231     &pci_reg_write4,
 232     &pci_reg_write4,
 233     &pci_reg_write4,
 234 };
 235
 236 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 237 {
 238     int devno = pci_dev->devfn >> 3, ret = 0;
 239
 240     switch (devno) {
 241         /* Two PCI slot */
 242         case 0x11:
 243         case 0x12:
 244             ret = (irq_num + devno - 0x10) % 4;
 245             break;
 246         default:
 247             printf("Error:%s:unknow dev number\n", __func__);
 248     }
 249
 250     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 251            pci_dev->devfn, irq_num, ret, devno);
 252
 253     return ret;
 254 }
 255
 256 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
 257 {
 258     qemu_irq *pic = opaque;
 259
 260     pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
 261
 262     qemu_set_irq(pic[irq_num], level);
 263 }
 264
 265 static void ppce500_pci_save(QEMUFile *f, void *opaque)
 266 {
 267     PPCE500PCIState *controller = opaque;
 268     int i;
 269
 270     pci_device_save(controller->pci_dev, f);
 271
 272     for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
 273         qemu_put_be32s(f, &controller->pob[i].potar);
 274         qemu_put_be32s(f, &controller->pob[i].potear);
 275         qemu_put_be32s(f, &controller->pob[i].powbar);
 276         qemu_put_be32s(f, &controller->pob[i].powar);
 277     }
 278
 279     for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
 280         qemu_put_be32s(f, &controller->pib[i].pitar);
 281         qemu_put_be32s(f, &controller->pib[i].piwbar);
 282         qemu_put_be32s(f, &controller->pib[i].piwbear);
 283         qemu_put_be32s(f, &controller->pib[i].piwar);
 284     }
 285     qemu_put_be32s(f, &controller->gasket_time);
 286 }
 287
 288 static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
 289 {
 290     PPCE500PCIState *controller = opaque;
 291     int i;
 292
 293     if (version_id != 1)
 294         return -EINVAL;
 295
 296     pci_device_load(controller->pci_dev, f);
 297
 298     for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
 299         qemu_get_be32s(f, &controller->pob[i].potar);
 300         qemu_get_be32s(f, &controller->pob[i].potear);
 301         qemu_get_be32s(f, &controller->pob[i].powbar);
 302         qemu_get_be32s(f, &controller->pob[i].powar);
 303     }
 304
 305     for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
 306         qemu_get_be32s(f, &controller->pib[i].pitar);
 307         qemu_get_be32s(f, &controller->pib[i].piwbar);
 308         qemu_get_be32s(f, &controller->pib[i].piwbear);
 309         qemu_get_be32s(f, &controller->pib[i].piwar);
 310     }
 311     qemu_get_be32s(f, &controller->gasket_time);
 312
 313     return 0;
 314 }
 315
 316 PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
 317 {
 318     PPCE500PCIState *controller;
 319     PCIDevice *d;
 320     int index;
 321     static int ppce500_pci_id;
 322
 323     controller = qemu_mallocz(sizeof(PPCE500PCIState));
 324
 325     controller->pci_state.bus = pci_register_bus(NULL, "pci",
 326                                                  mpc85xx_pci_set_irq,
 327                                                  mpc85xx_pci_map_irq,
 328                                                  pci_irqs, 0x88, 4);
 329     d = pci_register_device(controller->pci_state.bus,
 330                             "host bridge", sizeof(PCIDevice),
 331                             0, NULL, NULL);
 332
 333     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
 334     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
 335     pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
 336
 337     controller->pci_dev = d;
 338
 339     /* CFGADDR */
 340     index = cpu_register_io_memory(pcie500_cfgaddr_read,
 341                                    pcie500_cfgaddr_write, controller);
 342     if (index < 0)
 343         goto free;
 344     cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
 345
 346     /* CFGDATA */
 347     index = cpu_register_io_memory(pcie500_cfgdata_read,
 348                                    pcie500_cfgdata_write,
 349                                    &controller->pci_state);
 350     if (index < 0)
 351         goto free;
 352     cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
 353
 354     index = cpu_register_io_memory(e500_pci_reg_read,
 355                                    e500_pci_reg_write, controller);
 356     if (index < 0)
 357         goto free;
 358     cpu_register_physical_memory(registers + PCIE500_REG_BASE,
 359                                    PCIE500_REG_SIZE, index);
 360
 361     /* XXX load/save code not tested. */
 362     register_savevm("ppce500_pci", ppce500_pci_id++, 1,
 363                     ppce500_pci_save, ppce500_pci_load, controller);
 364
 365     return controller->pci_state.bus;
 366
 367 free:
 368     printf("%s error\n", __func__);
 369     qemu_free(controller);
 370     return NULL;
 371 }