4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-objects.h"
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
36 # define PCI_DPRINTF(format, ...) do { } while (0)
42 pci_set_irq_fn set_irq
;
43 pci_map_irq_fn map_irq
;
44 pci_hotplug_fn hotplug
;
45 DeviceState
*hotplug_qdev
;
47 PCIDevice
*devices
[256];
48 PCIDevice
*parent_dev
;
49 target_phys_addr_t mem_base
;
51 QLIST_HEAD(, PCIBus
) child
; /* this will be replaced by qdev later */
52 QLIST_ENTRY(PCIBus
) sibling
;/* this will be replaced by qdev later */
54 /* The bus IRQ state is the logical OR of the connected devices.
55 Keep a count of the number of devices with raised IRQs. */
60 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
62 static struct BusInfo pci_bus_info
= {
64 .size
= sizeof(PCIBus
),
65 .print_dev
= pcibus_dev_print
,
66 .props
= (Property
[]) {
67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
68 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
69 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
70 DEFINE_PROP_END_OF_LIST()
74 static void pci_update_mappings(PCIDevice
*d
);
75 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
76 static int pci_add_option_rom(PCIDevice
*pdev
);
78 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
79 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
84 QLIST_ENTRY(PCIHostBus
) next
;
86 static QLIST_HEAD(, PCIHostBus
) host_buses
;
88 static const VMStateDescription vmstate_pcibus
= {
91 .minimum_version_id
= 1,
92 .minimum_version_id_old
= 1,
93 .fields
= (VMStateField
[]) {
94 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
95 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
100 static int pci_bar(PCIDevice
*d
, int reg
)
104 if (reg
!= PCI_ROM_SLOT
)
105 return PCI_BASE_ADDRESS_0
+ reg
* 4;
107 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
108 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
111 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
113 return (d
->irq_state
>> irq_num
) & 0x1;
116 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
118 d
->irq_state
&= ~(0x1 << irq_num
);
119 d
->irq_state
|= level
<< irq_num
;
122 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
127 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
130 pci_dev
= bus
->parent_dev
;
132 bus
->irq_count
[irq_num
] += change
;
133 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
136 /* Update interrupt status bit in config space on interrupt
138 static void pci_update_irq_status(PCIDevice
*dev
)
140 if (dev
->irq_state
) {
141 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
143 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
147 static void pci_device_reset(PCIDevice
*dev
)
152 pci_update_irq_status(dev
);
153 dev
->config
[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
155 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
156 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
157 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
158 if (!dev
->io_regions
[r
].size
) {
161 pci_set_long(dev
->config
+ pci_bar(dev
, r
), dev
->io_regions
[r
].type
);
163 pci_update_mappings(dev
);
166 static void pci_bus_reset(void *opaque
)
168 PCIBus
*bus
= opaque
;
171 for (i
= 0; i
< bus
->nirq
; i
++) {
172 bus
->irq_count
[i
] = 0;
174 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
175 if (bus
->devices
[i
]) {
176 pci_device_reset(bus
->devices
[i
]);
181 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
183 struct PCIHostBus
*host
;
184 host
= qemu_mallocz(sizeof(*host
));
185 host
->domain
= domain
;
187 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
190 PCIBus
*pci_find_root_bus(int domain
)
192 struct PCIHostBus
*host
;
194 QLIST_FOREACH(host
, &host_buses
, next
) {
195 if (host
->domain
== domain
) {
203 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
204 const char *name
, int devfn_min
)
206 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
207 bus
->devfn_min
= devfn_min
;
210 QLIST_INIT(&bus
->child
);
211 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
213 vmstate_register(-1, &vmstate_pcibus
, bus
);
214 qemu_register_reset(pci_bus_reset
, bus
);
217 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
221 bus
= qemu_mallocz(sizeof(*bus
));
222 bus
->qbus
.qdev_allocated
= 1;
223 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
227 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
228 void *irq_opaque
, int nirq
)
230 bus
->set_irq
= set_irq
;
231 bus
->map_irq
= map_irq
;
232 bus
->irq_opaque
= irq_opaque
;
234 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
237 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
239 bus
->qbus
.allow_hotplug
= 1;
240 bus
->hotplug
= hotplug
;
241 bus
->hotplug_qdev
= qdev
;
244 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
)
246 bus
->mem_base
= base
;
249 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
250 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
251 void *irq_opaque
, int devfn_min
, int nirq
)
255 bus
= pci_bus_new(parent
, name
, devfn_min
);
256 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
260 static void pci_register_secondary_bus(PCIBus
*parent
,
263 pci_map_irq_fn map_irq
,
266 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
267 bus
->map_irq
= map_irq
;
268 bus
->parent_dev
= dev
;
270 QLIST_INIT(&bus
->child
);
271 QLIST_INSERT_HEAD(&parent
->child
, bus
, sibling
);
274 static void pci_unregister_secondary_bus(PCIBus
*bus
)
276 assert(QLIST_EMPTY(&bus
->child
));
277 QLIST_REMOVE(bus
, sibling
);
280 int pci_bus_num(PCIBus
*s
)
283 return 0; /* pci host bridge */
284 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
287 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
289 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
293 assert(size
== pci_config_size(s
));
294 config
= qemu_malloc(size
);
296 qemu_get_buffer(f
, config
, size
);
297 for (i
= 0; i
< size
; ++i
) {
298 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
]) {
303 memcpy(s
->config
, config
, size
);
305 pci_update_mappings(s
);
311 /* just put buffer */
312 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
314 const uint8_t **v
= pv
;
315 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
316 qemu_put_buffer(f
, *v
, size
);
319 static VMStateInfo vmstate_info_pci_config
= {
320 .name
= "pci config",
321 .get
= get_pci_config_device
,
322 .put
= put_pci_config_device
,
325 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
327 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
328 uint32_t irq_state
[PCI_NUM_PINS
];
330 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
331 irq_state
[i
] = qemu_get_be32(f
);
332 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
333 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
339 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
340 pci_set_irq_state(s
, i
, irq_state
[i
]);
346 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
349 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
351 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
352 qemu_put_be32(f
, pci_irq_state(s
, i
));
356 static VMStateInfo vmstate_info_pci_irq_state
= {
357 .name
= "pci irq state",
358 .get
= get_pci_irq_state
,
359 .put
= put_pci_irq_state
,
362 const VMStateDescription vmstate_pci_device
= {
365 .minimum_version_id
= 1,
366 .minimum_version_id_old
= 1,
367 .fields
= (VMStateField
[]) {
368 VMSTATE_INT32_LE(version_id
, PCIDevice
),
369 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
370 vmstate_info_pci_config
,
371 PCI_CONFIG_SPACE_SIZE
),
372 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
373 vmstate_info_pci_irq_state
,
374 PCI_NUM_PINS
* sizeof(int32_t)),
375 VMSTATE_END_OF_LIST()
379 const VMStateDescription vmstate_pcie_device
= {
382 .minimum_version_id
= 1,
383 .minimum_version_id_old
= 1,
384 .fields
= (VMStateField
[]) {
385 VMSTATE_INT32_LE(version_id
, PCIDevice
),
386 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
387 vmstate_info_pci_config
,
388 PCIE_CONFIG_SPACE_SIZE
),
389 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
390 vmstate_info_pci_irq_state
,
391 PCI_NUM_PINS
* sizeof(int32_t)),
392 VMSTATE_END_OF_LIST()
396 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
398 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
401 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
403 /* Clear interrupt status bit: it is implicit
404 * in irq_state which we are saving.
405 * This makes us compatible with old devices
406 * which never set or clear this bit. */
407 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
408 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
409 /* Restore the interrupt status bit. */
410 pci_update_irq_status(s
);
413 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
416 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
417 /* Restore the interrupt status bit. */
418 pci_update_irq_status(s
);
422 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
426 id
= (void*)(&pci_dev
->config
[PCI_SUBSYSTEM_VENDOR_ID
]);
427 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
428 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
433 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
435 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
440 unsigned long dom
= 0, bus
= 0;
444 val
= strtoul(p
, &e
, 16);
450 val
= strtoul(p
, &e
, 16);
457 val
= strtoul(p
, &e
, 16);
463 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
471 /* Note: QEMU doesn't implement domains other than 0 */
472 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
481 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
484 /* strip legacy tag */
485 if (!strncmp(addr
, "pci_addr=", 9)) {
488 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
489 monitor_printf(mon
, "Invalid pci address\n");
495 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
502 return pci_find_bus(pci_find_root_bus(0), 0);
505 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
510 return pci_find_bus(pci_find_root_bus(0), bus
);
513 static void pci_init_cmask(PCIDevice
*dev
)
515 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
516 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
517 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
518 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
519 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
520 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
521 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
522 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
525 static void pci_init_wmask(PCIDevice
*dev
)
527 int config_size
= pci_config_size(dev
);
529 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
530 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
531 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
532 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
533 PCI_COMMAND_INTX_DISABLE
);
535 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
536 config_size
- PCI_CONFIG_HEADER_SIZE
);
539 static void pci_init_wmask_bridge(PCIDevice
*d
)
541 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
542 PCI_SEC_LETENCY_TIMER */
543 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
546 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
547 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
548 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
549 PCI_MEMORY_RANGE_MASK
& 0xffff);
550 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
551 PCI_MEMORY_RANGE_MASK
& 0xffff);
552 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
553 PCI_PREF_RANGE_MASK
& 0xffff);
554 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
555 PCI_PREF_RANGE_MASK
& 0xffff);
557 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
558 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
560 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
, 0xffff);
563 static void pci_config_alloc(PCIDevice
*pci_dev
)
565 int config_size
= pci_config_size(pci_dev
);
567 pci_dev
->config
= qemu_mallocz(config_size
);
568 pci_dev
->cmask
= qemu_mallocz(config_size
);
569 pci_dev
->wmask
= qemu_mallocz(config_size
);
570 pci_dev
->used
= qemu_mallocz(config_size
);
573 static void pci_config_free(PCIDevice
*pci_dev
)
575 qemu_free(pci_dev
->config
);
576 qemu_free(pci_dev
->cmask
);
577 qemu_free(pci_dev
->wmask
);
578 qemu_free(pci_dev
->used
);
581 /* -1 for devfn means auto assign */
582 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
583 const char *name
, int devfn
,
584 PCIConfigReadFunc
*config_read
,
585 PCIConfigWriteFunc
*config_write
,
589 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
591 if (!bus
->devices
[devfn
])
594 error_report("PCI: no devfn available for %s, all in use", name
);
597 } else if (bus
->devices
[devfn
]) {
598 error_report("PCI: devfn %d not available for %s, in use by %s",
599 devfn
, name
, bus
->devices
[devfn
]->name
);
603 pci_dev
->devfn
= devfn
;
604 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
605 pci_dev
->irq_state
= 0;
606 pci_config_alloc(pci_dev
);
608 header_type
&= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
609 if (header_type
== PCI_HEADER_TYPE_NORMAL
) {
610 pci_set_default_subsystem_id(pci_dev
);
612 pci_init_cmask(pci_dev
);
613 pci_init_wmask(pci_dev
);
614 if (header_type
== PCI_HEADER_TYPE_BRIDGE
) {
615 pci_init_wmask_bridge(pci_dev
);
619 config_read
= pci_default_read_config
;
621 config_write
= pci_default_write_config
;
622 pci_dev
->config_read
= config_read
;
623 pci_dev
->config_write
= config_write
;
624 bus
->devices
[devfn
] = pci_dev
;
625 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
626 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
630 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
631 int instance_size
, int devfn
,
632 PCIConfigReadFunc
*config_read
,
633 PCIConfigWriteFunc
*config_write
)
637 pci_dev
= qemu_mallocz(instance_size
);
638 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
639 config_read
, config_write
,
640 PCI_HEADER_TYPE_NORMAL
);
641 if (pci_dev
== NULL
) {
642 hw_error("PCI: can't register device\n");
647 static target_phys_addr_t
pci_to_cpu_addr(PCIBus
*bus
,
648 target_phys_addr_t addr
)
650 return addr
+ bus
->mem_base
;
653 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
658 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
659 r
= &pci_dev
->io_regions
[i
];
660 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
662 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
663 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
665 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev
->bus
,
673 static int pci_unregister_device(DeviceState
*dev
)
675 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
676 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
680 ret
= info
->exit(pci_dev
);
684 pci_unregister_io_regions(pci_dev
);
686 qemu_free_irqs(pci_dev
->irq
);
687 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
688 pci_config_free(pci_dev
);
692 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
693 pcibus_t size
, int type
,
694 PCIMapIORegionFunc
*map_func
)
700 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
703 if (size
& (size
-1)) {
704 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
705 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
709 r
= &pci_dev
->io_regions
[region_num
];
710 r
->addr
= PCI_BAR_UNMAPPED
;
712 r
->filtered_size
= size
;
714 r
->map_func
= map_func
;
717 addr
= pci_bar(pci_dev
, region_num
);
718 if (region_num
== PCI_ROM_SLOT
) {
719 /* ROM enable bit is writeable */
720 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
722 pci_set_long(pci_dev
->config
+ addr
, type
);
723 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
724 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
725 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
726 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
728 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
729 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
733 static uint32_t pci_config_get_io_base(PCIDevice
*d
,
734 uint32_t base
, uint32_t base_upper16
)
738 val
= ((uint32_t)d
->config
[base
] & PCI_IO_RANGE_MASK
) << 8;
739 if (d
->config
[base
] & PCI_IO_RANGE_TYPE_32
) {
740 val
|= (uint32_t)pci_get_word(d
->config
+ base_upper16
) << 16;
745 static pcibus_t
pci_config_get_memory_base(PCIDevice
*d
, uint32_t base
)
747 return ((pcibus_t
)pci_get_word(d
->config
+ base
) & PCI_MEMORY_RANGE_MASK
)
751 static pcibus_t
pci_config_get_pref_base(PCIDevice
*d
,
752 uint32_t base
, uint32_t upper
)
757 tmp
= (pcibus_t
)pci_get_word(d
->config
+ base
);
758 val
= (tmp
& PCI_PREF_RANGE_MASK
) << 16;
759 if (tmp
& PCI_PREF_RANGE_TYPE_64
) {
760 val
|= (pcibus_t
)pci_get_long(d
->config
+ upper
) << 32;
765 static pcibus_t
pci_bridge_get_base(PCIDevice
*bridge
, uint8_t type
)
768 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
769 base
= pci_config_get_io_base(bridge
,
770 PCI_IO_BASE
, PCI_IO_BASE_UPPER16
);
772 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
773 base
= pci_config_get_pref_base(
774 bridge
, PCI_PREF_MEMORY_BASE
, PCI_PREF_BASE_UPPER32
);
776 base
= pci_config_get_memory_base(bridge
, PCI_MEMORY_BASE
);
783 static pcibus_t
pci_bridge_get_limit(PCIDevice
*bridge
, uint8_t type
)
786 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
787 limit
= pci_config_get_io_base(bridge
,
788 PCI_IO_LIMIT
, PCI_IO_LIMIT_UPPER16
);
789 limit
|= 0xfff; /* PCI bridge spec 3.2.5.6. */
791 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
792 limit
= pci_config_get_pref_base(
793 bridge
, PCI_PREF_MEMORY_LIMIT
, PCI_PREF_LIMIT_UPPER32
);
795 limit
= pci_config_get_memory_base(bridge
, PCI_MEMORY_LIMIT
);
797 limit
|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
802 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
805 pcibus_t base
= *addr
;
806 pcibus_t limit
= *addr
+ *size
- 1;
809 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
810 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
812 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
813 if (!(cmd
& PCI_COMMAND_IO
)) {
817 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
822 base
= MAX(base
, pci_bridge_get_base(br
, type
));
823 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
830 *size
= limit
- base
+ 1;
833 *addr
= PCI_BAR_UNMAPPED
;
837 static pcibus_t
pci_bar_address(PCIDevice
*d
,
838 int reg
, uint8_t type
, pcibus_t size
)
840 pcibus_t new_addr
, last_addr
;
841 int bar
= pci_bar(d
, reg
);
842 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
844 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
845 if (!(cmd
& PCI_COMMAND_IO
)) {
846 return PCI_BAR_UNMAPPED
;
848 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
849 last_addr
= new_addr
+ size
- 1;
850 /* NOTE: we have only 64K ioports on PC */
851 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
852 return PCI_BAR_UNMAPPED
;
857 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
858 return PCI_BAR_UNMAPPED
;
860 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
861 new_addr
= pci_get_quad(d
->config
+ bar
);
863 new_addr
= pci_get_long(d
->config
+ bar
);
865 /* the ROM slot has a specific enable bit */
866 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
867 return PCI_BAR_UNMAPPED
;
869 new_addr
&= ~(size
- 1);
870 last_addr
= new_addr
+ size
- 1;
871 /* NOTE: we do not support wrapping */
872 /* XXX: as we cannot support really dynamic
873 mappings, we handle specific values as invalid
875 if (last_addr
<= new_addr
|| new_addr
== 0 ||
876 last_addr
== PCI_BAR_UNMAPPED
) {
877 return PCI_BAR_UNMAPPED
;
880 /* Now pcibus_t is 64bit.
881 * Check if 32 bit BAR wraps around explicitly.
882 * Without this, PC ide doesn't work well.
883 * TODO: remove this work around.
885 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
886 return PCI_BAR_UNMAPPED
;
890 * OS is allowed to set BAR beyond its addressable
891 * bits. For example, 32 bit OS can set 64bit bar
892 * to >4G. Check it. TODO: we might need to support
893 * it in the future for e.g. PAE.
895 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
896 return PCI_BAR_UNMAPPED
;
902 static void pci_update_mappings(PCIDevice
*d
)
906 pcibus_t new_addr
, filtered_size
;
908 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
909 r
= &d
->io_regions
[i
];
911 /* this region isn't registered */
915 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
917 /* bridge filtering */
918 filtered_size
= r
->size
;
919 if (new_addr
!= PCI_BAR_UNMAPPED
) {
920 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
923 /* This bar isn't changed */
924 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
927 /* now do the real mapping */
928 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
929 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
931 /* NOTE: specific hack for IDE in PC case:
932 only one byte must be mapped. */
933 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
934 if (class == 0x0101 && r
->size
== 4) {
935 isa_unassign_ioport(r
->addr
+ 2, 1);
937 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
940 cpu_register_physical_memory(pci_to_cpu_addr(d
->bus
, r
->addr
),
943 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
947 r
->filtered_size
= filtered_size
;
948 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
950 * TODO: currently almost all the map funcions assumes
951 * filtered_size == size and addr & ~(size - 1) == addr.
952 * However with bridge filtering, they aren't always true.
953 * Teach them such cases, such that filtered_size < size and
954 * addr & (size - 1) != 0.
956 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
957 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
959 r
->map_func(d
, i
, pci_to_cpu_addr(d
->bus
, r
->addr
),
960 r
->filtered_size
, r
->type
);
966 static inline int pci_irq_disabled(PCIDevice
*d
)
968 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
971 /* Called after interrupt disabled field update in config space,
972 * assert/deassert interrupts if necessary.
973 * Gets original interrupt disable bit value (before update). */
974 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
976 int i
, disabled
= pci_irq_disabled(d
);
977 if (disabled
== was_irq_disabled
)
979 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
980 int state
= pci_irq_state(d
, i
);
981 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
985 uint32_t pci_default_read_config(PCIDevice
*d
,
986 uint32_t address
, int len
)
989 assert(len
== 1 || len
== 2 || len
== 4);
990 len
= MIN(len
, pci_config_size(d
) - address
);
991 memcpy(&val
, d
->config
+ address
, len
);
992 return le32_to_cpu(val
);
995 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
997 int i
, was_irq_disabled
= pci_irq_disabled(d
);
998 uint32_t config_size
= pci_config_size(d
);
1000 for (i
= 0; i
< l
&& addr
+ i
< config_size
; val
>>= 8, ++i
) {
1001 uint8_t wmask
= d
->wmask
[addr
+ i
];
1002 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1004 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1005 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1006 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1007 range_covers_byte(addr
, l
, PCI_COMMAND
))
1008 pci_update_mappings(d
);
1010 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1011 pci_update_irq_disabled(d
, was_irq_disabled
);
1014 /***********************************************************/
1015 /* generic PCI irq support */
1017 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1018 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1020 PCIDevice
*pci_dev
= opaque
;
1023 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1027 pci_set_irq_state(pci_dev
, irq_num
, level
);
1028 pci_update_irq_status(pci_dev
);
1029 if (pci_irq_disabled(pci_dev
))
1031 pci_change_irq_level(pci_dev
, irq_num
, change
);
1034 /***********************************************************/
1035 /* monitor info on PCI */
1042 static const pci_class_desc pci_class_descriptions
[] =
1044 { 0x0100, "SCSI controller"},
1045 { 0x0101, "IDE controller"},
1046 { 0x0102, "Floppy controller"},
1047 { 0x0103, "IPI controller"},
1048 { 0x0104, "RAID controller"},
1049 { 0x0106, "SATA controller"},
1050 { 0x0107, "SAS controller"},
1051 { 0x0180, "Storage controller"},
1052 { 0x0200, "Ethernet controller"},
1053 { 0x0201, "Token Ring controller"},
1054 { 0x0202, "FDDI controller"},
1055 { 0x0203, "ATM controller"},
1056 { 0x0280, "Network controller"},
1057 { 0x0300, "VGA controller"},
1058 { 0x0301, "XGA controller"},
1059 { 0x0302, "3D controller"},
1060 { 0x0380, "Display controller"},
1061 { 0x0400, "Video controller"},
1062 { 0x0401, "Audio controller"},
1064 { 0x0480, "Multimedia controller"},
1065 { 0x0500, "RAM controller"},
1066 { 0x0501, "Flash controller"},
1067 { 0x0580, "Memory controller"},
1068 { 0x0600, "Host bridge"},
1069 { 0x0601, "ISA bridge"},
1070 { 0x0602, "EISA bridge"},
1071 { 0x0603, "MC bridge"},
1072 { 0x0604, "PCI bridge"},
1073 { 0x0605, "PCMCIA bridge"},
1074 { 0x0606, "NUBUS bridge"},
1075 { 0x0607, "CARDBUS bridge"},
1076 { 0x0608, "RACEWAY bridge"},
1077 { 0x0680, "Bridge"},
1078 { 0x0c03, "USB controller"},
1082 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1083 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1088 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1089 d
= bus
->devices
[devfn
];
1096 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1097 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1099 bus
= pci_find_bus(bus
, bus_num
);
1102 pci_for_each_device_under_bus(bus
, fn
);
1106 static void pci_device_print(Monitor
*mon
, QDict
*device
)
1110 uint64_t addr
, size
;
1112 monitor_printf(mon
, " Bus %2" PRId64
", ", qdict_get_int(device
, "bus"));
1113 monitor_printf(mon
, "device %3" PRId64
", function %" PRId64
":\n",
1114 qdict_get_int(device
, "slot"),
1115 qdict_get_int(device
, "function"));
1116 monitor_printf(mon
, " ");
1118 qdict
= qdict_get_qdict(device
, "class_info");
1119 if (qdict_haskey(qdict
, "desc")) {
1120 monitor_printf(mon
, "%s", qdict_get_str(qdict
, "desc"));
1122 monitor_printf(mon
, "Class %04" PRId64
, qdict_get_int(qdict
, "class"));
1125 qdict
= qdict_get_qdict(device
, "id");
1126 monitor_printf(mon
, ": PCI device %04" PRIx64
":%04" PRIx64
"\n",
1127 qdict_get_int(qdict
, "device"),
1128 qdict_get_int(qdict
, "vendor"));
1130 if (qdict_haskey(device
, "irq")) {
1131 monitor_printf(mon
, " IRQ %" PRId64
".\n",
1132 qdict_get_int(device
, "irq"));
1135 if (qdict_haskey(device
, "pci_bridge")) {
1138 qdict
= qdict_get_qdict(device
, "pci_bridge");
1140 info
= qdict_get_qdict(qdict
, "bus");
1141 monitor_printf(mon
, " BUS %" PRId64
".\n",
1142 qdict_get_int(info
, "number"));
1143 monitor_printf(mon
, " secondary bus %" PRId64
".\n",
1144 qdict_get_int(info
, "secondary"));
1145 monitor_printf(mon
, " subordinate bus %" PRId64
".\n",
1146 qdict_get_int(info
, "subordinate"));
1148 info
= qdict_get_qdict(qdict
, "io_range");
1149 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1150 qdict_get_int(info
, "base"),
1151 qdict_get_int(info
, "limit"));
1153 info
= qdict_get_qdict(qdict
, "memory_range");
1155 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1156 qdict_get_int(info
, "base"),
1157 qdict_get_int(info
, "limit"));
1159 info
= qdict_get_qdict(qdict
, "prefetchable_range");
1160 monitor_printf(mon
, " prefetchable memory range "
1161 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1162 qdict_get_int(info
, "base"),
1163 qdict_get_int(info
, "limit"));
1166 QLIST_FOREACH_ENTRY(qdict_get_qlist(device
, "regions"), entry
) {
1167 qdict
= qobject_to_qdict(qlist_entry_obj(entry
));
1168 monitor_printf(mon
, " BAR%d: ", (int) qdict_get_int(qdict
, "bar"));
1170 addr
= qdict_get_int(qdict
, "address");
1171 size
= qdict_get_int(qdict
, "size");
1173 if (!strcmp(qdict_get_str(qdict
, "type"), "io")) {
1174 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1175 " [0x%04"FMT_PCIBUS
"].\n",
1176 addr
, addr
+ size
- 1);
1178 monitor_printf(mon
, "%d bit%s memory at 0x%08"FMT_PCIBUS
1179 " [0x%08"FMT_PCIBUS
"].\n",
1180 qdict_get_bool(qdict
, "mem_type_64") ? 64 : 32,
1181 qdict_get_bool(qdict
, "prefetch") ?
1182 " prefetchable" : "", addr
, addr
+ size
- 1);
1186 monitor_printf(mon
, " id \"%s\"\n", qdict_get_str(device
, "qdev_id"));
1188 if (qdict_haskey(device
, "pci_bridge")) {
1189 qdict
= qdict_get_qdict(device
, "pci_bridge");
1190 if (qdict_haskey(qdict
, "devices")) {
1192 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1193 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1199 void do_pci_info_print(Monitor
*mon
, const QObject
*data
)
1201 QListEntry
*bus
, *dev
;
1203 QLIST_FOREACH_ENTRY(qobject_to_qlist(data
), bus
) {
1204 QDict
*qdict
= qobject_to_qdict(qlist_entry_obj(bus
));
1205 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1206 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1211 static QObject
*pci_get_dev_class(const PCIDevice
*dev
)
1214 const pci_class_desc
*desc
;
1216 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1217 desc
= pci_class_descriptions
;
1218 while (desc
->desc
&& class != desc
->class)
1222 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1225 return qobject_from_jsonf("{ 'class': %d }", class);
1229 static QObject
*pci_get_dev_id(const PCIDevice
*dev
)
1231 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1232 pci_get_word(dev
->config
+ PCI_VENDOR_ID
),
1233 pci_get_word(dev
->config
+ PCI_DEVICE_ID
));
1236 static QObject
*pci_get_regions_list(const PCIDevice
*dev
)
1239 QList
*regions_list
;
1241 regions_list
= qlist_new();
1243 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1245 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1251 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1252 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1253 "'address': %" PRId64
", "
1254 "'size': %" PRId64
" }",
1255 i
, r
->addr
, r
->size
);
1257 int mem_type_64
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
;
1259 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1260 "'mem_type_64': %i, 'prefetch': %i, "
1261 "'address': %" PRId64
", "
1262 "'size': %" PRId64
" }",
1264 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
,
1268 qlist_append_obj(regions_list
, obj
);
1271 return QOBJECT(regions_list
);
1274 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
);
1276 static QObject
*pci_get_dev_dict(PCIDevice
*dev
, PCIBus
*bus
, int bus_num
)
1281 obj
= qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1284 PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
),
1285 pci_get_dev_class(dev
), pci_get_dev_id(dev
),
1286 pci_get_regions_list(dev
),
1287 dev
->qdev
.id
? dev
->qdev
.id
: "");
1289 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1290 QDict
*qdict
= qobject_to_qdict(obj
);
1291 qdict_put(qdict
, "irq", qint_from_int(dev
->config
[PCI_INTERRUPT_LINE
]));
1294 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1295 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1297 QObject
*pci_bridge
;
1299 pci_bridge
= qobject_from_jsonf("{ 'bus': "
1300 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1301 "'io_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1302 "'memory_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1303 "'prefetchable_range': { 'base': %" PRId64
", 'limit': %" PRId64
"} }",
1304 dev
->config
[PCI_PRIMARY_BUS
], dev
->config
[PCI_SECONDARY_BUS
],
1305 dev
->config
[PCI_SUBORDINATE_BUS
],
1306 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1307 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1308 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1309 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1310 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1311 PCI_BASE_ADDRESS_MEM_PREFETCH
),
1312 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1313 PCI_BASE_ADDRESS_MEM_PREFETCH
));
1315 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1316 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1319 qdict
= qobject_to_qdict(pci_bridge
);
1320 qdict_put_obj(qdict
, "devices",
1321 pci_get_devices_list(child_bus
,
1322 dev
->config
[PCI_SECONDARY_BUS
]));
1325 qdict
= qobject_to_qdict(obj
);
1326 qdict_put_obj(qdict
, "pci_bridge", pci_bridge
);
1332 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
)
1338 dev_list
= qlist_new();
1340 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1341 dev
= bus
->devices
[devfn
];
1343 qlist_append_obj(dev_list
, pci_get_dev_dict(dev
, bus
, bus_num
));
1347 return QOBJECT(dev_list
);
1350 static QObject
*pci_get_bus_dict(PCIBus
*bus
, int bus_num
)
1352 bus
= pci_find_bus(bus
, bus_num
);
1354 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1355 bus_num
, pci_get_devices_list(bus
, bus_num
));
1362 * do_pci_info(): PCI buses and devices information
1364 * The returned QObject is a QList of all buses. Each bus is
1365 * represented by a QDict, which has a key with a QList of all
1366 * PCI devices attached to it. Each device is represented by
1369 * The bus QDict contains the following:
1371 * - "bus": bus number
1372 * - "devices": a QList of QDicts, each QDict represents a PCI
1375 * The PCI device QDict contains the following:
1377 * - "bus": identical to the parent's bus number
1378 * - "slot": slot number
1379 * - "function": function number
1380 * - "class_info": a QDict containing:
1381 * - "desc": device class description (optional)
1382 * - "class": device class number
1383 * - "id": a QDict containing:
1384 * - "device": device ID
1385 * - "vendor": vendor ID
1386 * - "irq": device's IRQ if assigned (optional)
1387 * - "qdev_id": qdev id string
1388 * - "pci_bridge": It's a QDict, only present if this device is a
1389 * PCI bridge, contains:
1390 * - "bus": bus number
1391 * - "secondary": secondary bus number
1392 * - "subordinate": subordinate bus number
1393 * - "io_range": a QDict with memory range information
1394 * - "memory_range": a QDict with memory range information
1395 * - "prefetchable_range": a QDict with memory range information
1396 * - "devices": a QList of PCI devices if there's any attached (optional)
1397 * - "regions": a QList of QDicts, each QDict represents a
1398 * memory region of this device
1400 * The memory range QDict contains the following:
1402 * - "base": base memory address
1403 * - "limit": limit value
1405 * The region QDict can be an I/O region or a memory region,
1406 * an I/O region QDict contains the following:
1409 * - "bar": BAR number
1410 * - "address": memory address
1411 * - "size": memory size
1413 * A memory region QDict contains the following:
1415 * - "type": "memory"
1416 * - "bar": BAR number
1417 * - "address": memory address
1418 * - "size": memory size
1419 * - "mem_type_64": true or false
1420 * - "prefetch": true or false
1422 void do_pci_info(Monitor
*mon
, QObject
**ret_data
)
1425 struct PCIHostBus
*host
;
1427 bus_list
= qlist_new();
1429 QLIST_FOREACH(host
, &host_buses
, next
) {
1430 QObject
*obj
= pci_get_bus_dict(host
->bus
, 0);
1432 qlist_append_obj(bus_list
, obj
);
1436 *ret_data
= QOBJECT(bus_list
);
1439 static const char * const pci_nic_models
[] = {
1451 static const char * const pci_nic_names
[] = {
1463 /* Initialize a PCI NIC. */
1464 /* FIXME callers should check for failure, but don't */
1465 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1466 const char *default_devaddr
)
1468 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1475 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1479 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1481 error_report("Invalid PCI device address %s for device %s",
1482 devaddr
, pci_nic_names
[i
]);
1486 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1487 dev
= &pci_dev
->qdev
;
1489 dev
->id
= qemu_strdup(nd
->name
);
1490 qdev_set_nic_properties(dev
, nd
);
1491 if (qdev_init(dev
) < 0)
1496 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1497 const char *default_devaddr
)
1501 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1504 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1518 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1520 pci_update_mappings(d
);
1523 static void pci_bridge_update_mappings(PCIBus
*b
)
1527 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1529 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1530 pci_bridge_update_mappings(child
);
1534 static void pci_bridge_write_config(PCIDevice
*d
,
1535 uint32_t address
, uint32_t val
, int len
)
1537 pci_default_write_config(d
, address
, val
, len
);
1539 if (/* io base/limit */
1540 ranges_overlap(address
, len
, PCI_IO_BASE
, 2) ||
1542 /* memory base/limit, prefetchable base/limit and
1543 io base/limit upper 16 */
1544 ranges_overlap(address
, len
, PCI_MEMORY_BASE
, 20)) {
1545 pci_bridge_update_mappings(d
->bus
);
1549 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1557 if (pci_bus_num(bus
) == bus_num
) {
1562 if (!bus
->parent_dev
/* host pci bridge */ ||
1563 (bus
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1564 bus_num
<= bus
->parent_dev
->config
[PCI_SUBORDINATE_BUS
])) {
1565 for (; bus
; bus
= sec
) {
1566 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1567 assert(sec
->parent_dev
);
1568 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1571 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1572 bus_num
<= sec
->parent_dev
->config
[PCI_SUBORDINATE_BUS
]) {
1582 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
)
1584 bus
= pci_find_bus(bus
, bus_num
);
1589 return bus
->devices
[PCI_DEVFN(slot
, function
)];
1592 static int pci_bridge_initfn(PCIDevice
*dev
)
1594 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1596 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
1597 pci_config_set_device_id(s
->dev
.config
, s
->did
);
1599 pci_set_word(dev
->config
+ PCI_STATUS
,
1600 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1601 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
1602 dev
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_BRIDGE
;
1603 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
1604 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1608 static int pci_bridge_exitfn(PCIDevice
*pci_dev
)
1610 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, pci_dev
);
1611 PCIBus
*bus
= &s
->bus
;
1612 pci_unregister_secondary_bus(bus
);
1616 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
1617 pci_map_irq_fn map_irq
, const char *name
)
1622 dev
= pci_create(bus
, devfn
, "pci-bridge");
1623 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
1624 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
1625 qdev_init_nofail(&dev
->qdev
);
1627 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1628 pci_register_secondary_bus(bus
, &s
->bus
, &s
->dev
, map_irq
, name
);
1632 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
)
1634 return bus
->parent_dev
;
1637 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1639 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1640 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1644 /* initialize cap_present for pci_is_express() and pci_config_size() */
1645 if (info
->is_express
) {
1646 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1649 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1650 devfn
= pci_dev
->devfn
;
1651 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1652 info
->config_read
, info
->config_write
,
1654 if (pci_dev
== NULL
)
1656 rc
= info
->init(pci_dev
);
1661 if (pci_dev
->romfile
== NULL
&& info
->romfile
!= NULL
)
1662 pci_dev
->romfile
= qemu_strdup(info
->romfile
);
1663 pci_add_option_rom(pci_dev
);
1665 if (qdev
->hotplugged
)
1666 bus
->hotplug(bus
->hotplug_qdev
, pci_dev
, 1);
1670 static int pci_unplug_device(DeviceState
*qdev
)
1672 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1674 dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
, 0);
1678 void pci_qdev_register(PCIDeviceInfo
*info
)
1680 info
->qdev
.init
= pci_qdev_init
;
1681 info
->qdev
.unplug
= pci_unplug_device
;
1682 info
->qdev
.exit
= pci_unregister_device
;
1683 info
->qdev
.bus_info
= &pci_bus_info
;
1684 qdev_register(&info
->qdev
);
1687 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1689 while (info
->qdev
.name
) {
1690 pci_qdev_register(info
);
1695 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1699 dev
= qdev_create(&bus
->qbus
, name
);
1700 qdev_prop_set_uint32(dev
, "addr", devfn
);
1701 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1704 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1706 PCIDevice
*dev
= pci_create(bus
, devfn
, name
);
1707 qdev_init_nofail(&dev
->qdev
);
1711 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1713 int config_size
= pci_config_size(pdev
);
1714 int offset
= PCI_CONFIG_HEADER_SIZE
;
1716 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1719 else if (i
- offset
+ 1 == size
)
1724 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1729 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1732 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1733 prev
= next
+ PCI_CAP_LIST_NEXT
)
1734 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1742 static void pci_map_option_rom(PCIDevice
*pdev
, int region_num
, pcibus_t addr
, pcibus_t size
, int type
)
1744 cpu_register_physical_memory(addr
, size
, pdev
->rom_offset
);
1747 /* Add an option rom for the device */
1748 static int pci_add_option_rom(PCIDevice
*pdev
)
1756 if (strlen(pdev
->romfile
) == 0)
1759 if (!pdev
->rom_bar
) {
1761 * Load rom via fw_cfg instead of creating a rom bar,
1762 * for 0.11 compatibility.
1764 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1765 if (class == 0x0300) {
1766 rom_add_vga(pdev
->romfile
);
1768 rom_add_option(pdev
->romfile
);
1773 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1775 path
= qemu_strdup(pdev
->romfile
);
1778 size
= get_image_size(path
);
1780 error_report("%s: failed to find romfile \"%s\"",
1781 __FUNCTION__
, pdev
->romfile
);
1784 if (size
& (size
- 1)) {
1785 size
= 1 << qemu_fls(size
);
1788 pdev
->rom_offset
= qemu_ram_alloc(size
);
1790 ptr
= qemu_get_ram_ptr(pdev
->rom_offset
);
1791 load_image(path
, ptr
);
1794 pci_register_bar(pdev
, PCI_ROM_SLOT
, size
,
1795 0, pci_map_option_rom
);
1800 /* Reserve space and add capability to the linked list in pci config space */
1801 int pci_add_capability_at_offset(PCIDevice
*pdev
, uint8_t cap_id
,
1802 uint8_t offset
, uint8_t size
)
1804 uint8_t *config
= pdev
->config
+ offset
;
1805 config
[PCI_CAP_LIST_ID
] = cap_id
;
1806 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1807 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1808 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1809 memset(pdev
->used
+ offset
, 0xFF, size
);
1810 /* Make capability read-only by default */
1811 memset(pdev
->wmask
+ offset
, 0, size
);
1812 /* Check capability by default */
1813 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1817 /* Find and reserve space and add capability to the linked list
1818 * in pci config space */
1819 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1821 uint8_t offset
= pci_find_space(pdev
, size
);
1825 return pci_add_capability_at_offset(pdev
, cap_id
, offset
, size
);
1828 /* Unlink capability from the pci config space. */
1829 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1831 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1834 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1835 /* Make capability writeable again */
1836 memset(pdev
->wmask
+ offset
, 0xff, size
);
1837 /* Clear cmask as device-specific registers can't be checked */
1838 memset(pdev
->cmask
+ offset
, 0, size
);
1839 memset(pdev
->used
+ offset
, 0, size
);
1841 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1842 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1845 /* Reserve space for capability at a known offset (to call after load). */
1846 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1848 memset(pdev
->used
+ offset
, 0xff, size
);
1851 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1853 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1856 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1858 PCIDevice
*d
= (PCIDevice
*)dev
;
1859 const pci_class_desc
*desc
;
1864 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1865 desc
= pci_class_descriptions
;
1866 while (desc
->desc
&& class != desc
->class)
1869 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1871 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1874 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1875 "pci id %04x:%04x (sub %04x:%04x)\n",
1877 d
->config
[PCI_SECONDARY_BUS
],
1878 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1879 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1880 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1881 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1882 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1883 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1884 r
= &d
->io_regions
[i
];
1887 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1888 " [0x%"FMT_PCIBUS
"]\n",
1890 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1891 r
->addr
, r
->addr
+ r
->size
- 1);
1895 static PCIDeviceInfo bridge_info
= {
1896 .qdev
.name
= "pci-bridge",
1897 .qdev
.size
= sizeof(PCIBridge
),
1898 .init
= pci_bridge_initfn
,
1899 .exit
= pci_bridge_exitfn
,
1900 .config_write
= pci_bridge_write_config
,
1901 .header_type
= PCI_HEADER_TYPE_BRIDGE
,
1902 .qdev
.props
= (Property
[]) {
1903 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1904 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1905 DEFINE_PROP_END_OF_LIST(),
1909 static void pci_register_devices(void)
1911 pci_qdev_register(&bridge_info
);
1914 device_init(pci_register_devices
)