2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
46 static const int tcg_target_reg_alloc_order
[] = {
64 static const int tcg_target_call_iarg_regs
[6] = {
73 static const int tcg_target_call_oarg_regs
[2] = {
78 static uint8_t *tb_ret_addr
;
80 static void patch_reloc(uint8_t *code_ptr
, int type
,
81 tcg_target_long value
, tcg_target_long addend
)
86 if (value
!= (uint32_t)value
)
88 *(uint32_t *)code_ptr
= value
;
91 if (value
!= (int32_t)value
)
93 *(uint32_t *)code_ptr
= value
;
96 value
-= (long)code_ptr
;
97 if (value
!= (int32_t)value
)
99 *(uint32_t *)code_ptr
= value
;
106 /* maximum number of register used for input function arguments */
107 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
112 /* parse target specific constraints */
113 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
120 ct
->ct
|= TCG_CT_REG
;
121 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RAX
);
124 ct
->ct
|= TCG_CT_REG
;
125 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RBX
);
128 ct
->ct
|= TCG_CT_REG
;
129 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RCX
);
132 ct
->ct
|= TCG_CT_REG
;
133 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RDX
);
136 ct
->ct
|= TCG_CT_REG
;
137 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RSI
);
140 ct
->ct
|= TCG_CT_REG
;
141 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RDI
);
144 ct
->ct
|= TCG_CT_REG
;
145 tcg_regset_set32(ct
->u
.regs
, 0, 0xf);
148 ct
->ct
|= TCG_CT_REG
;
149 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
151 case 'L': /* qemu_ld/st constraint */
152 ct
->ct
|= TCG_CT_REG
;
153 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
154 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_RSI
);
155 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_RDI
);
158 ct
->ct
|= TCG_CT_CONST_S32
;
161 ct
->ct
|= TCG_CT_CONST_U32
;
171 /* test if a constant matches the constraint */
172 static inline int tcg_target_const_match(tcg_target_long val
,
173 const TCGArgConstraint
*arg_ct
)
177 if (ct
& TCG_CT_CONST
)
179 else if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
)
181 else if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
)
220 #define P_EXT 0x100 /* 0x0f opcode prefix */
221 #define P_REXW 0x200 /* set rex.w = 1 */
222 #define P_REXB_R 0x400 /* REG field as byte register */
223 #define P_REXB_RM 0x800 /* R/M field as byte register */
225 static const uint8_t tcg_cond_to_jcc
[10] = {
226 [TCG_COND_EQ
] = JCC_JE
,
227 [TCG_COND_NE
] = JCC_JNE
,
228 [TCG_COND_LT
] = JCC_JL
,
229 [TCG_COND_GE
] = JCC_JGE
,
230 [TCG_COND_LE
] = JCC_JLE
,
231 [TCG_COND_GT
] = JCC_JG
,
232 [TCG_COND_LTU
] = JCC_JB
,
233 [TCG_COND_GEU
] = JCC_JAE
,
234 [TCG_COND_LEU
] = JCC_JBE
,
235 [TCG_COND_GTU
] = JCC_JA
,
238 static void tcg_out_opc(TCGContext
*s
, int opc
, int r
, int rm
, int x
)
242 rex
|= (opc
& P_REXW
) >> 6; /* REX.W */
243 rex
|= (r
& 8) >> 1; /* REX.R */
244 rex
|= (x
& 8) >> 2; /* REX.X */
245 rex
|= (rm
& 8) >> 3; /* REX.B */
247 /* P_REXB_{R,RM} indicates that the given register is the low byte.
248 For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
249 as otherwise the encoding indicates %[abcd]h. Note that the values
250 that are ORed in merely indicate that the REX byte must be present;
251 those bits get discarded in output. */
252 rex
|= opc
& (r
>= 4 ? P_REXB_R
: 0);
253 rex
|= opc
& (rm
>= 4 ? P_REXB_RM
: 0);
256 tcg_out8(s
, (uint8_t)(rex
| 0x40));
261 tcg_out8(s
, opc
& 0xff);
264 static inline void tcg_out_modrm(TCGContext
*s
, int opc
, int r
, int rm
)
266 tcg_out_opc(s
, opc
, r
, rm
, 0);
267 tcg_out8(s
, 0xc0 | ((r
& 7) << 3) | (rm
& 7));
270 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
271 static inline void tcg_out_modrm_offset(TCGContext
*s
, int opc
, int r
, int rm
,
272 tcg_target_long offset
)
276 tcg_out_opc(s
, opc
, r
, 0, 0);
277 val
= offset
- ((tcg_target_long
)s
->code_ptr
+ 5 + (-rm
- 1));
278 if (val
== (int32_t)val
) {
280 tcg_out8(s
, 0x05 | ((r
& 7) << 3));
282 } else if (offset
== (int32_t)offset
) {
283 tcg_out8(s
, 0x04 | ((r
& 7) << 3));
284 tcg_out8(s
, 0x25); /* sib */
285 tcg_out32(s
, offset
);
289 } else if (offset
== 0 && (rm
& 7) != TCG_REG_RBP
) {
290 tcg_out_opc(s
, opc
, r
, rm
, 0);
291 if ((rm
& 7) == TCG_REG_RSP
) {
292 tcg_out8(s
, 0x04 | ((r
& 7) << 3));
295 tcg_out8(s
, 0x00 | ((r
& 7) << 3) | (rm
& 7));
297 } else if ((int8_t)offset
== offset
) {
298 tcg_out_opc(s
, opc
, r
, rm
, 0);
299 if ((rm
& 7) == TCG_REG_RSP
) {
300 tcg_out8(s
, 0x44 | ((r
& 7) << 3));
303 tcg_out8(s
, 0x40 | ((r
& 7) << 3) | (rm
& 7));
307 tcg_out_opc(s
, opc
, r
, rm
, 0);
308 if ((rm
& 7) == TCG_REG_RSP
) {
309 tcg_out8(s
, 0x84 | ((r
& 7) << 3));
312 tcg_out8(s
, 0x80 | ((r
& 7) << 3) | (rm
& 7));
314 tcg_out32(s
, offset
);
318 #if defined(CONFIG_SOFTMMU)
319 /* XXX: incomplete. index must be different from ESP */
320 static void tcg_out_modrm_offset2(TCGContext
*s
, int opc
, int r
, int rm
,
321 int index
, int shift
,
322 tcg_target_long offset
)
327 if (offset
== 0 && (rm
& 7) != TCG_REG_RBP
) {
329 } else if (offset
== (int8_t)offset
) {
331 } else if (offset
== (int32_t)offset
) {
337 tcg_out_opc(s
, opc
, r
, rm
, 0);
338 if ((rm
& 7) == TCG_REG_RSP
) {
339 tcg_out8(s
, mod
| ((r
& 7) << 3) | 0x04);
340 tcg_out8(s
, 0x04 | (rm
& 7));
342 tcg_out8(s
, mod
| ((r
& 7) << 3) | (rm
& 7));
345 tcg_out_opc(s
, opc
, r
, rm
, index
);
346 tcg_out8(s
, mod
| ((r
& 7) << 3) | 0x04);
347 tcg_out8(s
, (shift
<< 6) | ((index
& 7) << 3) | (rm
& 7));
351 } else if (mod
== 0x80) {
352 tcg_out32(s
, offset
);
357 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
359 tcg_out_modrm(s
, 0x8b | P_REXW
, ret
, arg
);
362 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
363 int ret
, tcg_target_long arg
)
366 tcg_out_modrm(s
, 0x01 | (ARITH_XOR
<< 3), ret
, ret
); /* xor r0,r0 */
367 } else if (arg
== (uint32_t)arg
|| type
== TCG_TYPE_I32
) {
368 tcg_out_opc(s
, 0xb8 + (ret
& 7), 0, ret
, 0);
370 } else if (arg
== (int32_t)arg
) {
371 tcg_out_modrm(s
, 0xc7 | P_REXW
, 0, ret
);
374 tcg_out_opc(s
, (0xb8 + (ret
& 7)) | P_REXW
, 0, ret
, 0);
376 tcg_out32(s
, arg
>> 32);
380 static void tcg_out_goto(TCGContext
*s
, int call
, uint8_t *target
)
384 disp
= target
- s
->code_ptr
- 5;
385 if (disp
== (target
- s
->code_ptr
- 5)) {
386 tcg_out8(s
, call
? 0xe8 : 0xe9);
389 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R10
, (tcg_target_long
) target
);
390 tcg_out_modrm(s
, 0xff, call
? 2 : 4, TCG_REG_R10
);
394 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int ret
,
395 int arg1
, tcg_target_long arg2
)
397 if (type
== TCG_TYPE_I32
)
398 tcg_out_modrm_offset(s
, 0x8b, ret
, arg1
, arg2
); /* movl */
400 tcg_out_modrm_offset(s
, 0x8b | P_REXW
, ret
, arg1
, arg2
); /* movq */
403 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
404 int arg1
, tcg_target_long arg2
)
406 if (type
== TCG_TYPE_I32
)
407 tcg_out_modrm_offset(s
, 0x89, arg
, arg1
, arg2
); /* movl */
409 tcg_out_modrm_offset(s
, 0x89 | P_REXW
, arg
, arg1
, arg2
); /* movq */
412 static inline void tgen_arithi32(TCGContext
*s
, int c
, int r0
, int32_t val
)
414 if ((c
== ARITH_ADD
&& val
== 1) || (c
== ARITH_SUB
&& val
== -1)) {
416 tcg_out_modrm(s
, 0xff, 0, r0
);
417 } else if ((c
== ARITH_ADD
&& val
== -1) || (c
== ARITH_SUB
&& val
== 1)) {
419 tcg_out_modrm(s
, 0xff, 1, r0
);
420 } else if (val
== (int8_t)val
) {
421 tcg_out_modrm(s
, 0x83, c
, r0
);
423 } else if (c
== ARITH_AND
&& val
== 0xffu
) {
425 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXB_RM
, r0
, r0
);
426 } else if (c
== ARITH_AND
&& val
== 0xffffu
) {
428 tcg_out_modrm(s
, 0xb7 | P_EXT
, r0
, r0
);
430 tcg_out_modrm(s
, 0x81, c
, r0
);
435 static inline void tgen_arithi64(TCGContext
*s
, int c
, int r0
, int64_t val
)
437 if ((c
== ARITH_ADD
&& val
== 1) || (c
== ARITH_SUB
&& val
== -1)) {
439 tcg_out_modrm(s
, 0xff | P_REXW
, 0, r0
);
440 } else if ((c
== ARITH_ADD
&& val
== -1) || (c
== ARITH_SUB
&& val
== 1)) {
442 tcg_out_modrm(s
, 0xff | P_REXW
, 1, r0
);
443 } else if (c
== ARITH_AND
&& val
== 0xffffffffu
) {
444 /* 32-bit mov zero extends */
445 tcg_out_modrm(s
, 0x8b, r0
, r0
);
446 } else if (c
== ARITH_AND
&& val
== (uint32_t)val
) {
447 /* AND with no high bits set can use a 32-bit operation. */
448 tgen_arithi32(s
, c
, r0
, (uint32_t)val
);
449 } else if (val
== (int8_t)val
) {
450 tcg_out_modrm(s
, 0x83 | P_REXW
, c
, r0
);
452 } else if (val
== (int32_t)val
) {
453 tcg_out_modrm(s
, 0x81 | P_REXW
, c
, r0
);
460 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
463 tgen_arithi64(s
, ARITH_ADD
, reg
, val
);
466 static void tcg_out_jxx(TCGContext
*s
, int opc
, int label_index
)
469 TCGLabel
*l
= &s
->labels
[label_index
];
472 val
= l
->u
.value
- (tcg_target_long
)s
->code_ptr
;
474 if ((int8_t)val1
== val1
) {
478 tcg_out8(s
, 0x70 + opc
);
483 tcg_out32(s
, val
- 5);
486 tcg_out8(s
, 0x80 + opc
);
487 tcg_out32(s
, val
- 6);
495 tcg_out8(s
, 0x80 + opc
);
497 tcg_out_reloc(s
, s
->code_ptr
, R_386_PC32
, label_index
, -4);
502 static void tcg_out_brcond(TCGContext
*s
, int cond
,
503 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
504 int label_index
, int rexw
)
509 tcg_out_modrm(s
, 0x85 | rexw
, arg1
, arg1
);
512 tgen_arithi64(s
, ARITH_CMP
, arg1
, arg2
);
514 tgen_arithi32(s
, ARITH_CMP
, arg1
, arg2
);
517 tcg_out_modrm(s
, 0x01 | (ARITH_CMP
<< 3) | rexw
, arg2
, arg1
);
519 tcg_out_jxx(s
, tcg_cond_to_jcc
[cond
], label_index
);
522 #if defined(CONFIG_SOFTMMU)
524 #include "../../softmmu_defs.h"
526 static void *qemu_ld_helpers
[4] = {
533 static void *qemu_st_helpers
[4] = {
541 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
,
544 int addr_reg
, data_reg
, r0
, r1
, mem_index
, s_bits
, bswap
, rexw
;
546 #if defined(CONFIG_SOFTMMU)
547 uint8_t *label1_ptr
, *label2_ptr
;
558 #if TARGET_LONG_BITS == 32
563 #if defined(CONFIG_SOFTMMU)
565 tcg_out_modrm(s
, 0x8b | rexw
, r1
, addr_reg
);
568 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
570 tcg_out_modrm(s
, 0xc1 | rexw
, 5, r1
); /* shr $x, r1 */
571 tcg_out8(s
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
573 tcg_out_modrm(s
, 0x81 | rexw
, 4, r0
); /* andl $x, r0 */
574 tcg_out32(s
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
576 tcg_out_modrm(s
, 0x81, 4, r1
); /* andl $x, r1 */
577 tcg_out32(s
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
579 /* lea offset(r1, env), r1 */
580 tcg_out_modrm_offset2(s
, 0x8d | P_REXW
, r1
, r1
, TCG_AREG0
, 0,
581 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_read
));
584 tcg_out_modrm_offset(s
, 0x3b | rexw
, r0
, r1
, 0);
587 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
590 tcg_out8(s
, 0x70 + JCC_JE
);
591 label1_ptr
= s
->code_ptr
;
594 /* XXX: move that code at the end of the TB */
595 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_RSI
, mem_index
);
596 tcg_out_goto(s
, 1, qemu_ld_helpers
[s_bits
]);
601 tcg_out_modrm(s
, 0xbe | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
605 tcg_out_modrm(s
, 0xbf | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
609 tcg_out_modrm(s
, 0x63 | P_REXW
, data_reg
, TCG_REG_RAX
);
613 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
617 tcg_out_modrm(s
, 0xb7 | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
622 tcg_out_modrm(s
, 0x8b, data_reg
, TCG_REG_RAX
);
625 tcg_out_mov(s
, data_reg
, TCG_REG_RAX
);
631 label2_ptr
= s
->code_ptr
;
635 *label1_ptr
= s
->code_ptr
- label1_ptr
- 1;
638 tcg_out_modrm_offset(s
, 0x03 | P_REXW
, r0
, r1
, offsetof(CPUTLBEntry
, addend
) -
639 offsetof(CPUTLBEntry
, addr_read
));
642 if (GUEST_BASE
== (int32_t)GUEST_BASE
) {
647 /* movq $GUEST_BASE, r0 */
648 tcg_out_opc(s
, (0xb8 + (r0
& 7)) | P_REXW
, 0, r0
, 0);
649 tcg_out32(s
, GUEST_BASE
);
650 tcg_out32(s
, GUEST_BASE
>> 32);
651 /* addq addr_reg, r0 */
652 tcg_out_modrm(s
, 0x01 | P_REXW
, addr_reg
, r0
);
656 #ifdef TARGET_WORDS_BIGENDIAN
664 tcg_out_modrm_offset(s
, 0xb6 | P_EXT
, data_reg
, r0
, offset
);
668 tcg_out_modrm_offset(s
, 0xbe | P_EXT
| rexw
, data_reg
, r0
, offset
);
672 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, data_reg
, r0
, offset
);
674 /* rolw $8, data_reg */
676 tcg_out_modrm(s
, 0xc1, 0, data_reg
);
683 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, data_reg
, r0
, offset
);
684 /* rolw $8, data_reg */
686 tcg_out_modrm(s
, 0xc1, 0, data_reg
);
689 /* movswX data_reg, data_reg */
690 tcg_out_modrm(s
, 0xbf | P_EXT
| rexw
, data_reg
, data_reg
);
693 tcg_out_modrm_offset(s
, 0xbf | P_EXT
| rexw
, data_reg
, r0
, offset
);
697 /* movl (r0), data_reg */
698 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, offset
);
701 tcg_out_opc(s
, (0xc8 + (data_reg
& 7)) | P_EXT
, 0, data_reg
, 0);
706 /* movl (r0), data_reg */
707 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, offset
);
709 tcg_out_opc(s
, (0xc8 + (data_reg
& 7)) | P_EXT
, 0, data_reg
, 0);
711 tcg_out_modrm(s
, 0x63 | P_REXW
, data_reg
, data_reg
);
714 tcg_out_modrm_offset(s
, 0x63 | P_REXW
, data_reg
, r0
, offset
);
718 /* movq (r0), data_reg */
719 tcg_out_modrm_offset(s
, 0x8b | P_REXW
, data_reg
, r0
, offset
);
722 tcg_out_opc(s
, (0xc8 + (data_reg
& 7)) | P_EXT
| P_REXW
, 0, data_reg
, 0);
729 #if defined(CONFIG_SOFTMMU)
731 *label2_ptr
= s
->code_ptr
- label2_ptr
- 1;
735 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
,
738 int addr_reg
, data_reg
, r0
, r1
, mem_index
, s_bits
, bswap
, rexw
;
740 #if defined(CONFIG_SOFTMMU)
741 uint8_t *label1_ptr
, *label2_ptr
;
753 #if TARGET_LONG_BITS == 32
758 #if defined(CONFIG_SOFTMMU)
760 tcg_out_modrm(s
, 0x8b | rexw
, r1
, addr_reg
);
763 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
765 tcg_out_modrm(s
, 0xc1 | rexw
, 5, r1
); /* shr $x, r1 */
766 tcg_out8(s
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
768 tcg_out_modrm(s
, 0x81 | rexw
, 4, r0
); /* andl $x, r0 */
769 tcg_out32(s
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
771 tcg_out_modrm(s
, 0x81, 4, r1
); /* andl $x, r1 */
772 tcg_out32(s
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
774 /* lea offset(r1, env), r1 */
775 tcg_out_modrm_offset2(s
, 0x8d | P_REXW
, r1
, r1
, TCG_AREG0
, 0,
776 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_write
));
779 tcg_out_modrm_offset(s
, 0x3b | rexw
, r0
, r1
, 0);
782 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
785 tcg_out8(s
, 0x70 + JCC_JE
);
786 label1_ptr
= s
->code_ptr
;
789 /* XXX: move that code at the end of the TB */
793 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXB_RM
, TCG_REG_RSI
, data_reg
);
797 tcg_out_modrm(s
, 0xb7 | P_EXT
, TCG_REG_RSI
, data_reg
);
801 tcg_out_modrm(s
, 0x8b, TCG_REG_RSI
, data_reg
);
805 tcg_out_mov(s
, TCG_REG_RSI
, data_reg
);
808 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_RDX
, mem_index
);
809 tcg_out_goto(s
, 1, qemu_st_helpers
[s_bits
]);
813 label2_ptr
= s
->code_ptr
;
817 *label1_ptr
= s
->code_ptr
- label1_ptr
- 1;
820 tcg_out_modrm_offset(s
, 0x03 | P_REXW
, r0
, r1
, offsetof(CPUTLBEntry
, addend
) -
821 offsetof(CPUTLBEntry
, addr_write
));
824 if (GUEST_BASE
== (int32_t)GUEST_BASE
) {
829 /* movq $GUEST_BASE, r0 */
830 tcg_out_opc(s
, (0xb8 + (r0
& 7)) | P_REXW
, 0, r0
, 0);
831 tcg_out32(s
, GUEST_BASE
);
832 tcg_out32(s
, GUEST_BASE
>> 32);
833 /* addq addr_reg, r0 */
834 tcg_out_modrm(s
, 0x01 | P_REXW
, addr_reg
, r0
);
838 #ifdef TARGET_WORDS_BIGENDIAN
846 tcg_out_modrm_offset(s
, 0x88 | P_REXB_R
, data_reg
, r0
, offset
);
850 tcg_out_modrm(s
, 0x8b, r1
, data_reg
); /* movl */
851 tcg_out8(s
, 0x66); /* rolw $8, %ecx */
852 tcg_out_modrm(s
, 0xc1, 0, r1
);
858 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, offset
);
862 tcg_out_modrm(s
, 0x8b, r1
, data_reg
); /* movl */
864 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
, 0, r1
, 0);
868 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, offset
);
872 tcg_out_mov(s
, r1
, data_reg
);
874 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
| P_REXW
, 0, r1
, 0);
878 tcg_out_modrm_offset(s
, 0x89 | P_REXW
, data_reg
, r0
, offset
);
884 #if defined(CONFIG_SOFTMMU)
886 *label2_ptr
= s
->code_ptr
- label2_ptr
- 1;
890 static inline void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
891 const int *const_args
)
896 case INDEX_op_exit_tb
:
897 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_RAX
, args
[0]);
898 tcg_out_goto(s
, 0, tb_ret_addr
);
900 case INDEX_op_goto_tb
:
901 if (s
->tb_jmp_offset
) {
902 /* direct jump method */
903 tcg_out8(s
, 0xe9); /* jmp im */
904 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
907 /* indirect jump method */
909 tcg_out_modrm_offset(s
, 0xff, 4, -1,
910 (tcg_target_long
)(s
->tb_next
+
913 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
917 tcg_out_goto(s
, 1, (void *) args
[0]);
919 tcg_out_modrm(s
, 0xff, 2, args
[0]);
924 tcg_out_goto(s
, 0, (void *) args
[0]);
926 tcg_out_modrm(s
, 0xff, 4, args
[0]);
930 tcg_out_jxx(s
, JCC_JMP
, args
[0]);
932 case INDEX_op_movi_i32
:
933 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], (uint32_t)args
[1]);
935 case INDEX_op_movi_i64
:
936 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
938 case INDEX_op_ld8u_i32
:
939 case INDEX_op_ld8u_i64
:
941 tcg_out_modrm_offset(s
, 0xb6 | P_EXT
, args
[0], args
[1], args
[2]);
943 case INDEX_op_ld8s_i32
:
945 tcg_out_modrm_offset(s
, 0xbe | P_EXT
, args
[0], args
[1], args
[2]);
947 case INDEX_op_ld8s_i64
:
949 tcg_out_modrm_offset(s
, 0xbe | P_EXT
| P_REXW
, args
[0], args
[1], args
[2]);
951 case INDEX_op_ld16u_i32
:
952 case INDEX_op_ld16u_i64
:
954 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, args
[0], args
[1], args
[2]);
956 case INDEX_op_ld16s_i32
:
958 tcg_out_modrm_offset(s
, 0xbf | P_EXT
, args
[0], args
[1], args
[2]);
960 case INDEX_op_ld16s_i64
:
962 tcg_out_modrm_offset(s
, 0xbf | P_EXT
| P_REXW
, args
[0], args
[1], args
[2]);
964 case INDEX_op_ld_i32
:
965 case INDEX_op_ld32u_i64
:
967 tcg_out_modrm_offset(s
, 0x8b, args
[0], args
[1], args
[2]);
969 case INDEX_op_ld32s_i64
:
971 tcg_out_modrm_offset(s
, 0x63 | P_REXW
, args
[0], args
[1], args
[2]);
973 case INDEX_op_ld_i64
:
975 tcg_out_modrm_offset(s
, 0x8b | P_REXW
, args
[0], args
[1], args
[2]);
978 case INDEX_op_st8_i32
:
979 case INDEX_op_st8_i64
:
981 tcg_out_modrm_offset(s
, 0x88 | P_REXB_R
, args
[0], args
[1], args
[2]);
983 case INDEX_op_st16_i32
:
984 case INDEX_op_st16_i64
:
987 tcg_out_modrm_offset(s
, 0x89, args
[0], args
[1], args
[2]);
989 case INDEX_op_st_i32
:
990 case INDEX_op_st32_i64
:
992 tcg_out_modrm_offset(s
, 0x89, args
[0], args
[1], args
[2]);
994 case INDEX_op_st_i64
:
996 tcg_out_modrm_offset(s
, 0x89 | P_REXW
, args
[0], args
[1], args
[2]);
999 case INDEX_op_sub_i32
:
1002 case INDEX_op_and_i32
:
1005 case INDEX_op_or_i32
:
1008 case INDEX_op_xor_i32
:
1011 case INDEX_op_add_i32
:
1014 if (const_args
[2]) {
1015 tgen_arithi32(s
, c
, args
[0], args
[2]);
1017 tcg_out_modrm(s
, 0x01 | (c
<< 3), args
[2], args
[0]);
1021 case INDEX_op_sub_i64
:
1024 case INDEX_op_and_i64
:
1027 case INDEX_op_or_i64
:
1030 case INDEX_op_xor_i64
:
1033 case INDEX_op_add_i64
:
1036 if (const_args
[2]) {
1037 tgen_arithi64(s
, c
, args
[0], args
[2]);
1039 tcg_out_modrm(s
, 0x01 | (c
<< 3) | P_REXW
, args
[2], args
[0]);
1043 case INDEX_op_mul_i32
:
1044 if (const_args
[2]) {
1047 if (val
== (int8_t)val
) {
1048 tcg_out_modrm(s
, 0x6b, args
[0], args
[0]);
1051 tcg_out_modrm(s
, 0x69, args
[0], args
[0]);
1055 tcg_out_modrm(s
, 0xaf | P_EXT
, args
[0], args
[2]);
1058 case INDEX_op_mul_i64
:
1059 if (const_args
[2]) {
1062 if (val
== (int8_t)val
) {
1063 tcg_out_modrm(s
, 0x6b | P_REXW
, args
[0], args
[0]);
1066 tcg_out_modrm(s
, 0x69 | P_REXW
, args
[0], args
[0]);
1070 tcg_out_modrm(s
, 0xaf | P_EXT
| P_REXW
, args
[0], args
[2]);
1073 case INDEX_op_div2_i32
:
1074 tcg_out_modrm(s
, 0xf7, 7, args
[4]);
1076 case INDEX_op_divu2_i32
:
1077 tcg_out_modrm(s
, 0xf7, 6, args
[4]);
1079 case INDEX_op_div2_i64
:
1080 tcg_out_modrm(s
, 0xf7 | P_REXW
, 7, args
[4]);
1082 case INDEX_op_divu2_i64
:
1083 tcg_out_modrm(s
, 0xf7 | P_REXW
, 6, args
[4]);
1086 case INDEX_op_shl_i32
:
1089 if (const_args
[2]) {
1091 tcg_out_modrm(s
, 0xd1, c
, args
[0]);
1093 tcg_out_modrm(s
, 0xc1, c
, args
[0]);
1094 tcg_out8(s
, args
[2]);
1097 tcg_out_modrm(s
, 0xd3, c
, args
[0]);
1100 case INDEX_op_shr_i32
:
1103 case INDEX_op_sar_i32
:
1106 case INDEX_op_rotl_i32
:
1109 case INDEX_op_rotr_i32
:
1113 case INDEX_op_shl_i64
:
1116 if (const_args
[2]) {
1118 tcg_out_modrm(s
, 0xd1 | P_REXW
, c
, args
[0]);
1120 tcg_out_modrm(s
, 0xc1 | P_REXW
, c
, args
[0]);
1121 tcg_out8(s
, args
[2]);
1124 tcg_out_modrm(s
, 0xd3 | P_REXW
, c
, args
[0]);
1127 case INDEX_op_shr_i64
:
1130 case INDEX_op_sar_i64
:
1133 case INDEX_op_rotl_i64
:
1136 case INDEX_op_rotr_i64
:
1140 case INDEX_op_brcond_i32
:
1141 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1144 case INDEX_op_brcond_i64
:
1145 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1149 case INDEX_op_bswap16_i32
:
1150 case INDEX_op_bswap16_i64
:
1152 tcg_out_modrm(s
, 0xc1, SHIFT_ROL
, args
[0]);
1155 case INDEX_op_bswap32_i32
:
1156 case INDEX_op_bswap32_i64
:
1157 tcg_out_opc(s
, (0xc8 + (args
[0] & 7)) | P_EXT
, 0, args
[0], 0);
1159 case INDEX_op_bswap64_i64
:
1160 tcg_out_opc(s
, (0xc8 + (args
[0] & 7)) | P_EXT
| P_REXW
, 0, args
[0], 0);
1163 case INDEX_op_neg_i32
:
1164 tcg_out_modrm(s
, 0xf7, 3, args
[0]);
1166 case INDEX_op_neg_i64
:
1167 tcg_out_modrm(s
, 0xf7 | P_REXW
, 3, args
[0]);
1170 case INDEX_op_not_i32
:
1171 tcg_out_modrm(s
, 0xf7, 2, args
[0]);
1173 case INDEX_op_not_i64
:
1174 tcg_out_modrm(s
, 0xf7 | P_REXW
, 2, args
[0]);
1177 case INDEX_op_ext8s_i32
:
1178 tcg_out_modrm(s
, 0xbe | P_EXT
| P_REXB_RM
, args
[0], args
[1]);
1180 case INDEX_op_ext16s_i32
:
1181 tcg_out_modrm(s
, 0xbf | P_EXT
, args
[0], args
[1]);
1183 case INDEX_op_ext8s_i64
:
1184 tcg_out_modrm(s
, 0xbe | P_EXT
| P_REXW
, args
[0], args
[1]);
1186 case INDEX_op_ext16s_i64
:
1187 tcg_out_modrm(s
, 0xbf | P_EXT
| P_REXW
, args
[0], args
[1]);
1189 case INDEX_op_ext32s_i64
:
1190 tcg_out_modrm(s
, 0x63 | P_REXW
, args
[0], args
[1]);
1192 case INDEX_op_ext8u_i32
:
1193 case INDEX_op_ext8u_i64
:
1194 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXB_RM
, args
[0], args
[1]);
1196 case INDEX_op_ext16u_i32
:
1197 case INDEX_op_ext16u_i64
:
1198 tcg_out_modrm(s
, 0xb7 | P_EXT
, args
[0], args
[1]);
1200 case INDEX_op_ext32u_i64
:
1201 tcg_out_modrm(s
, 0x8b, args
[0], args
[1]);
1204 case INDEX_op_qemu_ld8u
:
1205 tcg_out_qemu_ld(s
, args
, 0);
1207 case INDEX_op_qemu_ld8s
:
1208 tcg_out_qemu_ld(s
, args
, 0 | 4);
1210 case INDEX_op_qemu_ld16u
:
1211 tcg_out_qemu_ld(s
, args
, 1);
1213 case INDEX_op_qemu_ld16s
:
1214 tcg_out_qemu_ld(s
, args
, 1 | 4);
1216 case INDEX_op_qemu_ld32u
:
1217 tcg_out_qemu_ld(s
, args
, 2);
1219 case INDEX_op_qemu_ld32s
:
1220 tcg_out_qemu_ld(s
, args
, 2 | 4);
1222 case INDEX_op_qemu_ld64
:
1223 tcg_out_qemu_ld(s
, args
, 3);
1226 case INDEX_op_qemu_st8
:
1227 tcg_out_qemu_st(s
, args
, 0);
1229 case INDEX_op_qemu_st16
:
1230 tcg_out_qemu_st(s
, args
, 1);
1232 case INDEX_op_qemu_st32
:
1233 tcg_out_qemu_st(s
, args
, 2);
1235 case INDEX_op_qemu_st64
:
1236 tcg_out_qemu_st(s
, args
, 3);
1244 static int tcg_target_callee_save_regs
[] = {
1249 /* TCG_REG_R14, */ /* currently used for the global env, so no
1254 static inline void tcg_out_push(TCGContext
*s
, int reg
)
1256 tcg_out_opc(s
, (0x50 + (reg
& 7)), 0, reg
, 0);
1259 static inline void tcg_out_pop(TCGContext
*s
, int reg
)
1261 tcg_out_opc(s
, (0x58 + (reg
& 7)), 0, reg
, 0);
1264 /* Generate global QEMU prologue and epilogue code */
1265 void tcg_target_qemu_prologue(TCGContext
*s
)
1267 int i
, frame_size
, push_size
, stack_addend
;
1270 /* save all callee saved registers */
1271 for(i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); i
++) {
1272 tcg_out_push(s
, tcg_target_callee_save_regs
[i
]);
1275 /* reserve some stack space */
1276 push_size
= 8 + ARRAY_SIZE(tcg_target_callee_save_regs
) * 8;
1277 frame_size
= push_size
+ TCG_STATIC_CALL_ARGS_SIZE
;
1278 frame_size
= (frame_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
1279 ~(TCG_TARGET_STACK_ALIGN
- 1);
1280 stack_addend
= frame_size
- push_size
;
1281 tcg_out_addi(s
, TCG_REG_RSP
, -stack_addend
);
1283 tcg_out_modrm(s
, 0xff, 4, TCG_REG_RDI
); /* jmp *%rdi */
1286 tb_ret_addr
= s
->code_ptr
;
1287 tcg_out_addi(s
, TCG_REG_RSP
, stack_addend
);
1288 for(i
= ARRAY_SIZE(tcg_target_callee_save_regs
) - 1; i
>= 0; i
--) {
1289 tcg_out_pop(s
, tcg_target_callee_save_regs
[i
]);
1291 tcg_out8(s
, 0xc3); /* ret */
1294 static const TCGTargetOpDef x86_64_op_defs
[] = {
1295 { INDEX_op_exit_tb
, { } },
1296 { INDEX_op_goto_tb
, { } },
1297 { INDEX_op_call
, { "ri" } }, /* XXX: might need a specific constant constraint */
1298 { INDEX_op_jmp
, { "ri" } }, /* XXX: might need a specific constant constraint */
1299 { INDEX_op_br
, { } },
1301 { INDEX_op_mov_i32
, { "r", "r" } },
1302 { INDEX_op_movi_i32
, { "r" } },
1303 { INDEX_op_ld8u_i32
, { "r", "r" } },
1304 { INDEX_op_ld8s_i32
, { "r", "r" } },
1305 { INDEX_op_ld16u_i32
, { "r", "r" } },
1306 { INDEX_op_ld16s_i32
, { "r", "r" } },
1307 { INDEX_op_ld_i32
, { "r", "r" } },
1308 { INDEX_op_st8_i32
, { "r", "r" } },
1309 { INDEX_op_st16_i32
, { "r", "r" } },
1310 { INDEX_op_st_i32
, { "r", "r" } },
1312 { INDEX_op_add_i32
, { "r", "0", "ri" } },
1313 { INDEX_op_mul_i32
, { "r", "0", "ri" } },
1314 { INDEX_op_div2_i32
, { "a", "d", "0", "1", "r" } },
1315 { INDEX_op_divu2_i32
, { "a", "d", "0", "1", "r" } },
1316 { INDEX_op_sub_i32
, { "r", "0", "ri" } },
1317 { INDEX_op_and_i32
, { "r", "0", "ri" } },
1318 { INDEX_op_or_i32
, { "r", "0", "ri" } },
1319 { INDEX_op_xor_i32
, { "r", "0", "ri" } },
1321 { INDEX_op_shl_i32
, { "r", "0", "ci" } },
1322 { INDEX_op_shr_i32
, { "r", "0", "ci" } },
1323 { INDEX_op_sar_i32
, { "r", "0", "ci" } },
1324 { INDEX_op_rotl_i32
, { "r", "0", "ci" } },
1325 { INDEX_op_rotr_i32
, { "r", "0", "ci" } },
1327 { INDEX_op_brcond_i32
, { "r", "ri" } },
1329 { INDEX_op_mov_i64
, { "r", "r" } },
1330 { INDEX_op_movi_i64
, { "r" } },
1331 { INDEX_op_ld8u_i64
, { "r", "r" } },
1332 { INDEX_op_ld8s_i64
, { "r", "r" } },
1333 { INDEX_op_ld16u_i64
, { "r", "r" } },
1334 { INDEX_op_ld16s_i64
, { "r", "r" } },
1335 { INDEX_op_ld32u_i64
, { "r", "r" } },
1336 { INDEX_op_ld32s_i64
, { "r", "r" } },
1337 { INDEX_op_ld_i64
, { "r", "r" } },
1338 { INDEX_op_st8_i64
, { "r", "r" } },
1339 { INDEX_op_st16_i64
, { "r", "r" } },
1340 { INDEX_op_st32_i64
, { "r", "r" } },
1341 { INDEX_op_st_i64
, { "r", "r" } },
1343 { INDEX_op_add_i64
, { "r", "0", "re" } },
1344 { INDEX_op_mul_i64
, { "r", "0", "re" } },
1345 { INDEX_op_div2_i64
, { "a", "d", "0", "1", "r" } },
1346 { INDEX_op_divu2_i64
, { "a", "d", "0", "1", "r" } },
1347 { INDEX_op_sub_i64
, { "r", "0", "re" } },
1348 { INDEX_op_and_i64
, { "r", "0", "reZ" } },
1349 { INDEX_op_or_i64
, { "r", "0", "re" } },
1350 { INDEX_op_xor_i64
, { "r", "0", "re" } },
1352 { INDEX_op_shl_i64
, { "r", "0", "ci" } },
1353 { INDEX_op_shr_i64
, { "r", "0", "ci" } },
1354 { INDEX_op_sar_i64
, { "r", "0", "ci" } },
1355 { INDEX_op_rotl_i64
, { "r", "0", "ci" } },
1356 { INDEX_op_rotr_i64
, { "r", "0", "ci" } },
1358 { INDEX_op_brcond_i64
, { "r", "re" } },
1360 { INDEX_op_bswap16_i32
, { "r", "0" } },
1361 { INDEX_op_bswap16_i64
, { "r", "0" } },
1362 { INDEX_op_bswap32_i32
, { "r", "0" } },
1363 { INDEX_op_bswap32_i64
, { "r", "0" } },
1364 { INDEX_op_bswap64_i64
, { "r", "0" } },
1366 { INDEX_op_neg_i32
, { "r", "0" } },
1367 { INDEX_op_neg_i64
, { "r", "0" } },
1369 { INDEX_op_not_i32
, { "r", "0" } },
1370 { INDEX_op_not_i64
, { "r", "0" } },
1372 { INDEX_op_ext8s_i32
, { "r", "r"} },
1373 { INDEX_op_ext16s_i32
, { "r", "r"} },
1374 { INDEX_op_ext8s_i64
, { "r", "r"} },
1375 { INDEX_op_ext16s_i64
, { "r", "r"} },
1376 { INDEX_op_ext32s_i64
, { "r", "r"} },
1377 { INDEX_op_ext8u_i32
, { "r", "r"} },
1378 { INDEX_op_ext16u_i32
, { "r", "r"} },
1379 { INDEX_op_ext8u_i64
, { "r", "r"} },
1380 { INDEX_op_ext16u_i64
, { "r", "r"} },
1381 { INDEX_op_ext32u_i64
, { "r", "r"} },
1383 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1384 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1385 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1386 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1387 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1388 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1389 { INDEX_op_qemu_ld64
, { "r", "L" } },
1391 { INDEX_op_qemu_st8
, { "L", "L" } },
1392 { INDEX_op_qemu_st16
, { "L", "L" } },
1393 { INDEX_op_qemu_st32
, { "L", "L" } },
1394 { INDEX_op_qemu_st64
, { "L", "L" } },
1399 void tcg_target_init(TCGContext
*s
)
1402 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1405 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1406 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffff);
1407 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1408 (1 << TCG_REG_RDI
) |
1409 (1 << TCG_REG_RSI
) |
1410 (1 << TCG_REG_RDX
) |
1411 (1 << TCG_REG_RCX
) |
1414 (1 << TCG_REG_RAX
) |
1415 (1 << TCG_REG_R10
) |
1416 (1 << TCG_REG_R11
));
1418 tcg_regset_clear(s
->reserved_regs
);
1419 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_RSP
);
1421 tcg_add_target_add_op_defs(x86_64_op_defs
);