qemu/pci: clarify pci config load routine
[qemu/aliguori-queue.git] / qemu-char.h
blobc0654bca259546bac4b1499663b822eaa1f495b3
1 #ifndef QEMU_CHAR_H
2 #define QEMU_CHAR_H
4 #include "qemu-common.h"
5 #include "qemu-queue.h"
6 #include "qemu-option.h"
7 #include "qemu-config.h"
9 /* character device */
11 #define CHR_EVENT_BREAK 0 /* serial break char */
12 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
13 #define CHR_EVENT_RESET 2 /* new connection established */
14 #define CHR_EVENT_MUX_IN 3 /* mux-focus was set to this terminal */
15 #define CHR_EVENT_MUX_OUT 4 /* mux-focus will move on */
16 #define CHR_EVENT_CLOSED 5 /* connection closed */
19 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
20 typedef struct {
21 int speed;
22 int parity;
23 int data_bits;
24 int stop_bits;
25 } QEMUSerialSetParams;
27 #define CHR_IOCTL_SERIAL_SET_BREAK 2
29 #define CHR_IOCTL_PP_READ_DATA 3
30 #define CHR_IOCTL_PP_WRITE_DATA 4
31 #define CHR_IOCTL_PP_READ_CONTROL 5
32 #define CHR_IOCTL_PP_WRITE_CONTROL 6
33 #define CHR_IOCTL_PP_READ_STATUS 7
34 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
35 #define CHR_IOCTL_PP_EPP_READ 9
36 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
37 #define CHR_IOCTL_PP_EPP_WRITE 11
38 #define CHR_IOCTL_PP_DATA_DIR 12
40 #define CHR_IOCTL_SERIAL_SET_TIOCM 13
41 #define CHR_IOCTL_SERIAL_GET_TIOCM 14
43 #define CHR_TIOCM_CTS 0x020
44 #define CHR_TIOCM_CAR 0x040
45 #define CHR_TIOCM_DSR 0x100
46 #define CHR_TIOCM_RI 0x080
47 #define CHR_TIOCM_DTR 0x002
48 #define CHR_TIOCM_RTS 0x004
50 typedef void IOEventHandler(void *opaque, int event);
52 struct CharDriverState {
53 void (*init)(struct CharDriverState *s);
54 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
55 void (*chr_update_read_handler)(struct CharDriverState *s);
56 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
57 int (*get_msgfd)(struct CharDriverState *s);
58 IOEventHandler *chr_event;
59 IOCanRWHandler *chr_can_read;
60 IOReadHandler *chr_read;
61 void *handler_opaque;
62 void (*chr_send_event)(struct CharDriverState *chr, int event);
63 void (*chr_close)(struct CharDriverState *chr);
64 void (*chr_accept_input)(struct CharDriverState *chr);
65 void *opaque;
66 QEMUBH *bh;
67 char *label;
68 char *filename;
69 QTAILQ_ENTRY(CharDriverState) next;
72 CharDriverState *qemu_chr_open_opts(QemuOpts *opts,
73 void (*init)(struct CharDriverState *s));
74 CharDriverState *qemu_chr_open(const char *label, const char *filename, void (*init)(struct CharDriverState *s));
75 void qemu_chr_close(CharDriverState *chr);
76 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
77 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
78 void qemu_chr_send_event(CharDriverState *s, int event);
79 void qemu_chr_add_handlers(CharDriverState *s,
80 IOCanRWHandler *fd_can_read,
81 IOReadHandler *fd_read,
82 IOEventHandler *fd_event,
83 void *opaque);
84 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
85 void qemu_chr_reset(CharDriverState *s);
86 void qemu_chr_initial_reset(void);
87 int qemu_chr_can_read(CharDriverState *s);
88 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
89 int qemu_chr_get_msgfd(CharDriverState *s);
90 void qemu_chr_accept_input(CharDriverState *s);
91 void qemu_chr_info(Monitor *mon);
92 CharDriverState *qemu_chr_find(const char *name);
94 extern int term_escape_char;
96 /* async I/O support */
98 int qemu_set_fd_handler2(int fd,
99 IOCanRWHandler *fd_read_poll,
100 IOHandler *fd_read,
101 IOHandler *fd_write,
102 void *opaque);
103 int qemu_set_fd_handler(int fd,
104 IOHandler *fd_read,
105 IOHandler *fd_write,
106 void *opaque);
108 #endif