hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "qemu-timer.h"
  24 #include "sysemu.h"
  25 #include "i2c.h"
  26 #include "smbus.h"
  27
  28 //#define DEBUG
  29
  30 /* i82731AB (PIIX4) compatible power management function */
  31 #define PM_FREQ 3579545
  32
  33 #define ACPI_DBG_IO_ADDR  0xb044
  34
  35 typedef struct PIIX4PMState {
  36     PCIDevice dev;
  37     uint16_t pmsts;
  38     uint16_t pmen;
  39     uint16_t pmcntrl;
  40
  41     APMState apm;
  42
  43     QEMUTimer *tmr_timer;
  44     int64_t tmr_overflow_time;
  45
  46     PMSMBus smb;
  47
  48     qemu_irq irq;
  49     qemu_irq cmos_s3;
  50     qemu_irq smi_irq;
  51     int kvm_enabled;
  52 } PIIX4PMState;
  53
  54 #define RSM_STS (1 << 15)
  55 #define PWRBTN_STS (1 << 8)
  56 #define RTC_EN (1 << 10)
  57 #define PWRBTN_EN (1 << 8)
  58 #define GBL_EN (1 << 5)
  59 #define TMROF_EN (1 << 0)
  60
  61 #define SCI_EN (1 << 0)
  62
  63 #define SUS_EN (1 << 13)
  64
  65 #define ACPI_ENABLE 0xf1
  66 #define ACPI_DISABLE 0xf0
  67
  68 static PIIX4PMState *pm_state;
  69
  70 static uint32_t get_pmtmr(PIIX4PMState *s)
  71 {
  72     uint32_t d;
  73     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  74     return d & 0xffffff;
  75 }
  76
  77 static int get_pmsts(PIIX4PMState *s)
  78 {
  79     int64_t d;
  80
  81     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  82     if (d >= s->tmr_overflow_time)
  83         s->pmsts |= TMROF_EN;
  84     return s->pmsts;
  85 }
  86
  87 static void pm_update_sci(PIIX4PMState *s)
  88 {
  89     int sci_level, pmsts;
  90     int64_t expire_time;
  91
  92     pmsts = get_pmsts(s);
  93     sci_level = (((pmsts & s->pmen) &
  94                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
  95     qemu_set_irq(s->irq, sci_level);
  96     /* schedule a timer interruption if needed */
  97     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
  98         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ);
  99         qemu_mod_timer(s->tmr_timer, expire_time);
 100     } else {
 101         qemu_del_timer(s->tmr_timer);
 102     }
 103 }
 104
 105 static void pm_tmr_timer(void *opaque)
 106 {
 107     PIIX4PMState *s = opaque;
 108     pm_update_sci(s);
 109 }
 110
 111 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 112 {
 113     PIIX4PMState *s = opaque;
 114     addr &= 0x3f;
 115     switch(addr) {
 116     case 0x00:
 117         {
 118             int64_t d;
 119             int pmsts;
 120             pmsts = get_pmsts(s);
 121             if (pmsts & val & TMROF_EN) {
 122                 /* if TMRSTS is reset, then compute the new overflow time */
 123                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ,
 124                              get_ticks_per_sec());
 125                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 126             }
 127             s->pmsts &= ~val;
 128             pm_update_sci(s);
 129         }
 130         break;
 131     case 0x02:
 132         s->pmen = val;
 133         pm_update_sci(s);
 134         break;
 135     case 0x04:
 136         {
 137             int sus_typ;
 138             s->pmcntrl = val & ~(SUS_EN);
 139             if (val & SUS_EN) {
 140                 /* change suspend type */
 141                 sus_typ = (val >> 10) & 7;
 142                 switch(sus_typ) {
 143                 case 0: /* soft power off */
 144                     qemu_system_shutdown_request();
 145                     break;
 146                 case 1:
 147                     /* RSM_STS should be set on resume. Pretend that resume
 148                        was caused by power button */
 149                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 150                     qemu_system_reset_request();
 151                     if (s->cmos_s3) {
 152                         qemu_irq_raise(s->cmos_s3);
 153                     }
 154                 default:
 155                     break;
 156                 }
 157             }
 158         }
 159         break;
 160     default:
 161         break;
 162     }
 163 #ifdef DEBUG
 164     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 165 #endif
 166 }
 167
 168 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 169 {
 170     PIIX4PMState *s = opaque;
 171     uint32_t val;
 172
 173     addr &= 0x3f;
 174     switch(addr) {
 175     case 0x00:
 176         val = get_pmsts(s);
 177         break;
 178     case 0x02:
 179         val = s->pmen;
 180         break;
 181     case 0x04:
 182         val = s->pmcntrl;
 183         break;
 184     default:
 185         val = 0;
 186         break;
 187     }
 188 #ifdef DEBUG
 189     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 190 #endif
 191     return val;
 192 }
 193
 194 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 195 {
 196     //    PIIX4PMState *s = opaque;
 197 #ifdef DEBUG
 198     addr &= 0x3f;
 199     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 200 #endif
 201 }
 202
 203 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 204 {
 205     PIIX4PMState *s = opaque;
 206     uint32_t val;
 207
 208     addr &= 0x3f;
 209     switch(addr) {
 210     case 0x08:
 211         val = get_pmtmr(s);
 212         break;
 213     default:
 214         val = 0;
 215         break;
 216     }
 217 #ifdef DEBUG
 218     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 219 #endif
 220     return val;
 221 }
 222
 223 static void apm_ctrl_changed(uint32_t val, void *arg)
 224 {
 225     PIIX4PMState *s = arg;
 226
 227     /* ACPI specs 3.0, 4.7.2.5 */
 228     if (val == ACPI_ENABLE) {
 229         s->pmcntrl |= SCI_EN;
 230     } else if (val == ACPI_DISABLE) {
 231         s->pmcntrl &= ~SCI_EN;
 232     }
 233
 234     if (s->dev.config[0x5b] & (1 << 1)) {
 235         if (s->smi_irq) {
 236             qemu_irq_raise(s->smi_irq);
 237         }
 238     }
 239 }
 240
 241 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 242 {
 243 #if defined(DEBUG)
 244     printf("ACPI: DBG: 0x%08x\n", val);
 245 #endif
 246 }
 247
 248 static void pm_io_space_update(PIIX4PMState *s)
 249 {
 250     uint32_t pm_io_base;
 251
 252     if (s->dev.config[0x80] & 1) {
 253         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 254         pm_io_base &= 0xffc0;
 255
 256         /* XXX: need to improve memory and ioport allocation */
 257 #if defined(DEBUG)
 258         printf("PM: mapping to 0x%x\n", pm_io_base);
 259 #endif
 260         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 261         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 262         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 263         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 264     }
 265 }
 266
 267 static void pm_write_config(PCIDevice *d,
 268                             uint32_t address, uint32_t val, int len)
 269 {
 270     pci_default_write_config(d, address, val, len);
 271     if (range_covers_byte(address, len, 0x80))
 272         pm_io_space_update((PIIX4PMState *)d);
 273 }
 274
 275 static int vmstate_acpi_post_load(void *opaque, int version_id)
 276 {
 277     PIIX4PMState *s = opaque;
 278
 279     pm_io_space_update(s);
 280     return 0;
 281 }
 282
 283 static const VMStateDescription vmstate_acpi = {
 284     .name = "piix4_pm",
 285     .version_id = 1,
 286     .minimum_version_id = 1,
 287     .minimum_version_id_old = 1,
 288     .post_load = vmstate_acpi_post_load,
 289     .fields      = (VMStateField []) {
 290         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 291         VMSTATE_UINT16(pmsts, PIIX4PMState),
 292         VMSTATE_UINT16(pmen, PIIX4PMState),
 293         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 294         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 295         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 296         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 297         VMSTATE_END_OF_LIST()
 298     }
 299 };
 300
 301 static void piix4_reset(void *opaque)
 302 {
 303     PIIX4PMState *s = opaque;
 304     uint8_t *pci_conf = s->dev.config;
 305
 306     pci_conf[0x58] = 0;
 307     pci_conf[0x59] = 0;
 308     pci_conf[0x5a] = 0;
 309     pci_conf[0x5b] = 0;
 310
 311     if (s->kvm_enabled) {
 312         /* Mark SMM as already inited (until KVM supports SMM). */
 313         pci_conf[0x5B] = 0x02;
 314     }
 315 }
 316
 317 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 318 {
 319     PIIX4PMState *s = opaque;
 320
 321     if (!s) {
 322         qemu_system_shutdown_request();
 323     } else if (s->pmen & PWRBTN_EN) {
 324         s->pmsts |= PWRBTN_EN;
 325         pm_update_sci(s);
 326     }
 327 }
 328
 329 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 330                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 331                        int kvm_enabled)
 332 {
 333     PIIX4PMState *s;
 334     uint8_t *pci_conf;
 335
 336     s = (PIIX4PMState *)pci_register_device(bus,
 337                                          "PM", sizeof(PIIX4PMState),
 338                                          devfn, NULL, pm_write_config);
 339     pm_state = s;
 340     pci_conf = s->dev.config;
 341     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 342     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 343     pci_conf[0x06] = 0x80;
 344     pci_conf[0x07] = 0x02;
 345     pci_conf[0x08] = 0x03; // revision number
 346     pci_conf[0x09] = 0x00;
 347     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 348     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 349     pci_conf[0x3d] = 0x01; // interrupt pin 1
 350
 351     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 352
 353     /* APM */
 354     apm_init(&s->apm, apm_ctrl_changed, s);
 355
 356     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 357
 358     s->kvm_enabled = kvm_enabled;
 359     if (s->kvm_enabled) {
 360         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 361          * support SMM mode. */
 362         pci_conf[0x5B] = 0x02;
 363     }
 364
 365     /* XXX: which specification is used ? The i82731AB has different
 366        mappings */
 367     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 368     pci_conf[0x63] = 0x60;
 369     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 370         (serial_hds[1] != NULL ? 0x90 : 0);
 371
 372     pci_conf[0x90] = smb_io_base | 1;
 373     pci_conf[0x91] = smb_io_base >> 8;
 374     pci_conf[0xd2] = 0x09;
 375     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 376     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 377
 378     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 379
 380     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 381
 382     vmstate_register(0, &vmstate_acpi, s);
 383
 384     pm_smbus_init(NULL, &s->smb);
 385     s->irq = sci_irq;
 386     s->cmos_s3 = cmos_s3;
 387     s->smi_irq = smi_irq;
 388     qemu_register_reset(piix4_reset, s);
 389
 390     return s->smb.smbus;
 391 }
 392
 393 #define GPE_BASE 0xafe0
 394 #define PCI_BASE 0xae00
 395 #define PCI_EJ_BASE 0xae08
 396
 397 struct gpe_regs {
 398     uint16_t sts; /* status */
 399     uint16_t en;  /* enabled */
 400 };
 401
 402 struct pci_status {
 403     uint32_t up;
 404     uint32_t down;
 405 };
 406
 407 static struct gpe_regs gpe;
 408 static struct pci_status pci0_status;
 409
 410 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 411 {
 412     if (addr & 1)
 413         return (val >> 8) & 0xff;
 414     return val & 0xff;
 415 }
 416
 417 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 418 {
 419     uint32_t val = 0;
 420     struct gpe_regs *g = opaque;
 421     switch (addr) {
 422         case GPE_BASE:
 423         case GPE_BASE + 1:
 424             val = gpe_read_val(g->sts, addr);
 425             break;
 426         case GPE_BASE + 2:
 427         case GPE_BASE + 3:
 428             val = gpe_read_val(g->en, addr);
 429             break;
 430         default:
 431             break;
 432     }
 433
 434 #if defined(DEBUG)
 435     printf("gpe read %x == %x\n", addr, val);
 436 #endif
 437     return val;
 438 }
 439
 440 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 441 {
 442     if (addr & 1)
 443         *cur = (*cur & 0xff) | (val << 8);
 444     else
 445         *cur = (*cur & 0xff00) | (val & 0xff);
 446 }
 447
 448 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 449 {
 450     uint16_t x1, x0 = val & 0xff;
 451     int shift = (addr & 1) ? 8 : 0;
 452
 453     x1 = (*cur >> shift) & 0xff;
 454
 455     x1 = x1 & ~x0;
 456
 457     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 458 }
 459
 460 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 461 {
 462     struct gpe_regs *g = opaque;
 463     switch (addr) {
 464         case GPE_BASE:
 465         case GPE_BASE + 1:
 466             gpe_reset_val(&g->sts, addr, val);
 467             break;
 468         case GPE_BASE + 2:
 469         case GPE_BASE + 3:
 470             gpe_write_val(&g->en, addr, val);
 471             break;
 472         default:
 473             break;
 474    }
 475
 476 #if defined(DEBUG)
 477     printf("gpe write %x <== %d\n", addr, val);
 478 #endif
 479 }
 480
 481 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 482 {
 483     uint32_t val = 0;
 484     struct pci_status *g = opaque;
 485     switch (addr) {
 486         case PCI_BASE:
 487             val = g->up;
 488             break;
 489         case PCI_BASE + 4:
 490             val = g->down;
 491             break;
 492         default:
 493             break;
 494     }
 495
 496 #if defined(DEBUG)
 497     printf("pcihotplug read %x == %x\n", addr, val);
 498 #endif
 499     return val;
 500 }
 501
 502 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 503 {
 504     struct pci_status *g = opaque;
 505     switch (addr) {
 506         case PCI_BASE:
 507             g->up = val;
 508             break;
 509         case PCI_BASE + 4:
 510             g->down = val;
 511             break;
 512    }
 513
 514 #if defined(DEBUG)
 515     printf("pcihotplug write %x <== %d\n", addr, val);
 516 #endif
 517 }
 518
 519 static uint32_t pciej_read(void *opaque, uint32_t addr)
 520 {
 521 #if defined(DEBUG)
 522     printf("pciej read %x\n", addr);
 523 #endif
 524     return 0;
 525 }
 526
 527 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 528 {
 529     BusState *bus = opaque;
 530     DeviceState *qdev, *next;
 531     PCIDevice *dev;
 532     int slot = ffs(val) - 1;
 533
 534     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 535         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 536         if (PCI_SLOT(dev->devfn) == slot) {
 537             qdev_free(qdev);
 538         }
 539     }
 540
 541
 542 #if defined(DEBUG)
 543     printf("pciej write %x <== %d\n", addr, val);
 544 #endif
 545 }
 546
 547 static int piix4_device_hotplug(PCIDevice *dev, int state);
 548
 549 void piix4_acpi_system_hot_add_init(PCIBus *bus)
 550 {
 551     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 552     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 553
 554     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 555     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 556
 557     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 558     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 559
 560     pci_bus_hotplug(bus, piix4_device_hotplug);
 561 }
 562
 563 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 564 {
 565     g->sts |= 2;
 566     p->up |= (1 << slot);
 567 }
 568
 569 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 570 {
 571     g->sts |= 2;
 572     p->down |= (1 << slot);
 573 }
 574
 575 static int piix4_device_hotplug(PCIDevice *dev, int state)
 576 {
 577     int slot = PCI_SLOT(dev->devfn);
 578
 579     pci0_status.up = 0;
 580     pci0_status.down = 0;
 581     if (state)
 582         enable_device(&pci0_status, &gpe, slot);
 583     else
 584         disable_device(&pci0_status, &gpe, slot);
 585     if (gpe.en & 2) {
 586         qemu_set_irq(pm_state->irq, 1);
 587         qemu_set_irq(pm_state->irq, 0);
 588     }
 589     return 0;
 590 }
 591
 592 struct acpi_table_header
 593 {
 594     char signature [4];    /* ACPI signature (4 ASCII characters) */
 595     uint32_t length;          /* Length of table, in bytes, including header */
 596     uint8_t revision;         /* ACPI Specification minor version # */
 597     uint8_t checksum;         /* To make sum of entire table == 0 */
 598     char oem_id [6];       /* OEM identification */
 599     char oem_table_id [8]; /* OEM table identification */
 600     uint32_t oem_revision;    /* OEM revision number */
 601     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 602     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 603 } __attribute__((packed));
 604
 605 char *acpi_tables;
 606 size_t acpi_tables_len;
 607
 608 static int acpi_checksum(const uint8_t *data, int len)
 609 {
 610     int sum, i;
 611     sum = 0;
 612     for(i = 0; i < len; i++)
 613         sum += data[i];
 614     return (-sum) & 0xff;
 615 }
 616
 617 int acpi_table_add(const char *t)
 618 {
 619     static const char *dfl_id = "QEMUQEMU";
 620     char buf[1024], *p, *f;
 621     struct acpi_table_header acpi_hdr;
 622     unsigned long val;
 623     size_t off;
 624
 625     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 626
 627     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 628         strncpy(acpi_hdr.signature, buf, 4);
 629     } else {
 630         strncpy(acpi_hdr.signature, dfl_id, 4);
 631     }
 632     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 633         val = strtoul(buf, &p, 10);
 634         if (val > 255 || *p != '\0')
 635             goto out;
 636     } else {
 637         val = 1;
 638     }
 639     acpi_hdr.revision = (int8_t)val;
 640
 641     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 642         strncpy(acpi_hdr.oem_id, buf, 6);
 643     } else {
 644         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 645     }
 646
 647     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 648         strncpy(acpi_hdr.oem_table_id, buf, 8);
 649     } else {
 650         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 651     }
 652
 653     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 654         val = strtol(buf, &p, 10);
 655         if(*p != '\0')
 656             goto out;
 657     } else {
 658         val = 1;
 659     }
 660     acpi_hdr.oem_revision = cpu_to_le32(val);
 661
 662     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 663         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 664     } else {
 665         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 666     }
 667
 668     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 669         val = strtol(buf, &p, 10);
 670         if(*p != '\0')
 671             goto out;
 672     } else {
 673         val = 1;
 674     }
 675     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 676
 677     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 678          buf[0] = '\0';
 679     }
 680
 681     acpi_hdr.length = sizeof(acpi_hdr);
 682
 683     f = buf;
 684     while (buf[0]) {
 685         struct stat s;
 686         char *n = strchr(f, ':');
 687         if (n)
 688             *n = '\0';
 689         if(stat(f, &s) < 0) {
 690             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 691             goto out;
 692         }
 693         acpi_hdr.length += s.st_size;
 694         if (!n)
 695             break;
 696         *n = ':';
 697         f = n + 1;
 698     }
 699
 700     if (!acpi_tables) {
 701         acpi_tables_len = sizeof(uint16_t);
 702         acpi_tables = qemu_mallocz(acpi_tables_len);
 703     }
 704     p = acpi_tables + acpi_tables_len;
 705     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 706     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 707
 708     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 709     *(uint16_t*)p = acpi_hdr.length;
 710     p += sizeof(uint16_t);
 711     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 712     off = sizeof(acpi_hdr);
 713
 714     f = buf;
 715     while (buf[0]) {
 716         struct stat s;
 717         int fd;
 718         char *n = strchr(f, ':');
 719         if (n)
 720             *n = '\0';
 721         fd = open(f, O_RDONLY);
 722
 723         if(fd < 0)
 724             goto out;
 725         if(fstat(fd, &s) < 0) {
 726             close(fd);
 727             goto out;
 728         }
 729
 730         do {
 731             int r;
 732             r = read(fd, p + off, s.st_size);
 733             if (r > 0) {
 734                 off += r;
 735                 s.st_size -= r;
 736             } else if ((r < 0 && errno != EINTR) || r == 0) {
 737                 close(fd);
 738                 goto out;
 739             }
 740         } while(s.st_size);
 741
 742         close(fd);
 743         if (!n)
 744             break;
 745         f = n + 1;
 746     }
 747
 748     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
 749     /* increase number of tables */
 750     (*(uint16_t*)acpi_tables) =
 751             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
 752     return 0;
 753 out:
 754     if (acpi_tables) {
 755         qemu_free(acpi_tables);
 756         acpi_tables = NULL;
 757     }
 758     return -1;
 759 }