target-microblaze/cpu.h

   1 /*
   2  *  MicroBlaze virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_MICROBLAZE_H
  20 #define CPU_MICROBLAZE_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define CPUState struct CPUMBState
  25
  26 #include "cpu-defs.h"
  27 struct CPUMBState;
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "mmu.h"
  30 #endif
  31
  32 #define TARGET_HAS_ICE 1
  33
  34 #define ELF_MACHINE     EM_XILINX_MICROBLAZE
  35
  36 #define EXCP_NMI        1
  37 #define EXCP_MMU        2
  38 #define EXCP_IRQ        3
  39 #define EXCP_BREAK      4
  40 #define EXCP_HW_BREAK   5
  41 #define EXCP_HW_EXCP    6
  42
  43 /* Register aliases. R0 - R15 */
  44 #define R_SP     1
  45 #define SR_PC    0
  46 #define SR_MSR   1
  47 #define SR_EAR   3
  48 #define SR_ESR   5
  49 #define SR_FSR   7
  50 #define SR_BTR   0xb
  51 #define SR_EDR   0xd
  52
  53 /* MSR flags.  */
  54 #define MSR_BE  (1<<0) /* 0x001 */
  55 #define MSR_IE  (1<<1) /* 0x002 */
  56 #define MSR_C   (1<<2) /* 0x004 */
  57 #define MSR_BIP (1<<3) /* 0x008 */
  58 #define MSR_FSL (1<<4) /* 0x010 */
  59 #define MSR_ICE (1<<5) /* 0x020 */
  60 #define MSR_DZ  (1<<6) /* 0x040 */
  61 #define MSR_DCE (1<<7) /* 0x080 */
  62 #define MSR_EE  (1<<8) /* 0x100 */
  63 #define MSR_EIP (1<<9) /* 0x200 */
  64 #define MSR_CC  (1<<31)
  65
  66 /* Machine State Register (MSR) Fields */
  67 #define MSR_UM (1<<11) /* User Mode */
  68 #define MSR_UMS        (1<<12) /* User Mode Save */
  69 #define MSR_VM (1<<13) /* Virtual Mode */
  70 #define MSR_VMS        (1<<14) /* Virtual Mode Save */
  71
  72 #define MSR_KERNEL      MSR_EE|MSR_VM
  73 //#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  74 #define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  75 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  76
  77 /* Exception State Register (ESR) Fields */
  78 #define          ESR_DIZ       (1<<11) /* Zone Protection */
  79 #define          ESR_S         (1<<10) /* Store instruction */
  80
  81 #define          ESR_EC_FSL             0
  82 #define          ESR_EC_UNALIGNED_DATA  1
  83 #define          ESR_EC_ILLEGAL_OP      2
  84 #define          ESR_EC_INSN_BUS        3
  85 #define          ESR_EC_DATA_BUS        4
  86 #define          ESR_EC_DIVZERO         5
  87 #define          ESR_EC_FPU             6
  88 #define          ESR_EC_PRIVINSN        7
  89 #define          ESR_EC_DATA_STORAGE    8
  90 #define          ESR_EC_INSN_STORAGE    9
  91 #define          ESR_EC_DATA_TLB        10
  92 #define          ESR_EC_INSN_TLB        11
  93
  94 /* Version reg.  */
  95 /* Basic PVR mask */
  96 #define PVR0_PVR_FULL_MASK              0x80000000
  97 #define PVR0_USE_BARREL_MASK            0x40000000
  98 #define PVR0_USE_DIV_MASK               0x20000000
  99 #define PVR0_USE_HW_MUL_MASK            0x10000000
 100 #define PVR0_USE_FPU_MASK               0x08000000
 101 #define PVR0_USE_EXC_MASK               0x04000000
 102 #define PVR0_USE_ICACHE_MASK            0x02000000
 103 #define PVR0_USE_DCACHE_MASK            0x01000000
 104 #define PVR0_USE_MMU                    0x00800000      /* new */
 105 #define PVR0_VERSION_MASK               0x0000FF00
 106 #define PVR0_USER1_MASK                 0x000000FF
 107
 108 /* User 2 PVR mask */
 109 #define PVR1_USER2_MASK                 0xFFFFFFFF
 110
 111 /* Configuration PVR masks */
 112 #define PVR2_D_OPB_MASK                 0x80000000
 113 #define PVR2_D_LMB_MASK                 0x40000000
 114 #define PVR2_I_OPB_MASK                 0x20000000
 115 #define PVR2_I_LMB_MASK                 0x10000000
 116 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 117 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 118 #define PVR2_D_PLB_MASK                 0x02000000      /* new */
 119 #define PVR2_I_PLB_MASK                 0x01000000      /* new */
 120 #define PVR2_INTERCONNECT               0x00800000      /* new */
 121 #define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 122 #define PVR2_USE_FSL_EXC                0x00040000      /* new */
 123 #define PVR2_USE_MSR_INSTR              0x00020000
 124 #define PVR2_USE_PCMP_INSTR             0x00010000
 125 #define PVR2_AREA_OPTIMISED             0x00008000
 126 #define PVR2_USE_BARREL_MASK            0x00004000
 127 #define PVR2_USE_DIV_MASK               0x00002000
 128 #define PVR2_USE_HW_MUL_MASK            0x00001000
 129 #define PVR2_USE_FPU_MASK               0x00000800
 130 #define PVR2_USE_MUL64_MASK             0x00000400
 131 #define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 132 #define PVR2_USE_IPLBEXC                0x00000100
 133 #define PVR2_USE_DPLBEXC                0x00000080
 134 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 135 #define PVR2_UNALIGNED_EXC_MASK         0x00000020
 136 #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 137 #define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 138 #define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 139 #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 140 #define PVR2_FPU_EXC_MASK               0x00000001
 141
 142 /* Debug and exception PVR masks */
 143 #define PVR3_DEBUG_ENABLED_MASK         0x80000000
 144 #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 145 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 146 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 147 #define PVR3_FSL_LINKS_MASK             0x00000380
 148
 149 /* ICache config PVR masks */
 150 #define PVR4_USE_ICACHE_MASK            0x80000000
 151 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 152 #define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 153 #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 154 #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 155 #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 156
 157 /* DCache config PVR masks */
 158 #define PVR5_USE_DCACHE_MASK            0x80000000
 159 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 160 #define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 161 #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 162 #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 163 #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 164
 165 /* ICache base address PVR mask */
 166 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 167
 168 /* ICache high address PVR mask */
 169 #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 170
 171 /* DCache base address PVR mask */
 172 #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 173
 174 /* DCache high address PVR mask */
 175 #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 176
 177 /* Target family PVR mask */
 178 #define PVR10_TARGET_FAMILY_MASK        0xFF000000
 179
 180 /* MMU descrtiption */
 181 #define PVR11_USE_MMU                   0xC0000000
 182 #define PVR11_MMU_ITLB_SIZE             0x38000000
 183 #define PVR11_MMU_DTLB_SIZE             0x07000000
 184 #define PVR11_MMU_TLB_ACCESS            0x00C00000
 185 #define PVR11_MMU_ZONES                 0x003C0000
 186 /* MSR Reset value PVR mask */
 187 #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 188
 189
 190
 191 /* CPU flags.  */
 192
 193 /* Condition codes.  */
 194 #define CC_GE  5
 195 #define CC_GT  4
 196 #define CC_LE  3
 197 #define CC_LT  2
 198 #define CC_NE  1
 199 #define CC_EQ  0
 200
 201 #define NB_MMU_MODES    3
 202 typedef struct CPUMBState {
 203     uint32_t debug;
 204     uint32_t btaken;
 205     uint32_t btarget;
 206     uint32_t bimm;
 207
 208     uint32_t imm;
 209     uint32_t regs[33];
 210     uint32_t sregs[24];
 211
 212     /* Internal flags.  */
 213 #define IMM_FLAG        4
 214 #define MSR_EE_FLAG     (1 << 8)
 215 #define DRTI_FLAG       (1 << 16)
 216 #define DRTE_FLAG       (1 << 17)
 217 #define DRTB_FLAG       (1 << 18)
 218 #define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 219 /* TB dependant CPUState.  */
 220 #define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG \
 221                          | DRTE_FLAG | DRTB_FLAG | MSR_EE_FLAG)
 222     uint32_t iflags;
 223
 224     struct {
 225         uint32_t regs[16];
 226     } pvr;
 227
 228 #if !defined(CONFIG_USER_ONLY)
 229     /* Unified MMU.  */
 230     struct microblaze_mmu mmu;
 231 #endif
 232
 233     CPU_COMMON
 234 } CPUMBState;
 235
 236 CPUState *cpu_mb_init(const char *cpu_model);
 237 int cpu_mb_exec(CPUState *s);
 238 void cpu_mb_close(CPUState *s);
 239 void do_interrupt(CPUState *env);
 240 /* you can call this signal handler from your SIGBUS and SIGSEGV
 241    signal handlers to inform the virtual CPU of exceptions. non zero
 242    is returned if the signal was handled by the virtual CPU.  */
 243 int cpu_mb_signal_handler(int host_signum, void *pinfo,
 244                           void *puc);
 245
 246 enum {
 247     CC_OP_DYNAMIC, /* Use env->cc_op  */
 248     CC_OP_FLAGS,
 249     CC_OP_CMP,
 250 };
 251
 252 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 253 #define TARGET_PAGE_BITS 12
 254 #define MMAP_SHIFT TARGET_PAGE_BITS
 255
 256 #define cpu_init cpu_mb_init
 257 #define cpu_exec cpu_mb_exec
 258 #define cpu_gen_code cpu_mb_gen_code
 259 #define cpu_signal_handler cpu_mb_signal_handler
 260
 261 #define CPU_SAVE_VERSION 1
 262
 263 /* MMU modes definitions */
 264 #define MMU_MODE0_SUFFIX _nommu
 265 #define MMU_MODE1_SUFFIX _kernel
 266 #define MMU_MODE2_SUFFIX _user
 267 #define MMU_NOMMU_IDX   0
 268 #define MMU_KERNEL_IDX  1
 269 #define MMU_USER_IDX    2
 270 /* See NB_MMU_MODES further up the file.  */
 271
 272 static inline int cpu_mmu_index (CPUState *env)
 273 {
 274         /* Are we in nommu mode?.  */
 275         if (!(env->sregs[SR_MSR] & MSR_VM))
 276             return MMU_NOMMU_IDX;
 277
 278         if (env->sregs[SR_MSR] & MSR_UM)
 279             return MMU_USER_IDX;
 280         return MMU_KERNEL_IDX;
 281 }
 282
 283 int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 284                             int mmu_idx, int is_softmmu);
 285 #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
 286
 287 #if defined(CONFIG_USER_ONLY)
 288 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 289 {
 290     if (newsp)
 291         env->regs[R_SP] = newsp;
 292     env->regs[3] = 0;
 293 }
 294 #endif
 295
 296 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 297 {
 298 }
 299
 300 static inline int cpu_interrupts_enabled(CPUState *env)
 301 {
 302     return env->sregs[SR_MSR] & MSR_IE;
 303 }
 304
 305 #include "cpu-all.h"
 306 #include "exec-all.h"
 307
 308 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 309 {
 310     env->sregs[SR_PC] = tb->pc;
 311 }
 312
 313 static inline target_ulong cpu_get_pc(CPUState *env)
 314 {
 315     return env->sregs[SR_PC];
 316 }
 317
 318 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 319                                         target_ulong *cs_base, int *flags)
 320 {
 321     *pc = env->sregs[SR_PC];
 322     *cs_base = 0;
 323     env->iflags |= env->sregs[SR_MSR] & MSR_EE;
 324     *flags = env->iflags & IFLAGS_TB_MASK;
 325 }
 326
 327 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 328                           int is_asi, int size);
 329 #endif