openpic: merge mpic and openpic timer handling
[qemu/agraf.git] / hw / pc.h
blob2237e86446af120036dbcb0902d1da383c5c5bc6
1 #ifndef HW_PC_H
2 #define HW_PC_H
4 #include "qemu-common.h"
5 #include "memory.h"
6 #include "ioport.h"
7 #include "isa.h"
8 #include "fdc.h"
9 #include "net.h"
10 #include "memory.h"
11 #include "ioapic.h"
13 /* PC-style peripherals (also used by other machines). */
15 /* parallel.c */
16 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
18 ISADevice *dev;
20 dev = isa_try_create(bus, "isa-parallel");
21 if (!dev) {
22 return false;
24 qdev_prop_set_uint32(&dev->qdev, "index", index);
25 qdev_prop_set_chr(&dev->qdev, "chardev", chr);
26 if (qdev_init(&dev->qdev) < 0) {
27 return false;
29 return true;
32 bool parallel_mm_init(MemoryRegion *address_space,
33 hwaddr base, int it_shift, qemu_irq irq,
34 CharDriverState *chr);
36 /* i8259.c */
38 extern DeviceState *isa_pic;
39 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
40 qemu_irq *kvm_i8259_init(ISABus *bus);
41 int pic_read_irq(DeviceState *d);
42 int pic_get_output(DeviceState *d);
43 void pic_info(Monitor *mon);
44 void irq_info(Monitor *mon);
46 /* Global System Interrupts */
48 #define GSI_NUM_PINS IOAPIC_NUM_PINS
50 typedef struct GSIState {
51 qemu_irq i8259_irq[ISA_NUM_IRQS];
52 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
53 } GSIState;
55 void gsi_handler(void *opaque, int n, int level);
57 /* vmport.c */
58 static inline void vmport_init(ISABus *bus)
60 isa_create_simple(bus, "vmport");
62 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
63 void vmmouse_get_data(uint32_t *data);
64 void vmmouse_set_data(const uint32_t *data);
66 /* pckbd.c */
68 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
69 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
70 MemoryRegion *region, ram_addr_t size,
71 hwaddr mask);
72 void i8042_isa_mouse_fake_event(void *opaque);
73 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
75 /* pc.c */
76 extern int fd_bootchk;
78 void pc_register_ferr_irq(qemu_irq irq);
79 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
81 void pc_cpus_init(const char *cpu_model);
82 void *pc_memory_init(MemoryRegion *system_memory,
83 const char *kernel_filename,
84 const char *kernel_cmdline,
85 const char *initrd_filename,
86 ram_addr_t below_4g_mem_size,
87 ram_addr_t above_4g_mem_size,
88 MemoryRegion *rom_memory,
89 MemoryRegion **ram_memory);
90 qemu_irq *pc_allocate_cpu_irq(void);
91 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
92 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
93 ISADevice **rtc_state,
94 ISADevice **floppy,
95 bool no_vmport);
96 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
97 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
98 const char *boot_device,
99 ISADevice *floppy, BusState *ide0, BusState *ide1,
100 ISADevice *s);
101 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
102 void pc_pci_device_init(PCIBus *pci_bus);
104 typedef void (*cpu_set_smm_t)(int smm, void *arg);
105 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
107 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
109 /* acpi.c */
110 extern int acpi_enabled;
111 extern char *acpi_tables;
112 extern size_t acpi_tables_len;
114 void acpi_bios_init(void);
115 int acpi_table_add(const char *table_desc);
117 /* acpi_piix.c */
119 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
120 qemu_irq sci_irq, qemu_irq smi_irq,
121 int kvm_enabled, void *fw_cfg);
122 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
124 /* hpet.c */
125 extern int no_hpet;
127 /* piix_pci.c */
128 struct PCII440FXState;
129 typedef struct PCII440FXState PCII440FXState;
131 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
132 ISABus **isa_bus, qemu_irq *pic,
133 MemoryRegion *address_space_mem,
134 MemoryRegion *address_space_io,
135 ram_addr_t ram_size,
136 hwaddr pci_hole_start,
137 hwaddr pci_hole_size,
138 hwaddr pci_hole64_start,
139 hwaddr pci_hole64_size,
140 MemoryRegion *pci_memory,
141 MemoryRegion *ram_memory);
143 /* piix4.c */
144 extern PCIDevice *piix4_dev;
145 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
147 /* vga.c */
148 enum vga_retrace_method {
149 VGA_RETRACE_DUMB,
150 VGA_RETRACE_PRECISE
153 extern enum vga_retrace_method vga_retrace_method;
155 int isa_vga_mm_init(hwaddr vram_base,
156 hwaddr ctrl_base, int it_shift,
157 MemoryRegion *address_space);
159 /* ne2000.c */
160 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
162 ISADevice *dev;
164 qemu_check_nic_model(nd, "ne2k_isa");
166 dev = isa_try_create(bus, "ne2k_isa");
167 if (!dev) {
168 return false;
170 qdev_prop_set_uint32(&dev->qdev, "iobase", base);
171 qdev_prop_set_uint32(&dev->qdev, "irq", irq);
172 qdev_set_nic_properties(&dev->qdev, nd);
173 qdev_init_nofail(&dev->qdev);
174 return true;
177 /* pc_sysfw.c */
178 void pc_system_firmware_init(MemoryRegion *rom_memory);
180 /* e820 types */
181 #define E820_RAM 1
182 #define E820_RESERVED 2
183 #define E820_ACPI 3
184 #define E820_NVS 4
185 #define E820_UNUSABLE 5
187 int e820_add_entry(uint64_t, uint64_t, uint32_t);
189 #endif