hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "serial.h"
  27 #include "apic.h"
  28 #include "fdc.h"
  29 #include "ide.h"
  30 #include "pci.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "i8254.h"
  40 #include "pcspk.h"
  41 #include "msi.h"
  42 #include "sysbus.h"
  43 #include "sysemu.h"
  44 #include "kvm.h"
  45 #include "kvm_i386.h"
  46 #include "xen.h"
  47 #include "blockdev.h"
  48 #include "hw/block-common.h"
  49 #include "ui/qemu-spice.h"
  50 #include "memory.h"
  51 #include "exec-memory.h"
  52 #include "arch_init.h"
  53 #include "bitmap.h"
  54
  55 /* debug PC/ISA interrupts */
  56 //#define DEBUG_IRQ
  57
  58 #ifdef DEBUG_IRQ
  59 #define DPRINTF(fmt, ...)                                       \
  60     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  61 #else
  62 #define DPRINTF(fmt, ...)
  63 #endif
  64
  65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  66 #define ACPI_DATA_SIZE       0x10000
  67 #define BIOS_CFG_IOPORT 0x510
  68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  73
  74 #define E820_NR_ENTRIES         16
  75
  76 struct e820_entry {
  77     uint64_t address;
  78     uint64_t length;
  79     uint32_t type;
  80 } QEMU_PACKED __attribute((__aligned__(4)));
  81
  82 struct e820_table {
  83     uint32_t count;
  84     struct e820_entry entry[E820_NR_ENTRIES];
  85 } QEMU_PACKED __attribute((__aligned__(4)));
  86
  87 static struct e820_table e820_table;
  88 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  89
  90 void gsi_handler(void *opaque, int n, int level)
  91 {
  92     GSIState *s = opaque;
  93
  94     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  95     if (n < ISA_NUM_IRQS) {
  96         qemu_set_irq(s->i8259_irq[n], level);
  97     }
  98     qemu_set_irq(s->ioapic_irq[n], level);
  99 }
 100
 101 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 102                            unsigned size)
 103 {
 104 }
 105
 106 /* MSDOS compatibility mode FPU exception support */
 107 static qemu_irq ferr_irq;
 108
 109 void pc_register_ferr_irq(qemu_irq irq)
 110 {
 111     ferr_irq = irq;
 112 }
 113
 114 /* XXX: add IGNNE support */
 115 void cpu_set_ferr(CPUX86State *s)
 116 {
 117     qemu_irq_raise(ferr_irq);
 118 }
 119
 120 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 121                            unsigned size)
 122 {
 123     qemu_irq_lower(ferr_irq);
 124 }
 125
 126 /* TSC handling */
 127 uint64_t cpu_get_tsc(CPUX86State *env)
 128 {
 129     return cpu_get_ticks();
 130 }
 131
 132 /* SMM support */
 133
 134 static cpu_set_smm_t smm_set;
 135 static void *smm_arg;
 136
 137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 138 {
 139     assert(smm_set == NULL);
 140     assert(smm_arg == NULL);
 141     smm_set = callback;
 142     smm_arg = arg;
 143 }
 144
 145 void cpu_smm_update(CPUX86State *env)
 146 {
 147     if (smm_set && smm_arg && env == first_cpu)
 148         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 149 }
 150
 151
 152 /* IRQ handling */
 153 int cpu_get_pic_interrupt(CPUX86State *env)
 154 {
 155     int intno;
 156
 157     intno = apic_get_interrupt(env->apic_state);
 158     if (intno >= 0) {
 159         return intno;
 160     }
 161     /* read the irq from the PIC */
 162     if (!apic_accept_pic_intr(env->apic_state)) {
 163         return -1;
 164     }
 165
 166     intno = pic_read_irq(isa_pic);
 167     return intno;
 168 }
 169
 170 static void pic_irq_request(void *opaque, int irq, int level)
 171 {
 172     CPUX86State *env = first_cpu;
 173
 174     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 175     if (env->apic_state) {
 176         while (env) {
 177             if (apic_accept_pic_intr(env->apic_state)) {
 178                 apic_deliver_pic_intr(env->apic_state, level);
 179             }
 180             env = env->next_cpu;
 181         }
 182     } else {
 183         if (level)
 184             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 185         else
 186             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 187     }
 188 }
 189
 190 /* PC cmos mappings */
 191
 192 #define REG_EQUIPMENT_BYTE          0x14
 193
 194 static int cmos_get_fd_drive_type(FDriveType fd0)
 195 {
 196     int val;
 197
 198     switch (fd0) {
 199     case FDRIVE_DRV_144:
 200         /* 1.44 Mb 3"5 drive */
 201         val = 4;
 202         break;
 203     case FDRIVE_DRV_288:
 204         /* 2.88 Mb 3"5 drive */
 205         val = 5;
 206         break;
 207     case FDRIVE_DRV_120:
 208         /* 1.2 Mb 5"5 drive */
 209         val = 2;
 210         break;
 211     case FDRIVE_DRV_NONE:
 212     default:
 213         val = 0;
 214         break;
 215     }
 216     return val;
 217 }
 218
 219 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 220                          int16_t cylinders, int8_t heads, int8_t sectors)
 221 {
 222     rtc_set_memory(s, type_ofs, 47);
 223     rtc_set_memory(s, info_ofs, cylinders);
 224     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 225     rtc_set_memory(s, info_ofs + 2, heads);
 226     rtc_set_memory(s, info_ofs + 3, 0xff);
 227     rtc_set_memory(s, info_ofs + 4, 0xff);
 228     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 229     rtc_set_memory(s, info_ofs + 6, cylinders);
 230     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 231     rtc_set_memory(s, info_ofs + 8, sectors);
 232 }
 233
 234 /* convert boot_device letter to something recognizable by the bios */
 235 static int boot_device2nibble(char boot_device)
 236 {
 237     switch(boot_device) {
 238     case 'a':
 239     case 'b':
 240         return 0x01; /* floppy boot */
 241     case 'c':
 242         return 0x02; /* hard drive boot */
 243     case 'd':
 244         return 0x03; /* CD-ROM boot */
 245     case 'n':
 246         return 0x04; /* Network boot */
 247     }
 248     return 0;
 249 }
 250
 251 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 252 {
 253 #define PC_MAX_BOOT_DEVICES 3
 254     int nbds, bds[3] = { 0, };
 255     int i;
 256
 257     nbds = strlen(boot_device);
 258     if (nbds > PC_MAX_BOOT_DEVICES) {
 259         error_report("Too many boot devices for PC");
 260         return(1);
 261     }
 262     for (i = 0; i < nbds; i++) {
 263         bds[i] = boot_device2nibble(boot_device[i]);
 264         if (bds[i] == 0) {
 265             error_report("Invalid boot device for PC: '%c'",
 266                          boot_device[i]);
 267             return(1);
 268         }
 269     }
 270     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 271     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 272     return(0);
 273 }
 274
 275 static int pc_boot_set(void *opaque, const char *boot_device)
 276 {
 277     return set_boot_dev(opaque, boot_device, 0);
 278 }
 279
 280 typedef struct pc_cmos_init_late_arg {
 281     ISADevice *rtc_state;
 282     BusState *idebus[2];
 283 } pc_cmos_init_late_arg;
 284
 285 static void pc_cmos_init_late(void *opaque)
 286 {
 287     pc_cmos_init_late_arg *arg = opaque;
 288     ISADevice *s = arg->rtc_state;
 289     int16_t cylinders;
 290     int8_t heads, sectors;
 291     int val;
 292     int i, trans;
 293
 294     val = 0;
 295     if (ide_get_geometry(arg->idebus[0], 0,
 296                          &cylinders, &heads, &sectors) >= 0) {
 297         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 298         val |= 0xf0;
 299     }
 300     if (ide_get_geometry(arg->idebus[0], 1,
 301                          &cylinders, &heads, &sectors) >= 0) {
 302         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 303         val |= 0x0f;
 304     }
 305     rtc_set_memory(s, 0x12, val);
 306
 307     val = 0;
 308     for (i = 0; i < 4; i++) {
 309         /* NOTE: ide_get_geometry() returns the physical
 310            geometry.  It is always such that: 1 <= sects <= 63, 1
 311            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 312            geometry can be different if a translation is done. */
 313         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 314                              &cylinders, &heads, &sectors) >= 0) {
 315             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 316             assert((trans & ~3) == 0);
 317             val |= trans << (i * 2);
 318         }
 319     }
 320     rtc_set_memory(s, 0x39, val);
 321
 322     qemu_unregister_reset(pc_cmos_init_late, opaque);
 323 }
 324
 325 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 326                   const char *boot_device,
 327                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 328                   ISADevice *s)
 329 {
 330     int val, nb, i;
 331     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 332     static pc_cmos_init_late_arg arg;
 333
 334     /* various important CMOS locations needed by PC/Bochs bios */
 335
 336     /* memory size */
 337     /* base memory (first MiB) */
 338     val = MIN(ram_size / 1024, 640);
 339     rtc_set_memory(s, 0x15, val);
 340     rtc_set_memory(s, 0x16, val >> 8);
 341     /* extended memory (next 64MiB) */
 342     if (ram_size > 1024 * 1024) {
 343         val = (ram_size - 1024 * 1024) / 1024;
 344     } else {
 345         val = 0;
 346     }
 347     if (val > 65535)
 348         val = 65535;
 349     rtc_set_memory(s, 0x17, val);
 350     rtc_set_memory(s, 0x18, val >> 8);
 351     rtc_set_memory(s, 0x30, val);
 352     rtc_set_memory(s, 0x31, val >> 8);
 353     /* memory between 16MiB and 4GiB */
 354     if (ram_size > 16 * 1024 * 1024) {
 355         val = (ram_size - 16 * 1024 * 1024) / 65536;
 356     } else {
 357         val = 0;
 358     }
 359     if (val > 65535)
 360         val = 65535;
 361     rtc_set_memory(s, 0x34, val);
 362     rtc_set_memory(s, 0x35, val >> 8);
 363     /* memory above 4GiB */
 364     val = above_4g_mem_size / 65536;
 365     rtc_set_memory(s, 0x5b, val);
 366     rtc_set_memory(s, 0x5c, val >> 8);
 367     rtc_set_memory(s, 0x5d, val >> 16);
 368
 369     /* set the number of CPU */
 370     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 371
 372     /* set boot devices, and disable floppy signature check if requested */
 373     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 374         exit(1);
 375     }
 376
 377     /* floppy type */
 378     if (floppy) {
 379         for (i = 0; i < 2; i++) {
 380             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 381         }
 382     }
 383     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 384         cmos_get_fd_drive_type(fd_type[1]);
 385     rtc_set_memory(s, 0x10, val);
 386
 387     val = 0;
 388     nb = 0;
 389     if (fd_type[0] < FDRIVE_DRV_NONE) {
 390         nb++;
 391     }
 392     if (fd_type[1] < FDRIVE_DRV_NONE) {
 393         nb++;
 394     }
 395     switch (nb) {
 396     case 0:
 397         break;
 398     case 1:
 399         val |= 0x01; /* 1 drive, ready for boot */
 400         break;
 401     case 2:
 402         val |= 0x41; /* 2 drives, ready for boot */
 403         break;
 404     }
 405     val |= 0x02; /* FPU is there */
 406     val |= 0x04; /* PS/2 mouse installed */
 407     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 408
 409     /* hard drives */
 410     arg.rtc_state = s;
 411     arg.idebus[0] = idebus0;
 412     arg.idebus[1] = idebus1;
 413     qemu_register_reset(pc_cmos_init_late, &arg);
 414 }
 415
 416 /* port 92 stuff: could be split off */
 417 typedef struct Port92State {
 418     ISADevice dev;
 419     MemoryRegion io;
 420     uint8_t outport;
 421     qemu_irq *a20_out;
 422 } Port92State;
 423
 424 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 425                          unsigned size)
 426 {
 427     Port92State *s = opaque;
 428
 429     DPRINTF("port92: write 0x%02x\n", val);
 430     s->outport = val;
 431     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 432     if (val & 1) {
 433         qemu_system_reset_request();
 434     }
 435 }
 436
 437 static uint64_t port92_read(void *opaque, hwaddr addr,
 438                             unsigned size)
 439 {
 440     Port92State *s = opaque;
 441     uint32_t ret;
 442
 443     ret = s->outport;
 444     DPRINTF("port92: read 0x%02x\n", ret);
 445     return ret;
 446 }
 447
 448 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 449 {
 450     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 451
 452     s->a20_out = a20_out;
 453 }
 454
 455 static const VMStateDescription vmstate_port92_isa = {
 456     .name = "port92",
 457     .version_id = 1,
 458     .minimum_version_id = 1,
 459     .minimum_version_id_old = 1,
 460     .fields      = (VMStateField []) {
 461         VMSTATE_UINT8(outport, Port92State),
 462         VMSTATE_END_OF_LIST()
 463     }
 464 };
 465
 466 static void port92_reset(DeviceState *d)
 467 {
 468     Port92State *s = container_of(d, Port92State, dev.qdev);
 469
 470     s->outport &= ~1;
 471 }
 472
 473 static const MemoryRegionOps port92_ops = {
 474     .read = port92_read,
 475     .write = port92_write,
 476     .impl = {
 477         .min_access_size = 1,
 478         .max_access_size = 1,
 479     },
 480     .endianness = DEVICE_LITTLE_ENDIAN,
 481 };
 482
 483 static int port92_initfn(ISADevice *dev)
 484 {
 485     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 486
 487     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 488     isa_register_ioport(dev, &s->io, 0x92);
 489
 490     s->outport = 0;
 491     return 0;
 492 }
 493
 494 static void port92_class_initfn(ObjectClass *klass, void *data)
 495 {
 496     DeviceClass *dc = DEVICE_CLASS(klass);
 497     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 498     ic->init = port92_initfn;
 499     dc->no_user = 1;
 500     dc->reset = port92_reset;
 501     dc->vmsd = &vmstate_port92_isa;
 502 }
 503
 504 static TypeInfo port92_info = {
 505     .name          = "port92",
 506     .parent        = TYPE_ISA_DEVICE,
 507     .instance_size = sizeof(Port92State),
 508     .class_init    = port92_class_initfn,
 509 };
 510
 511 static void port92_register_types(void)
 512 {
 513     type_register_static(&port92_info);
 514 }
 515
 516 type_init(port92_register_types)
 517
 518 static void handle_a20_line_change(void *opaque, int irq, int level)
 519 {
 520     CPUX86State *cpu = opaque;
 521
 522     /* XXX: send to all CPUs ? */
 523     /* XXX: add logic to handle multiple A20 line sources */
 524     cpu_x86_set_a20(cpu, level);
 525 }
 526
 527 /***********************************************************/
 528 /* Bochs BIOS debug ports */
 529
 530 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 531 {
 532     static const char shutdown_str[8] = "Shutdown";
 533     static int shutdown_index = 0;
 534
 535     switch(addr) {
 536     case 0x8900:
 537         /* same as Bochs power off */
 538         if (val == shutdown_str[shutdown_index]) {
 539             shutdown_index++;
 540             if (shutdown_index == 8) {
 541                 shutdown_index = 0;
 542                 qemu_system_shutdown_request();
 543             }
 544         } else {
 545             shutdown_index = 0;
 546         }
 547         break;
 548
 549     case 0x501:
 550     case 0x502:
 551         exit((val << 1) | 1);
 552     }
 553 }
 554
 555 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 556 {
 557     int index = le32_to_cpu(e820_table.count);
 558     struct e820_entry *entry;
 559
 560     if (index >= E820_NR_ENTRIES)
 561         return -EBUSY;
 562     entry = &e820_table.entry[index++];
 563
 564     entry->address = cpu_to_le64(address);
 565     entry->length = cpu_to_le64(length);
 566     entry->type = cpu_to_le32(type);
 567
 568     e820_table.count = cpu_to_le32(index);
 569     return index;
 570 }
 571
 572 static const MemoryRegionPortio bochs_bios_portio_list[] = {
 573     { 0x500, 1, 1, .write = bochs_bios_write, }, /* 0x500 */
 574     { 0x501, 1, 1, .write = bochs_bios_write, }, /* 0x501 */
 575     { 0x501, 2, 2, .write = bochs_bios_write, }, /* 0x501 */
 576     { 0x8900, 1, 1, .write = bochs_bios_write, }, /* 0x8900 */
 577     PORTIO_END_OF_LIST(),
 578 };
 579
 580 static void *bochs_bios_init(void)
 581 {
 582     void *fw_cfg;
 583     uint8_t *smbios_table;
 584     size_t smbios_len;
 585     uint64_t *numa_fw_cfg;
 586     int i, j;
 587     PortioList *bochs_bios_port_list = g_new(PortioList, 1);
 588
 589     portio_list_init(bochs_bios_port_list, bochs_bios_portio_list,
 590                      NULL, "bochs-bios");
 591     portio_list_add(bochs_bios_port_list, get_system_io(), 0x0);
 592
 593     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 594
 595     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 596     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 597     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 598                      acpi_tables_len);
 599     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 600
 601     smbios_table = smbios_get_table(&smbios_len);
 602     if (smbios_table)
 603         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 604                          smbios_table, smbios_len);
 605     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 606                      sizeof(struct e820_table));
 607
 608     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 609                      sizeof(struct hpet_fw_config));
 610     /* allocate memory for the NUMA channel: one (64bit) word for the number
 611      * of nodes, one word for each VCPU->node and one word for each node to
 612      * hold the amount of memory.
 613      */
 614     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 615     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 616     for (i = 0; i < max_cpus; i++) {
 617         for (j = 0; j < nb_numa_nodes; j++) {
 618             if (test_bit(i, node_cpumask[j])) {
 619                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 620                 break;
 621             }
 622         }
 623     }
 624     for (i = 0; i < nb_numa_nodes; i++) {
 625         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 626     }
 627     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 628                      (1 + max_cpus + nb_numa_nodes) * 8);
 629
 630     return fw_cfg;
 631 }
 632
 633 static long get_file_size(FILE *f)
 634 {
 635     long where, size;
 636
 637     /* XXX: on Unix systems, using fstat() probably makes more sense */
 638
 639     where = ftell(f);
 640     fseek(f, 0, SEEK_END);
 641     size = ftell(f);
 642     fseek(f, where, SEEK_SET);
 643
 644     return size;
 645 }
 646
 647 static void load_linux(void *fw_cfg,
 648                        const char *kernel_filename,
 649                        const char *initrd_filename,
 650                        const char *kernel_cmdline,
 651                        hwaddr max_ram_size)
 652 {
 653     uint16_t protocol;
 654     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 655     uint32_t initrd_max;
 656     uint8_t header[8192], *setup, *kernel, *initrd_data;
 657     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 658     FILE *f;
 659     char *vmode;
 660
 661     /* Align to 16 bytes as a paranoia measure */
 662     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 663
 664     /* load the kernel header */
 665     f = fopen(kernel_filename, "rb");
 666     if (!f || !(kernel_size = get_file_size(f)) ||
 667         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 668         MIN(ARRAY_SIZE(header), kernel_size)) {
 669         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 670                 kernel_filename, strerror(errno));
 671         exit(1);
 672     }
 673
 674     /* kernel protocol version */
 675 #if 0
 676     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 677 #endif
 678     if (ldl_p(header+0x202) == 0x53726448)
 679         protocol = lduw_p(header+0x206);
 680     else {
 681         /* This looks like a multiboot kernel. If it is, let's stop
 682            treating it like a Linux kernel. */
 683         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 684                            kernel_cmdline, kernel_size, header))
 685             return;
 686         protocol = 0;
 687     }
 688
 689     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 690         /* Low kernel */
 691         real_addr    = 0x90000;
 692         cmdline_addr = 0x9a000 - cmdline_size;
 693         prot_addr    = 0x10000;
 694     } else if (protocol < 0x202) {
 695         /* High but ancient kernel */
 696         real_addr    = 0x90000;
 697         cmdline_addr = 0x9a000 - cmdline_size;
 698         prot_addr    = 0x100000;
 699     } else {
 700         /* High and recent kernel */
 701         real_addr    = 0x10000;
 702         cmdline_addr = 0x20000;
 703         prot_addr    = 0x100000;
 704     }
 705
 706 #if 0
 707     fprintf(stderr,
 708             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 709             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 710             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 711             real_addr,
 712             cmdline_addr,
 713             prot_addr);
 714 #endif
 715
 716     /* highest address for loading the initrd */
 717     if (protocol >= 0x203)
 718         initrd_max = ldl_p(header+0x22c);
 719     else
 720         initrd_max = 0x37ffffff;
 721
 722     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 723         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 724
 725     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 726     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 727     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 728                      (uint8_t*)strdup(kernel_cmdline),
 729                      strlen(kernel_cmdline)+1);
 730
 731     if (protocol >= 0x202) {
 732         stl_p(header+0x228, cmdline_addr);
 733     } else {
 734         stw_p(header+0x20, 0xA33F);
 735         stw_p(header+0x22, cmdline_addr-real_addr);
 736     }
 737
 738     /* handle vga= parameter */
 739     vmode = strstr(kernel_cmdline, "vga=");
 740     if (vmode) {
 741         unsigned int video_mode;
 742         /* skip "vga=" */
 743         vmode += 4;
 744         if (!strncmp(vmode, "normal", 6)) {
 745             video_mode = 0xffff;
 746         } else if (!strncmp(vmode, "ext", 3)) {
 747             video_mode = 0xfffe;
 748         } else if (!strncmp(vmode, "ask", 3)) {
 749             video_mode = 0xfffd;
 750         } else {
 751             video_mode = strtol(vmode, NULL, 0);
 752         }
 753         stw_p(header+0x1fa, video_mode);
 754     }
 755
 756     /* loader type */
 757     /* High nybble = B reserved for QEMU; low nybble is revision number.
 758        If this code is substantially changed, you may want to consider
 759        incrementing the revision. */
 760     if (protocol >= 0x200)
 761         header[0x210] = 0xB0;
 762
 763     /* heap */
 764     if (protocol >= 0x201) {
 765         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 766         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 767     }
 768
 769     /* load initrd */
 770     if (initrd_filename) {
 771         if (protocol < 0x200) {
 772             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 773             exit(1);
 774         }
 775
 776         initrd_size = get_image_size(initrd_filename);
 777         if (initrd_size < 0) {
 778             fprintf(stderr, "qemu: error reading initrd %s\n",
 779                     initrd_filename);
 780             exit(1);
 781         }
 782
 783         initrd_addr = (initrd_max-initrd_size) & ~4095;
 784
 785         initrd_data = g_malloc(initrd_size);
 786         load_image(initrd_filename, initrd_data);
 787
 788         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 789         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 790         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 791
 792         stl_p(header+0x218, initrd_addr);
 793         stl_p(header+0x21c, initrd_size);
 794     }
 795
 796     /* load kernel and setup */
 797     setup_size = header[0x1f1];
 798     if (setup_size == 0)
 799         setup_size = 4;
 800     setup_size = (setup_size+1)*512;
 801     kernel_size -= setup_size;
 802
 803     setup  = g_malloc(setup_size);
 804     kernel = g_malloc(kernel_size);
 805     fseek(f, 0, SEEK_SET);
 806     if (fread(setup, 1, setup_size, f) != setup_size) {
 807         fprintf(stderr, "fread() failed\n");
 808         exit(1);
 809     }
 810     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 811         fprintf(stderr, "fread() failed\n");
 812         exit(1);
 813     }
 814     fclose(f);
 815     memcpy(setup, header, MIN(sizeof(header), setup_size));
 816
 817     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 818     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 819     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 820
 821     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 822     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 823     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 824
 825     option_rom[nb_option_roms].name = "linuxboot.bin";
 826     option_rom[nb_option_roms].bootindex = 0;
 827     nb_option_roms++;
 828 }
 829
 830 #define NE2000_NB_MAX 6
 831
 832 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 833                                               0x280, 0x380 };
 834 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 835
 836 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 837 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 838
 839 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 840 {
 841     static int nb_ne2k = 0;
 842
 843     if (nb_ne2k == NE2000_NB_MAX)
 844         return;
 845     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 846                     ne2000_irq[nb_ne2k], nd);
 847     nb_ne2k++;
 848 }
 849
 850 DeviceState *cpu_get_current_apic(void)
 851 {
 852     if (cpu_single_env) {
 853         return cpu_single_env->apic_state;
 854     } else {
 855         return NULL;
 856     }
 857 }
 858
 859 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 860 {
 861     CPUX86State *s = opaque;
 862
 863     if (level) {
 864         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 865     }
 866 }
 867
 868 void pc_cpus_init(const char *cpu_model)
 869 {
 870     int i;
 871
 872     /* init CPUs */
 873     if (cpu_model == NULL) {
 874 #ifdef TARGET_X86_64
 875         cpu_model = "qemu64";
 876 #else
 877         cpu_model = "qemu32";
 878 #endif
 879     }
 880
 881     for (i = 0; i < smp_cpus; i++) {
 882         if (!cpu_x86_init(cpu_model)) {
 883             fprintf(stderr, "Unable to find x86 CPU definition\n");
 884             exit(1);
 885         }
 886     }
 887 }
 888
 889 void *pc_memory_init(MemoryRegion *system_memory,
 890                     const char *kernel_filename,
 891                     const char *kernel_cmdline,
 892                     const char *initrd_filename,
 893                     ram_addr_t below_4g_mem_size,
 894                     ram_addr_t above_4g_mem_size,
 895                     MemoryRegion *rom_memory,
 896                     MemoryRegion **ram_memory)
 897 {
 898     int linux_boot, i;
 899     MemoryRegion *ram, *option_rom_mr;
 900     MemoryRegion *ram_below_4g, *ram_above_4g;
 901     void *fw_cfg;
 902
 903     linux_boot = (kernel_filename != NULL);
 904
 905     /* Allocate RAM.  We allocate it as a single memory region and use
 906      * aliases to address portions of it, mostly for backwards compatibility
 907      * with older qemus that used qemu_ram_alloc().
 908      */
 909     ram = g_malloc(sizeof(*ram));
 910     memory_region_init_ram(ram, "pc.ram",
 911                            below_4g_mem_size + above_4g_mem_size);
 912     vmstate_register_ram_global(ram);
 913     *ram_memory = ram;
 914     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 915     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 916                              0, below_4g_mem_size);
 917     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 918     if (above_4g_mem_size > 0) {
 919         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 920         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 921                                  below_4g_mem_size, above_4g_mem_size);
 922         memory_region_add_subregion(system_memory, 0x100000000ULL,
 923                                     ram_above_4g);
 924     }
 925
 926
 927     /* Initialize PC system firmware */
 928     pc_system_firmware_init(rom_memory);
 929
 930     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
 931     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
 932     vmstate_register_ram_global(option_rom_mr);
 933     memory_region_add_subregion_overlap(rom_memory,
 934                                         PC_ROM_MIN_VGA,
 935                                         option_rom_mr,
 936                                         1);
 937
 938     fw_cfg = bochs_bios_init();
 939     rom_set_fw(fw_cfg);
 940
 941     if (linux_boot) {
 942         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 943     }
 944
 945     for (i = 0; i < nb_option_roms; i++) {
 946         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 947     }
 948     return fw_cfg;
 949 }
 950
 951 qemu_irq *pc_allocate_cpu_irq(void)
 952 {
 953     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 954 }
 955
 956 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
 957 {
 958     DeviceState *dev = NULL;
 959
 960     if (pci_bus) {
 961         PCIDevice *pcidev = pci_vga_init(pci_bus);
 962         dev = pcidev ? &pcidev->qdev : NULL;
 963     } else if (isa_bus) {
 964         ISADevice *isadev = isa_vga_init(isa_bus);
 965         dev = isadev ? &isadev->qdev : NULL;
 966     }
 967     return dev;
 968 }
 969
 970 static void cpu_request_exit(void *opaque, int irq, int level)
 971 {
 972     CPUX86State *env = cpu_single_env;
 973
 974     if (env && level) {
 975         cpu_exit(env);
 976     }
 977 }
 978
 979 static const MemoryRegionOps ioport80_io_ops = {
 980     .write = ioport80_write,
 981     .endianness = DEVICE_NATIVE_ENDIAN,
 982     .impl = {
 983         .min_access_size = 1,
 984         .max_access_size = 1,
 985     },
 986 };
 987
 988 static const MemoryRegionOps ioportF0_io_ops = {
 989     .write = ioportF0_write,
 990     .endianness = DEVICE_NATIVE_ENDIAN,
 991     .impl = {
 992         .min_access_size = 1,
 993         .max_access_size = 1,
 994     },
 995 };
 996
 997 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 998                           ISADevice **rtc_state,
 999                           ISADevice **floppy,
1000                           bool no_vmport)
1001 {
1002     int i;
1003     DriveInfo *fd[MAX_FD];
1004     DeviceState *hpet = NULL;
1005     int pit_isa_irq = 0;
1006     qemu_irq pit_alt_irq = NULL;
1007     qemu_irq rtc_irq = NULL;
1008     qemu_irq *a20_line;
1009     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1010     qemu_irq *cpu_exit_irq;
1011     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1012     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1013
1014     memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1);
1015     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1016
1017     memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1);
1018     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1019
1020     /*
1021      * Check if an HPET shall be created.
1022      *
1023      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1024      * when the HPET wants to take over. Thus we have to disable the latter.
1025      */
1026     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1027         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1028
1029         if (hpet) {
1030             for (i = 0; i < GSI_NUM_PINS; i++) {
1031                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1032             }
1033             pit_isa_irq = -1;
1034             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1035             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1036         }
1037     }
1038     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1039
1040     qemu_register_boot_set(pc_boot_set, *rtc_state);
1041
1042     if (!xen_enabled()) {
1043         if (kvm_irqchip_in_kernel()) {
1044             pit = kvm_pit_init(isa_bus, 0x40);
1045         } else {
1046             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1047         }
1048         if (hpet) {
1049             /* connect PIT to output control line of the HPET */
1050             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1051         }
1052         pcspk_init(isa_bus, pit);
1053     }
1054
1055     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1056         if (serial_hds[i]) {
1057             serial_isa_init(isa_bus, i, serial_hds[i]);
1058         }
1059     }
1060
1061     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1062         if (parallel_hds[i]) {
1063             parallel_init(isa_bus, i, parallel_hds[i]);
1064         }
1065     }
1066
1067     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1068     i8042 = isa_create_simple(isa_bus, "i8042");
1069     i8042_setup_a20_line(i8042, &a20_line[0]);
1070     if (!no_vmport) {
1071         vmport_init(isa_bus);
1072         vmmouse = isa_try_create(isa_bus, "vmmouse");
1073     } else {
1074         vmmouse = NULL;
1075     }
1076     if (vmmouse) {
1077         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1078         qdev_init_nofail(&vmmouse->qdev);
1079     }
1080     port92 = isa_create_simple(isa_bus, "port92");
1081     port92_init(port92, &a20_line[1]);
1082
1083     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1084     DMA_init(0, cpu_exit_irq);
1085
1086     for(i = 0; i < MAX_FD; i++) {
1087         fd[i] = drive_get(IF_FLOPPY, 0, i);
1088     }
1089     *floppy = fdctrl_init_isa(isa_bus, fd);
1090 }
1091
1092 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1093 {
1094     int i;
1095
1096     for (i = 0; i < nb_nics; i++) {
1097         NICInfo *nd = &nd_table[i];
1098
1099         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1100             pc_init_ne2k_isa(isa_bus, nd);
1101         } else {
1102             pci_nic_init_nofail(nd, "e1000", NULL);
1103         }
1104     }
1105 }
1106
1107 void pc_pci_device_init(PCIBus *pci_bus)
1108 {
1109     int max_bus;
1110     int bus;
1111
1112     max_bus = drive_get_max_bus(IF_SCSI);
1113     for (bus = 0; bus <= max_bus; bus++) {
1114         pci_create_simple(pci_bus, -1, "lsi53c895a");
1115     }
1116 }
1117
1118 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1119 {
1120     DeviceState *dev;
1121     SysBusDevice *d;
1122     unsigned int i;
1123
1124     if (kvm_irqchip_in_kernel()) {
1125         dev = qdev_create(NULL, "kvm-ioapic");
1126     } else {
1127         dev = qdev_create(NULL, "ioapic");
1128     }
1129     if (parent_name) {
1130         object_property_add_child(object_resolve_path(parent_name, NULL),
1131                                   "ioapic", OBJECT(dev), NULL);
1132     }
1133     qdev_init_nofail(dev);
1134     d = sysbus_from_qdev(dev);
1135     sysbus_mmio_map(d, 0, 0xfec00000);
1136
1137     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1138         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1139     }
1140 }