hw/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/fifo8.h"
  30 #include "hw/ssi.h"
  31 #include "qemu/bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59
  60 /* interrupt mechanism */
  61 #define R_INTR_STATUS       (0x04 / 4)
  62 #define R_INTR_EN           (0x08 / 4)
  63 #define R_INTR_DIS          (0x0C / 4)
  64 #define R_INTR_MASK         (0x10 / 4)
  65 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  66 #define IXR_RX_FIFO_FULL        (1 << 5)
  67 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  68 #define IXR_TX_FIFO_FULL        (1 << 3)
  69 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  70 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  71 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  72 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  73
  74 #define R_EN                (0x14 / 4)
  75 #define R_DELAY             (0x18 / 4)
  76 #define R_TX_DATA           (0x1C / 4)
  77 #define R_RX_DATA           (0x20 / 4)
  78 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  79 #define R_TX_THRES          (0x28 / 4)
  80 #define R_RX_THRES          (0x2C / 4)
  81 #define R_TXD1              (0x80 / 4)
  82 #define R_TXD2              (0x84 / 4)
  83 #define R_TXD3              (0x88 / 4)
  84
  85 #define R_LQSPI_CFG         (0xa0 / 4)
  86 #define R_LQSPI_CFG_RESET       0x03A002EB
  87 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  88 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  89 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  90 #define LQSPI_CFG_U_PAGE        (1 << 28)
  91 #define LQSPI_CFG_MODE_EN       (1 << 25)
  92 #define LQSPI_CFG_MODE_WIDTH    8
  93 #define LQSPI_CFG_MODE_SHIFT    16
  94 #define LQSPI_CFG_DUMMY_WIDTH   3
  95 #define LQSPI_CFG_DUMMY_SHIFT   8
  96 #define LQSPI_CFG_INST_CODE     0xFF
  97
  98 #define R_LQSPI_STS         (0xA4 / 4)
  99 #define LQSPI_STS_WR_RECVD      (1 << 1)
 100
 101 #define R_MOD_ID            (0xFC / 4)
 102
 103 #define R_MAX (R_MOD_ID+1)
 104
 105 /* size of TXRX FIFOs */
 106 #define RXFF_A          32
 107 #define TXFF_A          32
 108
 109 /* 16MB per linear region */
 110 #define LQSPI_ADDRESS_BITS 24
 111 /* Bite off 4k chunks at a time */
 112 #define LQSPI_CACHE_SIZE 1024
 113
 114 #define SNOOP_CHECKING 0xFF
 115 #define SNOOP_NONE 0xFE
 116 #define SNOOP_STRIPING 0
 117
 118 typedef enum {
 119     READ = 0x3,
 120     FAST_READ = 0xb,
 121     DOR = 0x3b,
 122     QOR = 0x6b,
 123     DIOR = 0xbb,
 124     QIOR = 0xeb,
 125
 126     PP = 0x2,
 127     DPP = 0xa2,
 128     QPP = 0x32,
 129 } FlashCMD;
 130
 131 typedef struct {
 132     SysBusDevice busdev;
 133     MemoryRegion iomem;
 134     MemoryRegion mmlqspi;
 135
 136     qemu_irq irq;
 137     int irqline;
 138
 139     uint8_t num_cs;
 140     uint8_t num_busses;
 141
 142     uint8_t snoop_state;
 143     qemu_irq *cs_lines;
 144     SSIBus **spi;
 145
 146     Fifo8 rx_fifo;
 147     Fifo8 tx_fifo;
 148
 149     uint8_t num_txrx_bytes;
 150
 151     uint32_t regs[R_MAX];
 152
 153     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 154     hwaddr lqspi_cached_addr;
 155 } XilinxSPIPS;
 156
 157 #define TYPE_XILINX_SPIPS "xilinx,spips"
 158
 159 #define XILINX_SPIPS(obj) \
 160      OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 161
 162 static inline int num_effective_busses(XilinxSPIPS *s)
 163 {
 164     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 165             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 166 }
 167
 168 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 169 {
 170     int i, j;
 171     bool found = false;
 172     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 173
 174     for (i = 0; i < s->num_cs; i++) {
 175         for (j = 0; j < num_effective_busses(s); j++) {
 176             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 177             int cs_to_set = (j * s->num_cs + i + upage) %
 178                                 (s->num_cs * s->num_busses);
 179
 180             if (~field & (1 << i) && !found) {
 181                 DB_PRINT("selecting slave %d\n", i);
 182                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 183             } else {
 184                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 185             }
 186         }
 187         if (~field & (1 << i)) {
 188             found = true;
 189         }
 190     }
 191     if (!found) {
 192         s->snoop_state = SNOOP_CHECKING;
 193     }
 194 }
 195
 196 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 197 {
 198     /* These are set/cleared as they occur */
 199     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 200                                 IXR_TX_FIFO_MODE_FAIL);
 201     /* these are pure functions of fifo state, set them here */
 202     s->regs[R_INTR_STATUS] |=
 203         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 204         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 205         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 206         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 207     /* drive external interrupt pin */
 208     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 209                                                                 IXR_ALL);
 210     if (new_irqline != s->irqline) {
 211         s->irqline = new_irqline;
 212         qemu_set_irq(s->irq, s->irqline);
 213     }
 214 }
 215
 216 static void xilinx_spips_reset(DeviceState *d)
 217 {
 218     XilinxSPIPS *s = XILINX_SPIPS(d);
 219
 220     int i;
 221     for (i = 0; i < R_MAX; i++) {
 222         s->regs[i] = 0;
 223     }
 224
 225     fifo8_reset(&s->rx_fifo);
 226     fifo8_reset(&s->rx_fifo);
 227     /* non zero resets */
 228     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 229     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 230     s->regs[R_TX_THRES] = 1;
 231     s->regs[R_RX_THRES] = 1;
 232     /* FIXME: move magic number definition somewhere sensible */
 233     s->regs[R_MOD_ID] = 0x01090106;
 234     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 235     s->snoop_state = SNOOP_CHECKING;
 236     xilinx_spips_update_ixr(s);
 237     xilinx_spips_update_cs_lines(s);
 238 }
 239
 240 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 241 {
 242     for (;;) {
 243         int i;
 244         uint8_t rx;
 245         uint8_t tx = 0;
 246
 247         for (i = 0; i < num_effective_busses(s); ++i) {
 248             if (!i || s->snoop_state == SNOOP_STRIPING) {
 249                 if (fifo8_is_empty(&s->tx_fifo)) {
 250                     s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 251                     xilinx_spips_update_ixr(s);
 252                     return;
 253                 } else {
 254                     tx = fifo8_pop(&s->tx_fifo);
 255                 }
 256             }
 257             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
 258             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
 259             if (!i || s->snoop_state == SNOOP_STRIPING) {
 260                 if (fifo8_is_full(&s->rx_fifo)) {
 261                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 262                     DB_PRINT("rx FIFO overflow");
 263                 } else {
 264                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
 265                 }
 266             }
 267         }
 268
 269         switch (s->snoop_state) {
 270         case (SNOOP_CHECKING):
 271             switch (tx) { /* new instruction code */
 272             case READ: /* 3 address bytes, no dummy bytes/cycles */
 273             case PP:
 274             case DPP:
 275             case QPP:
 276                 s->snoop_state = 3;
 277                 break;
 278             case FAST_READ: /* 3 address bytes, 1 dummy byte */
 279             case DOR:
 280             case QOR:
 281             case DIOR: /* FIXME: these vary between vendor - set to spansion */
 282                 s->snoop_state = 4;
 283                 break;
 284             case QIOR: /* 3 address bytes, 2 dummy bytes */
 285                 s->snoop_state = 6;
 286                 break;
 287             default:
 288                 s->snoop_state = SNOOP_NONE;
 289             }
 290             break;
 291         case (SNOOP_STRIPING):
 292         case (SNOOP_NONE):
 293             break;
 294         default:
 295             s->snoop_state--;
 296         }
 297     }
 298 }
 299
 300 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 301 {
 302     int i;
 303
 304     *value = 0;
 305     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 306         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 307         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 308     }
 309 }
 310
 311 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 312                                                         unsigned size)
 313 {
 314     XilinxSPIPS *s = opaque;
 315     uint32_t mask = ~0;
 316     uint32_t ret;
 317
 318     addr >>= 2;
 319     switch (addr) {
 320     case R_CONFIG:
 321         mask = 0x0002FFFF;
 322         break;
 323     case R_INTR_STATUS:
 324     case R_INTR_MASK:
 325         mask = IXR_ALL;
 326         break;
 327     case  R_EN:
 328         mask = 0x1;
 329         break;
 330     case R_SLAVE_IDLE_COUNT:
 331         mask = 0xFF;
 332         break;
 333     case R_MOD_ID:
 334         mask = 0x01FFFFFF;
 335         break;
 336     case R_INTR_EN:
 337     case R_INTR_DIS:
 338     case R_TX_DATA:
 339         mask = 0;
 340         break;
 341     case R_RX_DATA:
 342         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 343         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 344         xilinx_spips_update_ixr(s);
 345         return ret;
 346     }
 347     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 348     return s->regs[addr] & mask;
 349
 350 }
 351
 352 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 353 {
 354     int i;
 355     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 356         if (s->regs[R_CONFIG] & ENDIAN) {
 357             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 358             value <<= 8;
 359         } else {
 360             fifo8_push(&s->tx_fifo, (uint8_t)value);
 361             value >>= 8;
 362         }
 363     }
 364 }
 365
 366 static void xilinx_spips_write(void *opaque, hwaddr addr,
 367                                         uint64_t value, unsigned size)
 368 {
 369     int mask = ~0;
 370     int man_start_com = 0;
 371     XilinxSPIPS *s = opaque;
 372
 373     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 374     addr >>= 2;
 375     switch (addr) {
 376     case R_CONFIG:
 377         mask = 0x0002FFFF;
 378         if (value & MAN_START_COM) {
 379             man_start_com = 1;
 380         }
 381         break;
 382     case R_INTR_STATUS:
 383         mask = IXR_ALL;
 384         s->regs[R_INTR_STATUS] &= ~(mask & value);
 385         goto no_reg_update;
 386     case R_INTR_DIS:
 387         mask = IXR_ALL;
 388         s->regs[R_INTR_MASK] &= ~(mask & value);
 389         goto no_reg_update;
 390     case R_INTR_EN:
 391         mask = IXR_ALL;
 392         s->regs[R_INTR_MASK] |= mask & value;
 393         goto no_reg_update;
 394     case R_EN:
 395         mask = 0x1;
 396         break;
 397     case R_SLAVE_IDLE_COUNT:
 398         mask = 0xFF;
 399         break;
 400     case R_RX_DATA:
 401     case R_INTR_MASK:
 402     case R_MOD_ID:
 403         mask = 0;
 404         break;
 405     case R_TX_DATA:
 406         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 407         goto no_reg_update;
 408     case R_TXD1:
 409         tx_data_bytes(s, (uint32_t)value, 1);
 410         goto no_reg_update;
 411     case R_TXD2:
 412         tx_data_bytes(s, (uint32_t)value, 2);
 413         goto no_reg_update;
 414     case R_TXD3:
 415         tx_data_bytes(s, (uint32_t)value, 3);
 416         goto no_reg_update;
 417     }
 418     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 419 no_reg_update:
 420     if (man_start_com) {
 421         xilinx_spips_flush_txfifo(s);
 422     }
 423     xilinx_spips_update_ixr(s);
 424     xilinx_spips_update_cs_lines(s);
 425 }
 426
 427 static const MemoryRegionOps spips_ops = {
 428     .read = xilinx_spips_read,
 429     .write = xilinx_spips_write,
 430     .endianness = DEVICE_LITTLE_ENDIAN,
 431 };
 432
 433 #define LQSPI_CACHE_SIZE 1024
 434
 435 static uint64_t
 436 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 437 {
 438     int i;
 439     XilinxSPIPS *s = opaque;
 440
 441     if (addr >= s->lqspi_cached_addr &&
 442             addr <= s->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 443         return s->lqspi_buf[(addr - s->lqspi_cached_addr) >> 2];
 444     } else {
 445         int flash_addr = (addr / num_effective_busses(s));
 446         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 447         int cache_entry = 0;
 448
 449         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 450
 451         fifo8_reset(&s->tx_fifo);
 452         fifo8_reset(&s->rx_fifo);
 453
 454         s->regs[R_CONFIG] &= ~CS;
 455         s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
 456         xilinx_spips_update_cs_lines(s);
 457
 458         /* instruction */
 459         DB_PRINT("pushing read instruction: %02x\n",
 460                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 461         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 462         /* read address */
 463         DB_PRINT("pushing read address %06x\n", flash_addr);
 464         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 465         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 466         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 467         /* mode bits */
 468         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 469             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 470                                               LQSPI_CFG_MODE_SHIFT,
 471                                               LQSPI_CFG_MODE_WIDTH));
 472         }
 473         /* dummy bytes */
 474         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 475                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 476             DB_PRINT("pushing dummy byte\n");
 477             fifo8_push(&s->tx_fifo, 0);
 478         }
 479         xilinx_spips_flush_txfifo(s);
 480         fifo8_reset(&s->rx_fifo);
 481
 482         DB_PRINT("starting QSPI data read\n");
 483
 484         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 485             tx_data_bytes(s, 0, 4);
 486             xilinx_spips_flush_txfifo(s);
 487             rx_data_bytes(s, &s->lqspi_buf[cache_entry], 4);
 488             cache_entry++;
 489         }
 490
 491         s->regs[R_CONFIG] |= CS;
 492         xilinx_spips_update_cs_lines(s);
 493
 494         s->lqspi_cached_addr = addr;
 495         return lqspi_read(opaque, addr, size);
 496     }
 497 }
 498
 499 static const MemoryRegionOps lqspi_ops = {
 500     .read = lqspi_read,
 501     .endianness = DEVICE_NATIVE_ENDIAN,
 502     .valid = {
 503         .min_access_size = 4,
 504         .max_access_size = 4
 505     }
 506 };
 507
 508 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
 509 {
 510     XilinxSPIPS *s = XILINX_SPIPS(dev);
 511     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 512     int i;
 513
 514     DB_PRINT("inited device model\n");
 515
 516     s->spi = g_new(SSIBus *, s->num_busses);
 517     for (i = 0; i < s->num_busses; ++i) {
 518         char bus_name[16];
 519         snprintf(bus_name, 16, "spi%d", i);
 520         s->spi[i] = ssi_create_bus(dev, bus_name);
 521     }
 522
 523     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
 524     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 525     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 526     sysbus_init_irq(sbd, &s->irq);
 527     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 528         sysbus_init_irq(sbd, &s->cs_lines[i]);
 529     }
 530
 531     memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
 532     sysbus_init_mmio(sbd, &s->iomem);
 533
 534     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 535                           (1 << LQSPI_ADDRESS_BITS) * 2);
 536     sysbus_init_mmio(sbd, &s->mmlqspi);
 537
 538     s->irqline = -1;
 539     s->lqspi_cached_addr = ~0ULL;
 540
 541     fifo8_create(&s->rx_fifo, RXFF_A);
 542     fifo8_create(&s->tx_fifo, TXFF_A);
 543 }
 544
 545 static int xilinx_spips_post_load(void *opaque, int version_id)
 546 {
 547     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 548     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 549     return 0;
 550 }
 551
 552 static const VMStateDescription vmstate_xilinx_spips = {
 553     .name = "xilinx_spips",
 554     .version_id = 2,
 555     .minimum_version_id = 2,
 556     .minimum_version_id_old = 2,
 557     .post_load = xilinx_spips_post_load,
 558     .fields = (VMStateField[]) {
 559         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 560         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 561         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 562         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 563         VMSTATE_END_OF_LIST()
 564     }
 565 };
 566
 567 static Property xilinx_spips_properties[] = {
 568     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 569     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 570     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 571     DEFINE_PROP_END_OF_LIST(),
 572 };
 573 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 574 {
 575     DeviceClass *dc = DEVICE_CLASS(klass);
 576
 577     dc->realize = xilinx_spips_realize;
 578     dc->reset = xilinx_spips_reset;
 579     dc->props = xilinx_spips_properties;
 580     dc->vmsd = &vmstate_xilinx_spips;
 581 }
 582
 583 static const TypeInfo xilinx_spips_info = {
 584     .name  = TYPE_XILINX_SPIPS,
 585     .parent = TYPE_SYS_BUS_DEVICE,
 586     .instance_size  = sizeof(XilinxSPIPS),
 587     .class_init = xilinx_spips_class_init,
 588 };
 589
 590 static void xilinx_spips_register_types(void)
 591 {
 592     type_register_static(&xilinx_spips_info);
 593 }
 594
 595 type_init(xilinx_spips_register_types)