hw/pcie_host.c

   1 /*
   2  * pcie_host.c
   3  * utility functions for pci express host bridge.
   4  *
   5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw.h"
  23 #include "pci.h"
  24 #include "pcie_host.h"
  25
  26 /*
  27  * PCI express mmcfig address
  28  * bit 20 - 28: bus number
  29  * bit 15 - 19: device number
  30  * bit 12 - 14: function number
  31  * bit  0 - 11: offset in configuration space of a given device
  32  */
  33 #define PCIE_MMCFG_SIZE_MAX             (1ULL << 28)
  34 #define PCIE_MMCFG_SIZE_MIN             (1ULL << 20)
  35 #define PCIE_MMCFG_BUS_BIT              20
  36 #define PCIE_MMCFG_BUS_MASK             0x1ff
  37 #define PCIE_MMCFG_DEVFN_BIT            12
  38 #define PCIE_MMCFG_DEVFN_MASK           0xff
  39 #define PCIE_MMCFG_CONFOFFSET_MASK      0xfff
  40 #define PCIE_MMCFG_BUS(addr)            (((addr) >> PCIE_MMCFG_BUS_BIT) & \
  41                                          PCIE_MMCFG_BUS_MASK)
  42 #define PCIE_MMCFG_DEVFN(addr)          (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
  43                                          PCIE_MMCFG_DEVFN_MASK)
  44 #define PCIE_MMCFG_CONFOFFSET(addr)     ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
  45
  46
  47 /* a helper function to get a PCIDevice for a given mmconfig address */
  48 static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
  49                                                      uint32_t mmcfg_addr)
  50 {
  51     return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
  52                            PCIE_MMCFG_DEVFN(mmcfg_addr));
  53 }
  54
  55 static void pcie_mmcfg_data_write(PCIBus *s,
  56                                   uint32_t mmcfg_addr, uint32_t val, int len)
  57 {
  58     PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
  59     uint32_t addr;
  60     uint32_t limit;
  61
  62     if (!pci_dev) {
  63         return;
  64     }
  65     addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
  66     limit = pci_config_size(pci_dev);
  67     if (limit <= addr) {
  68         /* conventional pci device can be behind pcie-to-pci bridge.
  69            256 <= addr < 4K has no effects. */
  70         return;
  71     }
  72     pci_host_config_write_common(pci_dev, addr, limit, val, len);
  73 }
  74
  75 static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
  76 {
  77     PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
  78     uint32_t addr;
  79     uint32_t limit;
  80
  81     if (!pci_dev) {
  82         return ~0x0;
  83     }
  84     addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
  85     limit = pci_config_size(pci_dev);
  86     if (limit <= addr) {
  87         /* conventional pci device can be behind pcie-to-pci bridge.
  88            256 <= addr < 4K has no effects. */
  89         return ~0x0;
  90     }
  91     return pci_host_config_read_common(pci_dev, addr, limit, len);
  92 }
  93
  94 static void pcie_mmcfg_data_writeb(void *opaque,
  95                                    target_phys_addr_t addr, uint32_t value)
  96 {
  97     PCIExpressHost *e = opaque;
  98     pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
  99 }
 100
 101 static void pcie_mmcfg_data_writew(void *opaque,
 102                                    target_phys_addr_t addr, uint32_t value)
 103 {
 104     PCIExpressHost *e = opaque;
 105     pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
 106 }
 107
 108 static void pcie_mmcfg_data_writel(void *opaque,
 109                                    target_phys_addr_t addr, uint32_t value)
 110 {
 111     PCIExpressHost *e = opaque;
 112     pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
 113 }
 114
 115 static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
 116 {
 117     PCIExpressHost *e = opaque;
 118     return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
 119 }
 120
 121 static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
 122 {
 123     PCIExpressHost *e = opaque;
 124     return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
 125 }
 126
 127 static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
 128 {
 129     PCIExpressHost *e = opaque;
 130     return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
 131 }
 132
 133
 134 static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
 135 {
 136     pcie_mmcfg_data_writeb,
 137     pcie_mmcfg_data_writew,
 138     pcie_mmcfg_data_writel,
 139 };
 140
 141 static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
 142 {
 143     pcie_mmcfg_data_readb,
 144     pcie_mmcfg_data_readw,
 145     pcie_mmcfg_data_readl,
 146 };
 147
 148 /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
 149 #define PCIE_BASE_ADDR_UNMAPPED  ((target_phys_addr_t)-1ULL)
 150
 151 int pcie_host_init(PCIExpressHost *e)
 152 {
 153     e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
 154     e->mmio_index =
 155         cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
 156                                DEVICE_NATIVE_ENDIAN);
 157     if (e->mmio_index < 0) {
 158         return -1;
 159     }
 160
 161     return 0;
 162 }
 163
 164 void pcie_host_mmcfg_unmap(PCIExpressHost *e)
 165 {
 166     if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
 167         cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
 168         e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
 169     }
 170 }
 171
 172 void pcie_host_mmcfg_map(PCIExpressHost *e,
 173                          target_phys_addr_t addr, uint32_t size)
 174 {
 175     assert(!(size & (size - 1)));       /* power of 2 */
 176     assert(size >= PCIE_MMCFG_SIZE_MIN);
 177     assert(size <= PCIE_MMCFG_SIZE_MAX);
 178
 179     e->base_addr = addr;
 180     e->size = size;
 181     cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
 182 }
 183
 184 void pcie_host_mmcfg_update(PCIExpressHost *e,
 185                             int enable,
 186                             target_phys_addr_t addr, uint32_t size)
 187 {
 188     pcie_host_mmcfg_unmap(e);
 189     if (enable) {
 190         pcie_host_mmcfg_map(e, addr, size);
 191     }
 192 }