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target-ppc: Add read and write of PPR SPR
[qemu/agraf.git] / target-ppc / translate_init.c
blob021a31e2098ebb16bda432988f5950b5fa2f92c9
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34
35 /* For user-mode emulation, we don't emulate any IRQ controller */
36 #if defined(CONFIG_USER_ONLY)
37 #define PPC_IRQ_INIT_FN(name) \
38 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
39 { \
40 }
41 #else
42 #define PPC_IRQ_INIT_FN(name) \
43 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
44 #endif
45
46 PPC_IRQ_INIT_FN(40x);
47 PPC_IRQ_INIT_FN(6xx);
48 PPC_IRQ_INIT_FN(970);
49 PPC_IRQ_INIT_FN(POWER7);
50 PPC_IRQ_INIT_FN(e500);
51
52 /* Generic callbacks:
53 * do nothing but store/retrieve spr value
54 */
55 static void spr_load_dump_spr(int sprn)
56 {
57 #ifdef PPC_DUMP_SPR_ACCESSES
58 TCGv_i32 t0 = tcg_const_i32(sprn);
59 gen_helper_load_dump_spr(cpu_env, t0);
60 tcg_temp_free_i32(t0);
61 #endif
62 }
63
64 static void spr_read_generic (void *opaque, int gprn, int sprn)
65 {
66 gen_load_spr(cpu_gpr[gprn], sprn);
67 spr_load_dump_spr(sprn);
68 }
69
70 static void spr_store_dump_spr(int sprn)
71 {
72 #ifdef PPC_DUMP_SPR_ACCESSES
73 TCGv_i32 t0 = tcg_const_i32(sprn);
74 gen_helper_store_dump_spr(cpu_env, t0);
75 tcg_temp_free_i32(t0);
76 #endif
77 }
78
79 static void spr_write_generic (void *opaque, int sprn, int gprn)
80 {
81 gen_store_spr(sprn, cpu_gpr[gprn]);
82 spr_store_dump_spr(sprn);
83 }
84
85 #if !defined(CONFIG_USER_ONLY)
86 static void spr_write_generic32(void *opaque, int sprn, int gprn)
87 {
88 #ifdef TARGET_PPC64
89 TCGv t0 = tcg_temp_new();
90 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
91 gen_store_spr(sprn, t0);
92 tcg_temp_free(t0);
93 spr_store_dump_spr(sprn);
94 #else
95 spr_write_generic(opaque, sprn, gprn);
96 #endif
97 }
98
99 static void spr_write_clear (void *opaque, int sprn, int gprn)
100 {
101 TCGv t0 = tcg_temp_new();
102 TCGv t1 = tcg_temp_new();
103 gen_load_spr(t0, sprn);
104 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
105 tcg_gen_and_tl(t0, t0, t1);
106 gen_store_spr(sprn, t0);
107 tcg_temp_free(t0);
108 tcg_temp_free(t1);
109 }
110 #endif
111
112 /* SPR common to all PowerPC */
113 /* XER */
114 static void spr_read_xer (void *opaque, int gprn, int sprn)
115 {
116 gen_read_xer(cpu_gpr[gprn]);
117 }
118
119 static void spr_write_xer (void *opaque, int sprn, int gprn)
120 {
121 gen_write_xer(cpu_gpr[gprn]);
122 }
123
124 /* LR */
125 static void spr_read_lr (void *opaque, int gprn, int sprn)
126 {
127 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
128 }
129
130 static void spr_write_lr (void *opaque, int sprn, int gprn)
131 {
132 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
133 }
134
135 /* CFAR */
136 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
137 static void spr_read_cfar (void *opaque, int gprn, int sprn)
138 {
139 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
140 }
141
142 static void spr_write_cfar (void *opaque, int sprn, int gprn)
143 {
144 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
145 }
146 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
147
148 /* CTR */
149 static void spr_read_ctr (void *opaque, int gprn, int sprn)
150 {
151 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
152 }
153
154 static void spr_write_ctr (void *opaque, int sprn, int gprn)
155 {
156 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
157 }
158
159 /* User read access to SPR */
160 /* USPRx */
161 /* UMMCRx */
162 /* UPMCx */
163 /* USIA */
164 /* UDECR */
165 static void spr_read_ureg (void *opaque, int gprn, int sprn)
166 {
167 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
168 }
169
170 /* SPR common to all non-embedded PowerPC */
171 /* DECR */
172 #if !defined(CONFIG_USER_ONLY)
173 static void spr_read_decr (void *opaque, int gprn, int sprn)
174 {
175 if (use_icount) {
176 gen_io_start();
177 }
178 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
179 if (use_icount) {
180 gen_io_end();
181 gen_stop_exception(opaque);
182 }
183 }
184
185 static void spr_write_decr (void *opaque, int sprn, int gprn)
186 {
187 if (use_icount) {
188 gen_io_start();
189 }
190 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
191 if (use_icount) {
192 gen_io_end();
193 gen_stop_exception(opaque);
194 }
195 }
196 #endif
197
198 /* SPR common to all non-embedded PowerPC, except 601 */
199 /* Time base */
200 static void spr_read_tbl (void *opaque, int gprn, int sprn)
201 {
202 if (use_icount) {
203 gen_io_start();
204 }
205 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
206 if (use_icount) {
207 gen_io_end();
208 gen_stop_exception(opaque);
209 }
210 }
211
212 static void spr_read_tbu (void *opaque, int gprn, int sprn)
213 {
214 if (use_icount) {
215 gen_io_start();
216 }
217 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
218 if (use_icount) {
219 gen_io_end();
220 gen_stop_exception(opaque);
221 }
222 }
223
224 __attribute__ (( unused ))
225 static void spr_read_atbl (void *opaque, int gprn, int sprn)
226 {
227 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbu (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
234 }
235
236 #if !defined(CONFIG_USER_ONLY)
237 static void spr_write_tbl (void *opaque, int sprn, int gprn)
238 {
239 if (use_icount) {
240 gen_io_start();
241 }
242 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
243 if (use_icount) {
244 gen_io_end();
245 gen_stop_exception(opaque);
246 }
247 }
248
249 static void spr_write_tbu (void *opaque, int sprn, int gprn)
250 {
251 if (use_icount) {
252 gen_io_start();
253 }
254 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
255 if (use_icount) {
256 gen_io_end();
257 gen_stop_exception(opaque);
258 }
259 }
260
261 __attribute__ (( unused ))
262 static void spr_write_atbl (void *opaque, int sprn, int gprn)
263 {
264 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbu (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
271 }
272
273 #if defined(TARGET_PPC64)
274 __attribute__ (( unused ))
275 static void spr_read_purr (void *opaque, int gprn, int sprn)
276 {
277 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
278 }
279 #endif
280 #endif
281
282 #if !defined(CONFIG_USER_ONLY)
283 /* IBAT0U...IBAT0U */
284 /* IBAT0L...IBAT7L */
285 static void spr_read_ibat (void *opaque, int gprn, int sprn)
286 {
287 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
288 }
289
290 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
291 {
292 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
293 }
294
295 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
296 {
297 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
298 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
299 tcg_temp_free_i32(t0);
300 }
301
302 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
303 {
304 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
305 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
306 tcg_temp_free_i32(t0);
307 }
308
309 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
310 {
311 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
312 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
313 tcg_temp_free_i32(t0);
314 }
315
316 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
317 {
318 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
319 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
320 tcg_temp_free_i32(t0);
321 }
322
323 /* DBAT0U...DBAT7U */
324 /* DBAT0L...DBAT7L */
325 static void spr_read_dbat (void *opaque, int gprn, int sprn)
326 {
327 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
328 }
329
330 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
331 {
332 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
333 }
334
335 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
336 {
337 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
338 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
339 tcg_temp_free_i32(t0);
340 }
341
342 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
343 {
344 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
345 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
346 tcg_temp_free_i32(t0);
347 }
348
349 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
350 {
351 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
352 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
353 tcg_temp_free_i32(t0);
354 }
355
356 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
357 {
358 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
359 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
360 tcg_temp_free_i32(t0);
361 }
362
363 /* SDR1 */
364 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
365 {
366 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
367 }
368
369 /* 64 bits PowerPC specific SPRs */
370 #if defined(TARGET_PPC64)
371 static void spr_read_hior (void *opaque, int gprn, int sprn)
372 {
373 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
374 }
375
376 static void spr_write_hior (void *opaque, int sprn, int gprn)
377 {
378 TCGv t0 = tcg_temp_new();
379 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
380 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
381 tcg_temp_free(t0);
382 }
383 #endif
384 #endif
385
386 /* PowerPC 601 specific registers */
387 /* RTC */
388 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
391 }
392
393 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
394 {
395 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
396 }
397
398 #if !defined(CONFIG_USER_ONLY)
399 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
402 }
403
404 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
405 {
406 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
407 }
408
409 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
410 {
411 DisasContext *ctx = opaque;
412
413 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
414 /* Must stop the translation as endianness may have changed */
415 gen_stop_exception(ctx);
416 }
417 #endif
418
419 /* Unified bats */
420 #if !defined(CONFIG_USER_ONLY)
421 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
422 {
423 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
424 }
425
426 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
427 {
428 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
429 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
430 tcg_temp_free_i32(t0);
431 }
432
433 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
434 {
435 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
436 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
437 tcg_temp_free_i32(t0);
438 }
439 #endif
440
441 /* PowerPC 40x specific registers */
442 #if !defined(CONFIG_USER_ONLY)
443 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
444 {
445 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
446 }
447
448 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
449 {
450 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
451 }
452
453 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
454 {
455 DisasContext *ctx = opaque;
456
457 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
458 /* We must stop translation as we may have rebooted */
459 gen_stop_exception(ctx);
460 }
461
462 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
470 }
471
472 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
473 {
474 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
475 }
476 #endif
477
478 /* PowerPC 403 specific registers */
479 /* PBL1 / PBU1 / PBL2 / PBU2 */
480 #if !defined(CONFIG_USER_ONLY)
481 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
482 {
483 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
484 }
485
486 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
487 {
488 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
489 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
490 tcg_temp_free_i32(t0);
491 }
492
493 static void spr_write_pir (void *opaque, int sprn, int gprn)
494 {
495 TCGv t0 = tcg_temp_new();
496 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
497 gen_store_spr(SPR_PIR, t0);
498 tcg_temp_free(t0);
499 }
500 #endif
501
502 /* SPE specific registers */
503 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
504 {
505 TCGv_i32 t0 = tcg_temp_new_i32();
506 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
507 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
508 tcg_temp_free_i32(t0);
509 }
510
511 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
512 {
513 TCGv_i32 t0 = tcg_temp_new_i32();
514 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
516 tcg_temp_free_i32(t0);
517 }
518
519 #if !defined(CONFIG_USER_ONLY)
520 /* Callback used to write the exception vector base */
521 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
522 {
523 TCGv t0 = tcg_temp_new();
524 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
525 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
526 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
527 gen_store_spr(sprn, t0);
528 tcg_temp_free(t0);
529 }
530
531 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
532 {
533 DisasContext *ctx = opaque;
534 int sprn_offs;
535
536 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR0;
538 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
539 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
540 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
541 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
542 } else {
543 printf("Trying to write an unknown exception vector %d %03x\n",
544 sprn, sprn);
545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
546 return;
547 }
548
549 TCGv t0 = tcg_temp_new();
550 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
551 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
552 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
553 gen_store_spr(sprn, t0);
554 tcg_temp_free(t0);
555 }
556 #endif
557
558 static inline void vscr_init (CPUPPCState *env, uint32_t val)
559 {
560 env->vscr = val;
561 /* Altivec always uses round-to-nearest */
562 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
563 set_flush_to_zero(vscr_nj, &env->vec_status);
564 }
565
566 #ifdef CONFIG_USER_ONLY
567 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
568 oea_read, oea_write, one_reg_id, initial_value) \
569 _spr_register(env, num, name, uea_read, uea_write, initial_value)
570 #else
571 #if !defined(CONFIG_KVM)
572 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, one_reg_id, initial_value) \
574 _spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, initial_value)
576 #else
577 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
578 oea_read, oea_write, one_reg_id, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, one_reg_id, initial_value)
581 #endif
582 #endif
583
584 #define spr_register(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, initial_value) \
586 spr_register_kvm(env, num, name, uea_read, uea_write, \
587 oea_read, oea_write, 0, initial_value)
588
589 static inline void _spr_register(CPUPPCState *env, int num,
590 const char *name,
591 void (*uea_read)(void *opaque, int gprn, int sprn),
592 void (*uea_write)(void *opaque, int sprn, int gprn),
593 #if !defined(CONFIG_USER_ONLY)
594
595 void (*oea_read)(void *opaque, int gprn, int sprn),
596 void (*oea_write)(void *opaque, int sprn, int gprn),
597 #endif
598 #if defined(CONFIG_KVM)
599 uint64_t one_reg_id,
600 #endif
601 target_ulong initial_value)
602 {
603 ppc_spr_t *spr;
604
605 spr = &env->spr_cb[num];
606 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
607 #if !defined(CONFIG_USER_ONLY)
608 spr->oea_read != NULL || spr->oea_write != NULL ||
609 #endif
610 spr->uea_read != NULL || spr->uea_write != NULL) {
611 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612 exit(1);
613 }
614 #if defined(PPC_DEBUG_SPR)
615 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616 name, initial_value);
617 #endif
618 spr->name = name;
619 spr->uea_read = uea_read;
620 spr->uea_write = uea_write;
621 #if !defined(CONFIG_USER_ONLY)
622 spr->oea_read = oea_read;
623 spr->oea_write = oea_write;
624 #endif
625 env->spr[num] = initial_value;
626 }
627
628 /* Generic PowerPC SPRs */
629 static void gen_spr_generic (CPUPPCState *env)
630 {
631 /* Integer processing */
632 spr_register(env, SPR_XER, "XER",
633 &spr_read_xer, &spr_write_xer,
634 &spr_read_xer, &spr_write_xer,
635 0x00000000);
636 /* Branch contol */
637 spr_register(env, SPR_LR, "LR",
638 &spr_read_lr, &spr_write_lr,
639 &spr_read_lr, &spr_write_lr,
640 0x00000000);
641 spr_register(env, SPR_CTR, "CTR",
642 &spr_read_ctr, &spr_write_ctr,
643 &spr_read_ctr, &spr_write_ctr,
644 0x00000000);
645 /* Interrupt processing */
646 spr_register(env, SPR_SRR0, "SRR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SRR1, "SRR1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* Processor control */
655 spr_register(env, SPR_SPRG0, "SPRG0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SPRG1, "SPRG1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 spr_register(env, SPR_SPRG2, "SPRG2",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 0x00000000);
667 spr_register(env, SPR_SPRG3, "SPRG3",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671 }
672
673 /* SPR common to all non-embedded PowerPC, including 601 */
674 static void gen_spr_ne_601 (CPUPPCState *env)
675 {
676 /* Exception processing */
677 spr_register_kvm(env, SPR_DSISR, "DSISR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 KVM_REG_PPC_DSISR, 0x00000000);
681 spr_register_kvm(env, SPR_DAR, "DAR",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 KVM_REG_PPC_DAR, 0x00000000);
685 /* Timer */
686 spr_register(env, SPR_DECR, "DECR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_decr, &spr_write_decr,
689 0x00000000);
690 /* Memory management */
691 spr_register(env, SPR_SDR1, "SDR1",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, &spr_write_sdr1,
694 0x00000000);
695 }
696
697 /* BATs 0-3 */
698 static void gen_low_BATs (CPUPPCState *env)
699 {
700 #if !defined(CONFIG_USER_ONLY)
701 spr_register(env, SPR_IBAT0U, "IBAT0U",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_ibat, &spr_write_ibatu,
704 0x00000000);
705 spr_register(env, SPR_IBAT0L, "IBAT0L",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_ibat, &spr_write_ibatl,
708 0x00000000);
709 spr_register(env, SPR_IBAT1U, "IBAT1U",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_ibat, &spr_write_ibatu,
712 0x00000000);
713 spr_register(env, SPR_IBAT1L, "IBAT1L",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_ibat, &spr_write_ibatl,
716 0x00000000);
717 spr_register(env, SPR_IBAT2U, "IBAT2U",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_ibat, &spr_write_ibatu,
720 0x00000000);
721 spr_register(env, SPR_IBAT2L, "IBAT2L",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_ibat, &spr_write_ibatl,
724 0x00000000);
725 spr_register(env, SPR_IBAT3U, "IBAT3U",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_ibat, &spr_write_ibatu,
728 0x00000000);
729 spr_register(env, SPR_IBAT3L, "IBAT3L",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_ibat, &spr_write_ibatl,
732 0x00000000);
733 spr_register(env, SPR_DBAT0U, "DBAT0U",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_dbat, &spr_write_dbatu,
736 0x00000000);
737 spr_register(env, SPR_DBAT0L, "DBAT0L",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_dbat, &spr_write_dbatl,
740 0x00000000);
741 spr_register(env, SPR_DBAT1U, "DBAT1U",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_dbat, &spr_write_dbatu,
744 0x00000000);
745 spr_register(env, SPR_DBAT1L, "DBAT1L",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_dbat, &spr_write_dbatl,
748 0x00000000);
749 spr_register(env, SPR_DBAT2U, "DBAT2U",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_dbat, &spr_write_dbatu,
752 0x00000000);
753 spr_register(env, SPR_DBAT2L, "DBAT2L",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_dbat, &spr_write_dbatl,
756 0x00000000);
757 spr_register(env, SPR_DBAT3U, "DBAT3U",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_dbat, &spr_write_dbatu,
760 0x00000000);
761 spr_register(env, SPR_DBAT3L, "DBAT3L",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_dbat, &spr_write_dbatl,
764 0x00000000);
765 env->nb_BATs += 4;
766 #endif
767 }
768
769 /* BATs 4-7 */
770 static void gen_high_BATs (CPUPPCState *env)
771 {
772 #if !defined(CONFIG_USER_ONLY)
773 spr_register(env, SPR_IBAT4U, "IBAT4U",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat_h, &spr_write_ibatu_h,
776 0x00000000);
777 spr_register(env, SPR_IBAT4L, "IBAT4L",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat_h, &spr_write_ibatl_h,
780 0x00000000);
781 spr_register(env, SPR_IBAT5U, "IBAT5U",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat_h, &spr_write_ibatu_h,
784 0x00000000);
785 spr_register(env, SPR_IBAT5L, "IBAT5L",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_ibat_h, &spr_write_ibatl_h,
788 0x00000000);
789 spr_register(env, SPR_IBAT6U, "IBAT6U",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_ibat_h, &spr_write_ibatu_h,
792 0x00000000);
793 spr_register(env, SPR_IBAT6L, "IBAT6L",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_ibat_h, &spr_write_ibatl_h,
796 0x00000000);
797 spr_register(env, SPR_IBAT7U, "IBAT7U",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_ibat_h, &spr_write_ibatu_h,
800 0x00000000);
801 spr_register(env, SPR_IBAT7L, "IBAT7L",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_ibat_h, &spr_write_ibatl_h,
804 0x00000000);
805 spr_register(env, SPR_DBAT4U, "DBAT4U",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat_h, &spr_write_dbatu_h,
808 0x00000000);
809 spr_register(env, SPR_DBAT4L, "DBAT4L",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat_h, &spr_write_dbatl_h,
812 0x00000000);
813 spr_register(env, SPR_DBAT5U, "DBAT5U",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat_h, &spr_write_dbatu_h,
816 0x00000000);
817 spr_register(env, SPR_DBAT5L, "DBAT5L",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_dbat_h, &spr_write_dbatl_h,
820 0x00000000);
821 spr_register(env, SPR_DBAT6U, "DBAT6U",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_dbat_h, &spr_write_dbatu_h,
824 0x00000000);
825 spr_register(env, SPR_DBAT6L, "DBAT6L",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_dbat_h, &spr_write_dbatl_h,
828 0x00000000);
829 spr_register(env, SPR_DBAT7U, "DBAT7U",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_dbat_h, &spr_write_dbatu_h,
832 0x00000000);
833 spr_register(env, SPR_DBAT7L, "DBAT7L",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_dbat_h, &spr_write_dbatl_h,
836 0x00000000);
837 env->nb_BATs += 4;
838 #endif
839 }
840
841 /* Generic PowerPC time base */
842 static void gen_tbl (CPUPPCState *env)
843 {
844 spr_register(env, SPR_VTBL, "TBL",
845 &spr_read_tbl, SPR_NOACCESS,
846 &spr_read_tbl, SPR_NOACCESS,
847 0x00000000);
848 spr_register(env, SPR_TBL, "TBL",
849 &spr_read_tbl, SPR_NOACCESS,
850 &spr_read_tbl, &spr_write_tbl,
851 0x00000000);
852 spr_register(env, SPR_VTBU, "TBU",
853 &spr_read_tbu, SPR_NOACCESS,
854 &spr_read_tbu, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_TBU, "TBU",
857 &spr_read_tbu, SPR_NOACCESS,
858 &spr_read_tbu, &spr_write_tbu,
859 0x00000000);
860 }
861
862 /* Softare table search registers */
863 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864 {
865 #if !defined(CONFIG_USER_ONLY)
866 env->nb_tlb = nb_tlbs;
867 env->nb_ways = nb_ways;
868 env->id_tlbs = 1;
869 env->tlb_type = TLB_6XX;
870 spr_register(env, SPR_DMISS, "DMISS",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_DCMP, "DCMP",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, SPR_NOACCESS,
877 0x00000000);
878 spr_register(env, SPR_HASH1, "HASH1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_HASH2, "HASH2",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_IMISS, "IMISS",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_ICMP, "ICMP",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_RPA, "RPA",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 #endif
899 }
900
901 /* SPR common to MPC755 and G2 */
902 static void gen_spr_G2_755 (CPUPPCState *env)
903 {
904 /* SGPRs */
905 spr_register(env, SPR_SPRG4, "SPRG4",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 spr_register(env, SPR_SPRG5, "SPRG5",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 spr_register(env, SPR_SPRG6, "SPRG6",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 spr_register(env, SPR_SPRG7, "SPRG7",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 }
922
923 /* SPR common to all 7xx PowerPC implementations */
924 static void gen_spr_7xx (CPUPPCState *env)
925 {
926 /* Breakpoints */
927 /* XXX : not implemented */
928 spr_register_kvm(env, SPR_DABR, "DABR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 KVM_REG_PPC_DABR, 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_IABR, "IABR",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* Cache management */
938 /* XXX : not implemented */
939 spr_register(env, SPR_ICTC, "ICTC",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Performance monitors */
944 /* XXX : not implemented */
945 spr_register(env, SPR_MMCR0, "MMCR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_MMCR1, "MMCR1",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC1, "PMC1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_PMC2, "PMC2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC3, "PMC3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_PMC4, "PMC4",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_SIAR, "SIAR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_UMMCR0, "UMMCR0",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_UMMCR1, "UMMCR1",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_UPMC1, "UPMC1",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_UPMC2, "UPMC2",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_UPMC3, "UPMC3",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_UPMC4, "UPMC4",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_USIAR, "USIAR",
1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
1014 /* External access control */
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_EAR, "EAR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 }
1021
1022 #ifdef TARGET_PPC64
1023 #ifndef CONFIG_USER_ONLY
1024 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1025 {
1026 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1027 spr_load_dump_spr(SPR_AMR);
1028 }
1029
1030 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1031 {
1032 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1033 spr_store_dump_spr(SPR_AMR);
1034 }
1035
1036 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1037 {
1038 TCGv t0 = tcg_temp_new();
1039
1040 gen_load_spr(t0, SPR_UAMOR);
1041 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1042 gen_store_spr(SPR_AMR, t0);
1043 spr_store_dump_spr(SPR_AMR);
1044 }
1045 #endif /* CONFIG_USER_ONLY */
1046
1047 static void gen_spr_amr (CPUPPCState *env)
1048 {
1049 #ifndef CONFIG_USER_ONLY
1050 /* Virtual Page Class Key protection */
1051 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1052 * userspace accessible, 29 is privileged. So we only need to set
1053 * the kvm ONE_REG id on one of them, we use 29 */
1054 spr_register(env, SPR_UAMR, "UAMR",
1055 &spr_read_uamr, &spr_write_uamr_pr,
1056 &spr_read_uamr, &spr_write_uamr,
1057 0);
1058 spr_register_kvm(env, SPR_AMR, "AMR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
1062 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 KVM_REG_PPC_UAMOR, 0);
1066 #endif /* !CONFIG_USER_ONLY */
1067 }
1068 #endif /* TARGET_PPC64 */
1069
1070 static void gen_spr_thrm (CPUPPCState *env)
1071 {
1072 /* Thermal management */
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_THRM1, "THRM1",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_THRM2, "THRM2",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* XXX : not implemented */
1084 spr_register(env, SPR_THRM3, "THRM3",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 }
1089
1090 /* SPR specific to PowerPC 604 implementation */
1091 static void gen_spr_604 (CPUPPCState *env)
1092 {
1093 /* Processor identification */
1094 spr_register(env, SPR_PIR, "PIR",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_pir,
1097 0x00000000);
1098 /* Breakpoints */
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_IABR, "IABR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* XXX : not implemented */
1105 spr_register_kvm(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 KVM_REG_PPC_DABR, 0x00000000);
1109 /* Performance counters */
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_MMCR0, "MMCR0",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_PMC1, "PMC1",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_PMC2, "PMC2",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_SIAR, "SIAR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, SPR_NOACCESS,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_SDA, "SDA",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, SPR_NOACCESS,
1134 0x00000000);
1135 /* External access control */
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_EAR, "EAR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 }
1142
1143 /* SPR specific to PowerPC 603 implementation */
1144 static void gen_spr_603 (CPUPPCState *env)
1145 {
1146 /* External access control */
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_EAR, "EAR",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 /* Breakpoints */
1153 /* XXX : not implemented */
1154 spr_register(env, SPR_IABR, "IABR",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1157 0x00000000);
1158
1159 }
1160
1161 /* SPR specific to PowerPC G2 implementation */
1162 static void gen_spr_G2 (CPUPPCState *env)
1163 {
1164 /* Memory base address */
1165 /* MBAR */
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_MBAR, "MBAR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* Exception processing */
1172 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 /* Breakpoints */
1181 /* XXX : not implemented */
1182 spr_register(env, SPR_DABR, "DABR",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* XXX : not implemented */
1187 spr_register(env, SPR_DABR2, "DABR2",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_generic,
1190 0x00000000);
1191 /* XXX : not implemented */
1192 spr_register(env, SPR_IABR, "IABR",
1193 SPR_NOACCESS, SPR_NOACCESS,
1194 &spr_read_generic, &spr_write_generic,
1195 0x00000000);
1196 /* XXX : not implemented */
1197 spr_register(env, SPR_IABR2, "IABR2",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_generic, &spr_write_generic,
1200 0x00000000);
1201 /* XXX : not implemented */
1202 spr_register(env, SPR_IBCR, "IBCR",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* XXX : not implemented */
1207 spr_register(env, SPR_DBCR, "DBCR",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 }
1212
1213 /* SPR specific to PowerPC 602 implementation */
1214 static void gen_spr_602 (CPUPPCState *env)
1215 {
1216 /* ESA registers */
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_SER, "SER",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* XXX : not implemented */
1223 spr_register(env, SPR_SEBR, "SEBR",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* XXX : not implemented */
1228 spr_register(env, SPR_ESASRR, "ESASRR",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 /* Floating point status */
1233 /* XXX : not implemented */
1234 spr_register(env, SPR_SP, "SP",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 /* XXX : not implemented */
1239 spr_register(env, SPR_LT, "LT",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 /* Watchdog timer */
1244 /* XXX : not implemented */
1245 spr_register(env, SPR_TCR, "TCR",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
1249 /* Interrupt base */
1250 spr_register(env, SPR_IBR, "IBR",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 /* XXX : not implemented */
1255 spr_register(env, SPR_IABR, "IABR",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
1259 }
1260
1261 /* SPR specific to PowerPC 601 implementation */
1262 static void gen_spr_601 (CPUPPCState *env)
1263 {
1264 /* Multiplication/division register */
1265 /* MQ */
1266 spr_register(env, SPR_MQ, "MQ",
1267 &spr_read_generic, &spr_write_generic,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270 /* RTC registers */
1271 spr_register(env, SPR_601_RTCU, "RTCU",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 SPR_NOACCESS, &spr_write_601_rtcu,
1274 0x00000000);
1275 spr_register(env, SPR_601_VRTCU, "RTCU",
1276 &spr_read_601_rtcu, SPR_NOACCESS,
1277 &spr_read_601_rtcu, SPR_NOACCESS,
1278 0x00000000);
1279 spr_register(env, SPR_601_RTCL, "RTCL",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 SPR_NOACCESS, &spr_write_601_rtcl,
1282 0x00000000);
1283 spr_register(env, SPR_601_VRTCL, "RTCL",
1284 &spr_read_601_rtcl, SPR_NOACCESS,
1285 &spr_read_601_rtcl, SPR_NOACCESS,
1286 0x00000000);
1287 /* Timer */
1288 #if 0 /* ? */
1289 spr_register(env, SPR_601_UDECR, "UDECR",
1290 &spr_read_decr, SPR_NOACCESS,
1291 &spr_read_decr, SPR_NOACCESS,
1292 0x00000000);
1293 #endif
1294 /* External access control */
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_EAR, "EAR",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300 /* Memory management */
1301 #if !defined(CONFIG_USER_ONLY)
1302 spr_register(env, SPR_IBAT0U, "IBAT0U",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_601_ubat, &spr_write_601_ubatu,
1305 0x00000000);
1306 spr_register(env, SPR_IBAT0L, "IBAT0L",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_601_ubat, &spr_write_601_ubatl,
1309 0x00000000);
1310 spr_register(env, SPR_IBAT1U, "IBAT1U",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_601_ubat, &spr_write_601_ubatu,
1313 0x00000000);
1314 spr_register(env, SPR_IBAT1L, "IBAT1L",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_601_ubat, &spr_write_601_ubatl,
1317 0x00000000);
1318 spr_register(env, SPR_IBAT2U, "IBAT2U",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_601_ubat, &spr_write_601_ubatu,
1321 0x00000000);
1322 spr_register(env, SPR_IBAT2L, "IBAT2L",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_601_ubat, &spr_write_601_ubatl,
1325 0x00000000);
1326 spr_register(env, SPR_IBAT3U, "IBAT3U",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_601_ubat, &spr_write_601_ubatu,
1329 0x00000000);
1330 spr_register(env, SPR_IBAT3L, "IBAT3L",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_601_ubat, &spr_write_601_ubatl,
1333 0x00000000);
1334 env->nb_BATs = 4;
1335 #endif
1336 }
1337
1338 static void gen_spr_74xx (CPUPPCState *env)
1339 {
1340 /* Processor identification */
1341 spr_register(env, SPR_PIR, "PIR",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_pir,
1344 0x00000000);
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_MMCR2, "MMCR2",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_UMMCR2, "UMMCR2",
1352 &spr_read_ureg, SPR_NOACCESS,
1353 &spr_read_ureg, SPR_NOACCESS,
1354 0x00000000);
1355 /* XXX: not implemented */
1356 spr_register(env, SPR_BAMR, "BAMR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_MSSCR0, "MSSCR0",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* Hardware implementation registers */
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_HID0, "HID0",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 /* XXX : not implemented */
1372 spr_register(env, SPR_HID1, "HID1",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 /* Altivec */
1377 spr_register(env, SPR_VRSAVE, "VRSAVE",
1378 &spr_read_generic, &spr_write_generic,
1379 &spr_read_generic, &spr_write_generic,
1380 0x00000000);
1381 /* XXX : not implemented */
1382 spr_register(env, SPR_L2CR, "L2CR",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_generic,
1385 0x00000000);
1386 /* Not strictly an SPR */
1387 vscr_init(env, 0x00010000);
1388 }
1389
1390 static void gen_l3_ctrl (CPUPPCState *env)
1391 {
1392 /* L3CR */
1393 /* XXX : not implemented */
1394 spr_register(env, SPR_L3CR, "L3CR",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398 /* L3ITCR0 */
1399 /* XXX : not implemented */
1400 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000);
1404 /* L3PM */
1405 /* XXX : not implemented */
1406 spr_register(env, SPR_L3PM, "L3PM",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410 }
1411
1412 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1413 {
1414 #if !defined(CONFIG_USER_ONLY)
1415 env->nb_tlb = nb_tlbs;
1416 env->nb_ways = nb_ways;
1417 env->id_tlbs = 1;
1418 env->tlb_type = TLB_6XX;
1419 /* XXX : not implemented */
1420 spr_register(env, SPR_PTEHI, "PTEHI",
1421 SPR_NOACCESS, SPR_NOACCESS,
1422 &spr_read_generic, &spr_write_generic,
1423 0x00000000);
1424 /* XXX : not implemented */
1425 spr_register(env, SPR_PTELO, "PTELO",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429 /* XXX : not implemented */
1430 spr_register(env, SPR_TLBMISS, "TLBMISS",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_generic, &spr_write_generic,
1433 0x00000000);
1434 #endif
1435 }
1436
1437 #if !defined(CONFIG_USER_ONLY)
1438 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1439 {
1440 TCGv t0 = tcg_temp_new();
1441
1442 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1443 gen_store_spr(sprn, t0);
1444 tcg_temp_free(t0);
1445 }
1446
1447 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1448 {
1449 TCGv_i32 t0 = tcg_const_i32(sprn);
1450 gen_helper_booke206_tlbflush(cpu_env, t0);
1451 tcg_temp_free_i32(t0);
1452 }
1453
1454 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1455 {
1456 TCGv_i32 t0 = tcg_const_i32(sprn);
1457 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1458 tcg_temp_free_i32(t0);
1459 }
1460 #endif
1461
1462 static void gen_spr_usprgh (CPUPPCState *env)
1463 {
1464 spr_register(env, SPR_USPRG4, "USPRG4",
1465 &spr_read_ureg, SPR_NOACCESS,
1466 &spr_read_ureg, SPR_NOACCESS,
1467 0x00000000);
1468 spr_register(env, SPR_USPRG5, "USPRG5",
1469 &spr_read_ureg, SPR_NOACCESS,
1470 &spr_read_ureg, SPR_NOACCESS,
1471 0x00000000);
1472 spr_register(env, SPR_USPRG6, "USPRG6",
1473 &spr_read_ureg, SPR_NOACCESS,
1474 &spr_read_ureg, SPR_NOACCESS,
1475 0x00000000);
1476 spr_register(env, SPR_USPRG7, "USPRG7",
1477 &spr_read_ureg, SPR_NOACCESS,
1478 &spr_read_ureg, SPR_NOACCESS,
1479 0x00000000);
1480 }
1481
1482 /* PowerPC BookE SPR */
1483 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1484 {
1485 const char *ivor_names[64] = {
1486 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1487 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1488 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1489 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1490 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1491 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1492 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1493 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1494 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1495 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1496 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1497 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1498 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1499 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1500 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1501 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1502 };
1503 #define SPR_BOOKE_IVORxx (-1)
1504 int ivor_sprn[64] = {
1505 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1506 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1507 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1508 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1509 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1510 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1511 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1512 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1513 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1514 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1515 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1516 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1517 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1518 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1519 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1520 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1521 };
1522 int i;
1523
1524 /* Interrupt processing */
1525 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533 /* Debug */
1534 /* XXX : not implemented */
1535 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* XXX : not implemented */
1540 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 &spr_read_generic, &spr_write_generic,
1543 0x00000000);
1544 /* XXX : not implemented */
1545 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 /* XXX : not implemented */
1550 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* XXX : not implemented */
1555 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_40x_dbcr0,
1558 0x00000000);
1559 /* XXX : not implemented */
1560 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 /* XXX : not implemented */
1565 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 /* XXX : not implemented */
1570 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_clear,
1573 0x00000000);
1574 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 spr_register(env, SPR_BOOKE_ESR, "ESR",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_excp_prefix,
1585 0x00000000);
1586 /* Exception vectors */
1587 for (i = 0; i < 64; i++) {
1588 if (ivor_mask & (1ULL << i)) {
1589 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1590 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1591 exit(1);
1592 }
1593 spr_register(env, ivor_sprn[i], ivor_names[i],
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_excp_vector,
1596 0x00000000);
1597 }
1598 }
1599 spr_register(env, SPR_BOOKE_PID, "PID",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_booke_pid,
1602 0x00000000);
1603 spr_register(env, SPR_BOOKE_TCR, "TCR",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_booke_tcr,
1606 0x00000000);
1607 spr_register(env, SPR_BOOKE_TSR, "TSR",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_booke_tsr,
1610 0x00000000);
1611 /* Timer */
1612 spr_register(env, SPR_DECR, "DECR",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_decr, &spr_write_decr,
1615 0x00000000);
1616 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 SPR_NOACCESS, &spr_write_generic,
1619 0x00000000);
1620 /* SPRGs */
1621 spr_register(env, SPR_USPRG0, "USPRG0",
1622 &spr_read_generic, &spr_write_generic,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625 spr_register(env, SPR_SPRG4, "SPRG4",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_generic,
1628 0x00000000);
1629 spr_register(env, SPR_SPRG5, "SPRG5",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 spr_register(env, SPR_SPRG6, "SPRG6",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637 spr_register(env, SPR_SPRG7, "SPRG7",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_generic,
1640 0x00000000);
1641 }
1642
1643 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1644 uint32_t maxsize, uint32_t flags,
1645 uint32_t nentries)
1646 {
1647 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1648 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1649 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1650 flags | nentries;
1651 }
1652
1653 /* BookE 2.06 storage control registers */
1654 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1655 uint32_t *tlbncfg)
1656 {
1657 #if !defined(CONFIG_USER_ONLY)
1658 const char *mas_names[8] = {
1659 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1660 };
1661 int mas_sprn[8] = {
1662 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1663 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1664 };
1665 int i;
1666
1667 /* TLB assist registers */
1668 /* XXX : not implemented */
1669 for (i = 0; i < 8; i++) {
1670 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1671 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1672 uea_write = &spr_write_generic;
1673 }
1674 if (mas_mask & (1 << i)) {
1675 spr_register(env, mas_sprn[i], mas_names[i],
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, uea_write,
1678 0x00000000);
1679 }
1680 }
1681 if (env->nb_pids > 1) {
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_BOOKE_PID1, "PID1",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_booke_pid,
1686 0x00000000);
1687 }
1688 if (env->nb_pids > 2) {
1689 /* XXX : not implemented */
1690 spr_register(env, SPR_BOOKE_PID2, "PID2",
1691 SPR_NOACCESS, SPR_NOACCESS,
1692 &spr_read_generic, &spr_write_booke_pid,
1693 0x00000000);
1694 }
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_MMUCFG, "MMUCFG",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, SPR_NOACCESS,
1699 0x00000000); /* TOFIX */
1700 switch (env->nb_ways) {
1701 case 4:
1702 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, SPR_NOACCESS,
1705 tlbncfg[3]);
1706 /* Fallthru */
1707 case 3:
1708 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, SPR_NOACCESS,
1711 tlbncfg[2]);
1712 /* Fallthru */
1713 case 2:
1714 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, SPR_NOACCESS,
1717 tlbncfg[1]);
1718 /* Fallthru */
1719 case 1:
1720 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, SPR_NOACCESS,
1723 tlbncfg[0]);
1724 /* Fallthru */
1725 case 0:
1726 default:
1727 break;
1728 }
1729 #endif
1730
1731 gen_spr_usprgh(env);
1732 }
1733
1734 /* SPR specific to PowerPC 440 implementation */
1735 static void gen_spr_440 (CPUPPCState *env)
1736 {
1737 /* Cache control */
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_440_DNV0, "DNV0",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_DNV1, "DNV1",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_440_DNV2, "DNV2",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_440_DNV3, "DNV3",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, &spr_write_generic,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_440_DTV0, "DTV0",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_440_DTV1, "DTV1",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_440_DTV2, "DTV2",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_440_DTV3, "DTV3",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_440_DVLIM, "DVLIM",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_440_INV0, "INV0",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_440_INV1, "INV1",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_440_INV2, "INV2",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_440_INV3, "INV3",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_440_ITV0, "ITV0",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_440_ITV1, "ITV1",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* XXX : not implemented */
1814 spr_register(env, SPR_440_ITV2, "ITV2",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 /* XXX : not implemented */
1819 spr_register(env, SPR_440_ITV3, "ITV3",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 /* XXX : not implemented */
1824 spr_register(env, SPR_440_IVLIM, "IVLIM",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 /* Cache debug */
1829 /* XXX : not implemented */
1830 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, SPR_NOACCESS,
1833 0x00000000);
1834 /* XXX : not implemented */
1835 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, SPR_NOACCESS,
1838 0x00000000);
1839 /* XXX : not implemented */
1840 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, SPR_NOACCESS,
1843 0x00000000);
1844 /* XXX : not implemented */
1845 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1846 SPR_NOACCESS, SPR_NOACCESS,
1847 &spr_read_generic, SPR_NOACCESS,
1848 0x00000000);
1849 /* XXX : not implemented */
1850 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_generic, SPR_NOACCESS,
1853 0x00000000);
1854 /* XXX : not implemented */
1855 spr_register(env, SPR_440_DBDR, "DBDR",
1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, &spr_write_generic,
1858 0x00000000);
1859 /* Processor control */
1860 spr_register(env, SPR_4xx_CCR0, "CCR0",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_generic, &spr_write_generic,
1863 0x00000000);
1864 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, SPR_NOACCESS,
1867 0x00000000);
1868 /* Storage control */
1869 spr_register(env, SPR_440_MMUCR, "MMUCR",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 }
1874
1875 /* SPR shared between PowerPC 40x implementations */
1876 static void gen_spr_40x (CPUPPCState *env)
1877 {
1878 /* Cache */
1879 /* not emulated, as QEMU do not emulate caches */
1880 spr_register(env, SPR_40x_DCCR, "DCCR",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0x00000000);
1884 /* not emulated, as QEMU do not emulate caches */
1885 spr_register(env, SPR_40x_ICCR, "ICCR",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 &spr_read_generic, &spr_write_generic,
1888 0x00000000);
1889 /* not emulated, as QEMU do not emulate caches */
1890 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, SPR_NOACCESS,
1893 0x00000000);
1894 /* Exception */
1895 spr_register(env, SPR_40x_DEAR, "DEAR",
1896 SPR_NOACCESS, SPR_NOACCESS,
1897 &spr_read_generic, &spr_write_generic,
1898 0x00000000);
1899 spr_register(env, SPR_40x_ESR, "ESR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
1903 spr_register(env, SPR_40x_EVPR, "EVPR",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_excp_prefix,
1906 0x00000000);
1907 spr_register(env, SPR_40x_SRR2, "SRR2",
1908 &spr_read_generic, &spr_write_generic,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 spr_register(env, SPR_40x_SRR3, "SRR3",
1912 &spr_read_generic, &spr_write_generic,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915 /* Timers */
1916 spr_register(env, SPR_40x_PIT, "PIT",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_40x_pit, &spr_write_40x_pit,
1919 0x00000000);
1920 spr_register(env, SPR_40x_TCR, "TCR",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_booke_tcr,
1923 0x00000000);
1924 spr_register(env, SPR_40x_TSR, "TSR",
1925 SPR_NOACCESS, SPR_NOACCESS,
1926 &spr_read_generic, &spr_write_booke_tsr,
1927 0x00000000);
1928 }
1929
1930 /* SPR specific to PowerPC 405 implementation */
1931 static void gen_spr_405 (CPUPPCState *env)
1932 {
1933 /* MMU */
1934 spr_register(env, SPR_40x_PID, "PID",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_generic, &spr_write_generic,
1937 0x00000000);
1938 spr_register(env, SPR_4xx_CCR0, "CCR0",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00700000);
1942 /* Debug interface */
1943 /* XXX : not implemented */
1944 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 &spr_read_generic, &spr_write_40x_dbcr0,
1947 0x00000000);
1948 /* XXX : not implemented */
1949 spr_register(env, SPR_405_DBCR1, "DBCR1",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 /* XXX : not implemented */
1954 spr_register(env, SPR_40x_DBSR, "DBSR",
1955 SPR_NOACCESS, SPR_NOACCESS,
1956 &spr_read_generic, &spr_write_clear,
1957 /* Last reset was system reset */
1958 0x00000300);
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_40x_DAC1, "DAC1",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964 spr_register(env, SPR_40x_DAC2, "DAC2",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, &spr_write_generic,
1967 0x00000000);
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_405_DVC1, "DVC1",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, &spr_write_generic,
1972 0x00000000);
1973 /* XXX : not implemented */
1974 spr_register(env, SPR_405_DVC2, "DVC2",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 /* XXX : not implemented */
1979 spr_register(env, SPR_40x_IAC1, "IAC1",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_generic,
1982 0x00000000);
1983 spr_register(env, SPR_40x_IAC2, "IAC2",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_405_IAC3, "IAC3",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_405_IAC4, "IAC4",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_generic,
1996 0x00000000);
1997 /* Storage control */
1998 /* XXX: TODO: not implemented */
1999 spr_register(env, SPR_405_SLER, "SLER",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_40x_sler,
2002 0x00000000);
2003 spr_register(env, SPR_40x_ZPR, "ZPR",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_generic,
2006 0x00000000);
2007 /* XXX : not implemented */
2008 spr_register(env, SPR_405_SU0R, "SU0R",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012 /* SPRG */
2013 spr_register(env, SPR_USPRG0, "USPRG0",
2014 &spr_read_ureg, SPR_NOACCESS,
2015 &spr_read_ureg, SPR_NOACCESS,
2016 0x00000000);
2017 spr_register(env, SPR_SPRG4, "SPRG4",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 spr_register(env, SPR_SPRG5, "SPRG5",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 spr_register(env, SPR_SPRG6, "SPRG6",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029 spr_register(env, SPR_SPRG7, "SPRG7",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 gen_spr_usprgh(env);
2034 }
2035
2036 /* SPR shared between PowerPC 401 & 403 implementations */
2037 static void gen_spr_401_403 (CPUPPCState *env)
2038 {
2039 /* Time base */
2040 spr_register(env, SPR_403_VTBL, "TBL",
2041 &spr_read_tbl, SPR_NOACCESS,
2042 &spr_read_tbl, SPR_NOACCESS,
2043 0x00000000);
2044 spr_register(env, SPR_403_TBL, "TBL",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 SPR_NOACCESS, &spr_write_tbl,
2047 0x00000000);
2048 spr_register(env, SPR_403_VTBU, "TBU",
2049 &spr_read_tbu, SPR_NOACCESS,
2050 &spr_read_tbu, SPR_NOACCESS,
2051 0x00000000);
2052 spr_register(env, SPR_403_TBU, "TBU",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 SPR_NOACCESS, &spr_write_tbu,
2055 0x00000000);
2056 /* Debug */
2057 /* not emulated, as QEMU do not emulate caches */
2058 spr_register(env, SPR_403_CDBCR, "CDBCR",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 }
2063
2064 /* SPR specific to PowerPC 401 implementation */
2065 static void gen_spr_401 (CPUPPCState *env)
2066 {
2067 /* Debug interface */
2068 /* XXX : not implemented */
2069 spr_register(env, SPR_40x_DBCR0, "DBCR",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_40x_dbcr0,
2072 0x00000000);
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_40x_DBSR, "DBSR",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_clear,
2077 /* Last reset was system reset */
2078 0x00000300);
2079 /* XXX : not implemented */
2080 spr_register(env, SPR_40x_DAC1, "DAC",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 /* XXX : not implemented */
2085 spr_register(env, SPR_40x_IAC1, "IAC",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089 /* Storage control */
2090 /* XXX: TODO: not implemented */
2091 spr_register(env, SPR_405_SLER, "SLER",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_40x_sler,
2094 0x00000000);
2095 /* not emulated, as QEMU never does speculative access */
2096 spr_register(env, SPR_40x_SGR, "SGR",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0xFFFFFFFF);
2100 /* not emulated, as QEMU do not emulate caches */
2101 spr_register(env, SPR_40x_DCWR, "DCWR",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_generic, &spr_write_generic,
2104 0x00000000);
2105 }
2106
2107 static void gen_spr_401x2 (CPUPPCState *env)
2108 {
2109 gen_spr_401(env);
2110 spr_register(env, SPR_40x_PID, "PID",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2114 spr_register(env, SPR_40x_ZPR, "ZPR",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 }
2119
2120 /* SPR specific to PowerPC 403 implementation */
2121 static void gen_spr_403 (CPUPPCState *env)
2122 {
2123 /* Debug interface */
2124 /* XXX : not implemented */
2125 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_40x_dbcr0,
2128 0x00000000);
2129 /* XXX : not implemented */
2130 spr_register(env, SPR_40x_DBSR, "DBSR",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 &spr_read_generic, &spr_write_clear,
2133 /* Last reset was system reset */
2134 0x00000300);
2135 /* XXX : not implemented */
2136 spr_register(env, SPR_40x_DAC1, "DAC1",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 /* XXX : not implemented */
2141 spr_register(env, SPR_40x_DAC2, "DAC2",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
2145 /* XXX : not implemented */
2146 spr_register(env, SPR_40x_IAC1, "IAC1",
2147 SPR_NOACCESS, SPR_NOACCESS,
2148 &spr_read_generic, &spr_write_generic,
2149 0x00000000);
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_40x_IAC2, "IAC2",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
2155 }
2156
2157 static void gen_spr_403_real (CPUPPCState *env)
2158 {
2159 spr_register(env, SPR_403_PBL1, "PBL1",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_403_pbr, &spr_write_403_pbr,
2162 0x00000000);
2163 spr_register(env, SPR_403_PBU1, "PBU1",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_403_pbr, &spr_write_403_pbr,
2166 0x00000000);
2167 spr_register(env, SPR_403_PBL2, "PBL2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_403_pbr, &spr_write_403_pbr,
2170 0x00000000);
2171 spr_register(env, SPR_403_PBU2, "PBU2",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_403_pbr, &spr_write_403_pbr,
2174 0x00000000);
2175 }
2176
2177 static void gen_spr_403_mmu (CPUPPCState *env)
2178 {
2179 /* MMU */
2180 spr_register(env, SPR_40x_PID, "PID",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184 spr_register(env, SPR_40x_ZPR, "ZPR",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188 }
2189
2190 /* SPR specific to PowerPC compression coprocessor extension */
2191 static void gen_spr_compress (CPUPPCState *env)
2192 {
2193 /* XXX : not implemented */
2194 spr_register(env, SPR_401_SKR, "SKR",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 }
2199
2200 static void gen_spr_5xx_8xx (CPUPPCState *env)
2201 {
2202 /* Exception processing */
2203 spr_register_kvm(env, SPR_DSISR, "DSISR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 KVM_REG_PPC_DSISR, 0x00000000);
2207 spr_register_kvm(env, SPR_DAR, "DAR",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, &spr_write_generic,
2210 KVM_REG_PPC_DAR, 0x00000000);
2211 /* Timer */
2212 spr_register(env, SPR_DECR, "DECR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_decr, &spr_write_decr,
2215 0x00000000);
2216 /* XXX : not implemented */
2217 spr_register(env, SPR_MPC_EIE, "EIE",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221 /* XXX : not implemented */
2222 spr_register(env, SPR_MPC_EID, "EID",
2223 SPR_NOACCESS, SPR_NOACCESS,
2224 &spr_read_generic, &spr_write_generic,
2225 0x00000000);
2226 /* XXX : not implemented */
2227 spr_register(env, SPR_MPC_NRI, "NRI",
2228 SPR_NOACCESS, SPR_NOACCESS,
2229 &spr_read_generic, &spr_write_generic,
2230 0x00000000);
2231 /* XXX : not implemented */
2232 spr_register(env, SPR_MPC_CMPA, "CMPA",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 &spr_read_generic, &spr_write_generic,
2235 0x00000000);
2236 /* XXX : not implemented */
2237 spr_register(env, SPR_MPC_CMPB, "CMPB",
2238 SPR_NOACCESS, SPR_NOACCESS,
2239 &spr_read_generic, &spr_write_generic,
2240 0x00000000);
2241 /* XXX : not implemented */
2242 spr_register(env, SPR_MPC_CMPC, "CMPC",
2243 SPR_NOACCESS, SPR_NOACCESS,
2244 &spr_read_generic, &spr_write_generic,
2245 0x00000000);
2246 /* XXX : not implemented */
2247 spr_register(env, SPR_MPC_CMPD, "CMPD",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 &spr_read_generic, &spr_write_generic,
2250 0x00000000);
2251 /* XXX : not implemented */
2252 spr_register(env, SPR_MPC_ECR, "ECR",
2253 SPR_NOACCESS, SPR_NOACCESS,
2254 &spr_read_generic, &spr_write_generic,
2255 0x00000000);
2256 /* XXX : not implemented */
2257 spr_register(env, SPR_MPC_DER, "DER",
2258 SPR_NOACCESS, SPR_NOACCESS,
2259 &spr_read_generic, &spr_write_generic,
2260 0x00000000);
2261 /* XXX : not implemented */
2262 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2263 SPR_NOACCESS, SPR_NOACCESS,
2264 &spr_read_generic, &spr_write_generic,
2265 0x00000000);
2266 /* XXX : not implemented */
2267 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2270 0x00000000);
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_MPC_CMPE, "CMPE",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_MPC_CMPF, "CMPF",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_MPC_CMPG, "CMPG",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_MPC_CMPH, "CMPH",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 /* XXX : not implemented */
2297 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 /* XXX : not implemented */
2302 spr_register(env, SPR_MPC_BAR, "BAR",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 /* XXX : not implemented */
2307 spr_register(env, SPR_MPC_DPDR, "DPDR",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0x00000000);
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_MPC_IMMR, "IMMR",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 }
2317
2318 static void gen_spr_5xx (CPUPPCState *env)
2319 {
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 /* XXX : not implemented */
2326 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 0x00000000);
2330 /* XXX : not implemented */
2331 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_generic, &spr_write_generic,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 }
2426
2427 static void gen_spr_8xx (CPUPPCState *env)
2428 {
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 }
2555
2556 // XXX: TODO
2557 /*
2558 * AMR => SPR 29 (Power 2.04)
2559 * CTRL => SPR 136 (Power 2.04)
2560 * CTRL => SPR 152 (Power 2.04)
2561 * SCOMC => SPR 276 (64 bits ?)
2562 * SCOMD => SPR 277 (64 bits ?)
2563 * TBU40 => SPR 286 (Power 2.04 hypv)
2564 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2565 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2566 * HDSISR => SPR 306 (Power 2.04 hypv)
2567 * HDAR => SPR 307 (Power 2.04 hypv)
2568 * PURR => SPR 309 (Power 2.04 hypv)
2569 * HDEC => SPR 310 (Power 2.04 hypv)
2570 * HIOR => SPR 311 (hypv)
2571 * RMOR => SPR 312 (970)
2572 * HRMOR => SPR 313 (Power 2.04 hypv)
2573 * HSRR0 => SPR 314 (Power 2.04 hypv)
2574 * HSRR1 => SPR 315 (Power 2.04 hypv)
2575 * LPCR => SPR 316 (970)
2576 * LPIDR => SPR 317 (970)
2577 * EPR => SPR 702 (Power 2.04 emb)
2578 * perf => 768-783 (Power 2.04)
2579 * perf => 784-799 (Power 2.04)
2580 * PPR => SPR 896 (Power 2.04)
2581 * EPLC => SPR 947 (Power 2.04 emb)
2582 * EPSC => SPR 948 (Power 2.04 emb)
2583 * DABRX => 1015 (Power 2.04 hypv)
2584 * FPECR => SPR 1022 (?)
2585 * ... and more (thermal management, performance counters, ...)
2586 */
2587
2588 /*****************************************************************************/
2589 /* Exception vectors models */
2590 static void init_excp_4xx_real (CPUPPCState *env)
2591 {
2592 #if !defined(CONFIG_USER_ONLY)
2593 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2594 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2595 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2596 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2597 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2598 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2599 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2600 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2601 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2602 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2603 env->ivor_mask = 0x0000FFF0UL;
2604 env->ivpr_mask = 0xFFFF0000UL;
2605 /* Hardware reset vector */
2606 env->hreset_vector = 0xFFFFFFFCUL;
2607 #endif
2608 }
2609
2610 static void init_excp_4xx_softmmu (CPUPPCState *env)
2611 {
2612 #if !defined(CONFIG_USER_ONLY)
2613 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2614 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2615 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2616 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2617 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2618 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2619 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2620 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2621 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2622 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2623 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2624 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2625 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2626 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2627 env->ivor_mask = 0x0000FFF0UL;
2628 env->ivpr_mask = 0xFFFF0000UL;
2629 /* Hardware reset vector */
2630 env->hreset_vector = 0xFFFFFFFCUL;
2631 #endif
2632 }
2633
2634 static void init_excp_MPC5xx (CPUPPCState *env)
2635 {
2636 #if !defined(CONFIG_USER_ONLY)
2637 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2638 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2639 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2640 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2641 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2642 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2643 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2644 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2645 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2646 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2647 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2648 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2649 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2650 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2651 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2652 env->ivor_mask = 0x0000FFF0UL;
2653 env->ivpr_mask = 0xFFFF0000UL;
2654 /* Hardware reset vector */
2655 env->hreset_vector = 0x00000100UL;
2656 #endif
2657 }
2658
2659 static void init_excp_MPC8xx (CPUPPCState *env)
2660 {
2661 #if !defined(CONFIG_USER_ONLY)
2662 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2663 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2664 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2665 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2666 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2667 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2668 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2669 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2670 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2671 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2672 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2673 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2674 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2675 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2676 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2677 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2678 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2679 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2680 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2681 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2682 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2683 env->ivor_mask = 0x0000FFF0UL;
2684 env->ivpr_mask = 0xFFFF0000UL;
2685 /* Hardware reset vector */
2686 env->hreset_vector = 0x00000100UL;
2687 #endif
2688 }
2689
2690 static void init_excp_G2 (CPUPPCState *env)
2691 {
2692 #if !defined(CONFIG_USER_ONLY)
2693 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2694 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2695 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2696 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2697 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2698 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2699 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2700 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2701 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2702 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2703 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2704 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2705 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2706 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2707 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2708 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2709 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2710 /* Hardware reset vector */
2711 env->hreset_vector = 0x00000100UL;
2712 #endif
2713 }
2714
2715 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2716 {
2717 #if !defined(CONFIG_USER_ONLY)
2718 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2719 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2738 env->ivor_mask = 0x0000FFF7UL;
2739 env->ivpr_mask = ivpr_mask;
2740 /* Hardware reset vector */
2741 env->hreset_vector = 0xFFFFFFFCUL;
2742 #endif
2743 }
2744
2745 static void init_excp_BookE (CPUPPCState *env)
2746 {
2747 #if !defined(CONFIG_USER_ONLY)
2748 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2763 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2764 env->ivor_mask = 0x0000FFE0UL;
2765 env->ivpr_mask = 0xFFFF0000UL;
2766 /* Hardware reset vector */
2767 env->hreset_vector = 0xFFFFFFFCUL;
2768 #endif
2769 }
2770
2771 static void init_excp_601 (CPUPPCState *env)
2772 {
2773 #if !defined(CONFIG_USER_ONLY)
2774 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2775 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2776 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2777 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2778 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2779 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2780 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2781 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2782 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2783 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2784 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2785 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2786 /* Hardware reset vector */
2787 env->hreset_vector = 0x00000100UL;
2788 #endif
2789 }
2790
2791 static void init_excp_602 (CPUPPCState *env)
2792 {
2793 #if !defined(CONFIG_USER_ONLY)
2794 /* XXX: exception prefix has a special behavior on 602 */
2795 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2796 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2797 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2798 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2799 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2800 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2801 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2802 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2803 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2804 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2805 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2806 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2807 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2808 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2809 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2810 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2811 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2812 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2813 /* Hardware reset vector */
2814 env->hreset_vector = 0x00000100UL;
2815 #endif
2816 }
2817
2818 static void init_excp_603 (CPUPPCState *env)
2819 {
2820 #if !defined(CONFIG_USER_ONLY)
2821 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2822 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2823 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2824 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2825 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2826 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2827 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2828 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2829 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2830 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2831 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2832 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2833 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2834 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2835 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2836 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2837 /* Hardware reset vector */
2838 env->hreset_vector = 0x00000100UL;
2839 #endif
2840 }
2841
2842 static void init_excp_604 (CPUPPCState *env)
2843 {
2844 #if !defined(CONFIG_USER_ONLY)
2845 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2846 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2847 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2848 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2849 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2850 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2851 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2852 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2853 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2854 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2855 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2856 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2857 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2858 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2859 /* Hardware reset vector */
2860 env->hreset_vector = 0x00000100UL;
2861 #endif
2862 }
2863
2864 static void init_excp_7x0 (CPUPPCState *env)
2865 {
2866 #if !defined(CONFIG_USER_ONLY)
2867 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2868 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2869 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2870 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2871 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2872 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2873 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2874 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2876 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2877 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2878 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2879 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2880 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2881 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2882 /* Hardware reset vector */
2883 env->hreset_vector = 0x00000100UL;
2884 #endif
2885 }
2886
2887 static void init_excp_750cl (CPUPPCState *env)
2888 {
2889 #if !defined(CONFIG_USER_ONLY)
2890 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2891 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2892 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2893 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2894 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2896 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2897 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2898 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2899 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2900 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2901 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2902 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2903 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2904 /* Hardware reset vector */
2905 env->hreset_vector = 0x00000100UL;
2906 #endif
2907 }
2908
2909 static void init_excp_750cx (CPUPPCState *env)
2910 {
2911 #if !defined(CONFIG_USER_ONLY)
2912 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2913 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2914 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2915 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2916 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2917 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2918 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2919 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2920 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2921 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2922 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2923 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2924 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2925 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2926 /* Hardware reset vector */
2927 env->hreset_vector = 0x00000100UL;
2928 #endif
2929 }
2930
2931 /* XXX: Check if this is correct */
2932 static void init_excp_7x5 (CPUPPCState *env)
2933 {
2934 #if !defined(CONFIG_USER_ONLY)
2935 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2936 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2937 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2938 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2939 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2940 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2941 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2942 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2943 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2944 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2945 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2946 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2947 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2948 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2949 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2950 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2951 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2952 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2953 /* Hardware reset vector */
2954 env->hreset_vector = 0x00000100UL;
2955 #endif
2956 }
2957
2958 static void init_excp_7400 (CPUPPCState *env)
2959 {
2960 #if !defined(CONFIG_USER_ONLY)
2961 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2962 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2963 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2964 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2965 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2967 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2968 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2969 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2970 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2971 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2972 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2973 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2974 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2975 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2976 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2977 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2978 /* Hardware reset vector */
2979 env->hreset_vector = 0x00000100UL;
2980 #endif
2981 }
2982
2983 static void init_excp_7450 (CPUPPCState *env)
2984 {
2985 #if !defined(CONFIG_USER_ONLY)
2986 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2987 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2988 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2989 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2990 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2991 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2992 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2993 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2994 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2995 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2996 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2997 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2998 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2999 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3000 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3001 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3002 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3003 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3004 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3005 /* Hardware reset vector */
3006 env->hreset_vector = 0x00000100UL;
3007 #endif
3008 }
3009
3010 #if defined (TARGET_PPC64)
3011 static void init_excp_970 (CPUPPCState *env)
3012 {
3013 #if !defined(CONFIG_USER_ONLY)
3014 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3015 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3016 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3017 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3018 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3019 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3020 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3021 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3022 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3023 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3024 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3025 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3026 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3027 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3028 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3029 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3030 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3031 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3032 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3033 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3034 /* Hardware reset vector */
3035 env->hreset_vector = 0x0000000000000100ULL;
3036 #endif
3037 }
3038
3039 static void init_excp_POWER7 (CPUPPCState *env)
3040 {
3041 #if !defined(CONFIG_USER_ONLY)
3042 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3043 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3044 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3045 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3046 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3047 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3048 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3049 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3050 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3051 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3052 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3053 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3054 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3055 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3056 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3057 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3058 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3059 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3060 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3061 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3062 /* Hardware reset vector */
3063 env->hreset_vector = 0x0000000000000100ULL;
3064 #endif
3065 }
3066 #endif
3067
3068 /*****************************************************************************/
3069 /* Power management enable checks */
3070 static int check_pow_none (CPUPPCState *env)
3071 {
3072 return 0;
3073 }
3074
3075 static int check_pow_nocheck (CPUPPCState *env)
3076 {
3077 return 1;
3078 }
3079
3080 static int check_pow_hid0 (CPUPPCState *env)
3081 {
3082 if (env->spr[SPR_HID0] & 0x00E00000)
3083 return 1;
3084
3085 return 0;
3086 }
3087
3088 static int check_pow_hid0_74xx (CPUPPCState *env)
3089 {
3090 if (env->spr[SPR_HID0] & 0x00600000)
3091 return 1;
3092
3093 return 0;
3094 }
3095
3096 /*****************************************************************************/
3097 /* PowerPC implementations definitions */
3098
3099 #define POWERPC_FAMILY(_name) \
3100 static void \
3101 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3102 \
3103 static const TypeInfo \
3104 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3105 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3106 .parent = TYPE_POWERPC_CPU, \
3107 .abstract = true, \
3108 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3109 }; \
3110 \
3111 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3112 { \
3113 type_register_static( \
3114 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3115 } \
3116 \
3117 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3118 \
3119 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3120
3121 static void init_proc_401 (CPUPPCState *env)
3122 {
3123 gen_spr_40x(env);
3124 gen_spr_401_403(env);
3125 gen_spr_401(env);
3126 init_excp_4xx_real(env);
3127 env->dcache_line_size = 32;
3128 env->icache_line_size = 32;
3129 /* Allocate hardware IRQ controller */
3130 ppc40x_irq_init(env);
3131
3132 SET_FIT_PERIOD(12, 16, 20, 24);
3133 SET_WDT_PERIOD(16, 20, 24, 28);
3134 }
3135
3136 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3137 {
3138 DeviceClass *dc = DEVICE_CLASS(oc);
3139 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3140
3141 dc->desc = "PowerPC 401";
3142 pcc->init_proc = init_proc_401;
3143 pcc->check_pow = check_pow_nocheck;
3144 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3145 PPC_WRTEE | PPC_DCR |
3146 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3147 PPC_CACHE_DCBZ |
3148 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3149 PPC_4xx_COMMON | PPC_40x_EXCP;
3150 pcc->insns_flags2 = PPC_NONE;
3151 pcc->msr_mask = 0x00000000000FD201ULL;
3152 pcc->mmu_model = POWERPC_MMU_REAL;
3153 pcc->excp_model = POWERPC_EXCP_40x;
3154 pcc->bus_model = PPC_FLAGS_INPUT_401;
3155 pcc->bfd_mach = bfd_mach_ppc_403;
3156 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3157 POWERPC_FLAG_BUS_CLK;
3158 }
3159
3160 static void init_proc_401x2 (CPUPPCState *env)
3161 {
3162 gen_spr_40x(env);
3163 gen_spr_401_403(env);
3164 gen_spr_401x2(env);
3165 gen_spr_compress(env);
3166 /* Memory management */
3167 #if !defined(CONFIG_USER_ONLY)
3168 env->nb_tlb = 64;
3169 env->nb_ways = 1;
3170 env->id_tlbs = 0;
3171 env->tlb_type = TLB_EMB;
3172 #endif
3173 init_excp_4xx_softmmu(env);
3174 env->dcache_line_size = 32;
3175 env->icache_line_size = 32;
3176 /* Allocate hardware IRQ controller */
3177 ppc40x_irq_init(env);
3178
3179 SET_FIT_PERIOD(12, 16, 20, 24);
3180 SET_WDT_PERIOD(16, 20, 24, 28);
3181 }
3182
3183 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3184 {
3185 DeviceClass *dc = DEVICE_CLASS(oc);
3186 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3187
3188 dc->desc = "PowerPC 401x2";
3189 pcc->init_proc = init_proc_401x2;
3190 pcc->check_pow = check_pow_nocheck;
3191 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3192 PPC_DCR | PPC_WRTEE |
3193 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3194 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3195 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3196 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3197 PPC_4xx_COMMON | PPC_40x_EXCP;
3198 pcc->insns_flags2 = PPC_NONE;
3199 pcc->msr_mask = 0x00000000001FD231ULL;
3200 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3201 pcc->excp_model = POWERPC_EXCP_40x;
3202 pcc->bus_model = PPC_FLAGS_INPUT_401;
3203 pcc->bfd_mach = bfd_mach_ppc_403;
3204 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3205 POWERPC_FLAG_BUS_CLK;
3206 }
3207
3208 static void init_proc_401x3 (CPUPPCState *env)
3209 {
3210 gen_spr_40x(env);
3211 gen_spr_401_403(env);
3212 gen_spr_401(env);
3213 gen_spr_401x2(env);
3214 gen_spr_compress(env);
3215 init_excp_4xx_softmmu(env);
3216 env->dcache_line_size = 32;
3217 env->icache_line_size = 32;
3218 /* Allocate hardware IRQ controller */
3219 ppc40x_irq_init(env);
3220
3221 SET_FIT_PERIOD(12, 16, 20, 24);
3222 SET_WDT_PERIOD(16, 20, 24, 28);
3223 }
3224
3225 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3226 {
3227 DeviceClass *dc = DEVICE_CLASS(oc);
3228 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3229
3230 dc->desc = "PowerPC 401x3";
3231 pcc->init_proc = init_proc_401x3;
3232 pcc->check_pow = check_pow_nocheck;
3233 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3234 PPC_DCR | PPC_WRTEE |
3235 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3236 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3237 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3238 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3239 PPC_4xx_COMMON | PPC_40x_EXCP;
3240 pcc->insns_flags2 = PPC_NONE;
3241 pcc->msr_mask = 0x00000000001FD631ULL;
3242 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3243 pcc->excp_model = POWERPC_EXCP_40x;
3244 pcc->bus_model = PPC_FLAGS_INPUT_401;
3245 pcc->bfd_mach = bfd_mach_ppc_403;
3246 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3247 POWERPC_FLAG_BUS_CLK;
3248 }
3249
3250 static void init_proc_IOP480 (CPUPPCState *env)
3251 {
3252 gen_spr_40x(env);
3253 gen_spr_401_403(env);
3254 gen_spr_401x2(env);
3255 gen_spr_compress(env);
3256 /* Memory management */
3257 #if !defined(CONFIG_USER_ONLY)
3258 env->nb_tlb = 64;
3259 env->nb_ways = 1;
3260 env->id_tlbs = 0;
3261 env->tlb_type = TLB_EMB;
3262 #endif
3263 init_excp_4xx_softmmu(env);
3264 env->dcache_line_size = 32;
3265 env->icache_line_size = 32;
3266 /* Allocate hardware IRQ controller */
3267 ppc40x_irq_init(env);
3268
3269 SET_FIT_PERIOD(8, 12, 16, 20);
3270 SET_WDT_PERIOD(16, 20, 24, 28);
3271 }
3272
3273 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3274 {
3275 DeviceClass *dc = DEVICE_CLASS(oc);
3276 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3277
3278 dc->desc = "IOP480";
3279 pcc->init_proc = init_proc_IOP480;
3280 pcc->check_pow = check_pow_nocheck;
3281 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3282 PPC_DCR | PPC_WRTEE |
3283 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3284 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3285 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3286 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3287 PPC_4xx_COMMON | PPC_40x_EXCP;
3288 pcc->insns_flags2 = PPC_NONE;
3289 pcc->msr_mask = 0x00000000001FD231ULL;
3290 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3291 pcc->excp_model = POWERPC_EXCP_40x;
3292 pcc->bus_model = PPC_FLAGS_INPUT_401;
3293 pcc->bfd_mach = bfd_mach_ppc_403;
3294 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3295 POWERPC_FLAG_BUS_CLK;
3296 }
3297
3298 static void init_proc_403 (CPUPPCState *env)
3299 {
3300 gen_spr_40x(env);
3301 gen_spr_401_403(env);
3302 gen_spr_403(env);
3303 gen_spr_403_real(env);
3304 init_excp_4xx_real(env);
3305 env->dcache_line_size = 32;
3306 env->icache_line_size = 32;
3307 /* Allocate hardware IRQ controller */
3308 ppc40x_irq_init(env);
3309
3310 SET_FIT_PERIOD(8, 12, 16, 20);
3311 SET_WDT_PERIOD(16, 20, 24, 28);
3312 }
3313
3314 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3315 {
3316 DeviceClass *dc = DEVICE_CLASS(oc);
3317 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3318
3319 dc->desc = "PowerPC 403";
3320 pcc->init_proc = init_proc_403;
3321 pcc->check_pow = check_pow_nocheck;
3322 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3323 PPC_DCR | PPC_WRTEE |
3324 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3325 PPC_CACHE_DCBZ |
3326 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3327 PPC_4xx_COMMON | PPC_40x_EXCP;
3328 pcc->insns_flags2 = PPC_NONE;
3329 pcc->msr_mask = 0x000000000007D00DULL;
3330 pcc->mmu_model = POWERPC_MMU_REAL;
3331 pcc->excp_model = POWERPC_EXCP_40x;
3332 pcc->bus_model = PPC_FLAGS_INPUT_401;
3333 pcc->bfd_mach = bfd_mach_ppc_403;
3334 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3335 POWERPC_FLAG_BUS_CLK;
3336 }
3337
3338 static void init_proc_403GCX (CPUPPCState *env)
3339 {
3340 gen_spr_40x(env);
3341 gen_spr_401_403(env);
3342 gen_spr_403(env);
3343 gen_spr_403_real(env);
3344 gen_spr_403_mmu(env);
3345 /* Bus access control */
3346 /* not emulated, as QEMU never does speculative access */
3347 spr_register(env, SPR_40x_SGR, "SGR",
3348 SPR_NOACCESS, SPR_NOACCESS,
3349 &spr_read_generic, &spr_write_generic,
3350 0xFFFFFFFF);
3351 /* not emulated, as QEMU do not emulate caches */
3352 spr_register(env, SPR_40x_DCWR, "DCWR",
3353 SPR_NOACCESS, SPR_NOACCESS,
3354 &spr_read_generic, &spr_write_generic,
3355 0x00000000);
3356 /* Memory management */
3357 #if !defined(CONFIG_USER_ONLY)
3358 env->nb_tlb = 64;
3359 env->nb_ways = 1;
3360 env->id_tlbs = 0;
3361 env->tlb_type = TLB_EMB;
3362 #endif
3363 init_excp_4xx_softmmu(env);
3364 env->dcache_line_size = 32;
3365 env->icache_line_size = 32;
3366 /* Allocate hardware IRQ controller */
3367 ppc40x_irq_init(env);
3368
3369 SET_FIT_PERIOD(8, 12, 16, 20);
3370 SET_WDT_PERIOD(16, 20, 24, 28);
3371 }
3372
3373 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3374 {
3375 DeviceClass *dc = DEVICE_CLASS(oc);
3376 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3377
3378 dc->desc = "PowerPC 403 GCX";
3379 pcc->init_proc = init_proc_403GCX;
3380 pcc->check_pow = check_pow_nocheck;
3381 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3382 PPC_DCR | PPC_WRTEE |
3383 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3384 PPC_CACHE_DCBZ |
3385 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3386 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3387 PPC_4xx_COMMON | PPC_40x_EXCP;
3388 pcc->insns_flags2 = PPC_NONE;
3389 pcc->msr_mask = 0x000000000007D00DULL;
3390 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3391 pcc->excp_model = POWERPC_EXCP_40x;
3392 pcc->bus_model = PPC_FLAGS_INPUT_401;
3393 pcc->bfd_mach = bfd_mach_ppc_403;
3394 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3395 POWERPC_FLAG_BUS_CLK;
3396 }
3397
3398 static void init_proc_405 (CPUPPCState *env)
3399 {
3400 /* Time base */
3401 gen_tbl(env);
3402 gen_spr_40x(env);
3403 gen_spr_405(env);
3404 /* Bus access control */
3405 /* not emulated, as QEMU never does speculative access */
3406 spr_register(env, SPR_40x_SGR, "SGR",
3407 SPR_NOACCESS, SPR_NOACCESS,
3408 &spr_read_generic, &spr_write_generic,
3409 0xFFFFFFFF);
3410 /* not emulated, as QEMU do not emulate caches */
3411 spr_register(env, SPR_40x_DCWR, "DCWR",
3412 SPR_NOACCESS, SPR_NOACCESS,
3413 &spr_read_generic, &spr_write_generic,
3414 0x00000000);
3415 /* Memory management */
3416 #if !defined(CONFIG_USER_ONLY)
3417 env->nb_tlb = 64;
3418 env->nb_ways = 1;
3419 env->id_tlbs = 0;
3420 env->tlb_type = TLB_EMB;
3421 #endif
3422 init_excp_4xx_softmmu(env);
3423 env->dcache_line_size = 32;
3424 env->icache_line_size = 32;
3425 /* Allocate hardware IRQ controller */
3426 ppc40x_irq_init(env);
3427
3428 SET_FIT_PERIOD(8, 12, 16, 20);
3429 SET_WDT_PERIOD(16, 20, 24, 28);
3430 }
3431
3432 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3433 {
3434 DeviceClass *dc = DEVICE_CLASS(oc);
3435 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3436
3437 dc->desc = "PowerPC 405";
3438 pcc->init_proc = init_proc_405;
3439 pcc->check_pow = check_pow_nocheck;
3440 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3441 PPC_DCR | PPC_WRTEE |
3442 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3443 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3444 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3445 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3446 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3447 pcc->insns_flags2 = PPC_NONE;
3448 pcc->msr_mask = 0x000000000006E630ULL;
3449 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3450 pcc->excp_model = POWERPC_EXCP_40x;
3451 pcc->bus_model = PPC_FLAGS_INPUT_405;
3452 pcc->bfd_mach = bfd_mach_ppc_403;
3453 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3454 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3455 }
3456
3457 static void init_proc_440EP (CPUPPCState *env)
3458 {
3459 /* Time base */
3460 gen_tbl(env);
3461 gen_spr_BookE(env, 0x000000000000FFFFULL);
3462 gen_spr_440(env);
3463 gen_spr_usprgh(env);
3464 /* Processor identification */
3465 spr_register(env, SPR_BOOKE_PIR, "PIR",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, &spr_write_pir,
3468 0x00000000);
3469 /* XXX : not implemented */
3470 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3471 SPR_NOACCESS, SPR_NOACCESS,
3472 &spr_read_generic, &spr_write_generic,
3473 0x00000000);
3474 /* XXX : not implemented */
3475 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3476 SPR_NOACCESS, SPR_NOACCESS,
3477 &spr_read_generic, &spr_write_generic,
3478 0x00000000);
3479 /* XXX : not implemented */
3480 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3481 SPR_NOACCESS, SPR_NOACCESS,
3482 &spr_read_generic, &spr_write_generic,
3483 0x00000000);
3484 /* XXX : not implemented */
3485 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3486 SPR_NOACCESS, SPR_NOACCESS,
3487 &spr_read_generic, &spr_write_generic,
3488 0x00000000);
3489 /* XXX : not implemented */
3490 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3491 SPR_NOACCESS, SPR_NOACCESS,
3492 &spr_read_generic, &spr_write_generic,
3493 0x00000000);
3494 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3495 SPR_NOACCESS, SPR_NOACCESS,
3496 &spr_read_generic, &spr_write_generic,
3497 0x00000000);
3498 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3499 SPR_NOACCESS, SPR_NOACCESS,
3500 &spr_read_generic, &spr_write_generic,
3501 0x00000000);
3502 /* XXX : not implemented */
3503 spr_register(env, SPR_440_CCR1, "CCR1",
3504 SPR_NOACCESS, SPR_NOACCESS,
3505 &spr_read_generic, &spr_write_generic,
3506 0x00000000);
3507 /* Memory management */
3508 #if !defined(CONFIG_USER_ONLY)
3509 env->nb_tlb = 64;
3510 env->nb_ways = 1;
3511 env->id_tlbs = 0;
3512 env->tlb_type = TLB_EMB;
3513 #endif
3514 init_excp_BookE(env);
3515 env->dcache_line_size = 32;
3516 env->icache_line_size = 32;
3517 ppc40x_irq_init(env);
3518
3519 SET_FIT_PERIOD(12, 16, 20, 24);
3520 SET_WDT_PERIOD(20, 24, 28, 32);
3521 }
3522
3523 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3524 {
3525 DeviceClass *dc = DEVICE_CLASS(oc);
3526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3527
3528 dc->desc = "PowerPC 440 EP";
3529 pcc->init_proc = init_proc_440EP;
3530 pcc->check_pow = check_pow_nocheck;
3531 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3532 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3533 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3534 PPC_FLOAT_STFIWX |
3535 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3536 PPC_CACHE | PPC_CACHE_ICBI |
3537 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3538 PPC_MEM_TLBSYNC | PPC_MFTB |
3539 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3540 PPC_440_SPEC;
3541 pcc->insns_flags2 = PPC_NONE;
3542 pcc->msr_mask = 0x000000000006FF30ULL;
3543 pcc->mmu_model = POWERPC_MMU_BOOKE;
3544 pcc->excp_model = POWERPC_EXCP_BOOKE;
3545 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3546 pcc->bfd_mach = bfd_mach_ppc_403;
3547 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3548 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3549 }
3550
3551 static void init_proc_440GP (CPUPPCState *env)
3552 {
3553 /* Time base */
3554 gen_tbl(env);
3555 gen_spr_BookE(env, 0x000000000000FFFFULL);
3556 gen_spr_440(env);
3557 gen_spr_usprgh(env);
3558 /* Processor identification */
3559 spr_register(env, SPR_BOOKE_PIR, "PIR",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_pir,
3562 0x00000000);
3563 /* XXX : not implemented */
3564 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3565 SPR_NOACCESS, SPR_NOACCESS,
3566 &spr_read_generic, &spr_write_generic,
3567 0x00000000);
3568 /* XXX : not implemented */
3569 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
3577 0x00000000);
3578 /* XXX : not implemented */
3579 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 /* Memory management */
3584 #if !defined(CONFIG_USER_ONLY)
3585 env->nb_tlb = 64;
3586 env->nb_ways = 1;
3587 env->id_tlbs = 0;
3588 env->tlb_type = TLB_EMB;
3589 #endif
3590 init_excp_BookE(env);
3591 env->dcache_line_size = 32;
3592 env->icache_line_size = 32;
3593 /* XXX: TODO: allocate internal IRQ controller */
3594
3595 SET_FIT_PERIOD(12, 16, 20, 24);
3596 SET_WDT_PERIOD(20, 24, 28, 32);
3597 }
3598
3599 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3600 {
3601 DeviceClass *dc = DEVICE_CLASS(oc);
3602 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3603
3604 dc->desc = "PowerPC 440 GP";
3605 pcc->init_proc = init_proc_440GP;
3606 pcc->check_pow = check_pow_nocheck;
3607 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3608 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3609 PPC_CACHE | PPC_CACHE_ICBI |
3610 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3611 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3612 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3613 PPC_440_SPEC;
3614 pcc->insns_flags2 = PPC_NONE;
3615 pcc->msr_mask = 0x000000000006FF30ULL;
3616 pcc->mmu_model = POWERPC_MMU_BOOKE;
3617 pcc->excp_model = POWERPC_EXCP_BOOKE;
3618 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3619 pcc->bfd_mach = bfd_mach_ppc_403;
3620 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3621 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3622 }
3623
3624 static void init_proc_440x4 (CPUPPCState *env)
3625 {
3626 /* Time base */
3627 gen_tbl(env);
3628 gen_spr_BookE(env, 0x000000000000FFFFULL);
3629 gen_spr_440(env);
3630 gen_spr_usprgh(env);
3631 /* Processor identification */
3632 spr_register(env, SPR_BOOKE_PIR, "PIR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_pir,
3635 0x00000000);
3636 /* XXX : not implemented */
3637 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657 #if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
3661 env->tlb_type = TLB_EMB;
3662 #endif
3663 init_excp_BookE(env);
3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
3666 /* XXX: TODO: allocate internal IRQ controller */
3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
3670 }
3671
3672 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3673 {
3674 DeviceClass *dc = DEVICE_CLASS(oc);
3675 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3676
3677 dc->desc = "PowerPC 440x4";
3678 pcc->init_proc = init_proc_440x4;
3679 pcc->check_pow = check_pow_nocheck;
3680 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3681 PPC_DCR | PPC_WRTEE |
3682 PPC_CACHE | PPC_CACHE_ICBI |
3683 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3684 PPC_MEM_TLBSYNC | PPC_MFTB |
3685 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3686 PPC_440_SPEC;
3687 pcc->insns_flags2 = PPC_NONE;
3688 pcc->msr_mask = 0x000000000006FF30ULL;
3689 pcc->mmu_model = POWERPC_MMU_BOOKE;
3690 pcc->excp_model = POWERPC_EXCP_BOOKE;
3691 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3692 pcc->bfd_mach = bfd_mach_ppc_403;
3693 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3694 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3695 }
3696
3697 static void init_proc_440x5 (CPUPPCState *env)
3698 {
3699 /* Time base */
3700 gen_tbl(env);
3701 gen_spr_BookE(env, 0x000000000000FFFFULL);
3702 gen_spr_440(env);
3703 gen_spr_usprgh(env);
3704 /* Processor identification */
3705 spr_register(env, SPR_BOOKE_PIR, "PIR",
3706 SPR_NOACCESS, SPR_NOACCESS,
3707 &spr_read_generic, &spr_write_pir,
3708 0x00000000);
3709 /* XXX : not implemented */
3710 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3711 SPR_NOACCESS, SPR_NOACCESS,
3712 &spr_read_generic, &spr_write_generic,
3713 0x00000000);
3714 /* XXX : not implemented */
3715 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3716 SPR_NOACCESS, SPR_NOACCESS,
3717 &spr_read_generic, &spr_write_generic,
3718 0x00000000);
3719 /* XXX : not implemented */
3720 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_generic,
3723 0x00000000);
3724 /* XXX : not implemented */
3725 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 /* XXX : not implemented */
3730 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3731 SPR_NOACCESS, SPR_NOACCESS,
3732 &spr_read_generic, &spr_write_generic,
3733 0x00000000);
3734 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
3742 /* XXX : not implemented */
3743 spr_register(env, SPR_440_CCR1, "CCR1",
3744 SPR_NOACCESS, SPR_NOACCESS,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
3747 /* Memory management */
3748 #if !defined(CONFIG_USER_ONLY)
3749 env->nb_tlb = 64;
3750 env->nb_ways = 1;
3751 env->id_tlbs = 0;
3752 env->tlb_type = TLB_EMB;
3753 #endif
3754 init_excp_BookE(env);
3755 env->dcache_line_size = 32;
3756 env->icache_line_size = 32;
3757 ppc40x_irq_init(env);
3758
3759 SET_FIT_PERIOD(12, 16, 20, 24);
3760 SET_WDT_PERIOD(20, 24, 28, 32);
3761 }
3762
3763 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3764 {
3765 DeviceClass *dc = DEVICE_CLASS(oc);
3766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3767
3768 dc->desc = "PowerPC 440x5";
3769 pcc->init_proc = init_proc_440x5;
3770 pcc->check_pow = check_pow_nocheck;
3771 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3772 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3773 PPC_CACHE | PPC_CACHE_ICBI |
3774 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3775 PPC_MEM_TLBSYNC | PPC_MFTB |
3776 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3777 PPC_440_SPEC;
3778 pcc->insns_flags2 = PPC_NONE;
3779 pcc->msr_mask = 0x000000000006FF30ULL;
3780 pcc->mmu_model = POWERPC_MMU_BOOKE;
3781 pcc->excp_model = POWERPC_EXCP_BOOKE;
3782 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3783 pcc->bfd_mach = bfd_mach_ppc_403;
3784 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3785 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3786 }
3787
3788 static void init_proc_460 (CPUPPCState *env)
3789 {
3790 /* Time base */
3791 gen_tbl(env);
3792 gen_spr_BookE(env, 0x000000000000FFFFULL);
3793 gen_spr_440(env);
3794 gen_spr_usprgh(env);
3795 /* Processor identification */
3796 spr_register(env, SPR_BOOKE_PIR, "PIR",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_pir,
3799 0x00000000);
3800 /* XXX : not implemented */
3801 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* XXX : not implemented */
3806 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810 /* XXX : not implemented */
3811 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3812 SPR_NOACCESS, SPR_NOACCESS,
3813 &spr_read_generic, &spr_write_generic,
3814 0x00000000);
3815 /* XXX : not implemented */
3816 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3817 SPR_NOACCESS, SPR_NOACCESS,
3818 &spr_read_generic, &spr_write_generic,
3819 0x00000000);
3820 /* XXX : not implemented */
3821 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3822 SPR_NOACCESS, SPR_NOACCESS,
3823 &spr_read_generic, &spr_write_generic,
3824 0x00000000);
3825 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3826 SPR_NOACCESS, SPR_NOACCESS,
3827 &spr_read_generic, &spr_write_generic,
3828 0x00000000);
3829 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3830 SPR_NOACCESS, SPR_NOACCESS,
3831 &spr_read_generic, &spr_write_generic,
3832 0x00000000);
3833 /* XXX : not implemented */
3834 spr_register(env, SPR_440_CCR1, "CCR1",
3835 SPR_NOACCESS, SPR_NOACCESS,
3836 &spr_read_generic, &spr_write_generic,
3837 0x00000000);
3838 /* XXX : not implemented */
3839 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3840 &spr_read_generic, &spr_write_generic,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* Memory management */
3844 #if !defined(CONFIG_USER_ONLY)
3845 env->nb_tlb = 64;
3846 env->nb_ways = 1;
3847 env->id_tlbs = 0;
3848 env->tlb_type = TLB_EMB;
3849 #endif
3850 init_excp_BookE(env);
3851 env->dcache_line_size = 32;
3852 env->icache_line_size = 32;
3853 /* XXX: TODO: allocate internal IRQ controller */
3854
3855 SET_FIT_PERIOD(12, 16, 20, 24);
3856 SET_WDT_PERIOD(20, 24, 28, 32);
3857 }
3858
3859 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3860 {
3861 DeviceClass *dc = DEVICE_CLASS(oc);
3862 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3863
3864 dc->desc = "PowerPC 460 (guessed)";
3865 pcc->init_proc = init_proc_460;
3866 pcc->check_pow = check_pow_nocheck;
3867 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3868 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3869 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3870 PPC_CACHE | PPC_CACHE_ICBI |
3871 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3872 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3873 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3874 PPC_440_SPEC;
3875 pcc->insns_flags2 = PPC_NONE;
3876 pcc->msr_mask = 0x000000000006FF30ULL;
3877 pcc->mmu_model = POWERPC_MMU_BOOKE;
3878 pcc->excp_model = POWERPC_EXCP_BOOKE;
3879 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3880 pcc->bfd_mach = bfd_mach_ppc_403;
3881 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3882 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3883 }
3884
3885 static void init_proc_460F (CPUPPCState *env)
3886 {
3887 /* Time base */
3888 gen_tbl(env);
3889 gen_spr_BookE(env, 0x000000000000FFFFULL);
3890 gen_spr_440(env);
3891 gen_spr_usprgh(env);
3892 /* Processor identification */
3893 spr_register(env, SPR_BOOKE_PIR, "PIR",
3894 SPR_NOACCESS, SPR_NOACCESS,
3895 &spr_read_generic, &spr_write_pir,
3896 0x00000000);
3897 /* XXX : not implemented */
3898 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3899 SPR_NOACCESS, SPR_NOACCESS,
3900 &spr_read_generic, &spr_write_generic,
3901 0x00000000);
3902 /* XXX : not implemented */
3903 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3904 SPR_NOACCESS, SPR_NOACCESS,
3905 &spr_read_generic, &spr_write_generic,
3906 0x00000000);
3907 /* XXX : not implemented */
3908 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* XXX : not implemented */
3913 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
3917 /* XXX : not implemented */
3918 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3919 SPR_NOACCESS, SPR_NOACCESS,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3923 SPR_NOACCESS, SPR_NOACCESS,
3924 &spr_read_generic, &spr_write_generic,
3925 0x00000000);
3926 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3927 SPR_NOACCESS, SPR_NOACCESS,
3928 &spr_read_generic, &spr_write_generic,
3929 0x00000000);
3930 /* XXX : not implemented */
3931 spr_register(env, SPR_440_CCR1, "CCR1",
3932 SPR_NOACCESS, SPR_NOACCESS,
3933 &spr_read_generic, &spr_write_generic,
3934 0x00000000);
3935 /* XXX : not implemented */
3936 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3937 &spr_read_generic, &spr_write_generic,
3938 &spr_read_generic, &spr_write_generic,
3939 0x00000000);
3940 /* Memory management */
3941 #if !defined(CONFIG_USER_ONLY)
3942 env->nb_tlb = 64;
3943 env->nb_ways = 1;
3944 env->id_tlbs = 0;
3945 env->tlb_type = TLB_EMB;
3946 #endif
3947 init_excp_BookE(env);
3948 env->dcache_line_size = 32;
3949 env->icache_line_size = 32;
3950 /* XXX: TODO: allocate internal IRQ controller */
3951
3952 SET_FIT_PERIOD(12, 16, 20, 24);
3953 SET_WDT_PERIOD(20, 24, 28, 32);
3954 }
3955
3956 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3957 {
3958 DeviceClass *dc = DEVICE_CLASS(oc);
3959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3960
3961 dc->desc = "PowerPC 460F (guessed)";
3962 pcc->init_proc = init_proc_460F;
3963 pcc->check_pow = check_pow_nocheck;
3964 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3965 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3966 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3967 PPC_FLOAT_STFIWX | PPC_MFTB |
3968 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3969 PPC_WRTEE | PPC_MFAPIDI |
3970 PPC_CACHE | PPC_CACHE_ICBI |
3971 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3972 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3973 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3974 PPC_440_SPEC;
3975 pcc->insns_flags2 = PPC_NONE;
3976 pcc->msr_mask = 0x000000000006FF30ULL;
3977 pcc->mmu_model = POWERPC_MMU_BOOKE;
3978 pcc->excp_model = POWERPC_EXCP_BOOKE;
3979 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3980 pcc->bfd_mach = bfd_mach_ppc_403;
3981 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3982 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3983 }
3984
3985 static void init_proc_MPC5xx (CPUPPCState *env)
3986 {
3987 /* Time base */
3988 gen_tbl(env);
3989 gen_spr_5xx_8xx(env);
3990 gen_spr_5xx(env);
3991 init_excp_MPC5xx(env);
3992 env->dcache_line_size = 32;
3993 env->icache_line_size = 32;
3994 /* XXX: TODO: allocate internal IRQ controller */
3995 }
3996
3997 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3998 {
3999 DeviceClass *dc = DEVICE_CLASS(oc);
4000 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4001
4002 dc->desc = "Freescale 5xx cores (aka RCPU)";
4003 pcc->init_proc = init_proc_MPC5xx;
4004 pcc->check_pow = check_pow_none;
4005 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4006 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4007 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4008 PPC_MFTB;
4009 pcc->insns_flags2 = PPC_NONE;
4010 pcc->msr_mask = 0x000000000001FF43ULL;
4011 pcc->mmu_model = POWERPC_MMU_REAL;
4012 pcc->excp_model = POWERPC_EXCP_603;
4013 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4014 pcc->bfd_mach = bfd_mach_ppc_505;
4015 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4016 POWERPC_FLAG_BUS_CLK;
4017 }
4018
4019 static void init_proc_MPC8xx (CPUPPCState *env)
4020 {
4021 /* Time base */
4022 gen_tbl(env);
4023 gen_spr_5xx_8xx(env);
4024 gen_spr_8xx(env);
4025 init_excp_MPC8xx(env);
4026 env->dcache_line_size = 32;
4027 env->icache_line_size = 32;
4028 /* XXX: TODO: allocate internal IRQ controller */
4029 }
4030
4031 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4032 {
4033 DeviceClass *dc = DEVICE_CLASS(oc);
4034 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4035
4036 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4037 pcc->init_proc = init_proc_MPC8xx;
4038 pcc->check_pow = check_pow_none;
4039 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4040 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4041 PPC_CACHE_ICBI | PPC_MFTB;
4042 pcc->insns_flags2 = PPC_NONE;
4043 pcc->msr_mask = 0x000000000001F673ULL;
4044 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4045 pcc->excp_model = POWERPC_EXCP_603;
4046 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4047 pcc->bfd_mach = bfd_mach_ppc_860;
4048 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4049 POWERPC_FLAG_BUS_CLK;
4050 }
4051
4052 /* Freescale 82xx cores (aka PowerQUICC-II) */
4053
4054 static void init_proc_G2 (CPUPPCState *env)
4055 {
4056 gen_spr_ne_601(env);
4057 gen_spr_G2_755(env);
4058 gen_spr_G2(env);
4059 /* Time base */
4060 gen_tbl(env);
4061 /* External access control */
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_EAR, "EAR",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* Hardware implementation register */
4068 /* XXX : not implemented */
4069 spr_register(env, SPR_HID0, "HID0",
4070 SPR_NOACCESS, SPR_NOACCESS,
4071 &spr_read_generic, &spr_write_generic,
4072 0x00000000);
4073 /* XXX : not implemented */
4074 spr_register(env, SPR_HID1, "HID1",
4075 SPR_NOACCESS, SPR_NOACCESS,
4076 &spr_read_generic, &spr_write_generic,
4077 0x00000000);
4078 /* XXX : not implemented */
4079 spr_register(env, SPR_HID2, "HID2",
4080 SPR_NOACCESS, SPR_NOACCESS,
4081 &spr_read_generic, &spr_write_generic,
4082 0x00000000);
4083 /* Memory management */
4084 gen_low_BATs(env);
4085 gen_high_BATs(env);
4086 gen_6xx_7xx_soft_tlb(env, 64, 2);
4087 init_excp_G2(env);
4088 env->dcache_line_size = 32;
4089 env->icache_line_size = 32;
4090 /* Allocate hardware IRQ controller */
4091 ppc6xx_irq_init(env);
4092 }
4093
4094 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4095 {
4096 DeviceClass *dc = DEVICE_CLASS(oc);
4097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4098
4099 dc->desc = "PowerPC G2";
4100 pcc->init_proc = init_proc_G2;
4101 pcc->check_pow = check_pow_hid0;
4102 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4103 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4104 PPC_FLOAT_STFIWX |
4105 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4106 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4107 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4108 PPC_SEGMENT | PPC_EXTERN;
4109 pcc->insns_flags2 = PPC_NONE;
4110 pcc->msr_mask = 0x000000000006FFF2ULL;
4111 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4112 pcc->excp_model = POWERPC_EXCP_G2;
4113 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4114 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4115 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4116 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4117 }
4118
4119 static void init_proc_G2LE (CPUPPCState *env)
4120 {
4121 gen_spr_ne_601(env);
4122 gen_spr_G2_755(env);
4123 gen_spr_G2(env);
4124 /* Time base */
4125 gen_tbl(env);
4126 /* External access control */
4127 /* XXX : not implemented */
4128 spr_register(env, SPR_EAR, "EAR",
4129 SPR_NOACCESS, SPR_NOACCESS,
4130 &spr_read_generic, &spr_write_generic,
4131 0x00000000);
4132 /* Hardware implementation register */
4133 /* XXX : not implemented */
4134 spr_register(env, SPR_HID0, "HID0",
4135 SPR_NOACCESS, SPR_NOACCESS,
4136 &spr_read_generic, &spr_write_generic,
4137 0x00000000);
4138 /* XXX : not implemented */
4139 spr_register(env, SPR_HID1, "HID1",
4140 SPR_NOACCESS, SPR_NOACCESS,
4141 &spr_read_generic, &spr_write_generic,
4142 0x00000000);
4143 /* XXX : not implemented */
4144 spr_register(env, SPR_HID2, "HID2",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148 /* Breakpoints */
4149 /* XXX : not implemented */
4150 spr_register(env, SPR_DABR, "DABR",
4151 SPR_NOACCESS, SPR_NOACCESS,
4152 &spr_read_generic, &spr_write_generic,
4153 0x00000000);
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_DABR2, "DABR2",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_IABR2, "IABR2",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 /* XXX : not implemented */
4165 spr_register(env, SPR_IBCR, "IBCR",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* XXX : not implemented */
4170 spr_register(env, SPR_DBCR, "DBCR",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_generic,
4173 0x00000000);
4174
4175 /* Memory management */
4176 gen_low_BATs(env);
4177 gen_high_BATs(env);
4178 gen_6xx_7xx_soft_tlb(env, 64, 2);
4179 init_excp_G2(env);
4180 env->dcache_line_size = 32;
4181 env->icache_line_size = 32;
4182 /* Allocate hardware IRQ controller */
4183 ppc6xx_irq_init(env);
4184 }
4185
4186 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4187 {
4188 DeviceClass *dc = DEVICE_CLASS(oc);
4189 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4190
4191 dc->desc = "PowerPC G2LE";
4192 pcc->init_proc = init_proc_G2LE;
4193 pcc->check_pow = check_pow_hid0;
4194 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4195 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4196 PPC_FLOAT_STFIWX |
4197 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4198 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4199 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4200 PPC_SEGMENT | PPC_EXTERN;
4201 pcc->insns_flags2 = PPC_NONE;
4202 pcc->msr_mask = 0x000000000007FFF3ULL;
4203 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4204 pcc->excp_model = POWERPC_EXCP_G2;
4205 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4206 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4207 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4208 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4209 }
4210
4211 static void init_proc_e200 (CPUPPCState *env)
4212 {
4213 /* Time base */
4214 gen_tbl(env);
4215 gen_spr_BookE(env, 0x000000070000FFFFULL);
4216 /* XXX : not implemented */
4217 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4218 &spr_read_spefscr, &spr_write_spefscr,
4219 &spr_read_spefscr, &spr_write_spefscr,
4220 0x00000000);
4221 /* Memory management */
4222 gen_spr_BookE206(env, 0x0000005D, NULL);
4223 /* XXX : not implemented */
4224 spr_register(env, SPR_HID0, "HID0",
4225 SPR_NOACCESS, SPR_NOACCESS,
4226 &spr_read_generic, &spr_write_generic,
4227 0x00000000);
4228 /* XXX : not implemented */
4229 spr_register(env, SPR_HID1, "HID1",
4230 SPR_NOACCESS, SPR_NOACCESS,
4231 &spr_read_generic, &spr_write_generic,
4232 0x00000000);
4233 /* XXX : not implemented */
4234 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0x00000000);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4240 SPR_NOACCESS, SPR_NOACCESS,
4241 &spr_read_generic, &spr_write_generic,
4242 0x00000000);
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
4248 /* XXX : not implemented */
4249 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4250 SPR_NOACCESS, SPR_NOACCESS,
4251 &spr_read_generic, &spr_write_generic,
4252 0x00000000);
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 /* XXX : not implemented */
4259 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, &spr_write_generic,
4262 0x00000000);
4263 /* XXX : not implemented */
4264 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4265 SPR_NOACCESS, SPR_NOACCESS,
4266 &spr_read_generic, &spr_write_generic,
4267 0x00000000);
4268 /* XXX : not implemented */
4269 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4270 SPR_NOACCESS, SPR_NOACCESS,
4271 &spr_read_generic, &spr_write_generic,
4272 0x00000000);
4273 /* XXX : not implemented */
4274 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* XXX : not implemented */
4279 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* XXX : not implemented */
4284 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* XXX : not implemented */
4289 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4290 SPR_NOACCESS, SPR_NOACCESS,
4291 &spr_read_generic, &spr_write_generic,
4292 0x00000000);
4293 /* XXX : not implemented */
4294 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4295 SPR_NOACCESS, SPR_NOACCESS,
4296 &spr_read_generic, &spr_write_generic,
4297 0x00000000); /* TOFIX */
4298 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4303 SPR_NOACCESS, SPR_NOACCESS,
4304 &spr_read_generic, &spr_write_generic,
4305 0x00000000);
4306 #if !defined(CONFIG_USER_ONLY)
4307 env->nb_tlb = 64;
4308 env->nb_ways = 1;
4309 env->id_tlbs = 0;
4310 env->tlb_type = TLB_EMB;
4311 #endif
4312 init_excp_e200(env, 0xFFFF0000UL);
4313 env->dcache_line_size = 32;
4314 env->icache_line_size = 32;
4315 /* XXX: TODO: allocate internal IRQ controller */
4316 }
4317
4318 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4319 {
4320 DeviceClass *dc = DEVICE_CLASS(oc);
4321 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4322
4323 dc->desc = "e200 core";
4324 pcc->init_proc = init_proc_e200;
4325 pcc->check_pow = check_pow_hid0;
4326 /* XXX: unimplemented instructions:
4327 * dcblc
4328 * dcbtlst
4329 * dcbtstls
4330 * icblc
4331 * icbtls
4332 * tlbivax
4333 * all SPE multiply-accumulate instructions
4334 */
4335 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4336 PPC_SPE | PPC_SPE_SINGLE |
4337 PPC_WRTEE | PPC_RFDI |
4338 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4339 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4340 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4341 PPC_BOOKE;
4342 pcc->insns_flags2 = PPC_NONE;
4343 pcc->msr_mask = 0x000000000606FF30ULL;
4344 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4345 pcc->excp_model = POWERPC_EXCP_BOOKE;
4346 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4347 pcc->bfd_mach = bfd_mach_ppc_860;
4348 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4349 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4350 POWERPC_FLAG_BUS_CLK;
4351 }
4352
4353 static void init_proc_e300 (CPUPPCState *env)
4354 {
4355 gen_spr_ne_601(env);
4356 gen_spr_603(env);
4357 /* Time base */
4358 gen_tbl(env);
4359 /* hardware implementation registers */
4360 /* XXX : not implemented */
4361 spr_register(env, SPR_HID0, "HID0",
4362 SPR_NOACCESS, SPR_NOACCESS,
4363 &spr_read_generic, &spr_write_generic,
4364 0x00000000);
4365 /* XXX : not implemented */
4366 spr_register(env, SPR_HID1, "HID1",
4367 SPR_NOACCESS, SPR_NOACCESS,
4368 &spr_read_generic, &spr_write_generic,
4369 0x00000000);
4370 /* XXX : not implemented */
4371 spr_register(env, SPR_HID2, "HID2",
4372 SPR_NOACCESS, SPR_NOACCESS,
4373 &spr_read_generic, &spr_write_generic,
4374 0x00000000);
4375 /* Memory management */
4376 gen_low_BATs(env);
4377 gen_high_BATs(env);
4378 gen_6xx_7xx_soft_tlb(env, 64, 2);
4379 init_excp_603(env);
4380 env->dcache_line_size = 32;
4381 env->icache_line_size = 32;
4382 /* Allocate hardware IRQ controller */
4383 ppc6xx_irq_init(env);
4384 }
4385
4386 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4387 {
4388 DeviceClass *dc = DEVICE_CLASS(oc);
4389 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4390
4391 dc->desc = "e300 core";
4392 pcc->init_proc = init_proc_e300;
4393 pcc->check_pow = check_pow_hid0;
4394 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4395 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4396 PPC_FLOAT_STFIWX |
4397 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4398 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4399 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4400 PPC_SEGMENT | PPC_EXTERN;
4401 pcc->insns_flags2 = PPC_NONE;
4402 pcc->msr_mask = 0x000000000007FFF3ULL;
4403 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4404 pcc->excp_model = POWERPC_EXCP_603;
4405 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4406 pcc->bfd_mach = bfd_mach_ppc_603;
4407 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4408 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4409 }
4410
4411 #if !defined(CONFIG_USER_ONLY)
4412 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4413 {
4414 TCGv val = tcg_temp_new();
4415 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4416 gen_store_spr(SPR_BOOKE_MAS3, val);
4417 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4418 gen_store_spr(SPR_BOOKE_MAS7, val);
4419 tcg_temp_free(val);
4420 }
4421
4422 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4423 {
4424 TCGv mas7 = tcg_temp_new();
4425 TCGv mas3 = tcg_temp_new();
4426 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4427 tcg_gen_shli_tl(mas7, mas7, 32);
4428 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4429 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4430 tcg_temp_free(mas3);
4431 tcg_temp_free(mas7);
4432 }
4433
4434 #endif
4435
4436 enum fsl_e500_version {
4437 fsl_e500v1,
4438 fsl_e500v2,
4439 fsl_e500mc,
4440 fsl_e5500,
4441 };
4442
4443 static void init_proc_e500 (CPUPPCState *env, int version)
4444 {
4445 uint32_t tlbncfg[2];
4446 uint64_t ivor_mask;
4447 uint64_t ivpr_mask = 0xFFFF0000ULL;
4448 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4449 | 0x0020; /* 32 kb */
4450 #if !defined(CONFIG_USER_ONLY)
4451 int i;
4452 #endif
4453
4454 /* Time base */
4455 gen_tbl(env);
4456 /*
4457 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4458 * complain when accessing them.
4459 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4460 */
4461 switch (version) {
4462 case fsl_e500v1:
4463 case fsl_e500v2:
4464 default:
4465 ivor_mask = 0x0000000F0000FFFFULL;
4466 break;
4467 case fsl_e500mc:
4468 case fsl_e5500:
4469 ivor_mask = 0x000003FE0000FFFFULL;
4470 break;
4471 }
4472 gen_spr_BookE(env, ivor_mask);
4473 /* Processor identification */
4474 spr_register(env, SPR_BOOKE_PIR, "PIR",
4475 SPR_NOACCESS, SPR_NOACCESS,
4476 &spr_read_generic, &spr_write_pir,
4477 0x00000000);
4478 /* XXX : not implemented */
4479 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4480 &spr_read_spefscr, &spr_write_spefscr,
4481 &spr_read_spefscr, &spr_write_spefscr,
4482 0x00000000);
4483 #if !defined(CONFIG_USER_ONLY)
4484 /* Memory management */
4485 env->nb_pids = 3;
4486 env->nb_ways = 2;
4487 env->id_tlbs = 0;
4488 switch (version) {
4489 case fsl_e500v1:
4490 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4491 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4492 break;
4493 case fsl_e500v2:
4494 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4495 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4496 break;
4497 case fsl_e500mc:
4498 case fsl_e5500:
4499 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4500 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4501 break;
4502 default:
4503 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4504 }
4505 #endif
4506 /* Cache sizes */
4507 switch (version) {
4508 case fsl_e500v1:
4509 case fsl_e500v2:
4510 env->dcache_line_size = 32;
4511 env->icache_line_size = 32;
4512 break;
4513 case fsl_e500mc:
4514 case fsl_e5500:
4515 env->dcache_line_size = 64;
4516 env->icache_line_size = 64;
4517 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4518 break;
4519 default:
4520 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4521 }
4522 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4523 /* XXX : not implemented */
4524 spr_register(env, SPR_HID0, "HID0",
4525 SPR_NOACCESS, SPR_NOACCESS,
4526 &spr_read_generic, &spr_write_generic,
4527 0x00000000);
4528 /* XXX : not implemented */
4529 spr_register(env, SPR_HID1, "HID1",
4530 SPR_NOACCESS, SPR_NOACCESS,
4531 &spr_read_generic, &spr_write_generic,
4532 0x00000000);
4533 /* XXX : not implemented */
4534 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4535 SPR_NOACCESS, SPR_NOACCESS,
4536 &spr_read_generic, &spr_write_generic,
4537 0x00000000);
4538 /* XXX : not implemented */
4539 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4540 SPR_NOACCESS, SPR_NOACCESS,
4541 &spr_read_generic, &spr_write_generic,
4542 0x00000000);
4543 /* XXX : not implemented */
4544 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
4548 /* XXX : not implemented */
4549 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
4553 /* XXX : not implemented */
4554 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4555 SPR_NOACCESS, SPR_NOACCESS,
4556 &spr_read_generic, &spr_write_generic,
4557 0x00000000);
4558 /* XXX : not implemented */
4559 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4560 SPR_NOACCESS, SPR_NOACCESS,
4561 &spr_read_generic, &spr_write_generic,
4562 0x00000000);
4563 /* XXX : not implemented */
4564 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4565 SPR_NOACCESS, SPR_NOACCESS,
4566 &spr_read_generic, &spr_write_generic,
4567 l1cfg0);
4568 /* XXX : not implemented */
4569 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4570 SPR_NOACCESS, SPR_NOACCESS,
4571 &spr_read_generic, &spr_write_e500_l1csr0,
4572 0x00000000);
4573 /* XXX : not implemented */
4574 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4575 SPR_NOACCESS, SPR_NOACCESS,
4576 &spr_read_generic, &spr_write_generic,
4577 0x00000000);
4578 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4579 SPR_NOACCESS, SPR_NOACCESS,
4580 &spr_read_generic, &spr_write_generic,
4581 0x00000000);
4582 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4583 SPR_NOACCESS, SPR_NOACCESS,
4584 &spr_read_generic, &spr_write_generic,
4585 0x00000000);
4586 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4587 SPR_NOACCESS, SPR_NOACCESS,
4588 &spr_read_generic, &spr_write_booke206_mmucsr0,
4589 0x00000000);
4590 spr_register(env, SPR_BOOKE_EPR, "EPR",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, SPR_NOACCESS,
4593 0x00000000);
4594 /* XXX better abstract into Emb.xxx features */
4595 if (version == fsl_e5500) {
4596 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4601 SPR_NOACCESS, SPR_NOACCESS,
4602 &spr_read_mas73, &spr_write_mas73,
4603 0x00000000);
4604 ivpr_mask = (target_ulong)~0xFFFFULL;
4605 }
4606
4607 #if !defined(CONFIG_USER_ONLY)
4608 env->nb_tlb = 0;
4609 env->tlb_type = TLB_MAS;
4610 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4611 env->nb_tlb += booke206_tlb_size(env, i);
4612 }
4613 #endif
4614
4615 init_excp_e200(env, ivpr_mask);
4616 /* Allocate hardware IRQ controller */
4617 ppce500_irq_init(env);
4618 }
4619
4620 static void init_proc_e500v1(CPUPPCState *env)
4621 {
4622 init_proc_e500(env, fsl_e500v1);
4623 }
4624
4625 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4626 {
4627 DeviceClass *dc = DEVICE_CLASS(oc);
4628 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4629
4630 dc->desc = "e500v1 core";
4631 pcc->init_proc = init_proc_e500v1;
4632 pcc->check_pow = check_pow_hid0;
4633 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4634 PPC_SPE | PPC_SPE_SINGLE |
4635 PPC_WRTEE | PPC_RFDI |
4636 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4637 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4638 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4639 pcc->insns_flags2 = PPC2_BOOKE206;
4640 pcc->msr_mask = 0x000000000606FF30ULL;
4641 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4642 pcc->excp_model = POWERPC_EXCP_BOOKE;
4643 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4644 pcc->bfd_mach = bfd_mach_ppc_860;
4645 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4646 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4647 POWERPC_FLAG_BUS_CLK;
4648 }
4649
4650 static void init_proc_e500v2(CPUPPCState *env)
4651 {
4652 init_proc_e500(env, fsl_e500v2);
4653 }
4654
4655 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4656 {
4657 DeviceClass *dc = DEVICE_CLASS(oc);
4658 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4659
4660 dc->desc = "e500v2 core";
4661 pcc->init_proc = init_proc_e500v2;
4662 pcc->check_pow = check_pow_hid0;
4663 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4664 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4665 PPC_WRTEE | PPC_RFDI |
4666 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4667 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4668 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4669 pcc->insns_flags2 = PPC2_BOOKE206;
4670 pcc->msr_mask = 0x000000000606FF30ULL;
4671 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4672 pcc->excp_model = POWERPC_EXCP_BOOKE;
4673 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4674 pcc->bfd_mach = bfd_mach_ppc_860;
4675 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4676 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4677 POWERPC_FLAG_BUS_CLK;
4678 }
4679
4680 static void init_proc_e500mc(CPUPPCState *env)
4681 {
4682 init_proc_e500(env, fsl_e500mc);
4683 }
4684
4685 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4686 {
4687 DeviceClass *dc = DEVICE_CLASS(oc);
4688 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4689
4690 dc->desc = "e500mc core";
4691 pcc->init_proc = init_proc_e500mc;
4692 pcc->check_pow = check_pow_none;
4693 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4694 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4695 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4696 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4697 PPC_FLOAT | PPC_FLOAT_FRES |
4698 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4699 PPC_FLOAT_STFIWX | PPC_WAIT |
4700 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4701 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4702 pcc->msr_mask = 0x000000001402FB36ULL;
4703 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4704 pcc->excp_model = POWERPC_EXCP_BOOKE;
4705 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4706 /* FIXME: figure out the correct flag for e500mc */
4707 pcc->bfd_mach = bfd_mach_ppc_e500;
4708 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4709 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4710 }
4711
4712 #ifdef TARGET_PPC64
4713 static void init_proc_e5500(CPUPPCState *env)
4714 {
4715 init_proc_e500(env, fsl_e5500);
4716 }
4717
4718 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4719 {
4720 DeviceClass *dc = DEVICE_CLASS(oc);
4721 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4722
4723 dc->desc = "e5500 core";
4724 pcc->init_proc = init_proc_e5500;
4725 pcc->check_pow = check_pow_none;
4726 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4727 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4728 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4729 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4730 PPC_FLOAT | PPC_FLOAT_FRES |
4731 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4732 PPC_FLOAT_STFIWX | PPC_WAIT |
4733 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4734 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4735 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4736 pcc->msr_mask = 0x000000009402FB36ULL;
4737 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4738 pcc->excp_model = POWERPC_EXCP_BOOKE;
4739 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4740 /* FIXME: figure out the correct flag for e5500 */
4741 pcc->bfd_mach = bfd_mach_ppc_e500;
4742 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4743 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4744 }
4745 #endif
4746
4747 /* Non-embedded PowerPC */
4748
4749 /* POWER : same as 601, without mfmsr, mfsr */
4750 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4751 {
4752 DeviceClass *dc = DEVICE_CLASS(oc);
4753 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4754
4755 dc->desc = "POWER";
4756 /* pcc->insns_flags = XXX_TODO; */
4757 /* POWER RSC (from RAD6000) */
4758 pcc->msr_mask = 0x00000000FEF0ULL;
4759 }
4760
4761 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4762
4763 static void init_proc_601 (CPUPPCState *env)
4764 {
4765 gen_spr_ne_601(env);
4766 gen_spr_601(env);
4767 /* Hardware implementation registers */
4768 /* XXX : not implemented */
4769 spr_register(env, SPR_HID0, "HID0",
4770 SPR_NOACCESS, SPR_NOACCESS,
4771 &spr_read_generic, &spr_write_hid0_601,
4772 0x80010080);
4773 /* XXX : not implemented */
4774 spr_register(env, SPR_HID1, "HID1",
4775 SPR_NOACCESS, SPR_NOACCESS,
4776 &spr_read_generic, &spr_write_generic,
4777 0x00000000);
4778 /* XXX : not implemented */
4779 spr_register(env, SPR_601_HID2, "HID2",
4780 SPR_NOACCESS, SPR_NOACCESS,
4781 &spr_read_generic, &spr_write_generic,
4782 0x00000000);
4783 /* XXX : not implemented */
4784 spr_register(env, SPR_601_HID5, "HID5",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788 /* Memory management */
4789 init_excp_601(env);
4790 /* XXX: beware that dcache line size is 64
4791 * but dcbz uses 32 bytes "sectors"
4792 * XXX: this breaks clcs instruction !
4793 */
4794 env->dcache_line_size = 32;
4795 env->icache_line_size = 64;
4796 /* Allocate hardware IRQ controller */
4797 ppc6xx_irq_init(env);
4798 }
4799
4800 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4801 {
4802 DeviceClass *dc = DEVICE_CLASS(oc);
4803 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4804
4805 dc->desc = "PowerPC 601";
4806 pcc->init_proc = init_proc_601;
4807 pcc->check_pow = check_pow_none;
4808 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4809 PPC_FLOAT |
4810 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4811 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4812 PPC_SEGMENT | PPC_EXTERN;
4813 pcc->insns_flags2 = PPC_NONE;
4814 pcc->msr_mask = 0x000000000000FD70ULL;
4815 pcc->mmu_model = POWERPC_MMU_601;
4816 #if defined(CONFIG_SOFTMMU)
4817 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4818 #endif
4819 pcc->excp_model = POWERPC_EXCP_601;
4820 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4821 pcc->bfd_mach = bfd_mach_ppc_601;
4822 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4823 }
4824
4825 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4826
4827 static void init_proc_601v (CPUPPCState *env)
4828 {
4829 init_proc_601(env);
4830 /* XXX : not implemented */
4831 spr_register(env, SPR_601_HID15, "HID15",
4832 SPR_NOACCESS, SPR_NOACCESS,
4833 &spr_read_generic, &spr_write_generic,
4834 0x00000000);
4835 }
4836
4837 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4838 {
4839 DeviceClass *dc = DEVICE_CLASS(oc);
4840 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4841
4842 dc->desc = "PowerPC 601v";
4843 pcc->init_proc = init_proc_601v;
4844 pcc->check_pow = check_pow_none;
4845 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4846 PPC_FLOAT |
4847 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4848 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4849 PPC_SEGMENT | PPC_EXTERN;
4850 pcc->insns_flags2 = PPC_NONE;
4851 pcc->msr_mask = 0x000000000000FD70ULL;
4852 pcc->mmu_model = POWERPC_MMU_601;
4853 #if defined(CONFIG_SOFTMMU)
4854 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4855 #endif
4856 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4857 pcc->bfd_mach = bfd_mach_ppc_601;
4858 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4859 }
4860
4861 static void init_proc_602 (CPUPPCState *env)
4862 {
4863 gen_spr_ne_601(env);
4864 gen_spr_602(env);
4865 /* Time base */
4866 gen_tbl(env);
4867 /* hardware implementation registers */
4868 /* XXX : not implemented */
4869 spr_register(env, SPR_HID0, "HID0",
4870 SPR_NOACCESS, SPR_NOACCESS,
4871 &spr_read_generic, &spr_write_generic,
4872 0x00000000);
4873 /* XXX : not implemented */
4874 spr_register(env, SPR_HID1, "HID1",
4875 SPR_NOACCESS, SPR_NOACCESS,
4876 &spr_read_generic, &spr_write_generic,
4877 0x00000000);
4878 /* Memory management */
4879 gen_low_BATs(env);
4880 gen_6xx_7xx_soft_tlb(env, 64, 2);
4881 init_excp_602(env);
4882 env->dcache_line_size = 32;
4883 env->icache_line_size = 32;
4884 /* Allocate hardware IRQ controller */
4885 ppc6xx_irq_init(env);
4886 }
4887
4888 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4889 {
4890 DeviceClass *dc = DEVICE_CLASS(oc);
4891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4892
4893 dc->desc = "PowerPC 602";
4894 pcc->init_proc = init_proc_602;
4895 pcc->check_pow = check_pow_hid0;
4896 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4897 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4898 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4899 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4900 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4901 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4902 PPC_SEGMENT | PPC_602_SPEC;
4903 pcc->insns_flags2 = PPC_NONE;
4904 pcc->msr_mask = 0x0000000000C7FF73ULL;
4905 /* XXX: 602 MMU is quite specific. Should add a special case */
4906 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4907 pcc->excp_model = POWERPC_EXCP_602;
4908 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4909 pcc->bfd_mach = bfd_mach_ppc_602;
4910 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4911 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4912 }
4913
4914 static void init_proc_603 (CPUPPCState *env)
4915 {
4916 gen_spr_ne_601(env);
4917 gen_spr_603(env);
4918 /* Time base */
4919 gen_tbl(env);
4920 /* hardware implementation registers */
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_HID0, "HID0",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926 /* XXX : not implemented */
4927 spr_register(env, SPR_HID1, "HID1",
4928 SPR_NOACCESS, SPR_NOACCESS,
4929 &spr_read_generic, &spr_write_generic,
4930 0x00000000);
4931 /* Memory management */
4932 gen_low_BATs(env);
4933 gen_6xx_7xx_soft_tlb(env, 64, 2);
4934 init_excp_603(env);
4935 env->dcache_line_size = 32;
4936 env->icache_line_size = 32;
4937 /* Allocate hardware IRQ controller */
4938 ppc6xx_irq_init(env);
4939 }
4940
4941 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4942 {
4943 DeviceClass *dc = DEVICE_CLASS(oc);
4944 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4945
4946 dc->desc = "PowerPC 603";
4947 pcc->init_proc = init_proc_603;
4948 pcc->check_pow = check_pow_hid0;
4949 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4950 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4951 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4952 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4953 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4954 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4955 PPC_SEGMENT | PPC_EXTERN;
4956 pcc->insns_flags2 = PPC_NONE;
4957 pcc->msr_mask = 0x000000000007FF73ULL;
4958 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4959 pcc->excp_model = POWERPC_EXCP_603;
4960 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4961 pcc->bfd_mach = bfd_mach_ppc_603;
4962 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4963 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4964 }
4965
4966 static void init_proc_603E (CPUPPCState *env)
4967 {
4968 gen_spr_ne_601(env);
4969 gen_spr_603(env);
4970 /* Time base */
4971 gen_tbl(env);
4972 /* hardware implementation registers */
4973 /* XXX : not implemented */
4974 spr_register(env, SPR_HID0, "HID0",
4975 SPR_NOACCESS, SPR_NOACCESS,
4976 &spr_read_generic, &spr_write_generic,
4977 0x00000000);
4978 /* XXX : not implemented */
4979 spr_register(env, SPR_HID1, "HID1",
4980 SPR_NOACCESS, SPR_NOACCESS,
4981 &spr_read_generic, &spr_write_generic,
4982 0x00000000);
4983 /* XXX : not implemented */
4984 spr_register(env, SPR_IABR, "IABR",
4985 SPR_NOACCESS, SPR_NOACCESS,
4986 &spr_read_generic, &spr_write_generic,
4987 0x00000000);
4988 /* Memory management */
4989 gen_low_BATs(env);
4990 gen_6xx_7xx_soft_tlb(env, 64, 2);
4991 init_excp_603(env);
4992 env->dcache_line_size = 32;
4993 env->icache_line_size = 32;
4994 /* Allocate hardware IRQ controller */
4995 ppc6xx_irq_init(env);
4996 }
4997
4998 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4999 {
5000 DeviceClass *dc = DEVICE_CLASS(oc);
5001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5002
5003 dc->desc = "PowerPC 603e";
5004 pcc->init_proc = init_proc_603E;
5005 pcc->check_pow = check_pow_hid0;
5006 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5007 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5008 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5009 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5010 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5011 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5012 PPC_SEGMENT | PPC_EXTERN;
5013 pcc->insns_flags2 = PPC_NONE;
5014 pcc->msr_mask = 0x000000000007FF73ULL;
5015 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5016 pcc->excp_model = POWERPC_EXCP_603E;
5017 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5018 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5019 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5020 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5021 }
5022
5023 static void init_proc_604 (CPUPPCState *env)
5024 {
5025 gen_spr_ne_601(env);
5026 gen_spr_604(env);
5027 /* Time base */
5028 gen_tbl(env);
5029 /* Hardware implementation registers */
5030 /* XXX : not implemented */
5031 spr_register(env, SPR_HID0, "HID0",
5032 SPR_NOACCESS, SPR_NOACCESS,
5033 &spr_read_generic, &spr_write_generic,
5034 0x00000000);
5035 /* Memory management */
5036 gen_low_BATs(env);
5037 init_excp_604(env);
5038 env->dcache_line_size = 32;
5039 env->icache_line_size = 32;
5040 /* Allocate hardware IRQ controller */
5041 ppc6xx_irq_init(env);
5042 }
5043
5044 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5045 {
5046 DeviceClass *dc = DEVICE_CLASS(oc);
5047 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5048
5049 dc->desc = "PowerPC 604";
5050 pcc->init_proc = init_proc_604;
5051 pcc->check_pow = check_pow_nocheck;
5052 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5053 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5054 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5055 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5056 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5057 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5058 PPC_SEGMENT | PPC_EXTERN;
5059 pcc->insns_flags2 = PPC_NONE;
5060 pcc->msr_mask = 0x000000000005FF77ULL;
5061 pcc->mmu_model = POWERPC_MMU_32B;
5062 #if defined(CONFIG_SOFTMMU)
5063 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5064 #endif
5065 pcc->excp_model = POWERPC_EXCP_604;
5066 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5067 pcc->bfd_mach = bfd_mach_ppc_604;
5068 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5069 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5070 }
5071
5072 static void init_proc_604E (CPUPPCState *env)
5073 {
5074 gen_spr_ne_601(env);
5075 gen_spr_604(env);
5076 /* XXX : not implemented */
5077 spr_register(env, SPR_MMCR1, "MMCR1",
5078 SPR_NOACCESS, SPR_NOACCESS,
5079 &spr_read_generic, &spr_write_generic,
5080 0x00000000);
5081 /* XXX : not implemented */
5082 spr_register(env, SPR_PMC3, "PMC3",
5083 SPR_NOACCESS, SPR_NOACCESS,
5084 &spr_read_generic, &spr_write_generic,
5085 0x00000000);
5086 /* XXX : not implemented */
5087 spr_register(env, SPR_PMC4, "PMC4",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_generic,
5090 0x00000000);
5091 /* Time base */
5092 gen_tbl(env);
5093 /* Hardware implementation registers */
5094 /* XXX : not implemented */
5095 spr_register(env, SPR_HID0, "HID0",
5096 SPR_NOACCESS, SPR_NOACCESS,
5097 &spr_read_generic, &spr_write_generic,
5098 0x00000000);
5099 /* XXX : not implemented */
5100 spr_register(env, SPR_HID1, "HID1",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 0x00000000);
5104 /* Memory management */
5105 gen_low_BATs(env);
5106 init_excp_604(env);
5107 env->dcache_line_size = 32;
5108 env->icache_line_size = 32;
5109 /* Allocate hardware IRQ controller */
5110 ppc6xx_irq_init(env);
5111 }
5112
5113 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5114 {
5115 DeviceClass *dc = DEVICE_CLASS(oc);
5116 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5117
5118 dc->desc = "PowerPC 604E";
5119 pcc->init_proc = init_proc_604E;
5120 pcc->check_pow = check_pow_nocheck;
5121 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5122 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5123 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5124 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5125 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5126 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5127 PPC_SEGMENT | PPC_EXTERN;
5128 pcc->insns_flags2 = PPC_NONE;
5129 pcc->msr_mask = 0x000000000005FF77ULL;
5130 pcc->mmu_model = POWERPC_MMU_32B;
5131 #if defined(CONFIG_SOFTMMU)
5132 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5133 #endif
5134 pcc->excp_model = POWERPC_EXCP_604;
5135 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5136 pcc->bfd_mach = bfd_mach_ppc_604;
5137 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5138 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5139 }
5140
5141 static void init_proc_740 (CPUPPCState *env)
5142 {
5143 gen_spr_ne_601(env);
5144 gen_spr_7xx(env);
5145 /* Time base */
5146 gen_tbl(env);
5147 /* Thermal management */
5148 gen_spr_thrm(env);
5149 /* Hardware implementation registers */
5150 /* XXX : not implemented */
5151 spr_register(env, SPR_HID0, "HID0",
5152 SPR_NOACCESS, SPR_NOACCESS,
5153 &spr_read_generic, &spr_write_generic,
5154 0x00000000);
5155 /* XXX : not implemented */
5156 spr_register(env, SPR_HID1, "HID1",
5157 SPR_NOACCESS, SPR_NOACCESS,
5158 &spr_read_generic, &spr_write_generic,
5159 0x00000000);
5160 /* Memory management */
5161 gen_low_BATs(env);
5162 init_excp_7x0(env);
5163 env->dcache_line_size = 32;
5164 env->icache_line_size = 32;
5165 /* Allocate hardware IRQ controller */
5166 ppc6xx_irq_init(env);
5167 }
5168
5169 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5170 {
5171 DeviceClass *dc = DEVICE_CLASS(oc);
5172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5173
5174 dc->desc = "PowerPC 740";
5175 pcc->init_proc = init_proc_740;
5176 pcc->check_pow = check_pow_hid0;
5177 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5178 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5179 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5180 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5181 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5182 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5183 PPC_SEGMENT | PPC_EXTERN;
5184 pcc->insns_flags2 = PPC_NONE;
5185 pcc->msr_mask = 0x000000000005FF77ULL;
5186 pcc->mmu_model = POWERPC_MMU_32B;
5187 #if defined(CONFIG_SOFTMMU)
5188 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5189 #endif
5190 pcc->excp_model = POWERPC_EXCP_7x0;
5191 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5192 pcc->bfd_mach = bfd_mach_ppc_750;
5193 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5194 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5195 }
5196
5197 static void init_proc_750 (CPUPPCState *env)
5198 {
5199 gen_spr_ne_601(env);
5200 gen_spr_7xx(env);
5201 /* XXX : not implemented */
5202 spr_register(env, SPR_L2CR, "L2CR",
5203 SPR_NOACCESS, SPR_NOACCESS,
5204 &spr_read_generic, &spr_write_generic,
5205 0x00000000);
5206 /* Time base */
5207 gen_tbl(env);
5208 /* Thermal management */
5209 gen_spr_thrm(env);
5210 /* Hardware implementation registers */
5211 /* XXX : not implemented */
5212 spr_register(env, SPR_HID0, "HID0",
5213 SPR_NOACCESS, SPR_NOACCESS,
5214 &spr_read_generic, &spr_write_generic,
5215 0x00000000);
5216 /* XXX : not implemented */
5217 spr_register(env, SPR_HID1, "HID1",
5218 SPR_NOACCESS, SPR_NOACCESS,
5219 &spr_read_generic, &spr_write_generic,
5220 0x00000000);
5221 /* Memory management */
5222 gen_low_BATs(env);
5223 /* XXX: high BATs are also present but are known to be bugged on
5224 * die version 1.x
5225 */
5226 init_excp_7x0(env);
5227 env->dcache_line_size = 32;
5228 env->icache_line_size = 32;
5229 /* Allocate hardware IRQ controller */
5230 ppc6xx_irq_init(env);
5231 }
5232
5233 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5234 {
5235 DeviceClass *dc = DEVICE_CLASS(oc);
5236 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5237
5238 dc->desc = "PowerPC 750";
5239 pcc->init_proc = init_proc_750;
5240 pcc->check_pow = check_pow_hid0;
5241 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5242 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5243 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5244 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5245 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5246 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5247 PPC_SEGMENT | PPC_EXTERN;
5248 pcc->insns_flags2 = PPC_NONE;
5249 pcc->msr_mask = 0x000000000005FF77ULL;
5250 pcc->mmu_model = POWERPC_MMU_32B;
5251 #if defined(CONFIG_SOFTMMU)
5252 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5253 #endif
5254 pcc->excp_model = POWERPC_EXCP_7x0;
5255 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5256 pcc->bfd_mach = bfd_mach_ppc_750;
5257 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5258 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5259 }
5260
5261 static void init_proc_750cl (CPUPPCState *env)
5262 {
5263 gen_spr_ne_601(env);
5264 gen_spr_7xx(env);
5265 /* XXX : not implemented */
5266 spr_register(env, SPR_L2CR, "L2CR",
5267 SPR_NOACCESS, SPR_NOACCESS,
5268 &spr_read_generic, &spr_write_generic,
5269 0x00000000);
5270 /* Time base */
5271 gen_tbl(env);
5272 /* Thermal management */
5273 /* Those registers are fake on 750CL */
5274 spr_register(env, SPR_THRM1, "THRM1",
5275 SPR_NOACCESS, SPR_NOACCESS,
5276 &spr_read_generic, &spr_write_generic,
5277 0x00000000);
5278 spr_register(env, SPR_THRM2, "THRM2",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 spr_register(env, SPR_THRM3, "THRM3",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 /* XXX: not implemented */
5287 spr_register(env, SPR_750_TDCL, "TDCL",
5288 SPR_NOACCESS, SPR_NOACCESS,
5289 &spr_read_generic, &spr_write_generic,
5290 0x00000000);
5291 spr_register(env, SPR_750_TDCH, "TDCH",
5292 SPR_NOACCESS, SPR_NOACCESS,
5293 &spr_read_generic, &spr_write_generic,
5294 0x00000000);
5295 /* DMA */
5296 /* XXX : not implemented */
5297 spr_register(env, SPR_750_WPAR, "WPAR",
5298 SPR_NOACCESS, SPR_NOACCESS,
5299 &spr_read_generic, &spr_write_generic,
5300 0x00000000);
5301 spr_register(env, SPR_750_DMAL, "DMAL",
5302 SPR_NOACCESS, SPR_NOACCESS,
5303 &spr_read_generic, &spr_write_generic,
5304 0x00000000);
5305 spr_register(env, SPR_750_DMAU, "DMAU",
5306 SPR_NOACCESS, SPR_NOACCESS,
5307 &spr_read_generic, &spr_write_generic,
5308 0x00000000);
5309 /* Hardware implementation registers */
5310 /* XXX : not implemented */
5311 spr_register(env, SPR_HID0, "HID0",
5312 SPR_NOACCESS, SPR_NOACCESS,
5313 &spr_read_generic, &spr_write_generic,
5314 0x00000000);
5315 /* XXX : not implemented */
5316 spr_register(env, SPR_HID1, "HID1",
5317 SPR_NOACCESS, SPR_NOACCESS,
5318 &spr_read_generic, &spr_write_generic,
5319 0x00000000);
5320 /* XXX : not implemented */
5321 spr_register(env, SPR_750CL_HID2, "HID2",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
5324 0x00000000);
5325 /* XXX : not implemented */
5326 spr_register(env, SPR_750CL_HID4, "HID4",
5327 SPR_NOACCESS, SPR_NOACCESS,
5328 &spr_read_generic, &spr_write_generic,
5329 0x00000000);
5330 /* Quantization registers */
5331 /* XXX : not implemented */
5332 spr_register(env, SPR_750_GQR0, "GQR0",
5333 SPR_NOACCESS, SPR_NOACCESS,
5334 &spr_read_generic, &spr_write_generic,
5335 0x00000000);
5336 /* XXX : not implemented */
5337 spr_register(env, SPR_750_GQR1, "GQR1",
5338 SPR_NOACCESS, SPR_NOACCESS,
5339 &spr_read_generic, &spr_write_generic,
5340 0x00000000);
5341 /* XXX : not implemented */
5342 spr_register(env, SPR_750_GQR2, "GQR2",
5343 SPR_NOACCESS, SPR_NOACCESS,
5344 &spr_read_generic, &spr_write_generic,
5345 0x00000000);
5346 /* XXX : not implemented */
5347 spr_register(env, SPR_750_GQR3, "GQR3",
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_generic,
5350 0x00000000);
5351 /* XXX : not implemented */
5352 spr_register(env, SPR_750_GQR4, "GQR4",
5353 SPR_NOACCESS, SPR_NOACCESS,
5354 &spr_read_generic, &spr_write_generic,
5355 0x00000000);
5356 /* XXX : not implemented */
5357 spr_register(env, SPR_750_GQR5, "GQR5",
5358 SPR_NOACCESS, SPR_NOACCESS,
5359 &spr_read_generic, &spr_write_generic,
5360 0x00000000);
5361 /* XXX : not implemented */
5362 spr_register(env, SPR_750_GQR6, "GQR6",
5363 SPR_NOACCESS, SPR_NOACCESS,
5364 &spr_read_generic, &spr_write_generic,
5365 0x00000000);
5366 /* XXX : not implemented */
5367 spr_register(env, SPR_750_GQR7, "GQR7",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, &spr_write_generic,
5370 0x00000000);
5371 /* Memory management */
5372 gen_low_BATs(env);
5373 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5374 gen_high_BATs(env);
5375 init_excp_750cl(env);
5376 env->dcache_line_size = 32;
5377 env->icache_line_size = 32;
5378 /* Allocate hardware IRQ controller */
5379 ppc6xx_irq_init(env);
5380 }
5381
5382 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5383 {
5384 DeviceClass *dc = DEVICE_CLASS(oc);
5385 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5386
5387 dc->desc = "PowerPC 750 CL";
5388 pcc->init_proc = init_proc_750cl;
5389 pcc->check_pow = check_pow_hid0;
5390 /* XXX: not implemented:
5391 * cache lock instructions:
5392 * dcbz_l
5393 * floating point paired instructions
5394 * psq_lux
5395 * psq_lx
5396 * psq_stux
5397 * psq_stx
5398 * ps_abs
5399 * ps_add
5400 * ps_cmpo0
5401 * ps_cmpo1
5402 * ps_cmpu0
5403 * ps_cmpu1
5404 * ps_div
5405 * ps_madd
5406 * ps_madds0
5407 * ps_madds1
5408 * ps_merge00
5409 * ps_merge01
5410 * ps_merge10
5411 * ps_merge11
5412 * ps_mr
5413 * ps_msub
5414 * ps_mul
5415 * ps_muls0
5416 * ps_muls1
5417 * ps_nabs
5418 * ps_neg
5419 * ps_nmadd
5420 * ps_nmsub
5421 * ps_res
5422 * ps_rsqrte
5423 * ps_sel
5424 * ps_sub
5425 * ps_sum0
5426 * ps_sum1
5427 */
5428 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5429 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5430 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5431 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5432 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5433 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5434 PPC_SEGMENT | PPC_EXTERN;
5435 pcc->insns_flags2 = PPC_NONE;
5436 pcc->msr_mask = 0x000000000005FF77ULL;
5437 pcc->mmu_model = POWERPC_MMU_32B;
5438 #if defined(CONFIG_SOFTMMU)
5439 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5440 #endif
5441 pcc->excp_model = POWERPC_EXCP_7x0;
5442 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5443 pcc->bfd_mach = bfd_mach_ppc_750;
5444 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5445 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5446 }
5447
5448 static void init_proc_750cx (CPUPPCState *env)
5449 {
5450 gen_spr_ne_601(env);
5451 gen_spr_7xx(env);
5452 /* XXX : not implemented */
5453 spr_register(env, SPR_L2CR, "L2CR",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 /* Time base */
5458 gen_tbl(env);
5459 /* Thermal management */
5460 gen_spr_thrm(env);
5461 /* This register is not implemented but is present for compatibility */
5462 spr_register(env, SPR_SDA, "SDA",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
5466 /* Hardware implementation registers */
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_HID0, "HID0",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_HID1, "HID1",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* Memory management */
5478 gen_low_BATs(env);
5479 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5480 gen_high_BATs(env);
5481 init_excp_750cx(env);
5482 env->dcache_line_size = 32;
5483 env->icache_line_size = 32;
5484 /* Allocate hardware IRQ controller */
5485 ppc6xx_irq_init(env);
5486 }
5487
5488 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5489 {
5490 DeviceClass *dc = DEVICE_CLASS(oc);
5491 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5492
5493 dc->desc = "PowerPC 750CX";
5494 pcc->init_proc = init_proc_750cx;
5495 pcc->check_pow = check_pow_hid0;
5496 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5497 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5498 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5499 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5500 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5501 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5502 PPC_SEGMENT | PPC_EXTERN;
5503 pcc->insns_flags2 = PPC_NONE;
5504 pcc->msr_mask = 0x000000000005FF77ULL;
5505 pcc->mmu_model = POWERPC_MMU_32B;
5506 #if defined(CONFIG_SOFTMMU)
5507 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5508 #endif
5509 pcc->excp_model = POWERPC_EXCP_7x0;
5510 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5511 pcc->bfd_mach = bfd_mach_ppc_750;
5512 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5513 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5514 }
5515
5516 static void init_proc_750fx (CPUPPCState *env)
5517 {
5518 gen_spr_ne_601(env);
5519 gen_spr_7xx(env);
5520 /* XXX : not implemented */
5521 spr_register(env, SPR_L2CR, "L2CR",
5522 SPR_NOACCESS, SPR_NOACCESS,
5523 &spr_read_generic, &spr_write_generic,
5524 0x00000000);
5525 /* Time base */
5526 gen_tbl(env);
5527 /* Thermal management */
5528 gen_spr_thrm(env);
5529 /* XXX : not implemented */
5530 spr_register(env, SPR_750_THRM4, "THRM4",
5531 SPR_NOACCESS, SPR_NOACCESS,
5532 &spr_read_generic, &spr_write_generic,
5533 0x00000000);
5534 /* Hardware implementation registers */
5535 /* XXX : not implemented */
5536 spr_register(env, SPR_HID0, "HID0",
5537 SPR_NOACCESS, SPR_NOACCESS,
5538 &spr_read_generic, &spr_write_generic,
5539 0x00000000);
5540 /* XXX : not implemented */
5541 spr_register(env, SPR_HID1, "HID1",
5542 SPR_NOACCESS, SPR_NOACCESS,
5543 &spr_read_generic, &spr_write_generic,
5544 0x00000000);
5545 /* XXX : not implemented */
5546 spr_register(env, SPR_750FX_HID2, "HID2",
5547 SPR_NOACCESS, SPR_NOACCESS,
5548 &spr_read_generic, &spr_write_generic,
5549 0x00000000);
5550 /* Memory management */
5551 gen_low_BATs(env);
5552 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5553 gen_high_BATs(env);
5554 init_excp_7x0(env);
5555 env->dcache_line_size = 32;
5556 env->icache_line_size = 32;
5557 /* Allocate hardware IRQ controller */
5558 ppc6xx_irq_init(env);
5559 }
5560
5561 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5562 {
5563 DeviceClass *dc = DEVICE_CLASS(oc);
5564 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5565
5566 dc->desc = "PowerPC 750FX";
5567 pcc->init_proc = init_proc_750fx;
5568 pcc->check_pow = check_pow_hid0;
5569 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5570 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5571 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5572 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5573 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5574 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5575 PPC_SEGMENT | PPC_EXTERN;
5576 pcc->insns_flags2 = PPC_NONE;
5577 pcc->msr_mask = 0x000000000005FF77ULL;
5578 pcc->mmu_model = POWERPC_MMU_32B;
5579 #if defined(CONFIG_SOFTMMU)
5580 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5581 #endif
5582 pcc->excp_model = POWERPC_EXCP_7x0;
5583 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5584 pcc->bfd_mach = bfd_mach_ppc_750;
5585 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5586 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5587 }
5588
5589 static void init_proc_750gx (CPUPPCState *env)
5590 {
5591 gen_spr_ne_601(env);
5592 gen_spr_7xx(env);
5593 /* XXX : not implemented (XXX: different from 750fx) */
5594 spr_register(env, SPR_L2CR, "L2CR",
5595 SPR_NOACCESS, SPR_NOACCESS,
5596 &spr_read_generic, &spr_write_generic,
5597 0x00000000);
5598 /* Time base */
5599 gen_tbl(env);
5600 /* Thermal management */
5601 gen_spr_thrm(env);
5602 /* XXX : not implemented */
5603 spr_register(env, SPR_750_THRM4, "THRM4",
5604 SPR_NOACCESS, SPR_NOACCESS,
5605 &spr_read_generic, &spr_write_generic,
5606 0x00000000);
5607 /* Hardware implementation registers */
5608 /* XXX : not implemented (XXX: different from 750fx) */
5609 spr_register(env, SPR_HID0, "HID0",
5610 SPR_NOACCESS, SPR_NOACCESS,
5611 &spr_read_generic, &spr_write_generic,
5612 0x00000000);
5613 /* XXX : not implemented */
5614 spr_register(env, SPR_HID1, "HID1",
5615 SPR_NOACCESS, SPR_NOACCESS,
5616 &spr_read_generic, &spr_write_generic,
5617 0x00000000);
5618 /* XXX : not implemented (XXX: different from 750fx) */
5619 spr_register(env, SPR_750FX_HID2, "HID2",
5620 SPR_NOACCESS, SPR_NOACCESS,
5621 &spr_read_generic, &spr_write_generic,
5622 0x00000000);
5623 /* Memory management */
5624 gen_low_BATs(env);
5625 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5626 gen_high_BATs(env);
5627 init_excp_7x0(env);
5628 env->dcache_line_size = 32;
5629 env->icache_line_size = 32;
5630 /* Allocate hardware IRQ controller */
5631 ppc6xx_irq_init(env);
5632 }
5633
5634 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5635 {
5636 DeviceClass *dc = DEVICE_CLASS(oc);
5637 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5638
5639 dc->desc = "PowerPC 750GX";
5640 pcc->init_proc = init_proc_750gx;
5641 pcc->check_pow = check_pow_hid0;
5642 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5643 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5644 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5645 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5646 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5647 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5648 PPC_SEGMENT | PPC_EXTERN;
5649 pcc->insns_flags2 = PPC_NONE;
5650 pcc->msr_mask = 0x000000000005FF77ULL;
5651 pcc->mmu_model = POWERPC_MMU_32B;
5652 #if defined(CONFIG_SOFTMMU)
5653 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5654 #endif
5655 pcc->excp_model = POWERPC_EXCP_7x0;
5656 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5657 pcc->bfd_mach = bfd_mach_ppc_750;
5658 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5659 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5660 }
5661
5662 static void init_proc_745 (CPUPPCState *env)
5663 {
5664 gen_spr_ne_601(env);
5665 gen_spr_7xx(env);
5666 gen_spr_G2_755(env);
5667 /* Time base */
5668 gen_tbl(env);
5669 /* Thermal management */
5670 gen_spr_thrm(env);
5671 /* Hardware implementation registers */
5672 /* XXX : not implemented */
5673 spr_register(env, SPR_HID0, "HID0",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 &spr_read_generic, &spr_write_generic,
5676 0x00000000);
5677 /* XXX : not implemented */
5678 spr_register(env, SPR_HID1, "HID1",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 0x00000000);
5682 /* XXX : not implemented */
5683 spr_register(env, SPR_HID2, "HID2",
5684 SPR_NOACCESS, SPR_NOACCESS,
5685 &spr_read_generic, &spr_write_generic,
5686 0x00000000);
5687 /* Memory management */
5688 gen_low_BATs(env);
5689 gen_high_BATs(env);
5690 gen_6xx_7xx_soft_tlb(env, 64, 2);
5691 init_excp_7x5(env);
5692 env->dcache_line_size = 32;
5693 env->icache_line_size = 32;
5694 /* Allocate hardware IRQ controller */
5695 ppc6xx_irq_init(env);
5696 }
5697
5698 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5699 {
5700 DeviceClass *dc = DEVICE_CLASS(oc);
5701 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5702
5703 dc->desc = "PowerPC 745";
5704 pcc->init_proc = init_proc_745;
5705 pcc->check_pow = check_pow_hid0;
5706 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5707 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5708 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5709 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5710 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5711 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5712 PPC_SEGMENT | PPC_EXTERN;
5713 pcc->insns_flags2 = PPC_NONE;
5714 pcc->msr_mask = 0x000000000005FF77ULL;
5715 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5716 pcc->excp_model = POWERPC_EXCP_7x5;
5717 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5718 pcc->bfd_mach = bfd_mach_ppc_750;
5719 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5720 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5721 }
5722
5723 static void init_proc_755 (CPUPPCState *env)
5724 {
5725 gen_spr_ne_601(env);
5726 gen_spr_7xx(env);
5727 gen_spr_G2_755(env);
5728 /* Time base */
5729 gen_tbl(env);
5730 /* L2 cache control */
5731 /* XXX : not implemented */
5732 spr_register(env, SPR_L2CR, "L2CR",
5733 SPR_NOACCESS, SPR_NOACCESS,
5734 &spr_read_generic, &spr_write_generic,
5735 0x00000000);
5736 /* XXX : not implemented */
5737 spr_register(env, SPR_L2PMCR, "L2PMCR",
5738 SPR_NOACCESS, SPR_NOACCESS,
5739 &spr_read_generic, &spr_write_generic,
5740 0x00000000);
5741 /* Thermal management */
5742 gen_spr_thrm(env);
5743 /* Hardware implementation registers */
5744 /* XXX : not implemented */
5745 spr_register(env, SPR_HID0, "HID0",
5746 SPR_NOACCESS, SPR_NOACCESS,
5747 &spr_read_generic, &spr_write_generic,
5748 0x00000000);
5749 /* XXX : not implemented */
5750 spr_register(env, SPR_HID1, "HID1",
5751 SPR_NOACCESS, SPR_NOACCESS,
5752 &spr_read_generic, &spr_write_generic,
5753 0x00000000);
5754 /* XXX : not implemented */
5755 spr_register(env, SPR_HID2, "HID2",
5756 SPR_NOACCESS, SPR_NOACCESS,
5757 &spr_read_generic, &spr_write_generic,
5758 0x00000000);
5759 /* Memory management */
5760 gen_low_BATs(env);
5761 gen_high_BATs(env);
5762 gen_6xx_7xx_soft_tlb(env, 64, 2);
5763 init_excp_7x5(env);
5764 env->dcache_line_size = 32;
5765 env->icache_line_size = 32;
5766 /* Allocate hardware IRQ controller */
5767 ppc6xx_irq_init(env);
5768 }
5769
5770 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5771 {
5772 DeviceClass *dc = DEVICE_CLASS(oc);
5773 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5774
5775 dc->desc = "PowerPC 755";
5776 pcc->init_proc = init_proc_755;
5777 pcc->check_pow = check_pow_hid0;
5778 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5779 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5780 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5781 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5782 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5783 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5784 PPC_SEGMENT | PPC_EXTERN;
5785 pcc->insns_flags2 = PPC_NONE;
5786 pcc->msr_mask = 0x000000000005FF77ULL;
5787 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5788 pcc->excp_model = POWERPC_EXCP_7x5;
5789 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5790 pcc->bfd_mach = bfd_mach_ppc_750;
5791 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5792 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5793 }
5794
5795 static void init_proc_7400 (CPUPPCState *env)
5796 {
5797 gen_spr_ne_601(env);
5798 gen_spr_7xx(env);
5799 /* Time base */
5800 gen_tbl(env);
5801 /* 74xx specific SPR */
5802 gen_spr_74xx(env);
5803 /* XXX : not implemented */
5804 spr_register(env, SPR_UBAMR, "UBAMR",
5805 &spr_read_ureg, SPR_NOACCESS,
5806 &spr_read_ureg, SPR_NOACCESS,
5807 0x00000000);
5808 /* XXX: this seems not implemented on all revisions. */
5809 /* XXX : not implemented */
5810 spr_register(env, SPR_MSSCR1, "MSSCR1",
5811 SPR_NOACCESS, SPR_NOACCESS,
5812 &spr_read_generic, &spr_write_generic,
5813 0x00000000);
5814 /* Thermal management */
5815 gen_spr_thrm(env);
5816 /* Memory management */
5817 gen_low_BATs(env);
5818 init_excp_7400(env);
5819 env->dcache_line_size = 32;
5820 env->icache_line_size = 32;
5821 /* Allocate hardware IRQ controller */
5822 ppc6xx_irq_init(env);
5823 }
5824
5825 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5826 {
5827 DeviceClass *dc = DEVICE_CLASS(oc);
5828 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5829
5830 dc->desc = "PowerPC 7400 (aka G4)";
5831 pcc->init_proc = init_proc_7400;
5832 pcc->check_pow = check_pow_hid0;
5833 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5834 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5835 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5836 PPC_FLOAT_STFIWX |
5837 PPC_CACHE | PPC_CACHE_ICBI |
5838 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5839 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5840 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5841 PPC_MEM_TLBIA |
5842 PPC_SEGMENT | PPC_EXTERN |
5843 PPC_ALTIVEC;
5844 pcc->insns_flags2 = PPC_NONE;
5845 pcc->msr_mask = 0x000000000205FF77ULL;
5846 pcc->mmu_model = POWERPC_MMU_32B;
5847 #if defined(CONFIG_SOFTMMU)
5848 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5849 #endif
5850 pcc->excp_model = POWERPC_EXCP_74xx;
5851 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5852 pcc->bfd_mach = bfd_mach_ppc_7400;
5853 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5854 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5855 POWERPC_FLAG_BUS_CLK;
5856 }
5857
5858 static void init_proc_7410 (CPUPPCState *env)
5859 {
5860 gen_spr_ne_601(env);
5861 gen_spr_7xx(env);
5862 /* Time base */
5863 gen_tbl(env);
5864 /* 74xx specific SPR */
5865 gen_spr_74xx(env);
5866 /* XXX : not implemented */
5867 spr_register(env, SPR_UBAMR, "UBAMR",
5868 &spr_read_ureg, SPR_NOACCESS,
5869 &spr_read_ureg, SPR_NOACCESS,
5870 0x00000000);
5871 /* Thermal management */
5872 gen_spr_thrm(env);
5873 /* L2PMCR */
5874 /* XXX : not implemented */
5875 spr_register(env, SPR_L2PMCR, "L2PMCR",
5876 SPR_NOACCESS, SPR_NOACCESS,
5877 &spr_read_generic, &spr_write_generic,
5878 0x00000000);
5879 /* LDSTDB */
5880 /* XXX : not implemented */
5881 spr_register(env, SPR_LDSTDB, "LDSTDB",
5882 SPR_NOACCESS, SPR_NOACCESS,
5883 &spr_read_generic, &spr_write_generic,
5884 0x00000000);
5885 /* Memory management */
5886 gen_low_BATs(env);
5887 init_excp_7400(env);
5888 env->dcache_line_size = 32;
5889 env->icache_line_size = 32;
5890 /* Allocate hardware IRQ controller */
5891 ppc6xx_irq_init(env);
5892 }
5893
5894 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5895 {
5896 DeviceClass *dc = DEVICE_CLASS(oc);
5897 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5898
5899 dc->desc = "PowerPC 7410 (aka G4)";
5900 pcc->init_proc = init_proc_7410;
5901 pcc->check_pow = check_pow_hid0;
5902 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5903 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5904 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5905 PPC_FLOAT_STFIWX |
5906 PPC_CACHE | PPC_CACHE_ICBI |
5907 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5908 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5909 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5910 PPC_MEM_TLBIA |
5911 PPC_SEGMENT | PPC_EXTERN |
5912 PPC_ALTIVEC;
5913 pcc->insns_flags2 = PPC_NONE;
5914 pcc->msr_mask = 0x000000000205FF77ULL;
5915 pcc->mmu_model = POWERPC_MMU_32B;
5916 #if defined(CONFIG_SOFTMMU)
5917 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5918 #endif
5919 pcc->excp_model = POWERPC_EXCP_74xx;
5920 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5921 pcc->bfd_mach = bfd_mach_ppc_7400;
5922 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5923 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5924 POWERPC_FLAG_BUS_CLK;
5925 }
5926
5927 static void init_proc_7440 (CPUPPCState *env)
5928 {
5929 gen_spr_ne_601(env);
5930 gen_spr_7xx(env);
5931 /* Time base */
5932 gen_tbl(env);
5933 /* 74xx specific SPR */
5934 gen_spr_74xx(env);
5935 /* XXX : not implemented */
5936 spr_register(env, SPR_UBAMR, "UBAMR",
5937 &spr_read_ureg, SPR_NOACCESS,
5938 &spr_read_ureg, SPR_NOACCESS,
5939 0x00000000);
5940 /* LDSTCR */
5941 /* XXX : not implemented */
5942 spr_register(env, SPR_LDSTCR, "LDSTCR",
5943 SPR_NOACCESS, SPR_NOACCESS,
5944 &spr_read_generic, &spr_write_generic,
5945 0x00000000);
5946 /* ICTRL */
5947 /* XXX : not implemented */
5948 spr_register(env, SPR_ICTRL, "ICTRL",
5949 SPR_NOACCESS, SPR_NOACCESS,
5950 &spr_read_generic, &spr_write_generic,
5951 0x00000000);
5952 /* MSSSR0 */
5953 /* XXX : not implemented */
5954 spr_register(env, SPR_MSSSR0, "MSSSR0",
5955 SPR_NOACCESS, SPR_NOACCESS,
5956 &spr_read_generic, &spr_write_generic,
5957 0x00000000);
5958 /* PMC */
5959 /* XXX : not implemented */
5960 spr_register(env, SPR_PMC5, "PMC5",
5961 SPR_NOACCESS, SPR_NOACCESS,
5962 &spr_read_generic, &spr_write_generic,
5963 0x00000000);
5964 /* XXX : not implemented */
5965 spr_register(env, SPR_UPMC5, "UPMC5",
5966 &spr_read_ureg, SPR_NOACCESS,
5967 &spr_read_ureg, SPR_NOACCESS,
5968 0x00000000);
5969 /* XXX : not implemented */
5970 spr_register(env, SPR_PMC6, "PMC6",
5971 SPR_NOACCESS, SPR_NOACCESS,
5972 &spr_read_generic, &spr_write_generic,
5973 0x00000000);
5974 /* XXX : not implemented */
5975 spr_register(env, SPR_UPMC6, "UPMC6",
5976 &spr_read_ureg, SPR_NOACCESS,
5977 &spr_read_ureg, SPR_NOACCESS,
5978 0x00000000);
5979 /* Memory management */
5980 gen_low_BATs(env);
5981 gen_74xx_soft_tlb(env, 128, 2);
5982 init_excp_7450(env);
5983 env->dcache_line_size = 32;
5984 env->icache_line_size = 32;
5985 /* Allocate hardware IRQ controller */
5986 ppc6xx_irq_init(env);
5987 }
5988
5989 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5990 {
5991 DeviceClass *dc = DEVICE_CLASS(oc);
5992 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5993
5994 dc->desc = "PowerPC 7440 (aka G4)";
5995 pcc->init_proc = init_proc_7440;
5996 pcc->check_pow = check_pow_hid0_74xx;
5997 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5998 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5999 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6000 PPC_FLOAT_STFIWX |
6001 PPC_CACHE | PPC_CACHE_ICBI |
6002 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6003 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6004 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6005 PPC_MEM_TLBIA | PPC_74xx_TLB |
6006 PPC_SEGMENT | PPC_EXTERN |
6007 PPC_ALTIVEC;
6008 pcc->insns_flags2 = PPC_NONE;
6009 pcc->msr_mask = 0x000000000205FF77ULL;
6010 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6011 pcc->excp_model = POWERPC_EXCP_74xx;
6012 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6013 pcc->bfd_mach = bfd_mach_ppc_7400;
6014 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6015 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6016 POWERPC_FLAG_BUS_CLK;
6017 }
6018
6019 static void init_proc_7450 (CPUPPCState *env)
6020 {
6021 gen_spr_ne_601(env);
6022 gen_spr_7xx(env);
6023 /* Time base */
6024 gen_tbl(env);
6025 /* 74xx specific SPR */
6026 gen_spr_74xx(env);
6027 /* Level 3 cache control */
6028 gen_l3_ctrl(env);
6029 /* L3ITCR1 */
6030 /* XXX : not implemented */
6031 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6032 SPR_NOACCESS, SPR_NOACCESS,
6033 &spr_read_generic, &spr_write_generic,
6034 0x00000000);
6035 /* L3ITCR2 */
6036 /* XXX : not implemented */
6037 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_generic, &spr_write_generic,
6040 0x00000000);
6041 /* L3ITCR3 */
6042 /* XXX : not implemented */
6043 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6044 SPR_NOACCESS, SPR_NOACCESS,
6045 &spr_read_generic, &spr_write_generic,
6046 0x00000000);
6047 /* L3OHCR */
6048 /* XXX : not implemented */
6049 spr_register(env, SPR_L3OHCR, "L3OHCR",
6050 SPR_NOACCESS, SPR_NOACCESS,
6051 &spr_read_generic, &spr_write_generic,
6052 0x00000000);
6053 /* XXX : not implemented */
6054 spr_register(env, SPR_UBAMR, "UBAMR",
6055 &spr_read_ureg, SPR_NOACCESS,
6056 &spr_read_ureg, SPR_NOACCESS,
6057 0x00000000);
6058 /* LDSTCR */
6059 /* XXX : not implemented */
6060 spr_register(env, SPR_LDSTCR, "LDSTCR",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 &spr_read_generic, &spr_write_generic,
6063 0x00000000);
6064 /* ICTRL */
6065 /* XXX : not implemented */
6066 spr_register(env, SPR_ICTRL, "ICTRL",
6067 SPR_NOACCESS, SPR_NOACCESS,
6068 &spr_read_generic, &spr_write_generic,
6069 0x00000000);
6070 /* MSSSR0 */
6071 /* XXX : not implemented */
6072 spr_register(env, SPR_MSSSR0, "MSSSR0",
6073 SPR_NOACCESS, SPR_NOACCESS,
6074 &spr_read_generic, &spr_write_generic,
6075 0x00000000);
6076 /* PMC */
6077 /* XXX : not implemented */
6078 spr_register(env, SPR_PMC5, "PMC5",
6079 SPR_NOACCESS, SPR_NOACCESS,
6080 &spr_read_generic, &spr_write_generic,
6081 0x00000000);
6082 /* XXX : not implemented */
6083 spr_register(env, SPR_UPMC5, "UPMC5",
6084 &spr_read_ureg, SPR_NOACCESS,
6085 &spr_read_ureg, SPR_NOACCESS,
6086 0x00000000);
6087 /* XXX : not implemented */
6088 spr_register(env, SPR_PMC6, "PMC6",
6089 SPR_NOACCESS, SPR_NOACCESS,
6090 &spr_read_generic, &spr_write_generic,
6091 0x00000000);
6092 /* XXX : not implemented */
6093 spr_register(env, SPR_UPMC6, "UPMC6",
6094 &spr_read_ureg, SPR_NOACCESS,
6095 &spr_read_ureg, SPR_NOACCESS,
6096 0x00000000);
6097 /* Memory management */
6098 gen_low_BATs(env);
6099 gen_74xx_soft_tlb(env, 128, 2);
6100 init_excp_7450(env);
6101 env->dcache_line_size = 32;
6102 env->icache_line_size = 32;
6103 /* Allocate hardware IRQ controller */
6104 ppc6xx_irq_init(env);
6105 }
6106
6107 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6108 {
6109 DeviceClass *dc = DEVICE_CLASS(oc);
6110 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6111
6112 dc->desc = "PowerPC 7450 (aka G4)";
6113 pcc->init_proc = init_proc_7450;
6114 pcc->check_pow = check_pow_hid0_74xx;
6115 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6116 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6117 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6118 PPC_FLOAT_STFIWX |
6119 PPC_CACHE | PPC_CACHE_ICBI |
6120 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6121 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6122 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6123 PPC_MEM_TLBIA | PPC_74xx_TLB |
6124 PPC_SEGMENT | PPC_EXTERN |
6125 PPC_ALTIVEC;
6126 pcc->insns_flags2 = PPC_NONE;
6127 pcc->msr_mask = 0x000000000205FF77ULL;
6128 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6129 pcc->excp_model = POWERPC_EXCP_74xx;
6130 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6131 pcc->bfd_mach = bfd_mach_ppc_7400;
6132 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6133 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6134 POWERPC_FLAG_BUS_CLK;
6135 }
6136
6137 static void init_proc_7445 (CPUPPCState *env)
6138 {
6139 gen_spr_ne_601(env);
6140 gen_spr_7xx(env);
6141 /* Time base */
6142 gen_tbl(env);
6143 /* 74xx specific SPR */
6144 gen_spr_74xx(env);
6145 /* LDSTCR */
6146 /* XXX : not implemented */
6147 spr_register(env, SPR_LDSTCR, "LDSTCR",
6148 SPR_NOACCESS, SPR_NOACCESS,
6149 &spr_read_generic, &spr_write_generic,
6150 0x00000000);
6151 /* ICTRL */
6152 /* XXX : not implemented */
6153 spr_register(env, SPR_ICTRL, "ICTRL",
6154 SPR_NOACCESS, SPR_NOACCESS,
6155 &spr_read_generic, &spr_write_generic,
6156 0x00000000);
6157 /* MSSSR0 */
6158 /* XXX : not implemented */
6159 spr_register(env, SPR_MSSSR0, "MSSSR0",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 0x00000000);
6163 /* PMC */
6164 /* XXX : not implemented */
6165 spr_register(env, SPR_PMC5, "PMC5",
6166 SPR_NOACCESS, SPR_NOACCESS,
6167 &spr_read_generic, &spr_write_generic,
6168 0x00000000);
6169 /* XXX : not implemented */
6170 spr_register(env, SPR_UPMC5, "UPMC5",
6171 &spr_read_ureg, SPR_NOACCESS,
6172 &spr_read_ureg, SPR_NOACCESS,
6173 0x00000000);
6174 /* XXX : not implemented */
6175 spr_register(env, SPR_PMC6, "PMC6",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 /* XXX : not implemented */
6180 spr_register(env, SPR_UPMC6, "UPMC6",
6181 &spr_read_ureg, SPR_NOACCESS,
6182 &spr_read_ureg, SPR_NOACCESS,
6183 0x00000000);
6184 /* SPRGs */
6185 spr_register(env, SPR_SPRG4, "SPRG4",
6186 SPR_NOACCESS, SPR_NOACCESS,
6187 &spr_read_generic, &spr_write_generic,
6188 0x00000000);
6189 spr_register(env, SPR_USPRG4, "USPRG4",
6190 &spr_read_ureg, SPR_NOACCESS,
6191 &spr_read_ureg, SPR_NOACCESS,
6192 0x00000000);
6193 spr_register(env, SPR_SPRG5, "SPRG5",
6194 SPR_NOACCESS, SPR_NOACCESS,
6195 &spr_read_generic, &spr_write_generic,
6196 0x00000000);
6197 spr_register(env, SPR_USPRG5, "USPRG5",
6198 &spr_read_ureg, SPR_NOACCESS,
6199 &spr_read_ureg, SPR_NOACCESS,
6200 0x00000000);
6201 spr_register(env, SPR_SPRG6, "SPRG6",
6202 SPR_NOACCESS, SPR_NOACCESS,
6203 &spr_read_generic, &spr_write_generic,
6204 0x00000000);
6205 spr_register(env, SPR_USPRG6, "USPRG6",
6206 &spr_read_ureg, SPR_NOACCESS,
6207 &spr_read_ureg, SPR_NOACCESS,
6208 0x00000000);
6209 spr_register(env, SPR_SPRG7, "SPRG7",
6210 SPR_NOACCESS, SPR_NOACCESS,
6211 &spr_read_generic, &spr_write_generic,
6212 0x00000000);
6213 spr_register(env, SPR_USPRG7, "USPRG7",
6214 &spr_read_ureg, SPR_NOACCESS,
6215 &spr_read_ureg, SPR_NOACCESS,
6216 0x00000000);
6217 /* Memory management */
6218 gen_low_BATs(env);
6219 gen_high_BATs(env);
6220 gen_74xx_soft_tlb(env, 128, 2);
6221 init_excp_7450(env);
6222 env->dcache_line_size = 32;
6223 env->icache_line_size = 32;
6224 /* Allocate hardware IRQ controller */
6225 ppc6xx_irq_init(env);
6226 }
6227
6228 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6229 {
6230 DeviceClass *dc = DEVICE_CLASS(oc);
6231 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6232
6233 dc->desc = "PowerPC 7445 (aka G4)";
6234 pcc->init_proc = init_proc_7445;
6235 pcc->check_pow = check_pow_hid0_74xx;
6236 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6237 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6238 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6239 PPC_FLOAT_STFIWX |
6240 PPC_CACHE | PPC_CACHE_ICBI |
6241 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6242 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6243 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6244 PPC_MEM_TLBIA | PPC_74xx_TLB |
6245 PPC_SEGMENT | PPC_EXTERN |
6246 PPC_ALTIVEC;
6247 pcc->insns_flags2 = PPC_NONE;
6248 pcc->msr_mask = 0x000000000205FF77ULL;
6249 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6250 pcc->excp_model = POWERPC_EXCP_74xx;
6251 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6252 pcc->bfd_mach = bfd_mach_ppc_7400;
6253 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6254 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6255 POWERPC_FLAG_BUS_CLK;
6256 }
6257
6258 static void init_proc_7455 (CPUPPCState *env)
6259 {
6260 gen_spr_ne_601(env);
6261 gen_spr_7xx(env);
6262 /* Time base */
6263 gen_tbl(env);
6264 /* 74xx specific SPR */
6265 gen_spr_74xx(env);
6266 /* Level 3 cache control */
6267 gen_l3_ctrl(env);
6268 /* LDSTCR */
6269 /* XXX : not implemented */
6270 spr_register(env, SPR_LDSTCR, "LDSTCR",
6271 SPR_NOACCESS, SPR_NOACCESS,
6272 &spr_read_generic, &spr_write_generic,
6273 0x00000000);
6274 /* ICTRL */
6275 /* XXX : not implemented */
6276 spr_register(env, SPR_ICTRL, "ICTRL",
6277 SPR_NOACCESS, SPR_NOACCESS,
6278 &spr_read_generic, &spr_write_generic,
6279 0x00000000);
6280 /* MSSSR0 */
6281 /* XXX : not implemented */
6282 spr_register(env, SPR_MSSSR0, "MSSSR0",
6283 SPR_NOACCESS, SPR_NOACCESS,
6284 &spr_read_generic, &spr_write_generic,
6285 0x00000000);
6286 /* PMC */
6287 /* XXX : not implemented */
6288 spr_register(env, SPR_PMC5, "PMC5",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 /* XXX : not implemented */
6293 spr_register(env, SPR_UPMC5, "UPMC5",
6294 &spr_read_ureg, SPR_NOACCESS,
6295 &spr_read_ureg, SPR_NOACCESS,
6296 0x00000000);
6297 /* XXX : not implemented */
6298 spr_register(env, SPR_PMC6, "PMC6",
6299 SPR_NOACCESS, SPR_NOACCESS,
6300 &spr_read_generic, &spr_write_generic,
6301 0x00000000);
6302 /* XXX : not implemented */
6303 spr_register(env, SPR_UPMC6, "UPMC6",
6304 &spr_read_ureg, SPR_NOACCESS,
6305 &spr_read_ureg, SPR_NOACCESS,
6306 0x00000000);
6307 /* SPRGs */
6308 spr_register(env, SPR_SPRG4, "SPRG4",
6309 SPR_NOACCESS, SPR_NOACCESS,
6310 &spr_read_generic, &spr_write_generic,
6311 0x00000000);
6312 spr_register(env, SPR_USPRG4, "USPRG4",
6313 &spr_read_ureg, SPR_NOACCESS,
6314 &spr_read_ureg, SPR_NOACCESS,
6315 0x00000000);
6316 spr_register(env, SPR_SPRG5, "SPRG5",
6317 SPR_NOACCESS, SPR_NOACCESS,
6318 &spr_read_generic, &spr_write_generic,
6319 0x00000000);
6320 spr_register(env, SPR_USPRG5, "USPRG5",
6321 &spr_read_ureg, SPR_NOACCESS,
6322 &spr_read_ureg, SPR_NOACCESS,
6323 0x00000000);
6324 spr_register(env, SPR_SPRG6, "SPRG6",
6325 SPR_NOACCESS, SPR_NOACCESS,
6326 &spr_read_generic, &spr_write_generic,
6327 0x00000000);
6328 spr_register(env, SPR_USPRG6, "USPRG6",
6329 &spr_read_ureg, SPR_NOACCESS,
6330 &spr_read_ureg, SPR_NOACCESS,
6331 0x00000000);
6332 spr_register(env, SPR_SPRG7, "SPRG7",
6333 SPR_NOACCESS, SPR_NOACCESS,
6334 &spr_read_generic, &spr_write_generic,
6335 0x00000000);
6336 spr_register(env, SPR_USPRG7, "USPRG7",
6337 &spr_read_ureg, SPR_NOACCESS,
6338 &spr_read_ureg, SPR_NOACCESS,
6339 0x00000000);
6340 /* Memory management */
6341 gen_low_BATs(env);
6342 gen_high_BATs(env);
6343 gen_74xx_soft_tlb(env, 128, 2);
6344 init_excp_7450(env);
6345 env->dcache_line_size = 32;
6346 env->icache_line_size = 32;
6347 /* Allocate hardware IRQ controller */
6348 ppc6xx_irq_init(env);
6349 }
6350
6351 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6352 {
6353 DeviceClass *dc = DEVICE_CLASS(oc);
6354 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6355
6356 dc->desc = "PowerPC 7455 (aka G4)";
6357 pcc->init_proc = init_proc_7455;
6358 pcc->check_pow = check_pow_hid0_74xx;
6359 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6360 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6361 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6362 PPC_FLOAT_STFIWX |
6363 PPC_CACHE | PPC_CACHE_ICBI |
6364 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6365 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6366 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6367 PPC_MEM_TLBIA | PPC_74xx_TLB |
6368 PPC_SEGMENT | PPC_EXTERN |
6369 PPC_ALTIVEC;
6370 pcc->insns_flags2 = PPC_NONE;
6371 pcc->msr_mask = 0x000000000205FF77ULL;
6372 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6373 pcc->excp_model = POWERPC_EXCP_74xx;
6374 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6375 pcc->bfd_mach = bfd_mach_ppc_7400;
6376 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6377 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6378 POWERPC_FLAG_BUS_CLK;
6379 }
6380
6381 static void init_proc_7457 (CPUPPCState *env)
6382 {
6383 gen_spr_ne_601(env);
6384 gen_spr_7xx(env);
6385 /* Time base */
6386 gen_tbl(env);
6387 /* 74xx specific SPR */
6388 gen_spr_74xx(env);
6389 /* Level 3 cache control */
6390 gen_l3_ctrl(env);
6391 /* L3ITCR1 */
6392 /* XXX : not implemented */
6393 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6394 SPR_NOACCESS, SPR_NOACCESS,
6395 &spr_read_generic, &spr_write_generic,
6396 0x00000000);
6397 /* L3ITCR2 */
6398 /* XXX : not implemented */
6399 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6400 SPR_NOACCESS, SPR_NOACCESS,
6401 &spr_read_generic, &spr_write_generic,
6402 0x00000000);
6403 /* L3ITCR3 */
6404 /* XXX : not implemented */
6405 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6406 SPR_NOACCESS, SPR_NOACCESS,
6407 &spr_read_generic, &spr_write_generic,
6408 0x00000000);
6409 /* L3OHCR */
6410 /* XXX : not implemented */
6411 spr_register(env, SPR_L3OHCR, "L3OHCR",
6412 SPR_NOACCESS, SPR_NOACCESS,
6413 &spr_read_generic, &spr_write_generic,
6414 0x00000000);
6415 /* LDSTCR */
6416 /* XXX : not implemented */
6417 spr_register(env, SPR_LDSTCR, "LDSTCR",
6418 SPR_NOACCESS, SPR_NOACCESS,
6419 &spr_read_generic, &spr_write_generic,
6420 0x00000000);
6421 /* ICTRL */
6422 /* XXX : not implemented */
6423 spr_register(env, SPR_ICTRL, "ICTRL",
6424 SPR_NOACCESS, SPR_NOACCESS,
6425 &spr_read_generic, &spr_write_generic,
6426 0x00000000);
6427 /* MSSSR0 */
6428 /* XXX : not implemented */
6429 spr_register(env, SPR_MSSSR0, "MSSSR0",
6430 SPR_NOACCESS, SPR_NOACCESS,
6431 &spr_read_generic, &spr_write_generic,
6432 0x00000000);
6433 /* PMC */
6434 /* XXX : not implemented */
6435 spr_register(env, SPR_PMC5, "PMC5",
6436 SPR_NOACCESS, SPR_NOACCESS,
6437 &spr_read_generic, &spr_write_generic,
6438 0x00000000);
6439 /* XXX : not implemented */
6440 spr_register(env, SPR_UPMC5, "UPMC5",
6441 &spr_read_ureg, SPR_NOACCESS,
6442 &spr_read_ureg, SPR_NOACCESS,
6443 0x00000000);
6444 /* XXX : not implemented */
6445 spr_register(env, SPR_PMC6, "PMC6",
6446 SPR_NOACCESS, SPR_NOACCESS,
6447 &spr_read_generic, &spr_write_generic,
6448 0x00000000);
6449 /* XXX : not implemented */
6450 spr_register(env, SPR_UPMC6, "UPMC6",
6451 &spr_read_ureg, SPR_NOACCESS,
6452 &spr_read_ureg, SPR_NOACCESS,
6453 0x00000000);
6454 /* SPRGs */
6455 spr_register(env, SPR_SPRG4, "SPRG4",
6456 SPR_NOACCESS, SPR_NOACCESS,
6457 &spr_read_generic, &spr_write_generic,
6458 0x00000000);
6459 spr_register(env, SPR_USPRG4, "USPRG4",
6460 &spr_read_ureg, SPR_NOACCESS,
6461 &spr_read_ureg, SPR_NOACCESS,
6462 0x00000000);
6463 spr_register(env, SPR_SPRG5, "SPRG5",
6464 SPR_NOACCESS, SPR_NOACCESS,
6465 &spr_read_generic, &spr_write_generic,
6466 0x00000000);
6467 spr_register(env, SPR_USPRG5, "USPRG5",
6468 &spr_read_ureg, SPR_NOACCESS,
6469 &spr_read_ureg, SPR_NOACCESS,
6470 0x00000000);
6471 spr_register(env, SPR_SPRG6, "SPRG6",
6472 SPR_NOACCESS, SPR_NOACCESS,
6473 &spr_read_generic, &spr_write_generic,
6474 0x00000000);
6475 spr_register(env, SPR_USPRG6, "USPRG6",
6476 &spr_read_ureg, SPR_NOACCESS,
6477 &spr_read_ureg, SPR_NOACCESS,
6478 0x00000000);
6479 spr_register(env, SPR_SPRG7, "SPRG7",
6480 SPR_NOACCESS, SPR_NOACCESS,
6481 &spr_read_generic, &spr_write_generic,
6482 0x00000000);
6483 spr_register(env, SPR_USPRG7, "USPRG7",
6484 &spr_read_ureg, SPR_NOACCESS,
6485 &spr_read_ureg, SPR_NOACCESS,
6486 0x00000000);
6487 /* Memory management */
6488 gen_low_BATs(env);
6489 gen_high_BATs(env);
6490 gen_74xx_soft_tlb(env, 128, 2);
6491 init_excp_7450(env);
6492 env->dcache_line_size = 32;
6493 env->icache_line_size = 32;
6494 /* Allocate hardware IRQ controller */
6495 ppc6xx_irq_init(env);
6496 }
6497
6498 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6499 {
6500 DeviceClass *dc = DEVICE_CLASS(oc);
6501 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6502
6503 dc->desc = "PowerPC 7457 (aka G4)";
6504 pcc->init_proc = init_proc_7457;
6505 pcc->check_pow = check_pow_hid0_74xx;
6506 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6507 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6508 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6509 PPC_FLOAT_STFIWX |
6510 PPC_CACHE | PPC_CACHE_ICBI |
6511 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6512 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6513 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6514 PPC_MEM_TLBIA | PPC_74xx_TLB |
6515 PPC_SEGMENT | PPC_EXTERN |
6516 PPC_ALTIVEC;
6517 pcc->insns_flags2 = PPC_NONE;
6518 pcc->msr_mask = 0x000000000205FF77ULL;
6519 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6520 pcc->excp_model = POWERPC_EXCP_74xx;
6521 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6522 pcc->bfd_mach = bfd_mach_ppc_7400;
6523 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6524 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6525 POWERPC_FLAG_BUS_CLK;
6526 }
6527
6528 #if defined (TARGET_PPC64)
6529 #if defined(CONFIG_USER_ONLY)
6530 #define POWERPC970_HID5_INIT 0x00000080
6531 #else
6532 #define POWERPC970_HID5_INIT 0x00000000
6533 #endif
6534
6535 static int check_pow_970 (CPUPPCState *env)
6536 {
6537 if (env->spr[SPR_HID0] & 0x00600000)
6538 return 1;
6539
6540 return 0;
6541 }
6542
6543 static void init_proc_970 (CPUPPCState *env)
6544 {
6545 gen_spr_ne_601(env);
6546 gen_spr_7xx(env);
6547 /* Time base */
6548 gen_tbl(env);
6549 /* Hardware implementation registers */
6550 /* XXX : not implemented */
6551 spr_register(env, SPR_HID0, "HID0",
6552 SPR_NOACCESS, SPR_NOACCESS,
6553 &spr_read_generic, &spr_write_clear,
6554 0x60000000);
6555 /* XXX : not implemented */
6556 spr_register(env, SPR_HID1, "HID1",
6557 SPR_NOACCESS, SPR_NOACCESS,
6558 &spr_read_generic, &spr_write_generic,
6559 0x00000000);
6560 /* XXX : not implemented */
6561 spr_register(env, SPR_750FX_HID2, "HID2",
6562 SPR_NOACCESS, SPR_NOACCESS,
6563 &spr_read_generic, &spr_write_generic,
6564 0x00000000);
6565 /* XXX : not implemented */
6566 spr_register(env, SPR_970_HID5, "HID5",
6567 SPR_NOACCESS, SPR_NOACCESS,
6568 &spr_read_generic, &spr_write_generic,
6569 POWERPC970_HID5_INIT);
6570 /* XXX : not implemented */
6571 spr_register(env, SPR_L2CR, "L2CR",
6572 SPR_NOACCESS, SPR_NOACCESS,
6573 &spr_read_generic, &spr_write_generic,
6574 0x00000000);
6575 /* Memory management */
6576 /* XXX: not correct */
6577 gen_low_BATs(env);
6578 /* XXX : not implemented */
6579 spr_register(env, SPR_MMUCFG, "MMUCFG",
6580 SPR_NOACCESS, SPR_NOACCESS,
6581 &spr_read_generic, SPR_NOACCESS,
6582 0x00000000); /* TOFIX */
6583 /* XXX : not implemented */
6584 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6585 SPR_NOACCESS, SPR_NOACCESS,
6586 &spr_read_generic, &spr_write_generic,
6587 0x00000000); /* TOFIX */
6588 spr_register(env, SPR_HIOR, "SPR_HIOR",
6589 SPR_NOACCESS, SPR_NOACCESS,
6590 &spr_read_hior, &spr_write_hior,
6591 0x00000000);
6592 #if !defined(CONFIG_USER_ONLY)
6593 env->slb_nr = 32;
6594 #endif
6595 init_excp_970(env);
6596 env->dcache_line_size = 128;
6597 env->icache_line_size = 128;
6598 /* Allocate hardware IRQ controller */
6599 ppc970_irq_init(env);
6600 /* Can't find information on what this should be on reset. This
6601 * value is the one used by 74xx processors. */
6602 vscr_init(env, 0x00010000);
6603 }
6604
6605 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6606 {
6607 DeviceClass *dc = DEVICE_CLASS(oc);
6608 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6609
6610 dc->desc = "PowerPC 970";
6611 pcc->init_proc = init_proc_970;
6612 pcc->check_pow = check_pow_970;
6613 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6614 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6615 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6616 PPC_FLOAT_STFIWX |
6617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6618 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6620 PPC_64B | PPC_ALTIVEC |
6621 PPC_SEGMENT_64B | PPC_SLBI;
6622 pcc->insns_flags2 = PPC_NONE;
6623 pcc->msr_mask = 0x900000000204FF36ULL;
6624 pcc->mmu_model = POWERPC_MMU_64B;
6625 #if defined(CONFIG_SOFTMMU)
6626 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6627 #endif
6628 pcc->excp_model = POWERPC_EXCP_970;
6629 pcc->bus_model = PPC_FLAGS_INPUT_970;
6630 pcc->bfd_mach = bfd_mach_ppc64;
6631 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6632 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6633 POWERPC_FLAG_BUS_CLK;
6634 }
6635
6636 static int check_pow_970FX (CPUPPCState *env)
6637 {
6638 if (env->spr[SPR_HID0] & 0x00600000)
6639 return 1;
6640
6641 return 0;
6642 }
6643
6644 static void init_proc_970FX (CPUPPCState *env)
6645 {
6646 gen_spr_ne_601(env);
6647 gen_spr_7xx(env);
6648 /* Time base */
6649 gen_tbl(env);
6650 /* Hardware implementation registers */
6651 /* XXX : not implemented */
6652 spr_register(env, SPR_HID0, "HID0",
6653 SPR_NOACCESS, SPR_NOACCESS,
6654 &spr_read_generic, &spr_write_clear,
6655 0x60000000);
6656 /* XXX : not implemented */
6657 spr_register(env, SPR_HID1, "HID1",
6658 SPR_NOACCESS, SPR_NOACCESS,
6659 &spr_read_generic, &spr_write_generic,
6660 0x00000000);
6661 /* XXX : not implemented */
6662 spr_register(env, SPR_750FX_HID2, "HID2",
6663 SPR_NOACCESS, SPR_NOACCESS,
6664 &spr_read_generic, &spr_write_generic,
6665 0x00000000);
6666 /* XXX : not implemented */
6667 spr_register(env, SPR_970_HID5, "HID5",
6668 SPR_NOACCESS, SPR_NOACCESS,
6669 &spr_read_generic, &spr_write_generic,
6670 POWERPC970_HID5_INIT);
6671 /* XXX : not implemented */
6672 spr_register(env, SPR_L2CR, "L2CR",
6673 SPR_NOACCESS, SPR_NOACCESS,
6674 &spr_read_generic, &spr_write_generic,
6675 0x00000000);
6676 /* Memory management */
6677 /* XXX: not correct */
6678 gen_low_BATs(env);
6679 /* XXX : not implemented */
6680 spr_register(env, SPR_MMUCFG, "MMUCFG",
6681 SPR_NOACCESS, SPR_NOACCESS,
6682 &spr_read_generic, SPR_NOACCESS,
6683 0x00000000); /* TOFIX */
6684 /* XXX : not implemented */
6685 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6686 SPR_NOACCESS, SPR_NOACCESS,
6687 &spr_read_generic, &spr_write_generic,
6688 0x00000000); /* TOFIX */
6689 spr_register(env, SPR_HIOR, "SPR_HIOR",
6690 SPR_NOACCESS, SPR_NOACCESS,
6691 &spr_read_hior, &spr_write_hior,
6692 0x00000000);
6693 spr_register(env, SPR_CTRL, "SPR_CTRL",
6694 SPR_NOACCESS, SPR_NOACCESS,
6695 &spr_read_generic, &spr_write_generic,
6696 0x00000000);
6697 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6698 SPR_NOACCESS, SPR_NOACCESS,
6699 &spr_read_generic, &spr_write_generic,
6700 0x00000000);
6701 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6702 &spr_read_generic, &spr_write_generic,
6703 &spr_read_generic, &spr_write_generic,
6704 0x00000000);
6705 #if !defined(CONFIG_USER_ONLY)
6706 env->slb_nr = 64;
6707 #endif
6708 init_excp_970(env);
6709 env->dcache_line_size = 128;
6710 env->icache_line_size = 128;
6711 /* Allocate hardware IRQ controller */
6712 ppc970_irq_init(env);
6713 /* Can't find information on what this should be on reset. This
6714 * value is the one used by 74xx processors. */
6715 vscr_init(env, 0x00010000);
6716 }
6717
6718 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6719 {
6720 DeviceClass *dc = DEVICE_CLASS(oc);
6721 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6722
6723 dc->desc = "PowerPC 970FX (aka G5)";
6724 pcc->init_proc = init_proc_970FX;
6725 pcc->check_pow = check_pow_970FX;
6726 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6727 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6728 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6729 PPC_FLOAT_STFIWX |
6730 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6731 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6732 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6733 PPC_64B | PPC_ALTIVEC |
6734 PPC_SEGMENT_64B | PPC_SLBI;
6735 pcc->insns_flags2 = PPC_NONE;
6736 pcc->msr_mask = 0x800000000204FF36ULL;
6737 pcc->mmu_model = POWERPC_MMU_64B;
6738 #if defined(CONFIG_SOFTMMU)
6739 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6740 #endif
6741 pcc->excp_model = POWERPC_EXCP_970;
6742 pcc->bus_model = PPC_FLAGS_INPUT_970;
6743 pcc->bfd_mach = bfd_mach_ppc64;
6744 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6745 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6746 POWERPC_FLAG_BUS_CLK;
6747 }
6748
6749 static int check_pow_970GX (CPUPPCState *env)
6750 {
6751 if (env->spr[SPR_HID0] & 0x00600000)
6752 return 1;
6753
6754 return 0;
6755 }
6756
6757 static void init_proc_970GX (CPUPPCState *env)
6758 {
6759 gen_spr_ne_601(env);
6760 gen_spr_7xx(env);
6761 /* Time base */
6762 gen_tbl(env);
6763 /* Hardware implementation registers */
6764 /* XXX : not implemented */
6765 spr_register(env, SPR_HID0, "HID0",
6766 SPR_NOACCESS, SPR_NOACCESS,
6767 &spr_read_generic, &spr_write_clear,
6768 0x60000000);
6769 /* XXX : not implemented */
6770 spr_register(env, SPR_HID1, "HID1",
6771 SPR_NOACCESS, SPR_NOACCESS,
6772 &spr_read_generic, &spr_write_generic,
6773 0x00000000);
6774 /* XXX : not implemented */
6775 spr_register(env, SPR_750FX_HID2, "HID2",
6776 SPR_NOACCESS, SPR_NOACCESS,
6777 &spr_read_generic, &spr_write_generic,
6778 0x00000000);
6779 /* XXX : not implemented */
6780 spr_register(env, SPR_970_HID5, "HID5",
6781 SPR_NOACCESS, SPR_NOACCESS,
6782 &spr_read_generic, &spr_write_generic,
6783 POWERPC970_HID5_INIT);
6784 /* XXX : not implemented */
6785 spr_register(env, SPR_L2CR, "L2CR",
6786 SPR_NOACCESS, SPR_NOACCESS,
6787 &spr_read_generic, &spr_write_generic,
6788 0x00000000);
6789 /* Memory management */
6790 /* XXX: not correct */
6791 gen_low_BATs(env);
6792 /* XXX : not implemented */
6793 spr_register(env, SPR_MMUCFG, "MMUCFG",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 &spr_read_generic, SPR_NOACCESS,
6796 0x00000000); /* TOFIX */
6797 /* XXX : not implemented */
6798 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6799 SPR_NOACCESS, SPR_NOACCESS,
6800 &spr_read_generic, &spr_write_generic,
6801 0x00000000); /* TOFIX */
6802 spr_register(env, SPR_HIOR, "SPR_HIOR",
6803 SPR_NOACCESS, SPR_NOACCESS,
6804 &spr_read_hior, &spr_write_hior,
6805 0x00000000);
6806 #if !defined(CONFIG_USER_ONLY)
6807 env->slb_nr = 32;
6808 #endif
6809 init_excp_970(env);
6810 env->dcache_line_size = 128;
6811 env->icache_line_size = 128;
6812 /* Allocate hardware IRQ controller */
6813 ppc970_irq_init(env);
6814 /* Can't find information on what this should be on reset. This
6815 * value is the one used by 74xx processors. */
6816 vscr_init(env, 0x00010000);
6817 }
6818
6819 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6820 {
6821 DeviceClass *dc = DEVICE_CLASS(oc);
6822 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6823
6824 dc->desc = "PowerPC 970 GX";
6825 pcc->init_proc = init_proc_970GX;
6826 pcc->check_pow = check_pow_970GX;
6827 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6828 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6829 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6830 PPC_FLOAT_STFIWX |
6831 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6832 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6833 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6834 PPC_64B | PPC_ALTIVEC |
6835 PPC_SEGMENT_64B | PPC_SLBI;
6836 pcc->insns_flags2 = PPC_NONE;
6837 pcc->msr_mask = 0x800000000204FF36ULL;
6838 pcc->mmu_model = POWERPC_MMU_64B;
6839 #if defined(CONFIG_SOFTMMU)
6840 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6841 #endif
6842 pcc->excp_model = POWERPC_EXCP_970;
6843 pcc->bus_model = PPC_FLAGS_INPUT_970;
6844 pcc->bfd_mach = bfd_mach_ppc64;
6845 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6846 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6847 POWERPC_FLAG_BUS_CLK;
6848 }
6849
6850 static int check_pow_970MP (CPUPPCState *env)
6851 {
6852 if (env->spr[SPR_HID0] & 0x01C00000)
6853 return 1;
6854
6855 return 0;
6856 }
6857
6858 static void init_proc_970MP (CPUPPCState *env)
6859 {
6860 gen_spr_ne_601(env);
6861 gen_spr_7xx(env);
6862 /* Time base */
6863 gen_tbl(env);
6864 /* Hardware implementation registers */
6865 /* XXX : not implemented */
6866 spr_register(env, SPR_HID0, "HID0",
6867 SPR_NOACCESS, SPR_NOACCESS,
6868 &spr_read_generic, &spr_write_clear,
6869 0x60000000);
6870 /* XXX : not implemented */
6871 spr_register(env, SPR_HID1, "HID1",
6872 SPR_NOACCESS, SPR_NOACCESS,
6873 &spr_read_generic, &spr_write_generic,
6874 0x00000000);
6875 /* XXX : not implemented */
6876 spr_register(env, SPR_750FX_HID2, "HID2",
6877 SPR_NOACCESS, SPR_NOACCESS,
6878 &spr_read_generic, &spr_write_generic,
6879 0x00000000);
6880 /* XXX : not implemented */
6881 spr_register(env, SPR_970_HID5, "HID5",
6882 SPR_NOACCESS, SPR_NOACCESS,
6883 &spr_read_generic, &spr_write_generic,
6884 POWERPC970_HID5_INIT);
6885 /* XXX : not implemented */
6886 spr_register(env, SPR_L2CR, "L2CR",
6887 SPR_NOACCESS, SPR_NOACCESS,
6888 &spr_read_generic, &spr_write_generic,
6889 0x00000000);
6890 /* Memory management */
6891 /* XXX: not correct */
6892 gen_low_BATs(env);
6893 /* XXX : not implemented */
6894 spr_register(env, SPR_MMUCFG, "MMUCFG",
6895 SPR_NOACCESS, SPR_NOACCESS,
6896 &spr_read_generic, SPR_NOACCESS,
6897 0x00000000); /* TOFIX */
6898 /* XXX : not implemented */
6899 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6900 SPR_NOACCESS, SPR_NOACCESS,
6901 &spr_read_generic, &spr_write_generic,
6902 0x00000000); /* TOFIX */
6903 spr_register(env, SPR_HIOR, "SPR_HIOR",
6904 SPR_NOACCESS, SPR_NOACCESS,
6905 &spr_read_hior, &spr_write_hior,
6906 0x00000000);
6907 #if !defined(CONFIG_USER_ONLY)
6908 env->slb_nr = 32;
6909 #endif
6910 init_excp_970(env);
6911 env->dcache_line_size = 128;
6912 env->icache_line_size = 128;
6913 /* Allocate hardware IRQ controller */
6914 ppc970_irq_init(env);
6915 /* Can't find information on what this should be on reset. This
6916 * value is the one used by 74xx processors. */
6917 vscr_init(env, 0x00010000);
6918 }
6919
6920 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6921 {
6922 DeviceClass *dc = DEVICE_CLASS(oc);
6923 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6924
6925 dc->desc = "PowerPC 970 MP";
6926 pcc->init_proc = init_proc_970MP;
6927 pcc->check_pow = check_pow_970MP;
6928 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6929 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6930 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6931 PPC_FLOAT_STFIWX |
6932 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6933 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6934 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6935 PPC_64B | PPC_ALTIVEC |
6936 PPC_SEGMENT_64B | PPC_SLBI;
6937 pcc->insns_flags2 = PPC_NONE;
6938 pcc->msr_mask = 0x900000000204FF36ULL;
6939 pcc->mmu_model = POWERPC_MMU_64B;
6940 #if defined(CONFIG_SOFTMMU)
6941 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6942 #endif
6943 pcc->excp_model = POWERPC_EXCP_970;
6944 pcc->bus_model = PPC_FLAGS_INPUT_970;
6945 pcc->bfd_mach = bfd_mach_ppc64;
6946 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6947 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6948 POWERPC_FLAG_BUS_CLK;
6949 }
6950
6951 static void init_proc_POWER7 (CPUPPCState *env)
6952 {
6953 gen_spr_ne_601(env);
6954 gen_spr_7xx(env);
6955 /* Time base */
6956 gen_tbl(env);
6957 /* Processor identification */
6958 spr_register(env, SPR_PIR, "PIR",
6959 SPR_NOACCESS, SPR_NOACCESS,
6960 &spr_read_generic, &spr_write_pir,
6961 0x00000000);
6962 #if !defined(CONFIG_USER_ONLY)
6963 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6964 spr_register_kvm(env, SPR_PURR, "PURR",
6965 &spr_read_purr, SPR_NOACCESS,
6966 &spr_read_purr, SPR_NOACCESS,
6967 KVM_REG_PPC_PURR, 0x00000000);
6968 spr_register_kvm(env, SPR_SPURR, "SPURR",
6969 &spr_read_purr, SPR_NOACCESS,
6970 &spr_read_purr, SPR_NOACCESS,
6971 KVM_REG_PPC_SPURR, 0x00000000);
6972 spr_register(env, SPR_CFAR, "SPR_CFAR",
6973 SPR_NOACCESS, SPR_NOACCESS,
6974 &spr_read_cfar, &spr_write_cfar,
6975 0x00000000);
6976 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6977 SPR_NOACCESS, SPR_NOACCESS,
6978 &spr_read_generic, &spr_write_generic,
6979 KVM_REG_PPC_DSCR, 0x00000000);
6980 spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
6981 SPR_NOACCESS, SPR_NOACCESS,
6982 &spr_read_generic, &spr_write_generic,
6983 KVM_REG_PPC_MMCRA, 0x00000000);
6984 spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
6985 SPR_NOACCESS, SPR_NOACCESS,
6986 &spr_read_generic, &spr_write_generic,
6987 KVM_REG_PPC_PMC5, 0x00000000);
6988 spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
6989 SPR_NOACCESS, SPR_NOACCESS,
6990 &spr_read_generic, &spr_write_generic,
6991 KVM_REG_PPC_PMC6, 0x00000000);
6992 #endif /* !CONFIG_USER_ONLY */
6993 /* Memory management */
6994 /* XXX : not implemented */
6995 spr_register(env, SPR_MMUCFG, "MMUCFG",
6996 SPR_NOACCESS, SPR_NOACCESS,
6997 &spr_read_generic, SPR_NOACCESS,
6998 0x00000000); /* TOFIX */
6999 gen_spr_amr(env);
7000 /* XXX : not implemented */
7001 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7002 SPR_NOACCESS, SPR_NOACCESS,
7003 &spr_read_generic, &spr_write_generic,
7004 0x80800000);
7005 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7006 SPR_NOACCESS, SPR_NOACCESS,
7007 &spr_read_generic, &spr_write_generic,
7008 0x80800000);
7009 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7010 &spr_read_generic, &spr_write_generic,
7011 &spr_read_generic, &spr_write_generic,
7012 0x00000000);
7013 spr_register(env, SPR_PPR, "PPR",
7014 &spr_read_generic, &spr_write_generic,
7015 &spr_read_generic, &spr_write_generic,
7016 0x00000000);
7017 #if !defined(CONFIG_USER_ONLY)
7018 env->slb_nr = 32;
7019 #endif
7020 init_excp_POWER7(env);
7021 env->dcache_line_size = 128;
7022 env->icache_line_size = 128;
7023
7024 /* Allocate hardware IRQ controller */
7025 ppcPOWER7_irq_init(env);
7026 /* Can't find information on what this should be on reset. This
7027 * value is the one used by 74xx processors. */
7028 vscr_init(env, 0x00010000);
7029 }
7030
7031 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7032 {
7033 DeviceClass *dc = DEVICE_CLASS(oc);
7034 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7035
7036 dc->desc = "POWER7";
7037 pcc->init_proc = init_proc_POWER7;
7038 pcc->check_pow = check_pow_nocheck;
7039 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7040 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7041 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7042 PPC_FLOAT_STFIWX |
7043 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7044 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7045 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7046 PPC_64B | PPC_ALTIVEC |
7047 PPC_SEGMENT_64B | PPC_SLBI |
7048 PPC_POPCNTB | PPC_POPCNTWD;
7049 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
7050 pcc->msr_mask = 0x800000000204FF36ULL;
7051 pcc->mmu_model = POWERPC_MMU_2_06;
7052 #if defined(CONFIG_SOFTMMU)
7053 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7054 #endif
7055 pcc->excp_model = POWERPC_EXCP_POWER7;
7056 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7057 pcc->bfd_mach = bfd_mach_ppc64;
7058 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7059 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7060 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7061 pcc->l1_dcache_size = 0x8000;
7062 pcc->l1_icache_size = 0x8000;
7063 }
7064 #endif /* defined (TARGET_PPC64) */
7065
7066
7067 /*****************************************************************************/
7068 /* Generic CPU instantiation routine */
7069 static void init_ppc_proc(PowerPCCPU *cpu)
7070 {
7071 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7072 CPUPPCState *env = &cpu->env;
7073 #if !defined(CONFIG_USER_ONLY)
7074 int i;
7075
7076 env->irq_inputs = NULL;
7077 /* Set all exception vectors to an invalid address */
7078 for (i = 0; i < POWERPC_EXCP_NB; i++)
7079 env->excp_vectors[i] = (target_ulong)(-1ULL);
7080 env->ivor_mask = 0x00000000;
7081 env->ivpr_mask = 0x00000000;
7082 /* Default MMU definitions */
7083 env->nb_BATs = 0;
7084 env->nb_tlb = 0;
7085 env->nb_ways = 0;
7086 env->tlb_type = TLB_NONE;
7087 #endif
7088 /* Register SPR common to all PowerPC implementations */
7089 gen_spr_generic(env);
7090 spr_register(env, SPR_PVR, "PVR",
7091 /* Linux permits userspace to read PVR */
7092 #if defined(CONFIG_LINUX_USER)
7093 &spr_read_generic,
7094 #else
7095 SPR_NOACCESS,
7096 #endif
7097 SPR_NOACCESS,
7098 &spr_read_generic, SPR_NOACCESS,
7099 pcc->pvr);
7100 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7101 if (pcc->svr != POWERPC_SVR_NONE) {
7102 if (pcc->svr & POWERPC_SVR_E500) {
7103 spr_register(env, SPR_E500_SVR, "SVR",
7104 SPR_NOACCESS, SPR_NOACCESS,
7105 &spr_read_generic, SPR_NOACCESS,
7106 pcc->svr & ~POWERPC_SVR_E500);
7107 } else {
7108 spr_register(env, SPR_SVR, "SVR",
7109 SPR_NOACCESS, SPR_NOACCESS,
7110 &spr_read_generic, SPR_NOACCESS,
7111 pcc->svr);
7112 }
7113 }
7114 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7115 (*pcc->init_proc)(env);
7116
7117 /* MSR bits & flags consistency checks */
7118 if (env->msr_mask & (1 << 25)) {
7119 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7120 case POWERPC_FLAG_SPE:
7121 case POWERPC_FLAG_VRE:
7122 break;
7123 default:
7124 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7125 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7126 exit(1);
7127 }
7128 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7129 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7130 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7131 exit(1);
7132 }
7133 if (env->msr_mask & (1 << 17)) {
7134 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7135 case POWERPC_FLAG_TGPR:
7136 case POWERPC_FLAG_CE:
7137 break;
7138 default:
7139 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7140 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7141 exit(1);
7142 }
7143 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7144 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7145 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7146 exit(1);
7147 }
7148 if (env->msr_mask & (1 << 10)) {
7149 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7150 POWERPC_FLAG_UBLE)) {
7151 case POWERPC_FLAG_SE:
7152 case POWERPC_FLAG_DWE:
7153 case POWERPC_FLAG_UBLE:
7154 break;
7155 default:
7156 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7157 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7158 "POWERPC_FLAG_UBLE\n");
7159 exit(1);
7160 }
7161 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7162 POWERPC_FLAG_UBLE)) {
7163 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7164 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7165 "POWERPC_FLAG_UBLE\n");
7166 exit(1);
7167 }
7168 if (env->msr_mask & (1 << 9)) {
7169 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7170 case POWERPC_FLAG_BE:
7171 case POWERPC_FLAG_DE:
7172 break;
7173 default:
7174 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7175 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7176 exit(1);
7177 }
7178 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7179 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7180 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7181 exit(1);
7182 }
7183 if (env->msr_mask & (1 << 2)) {
7184 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7185 case POWERPC_FLAG_PX:
7186 case POWERPC_FLAG_PMM:
7187 break;
7188 default:
7189 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7190 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7191 exit(1);
7192 }
7193 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7194 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7195 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7196 exit(1);
7197 }
7198 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7199 fprintf(stderr, "PowerPC flags inconsistency\n"
7200 "Should define the time-base and decrementer clock source\n");
7201 exit(1);
7202 }
7203 /* Allocate TLBs buffer when needed */
7204 #if !defined(CONFIG_USER_ONLY)
7205 if (env->nb_tlb != 0) {
7206 int nb_tlb = env->nb_tlb;
7207 if (env->id_tlbs != 0)
7208 nb_tlb *= 2;
7209 switch (env->tlb_type) {
7210 case TLB_6XX:
7211 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7212 break;
7213 case TLB_EMB:
7214 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7215 break;
7216 case TLB_MAS:
7217 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7218 break;
7219 }
7220 /* Pre-compute some useful values */
7221 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7222 }
7223 if (env->irq_inputs == NULL) {
7224 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7225 " Attempt QEMU to crash very soon !\n");
7226 }
7227 #endif
7228 if (env->check_pow == NULL) {
7229 fprintf(stderr, "WARNING: no power management check handler "
7230 "registered.\n"
7231 " Attempt QEMU to crash very soon !\n");
7232 }
7233 }
7234
7235 #if defined(PPC_DUMP_CPU)
7236 static void dump_ppc_sprs (CPUPPCState *env)
7237 {
7238 ppc_spr_t *spr;
7239 #if !defined(CONFIG_USER_ONLY)
7240 uint32_t sr, sw;
7241 #endif
7242 uint32_t ur, uw;
7243 int i, j, n;
7244
7245 printf("Special purpose registers:\n");
7246 for (i = 0; i < 32; i++) {
7247 for (j = 0; j < 32; j++) {
7248 n = (i << 5) | j;
7249 spr = &env->spr_cb[n];
7250 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7251 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7252 #if !defined(CONFIG_USER_ONLY)
7253 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7254 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7255 if (sw || sr || uw || ur) {
7256 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7257 (i << 5) | j, (i << 5) | j, spr->name,
7258 sw ? 'w' : '-', sr ? 'r' : '-',
7259 uw ? 'w' : '-', ur ? 'r' : '-');
7260 }
7261 #else
7262 if (uw || ur) {
7263 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7264 (i << 5) | j, (i << 5) | j, spr->name,
7265 uw ? 'w' : '-', ur ? 'r' : '-');
7266 }
7267 #endif
7268 }
7269 }
7270 fflush(stdout);
7271 fflush(stderr);
7272 }
7273 #endif
7274
7275 /*****************************************************************************/
7276 #include <stdlib.h>
7277 #include <string.h>
7278
7279 /* Opcode types */
7280 enum {
7281 PPC_DIRECT = 0, /* Opcode routine */
7282 PPC_INDIRECT = 1, /* Indirect opcode table */
7283 };
7284
7285 static inline int is_indirect_opcode (void *handler)
7286 {
7287 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7288 }
7289
7290 static inline opc_handler_t **ind_table(void *handler)
7291 {
7292 return (opc_handler_t **)((uintptr_t)handler & ~3);
7293 }
7294
7295 /* Instruction table creation */
7296 /* Opcodes tables creation */
7297 static void fill_new_table (opc_handler_t **table, int len)
7298 {
7299 int i;
7300
7301 for (i = 0; i < len; i++)
7302 table[i] = &invalid_handler;
7303 }
7304
7305 static int create_new_table (opc_handler_t **table, unsigned char idx)
7306 {
7307 opc_handler_t **tmp;
7308
7309 tmp = malloc(0x20 * sizeof(opc_handler_t));
7310 fill_new_table(tmp, 0x20);
7311 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7312
7313 return 0;
7314 }
7315
7316 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7317 opc_handler_t *handler)
7318 {
7319 if (table[idx] != &invalid_handler)
7320 return -1;
7321 table[idx] = handler;
7322
7323 return 0;
7324 }
7325
7326 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7327 unsigned char idx, opc_handler_t *handler)
7328 {
7329 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7330 printf("*** ERROR: opcode %02x already assigned in main "
7331 "opcode table\n", idx);
7332 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7333 printf(" Registered handler '%s' - new handler '%s'\n",
7334 ppc_opcodes[idx]->oname, handler->oname);
7335 #endif
7336 return -1;
7337 }
7338
7339 return 0;
7340 }
7341
7342 static int register_ind_in_table (opc_handler_t **table,
7343 unsigned char idx1, unsigned char idx2,
7344 opc_handler_t *handler)
7345 {
7346 if (table[idx1] == &invalid_handler) {
7347 if (create_new_table(table, idx1) < 0) {
7348 printf("*** ERROR: unable to create indirect table "
7349 "idx=%02x\n", idx1);
7350 return -1;
7351 }
7352 } else {
7353 if (!is_indirect_opcode(table[idx1])) {
7354 printf("*** ERROR: idx %02x already assigned to a direct "
7355 "opcode\n", idx1);
7356 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7357 printf(" Registered handler '%s' - new handler '%s'\n",
7358 ind_table(table[idx1])[idx2]->oname, handler->oname);
7359 #endif
7360 return -1;
7361 }
7362 }
7363 if (handler != NULL &&
7364 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7365 printf("*** ERROR: opcode %02x already assigned in "
7366 "opcode table %02x\n", idx2, idx1);
7367 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7368 printf(" Registered handler '%s' - new handler '%s'\n",
7369 ind_table(table[idx1])[idx2]->oname, handler->oname);
7370 #endif
7371 return -1;
7372 }
7373
7374 return 0;
7375 }
7376
7377 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7378 unsigned char idx1, unsigned char idx2,
7379 opc_handler_t *handler)
7380 {
7381 int ret;
7382
7383 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7384
7385 return ret;
7386 }
7387
7388 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7389 unsigned char idx1, unsigned char idx2,
7390 unsigned char idx3, opc_handler_t *handler)
7391 {
7392 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7393 printf("*** ERROR: unable to join indirect table idx "
7394 "[%02x-%02x]\n", idx1, idx2);
7395 return -1;
7396 }
7397 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7398 handler) < 0) {
7399 printf("*** ERROR: unable to insert opcode "
7400 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7401 return -1;
7402 }
7403
7404 return 0;
7405 }
7406
7407 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7408 {
7409 if (insn->opc2 != 0xFF) {
7410 if (insn->opc3 != 0xFF) {
7411 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7412 insn->opc3, &insn->handler) < 0)
7413 return -1;
7414 } else {
7415 if (register_ind_insn(ppc_opcodes, insn->opc1,
7416 insn->opc2, &insn->handler) < 0)
7417 return -1;
7418 }
7419 } else {
7420 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7421 return -1;
7422 }
7423
7424 return 0;
7425 }
7426
7427 static int test_opcode_table (opc_handler_t **table, int len)
7428 {
7429 int i, count, tmp;
7430
7431 for (i = 0, count = 0; i < len; i++) {
7432 /* Consistency fixup */
7433 if (table[i] == NULL)
7434 table[i] = &invalid_handler;
7435 if (table[i] != &invalid_handler) {
7436 if (is_indirect_opcode(table[i])) {
7437 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7438 if (tmp == 0) {
7439 free(table[i]);
7440 table[i] = &invalid_handler;
7441 } else {
7442 count++;
7443 }
7444 } else {
7445 count++;
7446 }
7447 }
7448 }
7449
7450 return count;
7451 }
7452
7453 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7454 {
7455 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7456 printf("*** WARNING: no opcode defined !\n");
7457 }
7458
7459 /*****************************************************************************/
7460 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7461 {
7462 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7463 CPUPPCState *env = &cpu->env;
7464 opcode_t *opc;
7465
7466 fill_new_table(env->opcodes, 0x40);
7467 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7468 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7469 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7470 if (register_insn(env->opcodes, opc) < 0) {
7471 error_setg(errp, "ERROR initializing PowerPC instruction "
7472 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7473 opc->opc3);
7474 return;
7475 }
7476 }
7477 }
7478 fix_opcode_tables(env->opcodes);
7479 fflush(stdout);
7480 fflush(stderr);
7481 }
7482
7483 #if defined(PPC_DUMP_CPU)
7484 static void dump_ppc_insns (CPUPPCState *env)
7485 {
7486 opc_handler_t **table, *handler;
7487 const char *p, *q;
7488 uint8_t opc1, opc2, opc3;
7489
7490 printf("Instructions set:\n");
7491 /* opc1 is 6 bits long */
7492 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7493 table = env->opcodes;
7494 handler = table[opc1];
7495 if (is_indirect_opcode(handler)) {
7496 /* opc2 is 5 bits long */
7497 for (opc2 = 0; opc2 < 0x20; opc2++) {
7498 table = env->opcodes;
7499 handler = env->opcodes[opc1];
7500 table = ind_table(handler);
7501 handler = table[opc2];
7502 if (is_indirect_opcode(handler)) {
7503 table = ind_table(handler);
7504 /* opc3 is 5 bits long */
7505 for (opc3 = 0; opc3 < 0x20; opc3++) {
7506 handler = table[opc3];
7507 if (handler->handler != &gen_invalid) {
7508 /* Special hack to properly dump SPE insns */
7509 p = strchr(handler->oname, '_');
7510 if (p == NULL) {
7511 printf("INSN: %02x %02x %02x (%02d %04d) : "
7512 "%s\n",
7513 opc1, opc2, opc3, opc1,
7514 (opc3 << 5) | opc2,
7515 handler->oname);
7516 } else {
7517 q = "speundef";
7518 if ((p - handler->oname) != strlen(q) ||
7519 memcmp(handler->oname, q, strlen(q)) != 0) {
7520 /* First instruction */
7521 printf("INSN: %02x %02x %02x (%02d %04d) : "
7522 "%.*s\n",
7523 opc1, opc2 << 1, opc3, opc1,
7524 (opc3 << 6) | (opc2 << 1),
7525 (int)(p - handler->oname),
7526 handler->oname);
7527 }
7528 if (strcmp(p + 1, q) != 0) {
7529 /* Second instruction */
7530 printf("INSN: %02x %02x %02x (%02d %04d) : "
7531 "%s\n",
7532 opc1, (opc2 << 1) | 1, opc3, opc1,
7533 (opc3 << 6) | (opc2 << 1) | 1,
7534 p + 1);
7535 }
7536 }
7537 }
7538 }
7539 } else {
7540 if (handler->handler != &gen_invalid) {
7541 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7542 opc1, opc2, opc1, opc2, handler->oname);
7543 }
7544 }
7545 }
7546 } else {
7547 if (handler->handler != &gen_invalid) {
7548 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7549 opc1, opc1, handler->oname);
7550 }
7551 }
7552 }
7553 }
7554 #endif
7555
7556 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7557 {
7558 if (n < 32) {
7559 stfq_p(mem_buf, env->fpr[n]);
7560 return 8;
7561 }
7562 if (n == 32) {
7563 stl_p(mem_buf, env->fpscr);
7564 return 4;
7565 }
7566 return 0;
7567 }
7568
7569 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7570 {
7571 if (n < 32) {
7572 env->fpr[n] = ldfq_p(mem_buf);
7573 return 8;
7574 }
7575 if (n == 32) {
7576 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
7577 return 4;
7578 }
7579 return 0;
7580 }
7581
7582 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7583 {
7584 if (n < 32) {
7585 #ifdef HOST_WORDS_BIGENDIAN
7586 stq_p(mem_buf, env->avr[n].u64[0]);
7587 stq_p(mem_buf+8, env->avr[n].u64[1]);
7588 #else
7589 stq_p(mem_buf, env->avr[n].u64[1]);
7590 stq_p(mem_buf+8, env->avr[n].u64[0]);
7591 #endif
7592 return 16;
7593 }
7594 if (n == 32) {
7595 stl_p(mem_buf, env->vscr);
7596 return 4;
7597 }
7598 if (n == 33) {
7599 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7600 return 4;
7601 }
7602 return 0;
7603 }
7604
7605 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7606 {
7607 if (n < 32) {
7608 #ifdef HOST_WORDS_BIGENDIAN
7609 env->avr[n].u64[0] = ldq_p(mem_buf);
7610 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7611 #else
7612 env->avr[n].u64[1] = ldq_p(mem_buf);
7613 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7614 #endif
7615 return 16;
7616 }
7617 if (n == 32) {
7618 env->vscr = ldl_p(mem_buf);
7619 return 4;
7620 }
7621 if (n == 33) {
7622 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7623 return 4;
7624 }
7625 return 0;
7626 }
7627
7628 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7629 {
7630 if (n < 32) {
7631 #if defined(TARGET_PPC64)
7632 stl_p(mem_buf, env->gpr[n] >> 32);
7633 #else
7634 stl_p(mem_buf, env->gprh[n]);
7635 #endif
7636 return 4;
7637 }
7638 if (n == 32) {
7639 stq_p(mem_buf, env->spe_acc);
7640 return 8;
7641 }
7642 if (n == 33) {
7643 stl_p(mem_buf, env->spe_fscr);
7644 return 4;
7645 }
7646 return 0;
7647 }
7648
7649 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7650 {
7651 if (n < 32) {
7652 #if defined(TARGET_PPC64)
7653 target_ulong lo = (uint32_t)env->gpr[n];
7654 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7655 env->gpr[n] = lo | hi;
7656 #else
7657 env->gprh[n] = ldl_p(mem_buf);
7658 #endif
7659 return 4;
7660 }
7661 if (n == 32) {
7662 env->spe_acc = ldq_p(mem_buf);
7663 return 8;
7664 }
7665 if (n == 33) {
7666 env->spe_fscr = ldl_p(mem_buf);
7667 return 4;
7668 }
7669 return 0;
7670 }
7671
7672 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7673 {
7674 CPUPPCState *env = &cpu->env;
7675
7676 /* TCG doesn't (yet) emulate some groups of instructions that
7677 * are implemented on some otherwise supported CPUs (e.g. VSX
7678 * and decimal floating point instructions on POWER7). We
7679 * remove unsupported instruction groups from the cpu state's
7680 * instruction masks and hope the guest can cope. For at
7681 * least the pseries machine, the unavailability of these
7682 * instructions can be advertised to the guest via the device
7683 * tree. */
7684 if ((env->insns_flags & ~PPC_TCG_INSNS)
7685 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7686 fprintf(stderr, "Warning: Disabling some instructions which are not "
7687 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7688 env->insns_flags & ~PPC_TCG_INSNS,
7689 env->insns_flags2 & ~PPC_TCG_INSNS2);
7690 }
7691 env->insns_flags &= PPC_TCG_INSNS;
7692 env->insns_flags2 &= PPC_TCG_INSNS2;
7693 return 0;
7694 }
7695
7696 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
7697 {
7698 PowerPCCPU *cpu = POWERPC_CPU(dev);
7699 CPUPPCState *env = &cpu->env;
7700 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7701 Error *local_err = NULL;
7702 #if !defined(CONFIG_USER_ONLY)
7703 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7704 #endif
7705
7706 #if !defined(CONFIG_USER_ONLY)
7707 if (smp_threads > max_smt) {
7708 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7709 max_smt, kvm_enabled() ? "KVM" : "TCG");
7710 return;
7711 }
7712 #endif
7713
7714 if (kvm_enabled()) {
7715 if (kvmppc_fixup_cpu(cpu) != 0) {
7716 error_setg(errp, "Unable to virtualize selected CPU with KVM");
7717 return;
7718 }
7719 } else {
7720 if (ppc_fixup_cpu(cpu) != 0) {
7721 error_setg(errp, "Unable to emulate selected CPU with TCG");
7722 return;
7723 }
7724 }
7725
7726 #if defined(TARGET_PPCEMB)
7727 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7728 error_setg(errp, "CPU does not possess a BookE MMU. "
7729 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7730 "or choose another CPU model.");
7731 return;
7732 }
7733 #endif
7734
7735 create_ppc_opcodes(cpu, &local_err);
7736 if (local_err != NULL) {
7737 error_propagate(errp, local_err);
7738 return;
7739 }
7740 init_ppc_proc(cpu);
7741
7742 if (pcc->insns_flags & PPC_FLOAT) {
7743 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
7744 33, "power-fpu.xml", 0);
7745 }
7746 if (pcc->insns_flags & PPC_ALTIVEC) {
7747 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
7748 34, "power-altivec.xml", 0);
7749 }
7750 if (pcc->insns_flags & PPC_SPE) {
7751 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
7752 34, "power-spe.xml", 0);
7753 }
7754
7755 qemu_init_vcpu(env);
7756
7757 pcc->parent_realize(dev, errp);
7758
7759 #if defined(PPC_DUMP_CPU)
7760 {
7761 const char *mmu_model, *excp_model, *bus_model;
7762 switch (env->mmu_model) {
7763 case POWERPC_MMU_32B:
7764 mmu_model = "PowerPC 32";
7765 break;
7766 case POWERPC_MMU_SOFT_6xx:
7767 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7768 break;
7769 case POWERPC_MMU_SOFT_74xx:
7770 mmu_model = "PowerPC 74xx with software driven TLBs";
7771 break;
7772 case POWERPC_MMU_SOFT_4xx:
7773 mmu_model = "PowerPC 4xx with software driven TLBs";
7774 break;
7775 case POWERPC_MMU_SOFT_4xx_Z:
7776 mmu_model = "PowerPC 4xx with software driven TLBs "
7777 "and zones protections";
7778 break;
7779 case POWERPC_MMU_REAL:
7780 mmu_model = "PowerPC real mode only";
7781 break;
7782 case POWERPC_MMU_MPC8xx:
7783 mmu_model = "PowerPC MPC8xx";
7784 break;
7785 case POWERPC_MMU_BOOKE:
7786 mmu_model = "PowerPC BookE";
7787 break;
7788 case POWERPC_MMU_BOOKE206:
7789 mmu_model = "PowerPC BookE 2.06";
7790 break;
7791 case POWERPC_MMU_601:
7792 mmu_model = "PowerPC 601";
7793 break;
7794 #if defined (TARGET_PPC64)
7795 case POWERPC_MMU_64B:
7796 mmu_model = "PowerPC 64";
7797 break;
7798 #endif
7799 default:
7800 mmu_model = "Unknown or invalid";
7801 break;
7802 }
7803 switch (env->excp_model) {
7804 case POWERPC_EXCP_STD:
7805 excp_model = "PowerPC";
7806 break;
7807 case POWERPC_EXCP_40x:
7808 excp_model = "PowerPC 40x";
7809 break;
7810 case POWERPC_EXCP_601:
7811 excp_model = "PowerPC 601";
7812 break;
7813 case POWERPC_EXCP_602:
7814 excp_model = "PowerPC 602";
7815 break;
7816 case POWERPC_EXCP_603:
7817 excp_model = "PowerPC 603";
7818 break;
7819 case POWERPC_EXCP_603E:
7820 excp_model = "PowerPC 603e";
7821 break;
7822 case POWERPC_EXCP_604:
7823 excp_model = "PowerPC 604";
7824 break;
7825 case POWERPC_EXCP_7x0:
7826 excp_model = "PowerPC 740/750";
7827 break;
7828 case POWERPC_EXCP_7x5:
7829 excp_model = "PowerPC 745/755";
7830 break;
7831 case POWERPC_EXCP_74xx:
7832 excp_model = "PowerPC 74xx";
7833 break;
7834 case POWERPC_EXCP_BOOKE:
7835 excp_model = "PowerPC BookE";
7836 break;
7837 #if defined (TARGET_PPC64)
7838 case POWERPC_EXCP_970:
7839 excp_model = "PowerPC 970";
7840 break;
7841 #endif
7842 default:
7843 excp_model = "Unknown or invalid";
7844 break;
7845 }
7846 switch (env->bus_model) {
7847 case PPC_FLAGS_INPUT_6xx:
7848 bus_model = "PowerPC 6xx";
7849 break;
7850 case PPC_FLAGS_INPUT_BookE:
7851 bus_model = "PowerPC BookE";
7852 break;
7853 case PPC_FLAGS_INPUT_405:
7854 bus_model = "PowerPC 405";
7855 break;
7856 case PPC_FLAGS_INPUT_401:
7857 bus_model = "PowerPC 401/403";
7858 break;
7859 case PPC_FLAGS_INPUT_RCPU:
7860 bus_model = "RCPU / MPC8xx";
7861 break;
7862 #if defined (TARGET_PPC64)
7863 case PPC_FLAGS_INPUT_970:
7864 bus_model = "PowerPC 970";
7865 break;
7866 #endif
7867 default:
7868 bus_model = "Unknown or invalid";
7869 break;
7870 }
7871 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
7872 " MMU model : %s\n",
7873 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
7874 #if !defined(CONFIG_USER_ONLY)
7875 if (env->tlb != NULL) {
7876 printf(" %d %s TLB in %d ways\n",
7877 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
7878 env->nb_ways);
7879 }
7880 #endif
7881 printf(" Exceptions model : %s\n"
7882 " Bus model : %s\n",
7883 excp_model, bus_model);
7884 printf(" MSR features :\n");
7885 if (env->flags & POWERPC_FLAG_SPE)
7886 printf(" signal processing engine enable"
7887 "\n");
7888 else if (env->flags & POWERPC_FLAG_VRE)
7889 printf(" vector processor enable\n");
7890 if (env->flags & POWERPC_FLAG_TGPR)
7891 printf(" temporary GPRs\n");
7892 else if (env->flags & POWERPC_FLAG_CE)
7893 printf(" critical input enable\n");
7894 if (env->flags & POWERPC_FLAG_SE)
7895 printf(" single-step trace mode\n");
7896 else if (env->flags & POWERPC_FLAG_DWE)
7897 printf(" debug wait enable\n");
7898 else if (env->flags & POWERPC_FLAG_UBLE)
7899 printf(" user BTB lock enable\n");
7900 if (env->flags & POWERPC_FLAG_BE)
7901 printf(" branch-step trace mode\n");
7902 else if (env->flags & POWERPC_FLAG_DE)
7903 printf(" debug interrupt enable\n");
7904 if (env->flags & POWERPC_FLAG_PX)
7905 printf(" inclusive protection\n");
7906 else if (env->flags & POWERPC_FLAG_PMM)
7907 printf(" performance monitor mark\n");
7908 if (env->flags == POWERPC_FLAG_NONE)
7909 printf(" none\n");
7910 printf(" Time-base/decrementer clock source: %s\n",
7911 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
7912 }
7913 dump_ppc_insns(env);
7914 dump_ppc_sprs(env);
7915 fflush(stdout);
7916 #endif
7917 }
7918
7919 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7920 {
7921 ObjectClass *oc = (ObjectClass *)a;
7922 uint32_t pvr = *(uint32_t *)b;
7923 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7924
7925 /* -cpu host does a PVR lookup during construction */
7926 if (unlikely(strcmp(object_class_get_name(oc),
7927 TYPE_HOST_POWERPC_CPU) == 0)) {
7928 return -1;
7929 }
7930
7931 #if defined(TARGET_PPCEMB)
7932 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7933 return -1;
7934 }
7935 #endif
7936
7937 return pcc->pvr == pvr ? 0 : -1;
7938 }
7939
7940 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7941 {
7942 GSList *list, *item;
7943 PowerPCCPUClass *pcc = NULL;
7944
7945 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7946 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7947 if (item != NULL) {
7948 pcc = POWERPC_CPU_CLASS(item->data);
7949 }
7950 g_slist_free(list);
7951
7952 return pcc;
7953 }
7954
7955 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
7956 {
7957 ObjectClass *oc = (ObjectClass *)a;
7958 const char *name = b;
7959 #if defined(TARGET_PPCEMB)
7960 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7961 #endif
7962
7963 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
7964 #if defined(TARGET_PPCEMB)
7965 pcc->mmu_model == POWERPC_MMU_BOOKE &&
7966 #endif
7967 strcmp(object_class_get_name(oc) + strlen(name),
7968 "-" TYPE_POWERPC_CPU) == 0) {
7969 return 0;
7970 }
7971 return -1;
7972 }
7973
7974 #include <ctype.h>
7975
7976 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7977 {
7978 GSList *list, *item;
7979 ObjectClass *ret = NULL;
7980 const char *p;
7981 int i, len;
7982
7983 /* Check if the given name is a PVR */
7984 len = strlen(name);
7985 if (len == 10 && name[0] == '0' && name[1] == 'x') {
7986 p = name + 2;
7987 goto check_pvr;
7988 } else if (len == 8) {
7989 p = name;
7990 check_pvr:
7991 for (i = 0; i < 8; i++) {
7992 if (!qemu_isxdigit(*p++))
7993 break;
7994 }
7995 if (i == 8) {
7996 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
7997 return ret;
7998 }
7999 }
8000
8001 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8002 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8003 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
8004 }
8005 }
8006
8007 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8008 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8009 if (item != NULL) {
8010 ret = OBJECT_CLASS(item->data);
8011 }
8012 g_slist_free(list);
8013
8014 return ret;
8015 }
8016
8017 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
8018 {
8019 PowerPCCPU *cpu;
8020 CPUPPCState *env;
8021 ObjectClass *oc;
8022 Error *err = NULL;
8023
8024 oc = ppc_cpu_class_by_name(cpu_model);
8025 if (oc == NULL) {
8026 return NULL;
8027 }
8028
8029 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
8030 env = &cpu->env;
8031 env->cpu_model_str = cpu_model;
8032
8033 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
8034 if (err != NULL) {
8035 fprintf(stderr, "%s\n", error_get_pretty(err));
8036 error_free(err);
8037 object_unref(OBJECT(cpu));
8038 return NULL;
8039 }
8040
8041 return cpu;
8042 }
8043
8044 /* Sort by PVR, ordering special case "host" last. */
8045 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8046 {
8047 ObjectClass *oc_a = (ObjectClass *)a;
8048 ObjectClass *oc_b = (ObjectClass *)b;
8049 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8050 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8051 const char *name_a = object_class_get_name(oc_a);
8052 const char *name_b = object_class_get_name(oc_b);
8053
8054 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8055 return 1;
8056 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8057 return -1;
8058 } else {
8059 /* Avoid an integer overflow during subtraction */
8060 if (pcc_a->pvr < pcc_b->pvr) {
8061 return -1;
8062 } else if (pcc_a->pvr > pcc_b->pvr) {
8063 return 1;
8064 } else {
8065 return 0;
8066 }
8067 }
8068 }
8069
8070 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8071 {
8072 ObjectClass *oc = data;
8073 CPUListState *s = user_data;
8074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8075 const char *typename = object_class_get_name(oc);
8076 char *name;
8077 int i;
8078
8079 #if defined(TARGET_PPCEMB)
8080 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8081 return;
8082 }
8083 #endif
8084 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8085 return;
8086 }
8087
8088 name = g_strndup(typename,
8089 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8090 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8091 name, pcc->pvr);
8092 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8093 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8094 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8095
8096 if (alias_oc != oc) {
8097 continue;
8098 }
8099 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8100 alias->alias, name);
8101 }
8102 g_free(name);
8103 }
8104
8105 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8106 {
8107 CPUListState s = {
8108 .file = f,
8109 .cpu_fprintf = cpu_fprintf,
8110 };
8111 GSList *list;
8112
8113 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8114 list = g_slist_sort(list, ppc_cpu_list_compare);
8115 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8116 g_slist_free(list);
8117
8118 #ifdef CONFIG_KVM
8119 cpu_fprintf(f, "\n");
8120 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8121 #endif
8122 }
8123
8124 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8125 {
8126 ObjectClass *oc = data;
8127 CpuDefinitionInfoList **first = user_data;
8128 const char *typename;
8129 CpuDefinitionInfoList *entry;
8130 CpuDefinitionInfo *info;
8131 #if defined(TARGET_PPCEMB)
8132 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8133
8134 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8135 return;
8136 }
8137 #endif
8138
8139 typename = object_class_get_name(oc);
8140 info = g_malloc0(sizeof(*info));
8141 info->name = g_strndup(typename,
8142 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8143
8144 entry = g_malloc0(sizeof(*entry));
8145 entry->value = info;
8146 entry->next = *first;
8147 *first = entry;
8148 }
8149
8150 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8151 {
8152 CpuDefinitionInfoList *cpu_list = NULL;
8153 GSList *list;
8154 int i;
8155
8156 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8157 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8158 g_slist_free(list);
8159
8160 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8161 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8162 ObjectClass *oc;
8163 CpuDefinitionInfoList *entry;
8164 CpuDefinitionInfo *info;
8165
8166 oc = ppc_cpu_class_by_name(alias->model);
8167 if (oc == NULL) {
8168 continue;
8169 }
8170
8171 info = g_malloc0(sizeof(*info));
8172 info->name = g_strdup(alias->alias);
8173
8174 entry = g_malloc0(sizeof(*entry));
8175 entry->value = info;
8176 entry->next = cpu_list;
8177 cpu_list = entry;
8178 }
8179
8180 return cpu_list;
8181 }
8182
8183 /* CPUClass::reset() */
8184 static void ppc_cpu_reset(CPUState *s)
8185 {
8186 PowerPCCPU *cpu = POWERPC_CPU(s);
8187 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8188 CPUPPCState *env = &cpu->env;
8189 target_ulong msr;
8190
8191 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8192 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
8193 log_cpu_state(env, 0);
8194 }
8195
8196 pcc->parent_reset(s);
8197
8198 msr = (target_ulong)0;
8199 if (0) {
8200 /* XXX: find a suitable condition to enable the hypervisor mode */
8201 msr |= (target_ulong)MSR_HVB;
8202 }
8203 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8204 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8205 msr |= (target_ulong)1 << MSR_EP;
8206 #if defined(DO_SINGLE_STEP) && 0
8207 /* Single step trace mode */
8208 msr |= (target_ulong)1 << MSR_SE;
8209 msr |= (target_ulong)1 << MSR_BE;
8210 #endif
8211 #if defined(CONFIG_USER_ONLY)
8212 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8213 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8214 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8215 msr |= (target_ulong)1 << MSR_PR;
8216 #endif
8217
8218 #if defined(TARGET_PPC64)
8219 if (env->mmu_model & POWERPC_MMU_64) {
8220 env->msr |= (1ULL << MSR_SF);
8221 }
8222 #endif
8223
8224 hreg_store_msr(env, msr, 1);
8225
8226 #if !defined(CONFIG_USER_ONLY)
8227 env->nip = env->hreset_vector | env->excp_prefix;
8228 if (env->mmu_model != POWERPC_MMU_REAL) {
8229 ppc_tlb_invalidate_all(env);
8230 }
8231 #endif
8232
8233 hreg_compute_hflags(env);
8234 env->reserve_addr = (target_ulong)-1ULL;
8235 /* Be sure no exception or interrupt is pending */
8236 env->pending_interrupts = 0;
8237 env->exception_index = POWERPC_EXCP_NONE;
8238 env->error_code = 0;
8239
8240 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8241 env->vpa_addr = 0;
8242 env->slb_shadow_addr = 0;
8243 env->slb_shadow_size = 0;
8244 env->dtl_addr = 0;
8245 env->dtl_size = 0;
8246 #endif /* TARGET_PPC64 */
8247
8248 /* Flush all TLBs */
8249 tlb_flush(env, 1);
8250 }
8251
8252 static void ppc_cpu_initfn(Object *obj)
8253 {
8254 CPUState *cs = CPU(obj);
8255 PowerPCCPU *cpu = POWERPC_CPU(obj);
8256 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8257 CPUPPCState *env = &cpu->env;
8258
8259 cs->env_ptr = env;
8260 cpu_exec_init(env);
8261
8262 env->msr_mask = pcc->msr_mask;
8263 env->mmu_model = pcc->mmu_model;
8264 env->excp_model = pcc->excp_model;
8265 env->bus_model = pcc->bus_model;
8266 env->insns_flags = pcc->insns_flags;
8267 env->insns_flags2 = pcc->insns_flags2;
8268 env->flags = pcc->flags;
8269 env->bfd_mach = pcc->bfd_mach;
8270 env->check_pow = pcc->check_pow;
8271
8272 #if defined(TARGET_PPC64)
8273 if (pcc->sps) {
8274 env->sps = *pcc->sps;
8275 } else if (env->mmu_model & POWERPC_MMU_64) {
8276 /* Use default sets of page sizes */
8277 static const struct ppc_segment_page_sizes defsps = {
8278 .sps = {
8279 { .page_shift = 12, /* 4K */
8280 .slb_enc = 0,
8281 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8282 },
8283 { .page_shift = 24, /* 16M */
8284 .slb_enc = 0x100,
8285 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8286 },
8287 },
8288 };
8289 env->sps = defsps;
8290 }
8291 #endif /* defined(TARGET_PPC64) */
8292
8293 if (tcg_enabled()) {
8294 ppc_translate_init();
8295 }
8296 }
8297
8298 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8299 {
8300 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8301 CPUClass *cc = CPU_CLASS(oc);
8302 DeviceClass *dc = DEVICE_CLASS(oc);
8303
8304 pcc->parent_realize = dc->realize;
8305 dc->realize = ppc_cpu_realizefn;
8306
8307 pcc->parent_reset = cc->reset;
8308 cc->reset = ppc_cpu_reset;
8309
8310 cc->class_by_name = ppc_cpu_class_by_name;
8311 cc->do_interrupt = ppc_cpu_do_interrupt;
8312 }
8313
8314 static const TypeInfo ppc_cpu_type_info = {
8315 .name = TYPE_POWERPC_CPU,
8316 .parent = TYPE_CPU,
8317 .instance_size = sizeof(PowerPCCPU),
8318 .instance_init = ppc_cpu_initfn,
8319 .abstract = true,
8320 .class_size = sizeof(PowerPCCPUClass),
8321 .class_init = ppc_cpu_class_init,
8322 };
8323
8324 static void ppc_cpu_register_types(void)
8325 {
8326 type_register_static(&ppc_cpu_type_info);
8327 }
8328
8329 type_init(ppc_cpu_register_types)
Qemu with PowerPC KVM improvements